From: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Thu, 19 Jan 2017 04:11:21 +0000 (+0000)
Subject: Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to... 
X-Git-Tag: V10.0.0~39
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=196516047b2160dce14470e44207d5a7f098c3c8;p=freertos

Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.


git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2480 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
index 6e3a6cb23..f0c9f2a32 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
@@ -20,7 +20,7 @@
 							<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53" id="xilinx.arm.a53.target.gnu.base.debug.565045804" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.a53.target.gnu.base.debug"/>
 							<builder buildPath="${workspace_loc:/RTOSDemo_A53}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.a53.toolchain.builder.debug.1503003921" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.arm.a53.toolchain.builder.debug"/>
 							<tool id="xilinx.gnu.arm.a53.c.toolchain.assembler.debug.1142300561" name="ARM A53 gcc assembler" superClass="xilinx.gnu.arm.a53.c.toolchain.assembler.debug">
-								<option id="xilinx.gnu.both.assembler.option.flags.139020974" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
+								<option id="xilinx.gnu.both.assembler.option.flags.139020974" name="Assembler Flags" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
 								<inputType id="xilinx.gnu.assembler.input.478741574" superClass="xilinx.gnu.assembler.input"/>
 							</tool>
 							<tool id="xilinx.gnu.arm.a53.c.toolchain.compiler.debug.587400676" name="ARM A53 gcc compiler" superClass="xilinx.gnu.arm.a53.c.toolchain.compiler.debug">
@@ -29,14 +29,15 @@
 								<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1218722002" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
 									<listOptionValue builtIn="false" value="../../RTOSDemo_A53_bsp/psu_cortexa53_0/include"/>
 								</option>
-								<option id="xilinx.gnu.compiler.dircategory.includes.959905810" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
+								<option id="xilinx.gnu.compiler.dircategory.includes.959905810" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/portable/GCC/ARM_CA53_64_BIT}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo/Standard_Demo_Tasks/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src}&quot;"/>
 								</option>
-								<option id="xilinx.gnu.compiler.misc.other.1651312713" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
+								<option id="xilinx.gnu.compiler.misc.other.1651312713" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
+								<option id="xilinx.gnu.compiler.symbols.defined.890730491" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined" valueType="definedSymbols"/>
 								<inputType id="xilinx.gnu.arm.a53.c.compiler.input.1725216366" name="C source files" superClass="xilinx.gnu.arm.a53.c.compiler.input"/>
 							</tool>
 							<tool id="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug.986847379" name="ARM A53 g++ compiler" superClass="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug">
@@ -55,6 +56,7 @@
 									<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
 								</option>
 								<option id="xilinx.gnu.c.linker.option.lscript.210457854" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+								<option id="xilinx.gnu.c.link.option.other.791632065" name="Other options (-XLinker [option])" superClass="xilinx.gnu.c.link.option.other" valueType="stringList"/>
 								<inputType id="xilinx.gnu.linker.input.294386883" superClass="xilinx.gnu.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -164,4 +166,5 @@
 			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53GCCManagedMakePerProjectProfileC"/>
 		</scannerConfigBuildInfo>
 	</storageModule>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c
index 853527563..887e9688e 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c
@@ -288,64 +288,6 @@ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
 }
 /*-----------------------------------------------------------*/
 
-void *memcpy( void *pvDest, const void *pvSource, size_t xBytes )
-{
-/* The compiler used during development seems to err unless these volatiles are
-included at -O3 optimisation.  */
-volatile unsigned char *pcDest = ( volatile unsigned char * ) pvDest, *pcSource = ( volatile unsigned char * ) pvSource;
-size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-	if( pvDest != pvSource )
-	{
-		for( x = 0; x < xBytes; x++ )
-		{
-			pcDest[ x ] = pcSource[ x ];
-		}
-	}
-
-	return pvDest;
-}
-/*-----------------------------------------------------------*/
-
-void *memset( void *pvDest, int iValue, size_t xBytes )
-{
-/* The compiler used during development seems to err unless these volatiles are
-included at -O3 optimisation.  */
-volatile unsigned char * volatile pcDest = ( volatile unsigned char * volatile ) pvDest;
-volatile size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-	for( x = 0; x < xBytes; x++ )
-	{
-		pcDest[ x ] = ( unsigned char ) iValue;
-	}
-
-	return pvDest;
-}
-/*-----------------------------------------------------------*/
-
-int memcmp( const void *pvMem1, const void *pvMem2, size_t xBytes )
-{
-const volatile unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2;
-volatile size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-    for( x = 0; x < xBytes; x++ )
-    {
-        if( pucMem1[ x ] != pucMem2[ x ] )
-        {
-            break;
-        }
-    }
-
-    return xBytes - x;
-}
-/*-----------------------------------------------------------*/
-
 void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber )
 {
 	xil_printf( "ASSERT!  Line %lu of file %s\r\n", ulLineNumber, pcFileName );
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
index 7d8be3152..f9fa7224b 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
@@ -260,12 +260,12 @@
 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
 
 
 /******************************************************************/
@@ -275,12 +275,12 @@
 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
 
 
 /******************************************************************/
@@ -452,8 +452,6 @@
 
 
 /* Definitions for peripheral PSU_IOU_S */
-#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000
-#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF
 
 
 /* Definitions for peripheral PSU_IOU_SCNTR */
@@ -512,8 +510,6 @@
 
 
 /* Definitions for peripheral PSU_OCM_RAM_1 */
-#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
-#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
 
 
 /* Definitions for peripheral PSU_OCM_XMPU_CFG */
@@ -651,7 +647,7 @@
 
 /******************************************************************/
 
-#define  XPAR_XIPIPSU_NUM_INSTANCES  1
+#define  XPAR_XIPIPSU_NUM_INSTANCES  3
 
 /* Parameter definitions for peripheral psu_ipi_0 */
 #define  XPAR_PSU_IPI_0_DEVICE_ID  0
@@ -660,6 +656,20 @@
 #define  XPAR_PSU_IPI_0_BUFFER_INDEX  2
 #define  XPAR_PSU_IPI_0_INT_ID  67
 
+/* Parameter definitions for peripheral psu_ipi_1 */
+#define  XPAR_PSU_IPI_1_DEVICE_ID  1
+#define  XPAR_PSU_IPI_1_BASE_ADDRESS  0xFF310000
+#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100
+#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0
+#define  XPAR_PSU_IPI_1_INT_ID  65
+
+/* Parameter definitions for peripheral psu_ipi_2 */
+#define  XPAR_PSU_IPI_2_DEVICE_ID  2
+#define  XPAR_PSU_IPI_2_BASE_ADDRESS  0xFF320000
+#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200
+#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1
+#define  XPAR_PSU_IPI_2_INT_ID  66
+
 /* Canonical definitions for peripheral psu_ipi_0 */
 #define  XPAR_XIPIPSU_0_DEVICE_ID	XPAR_PSU_IPI_0_DEVICE_ID
 #define  XPAR_XIPIPSU_0_BASE_ADDRESS	XPAR_PSU_IPI_0_BASE_ADDRESS
@@ -667,6 +677,20 @@
 #define  XPAR_XIPIPSU_0_BUFFER_INDEX	XPAR_PSU_IPI_0_BUFFER_INDEX
 #define  XPAR_XIPIPSU_0_INT_ID	XPAR_PSU_IPI_0_INT_ID
 
+/* Canonical definitions for peripheral psu_ipi_1 */
+#define  XPAR_XIPIPSU_1_DEVICE_ID	XPAR_PSU_IPI_1_DEVICE_ID
+#define  XPAR_XIPIPSU_1_BASE_ADDRESS	XPAR_PSU_IPI_1_BASE_ADDRESS
+#define  XPAR_XIPIPSU_1_BIT_MASK	XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPSU_1_BUFFER_INDEX	XPAR_PSU_IPI_1_BUFFER_INDEX
+#define  XPAR_XIPIPSU_1_INT_ID	XPAR_PSU_IPI_1_INT_ID
+
+/* Canonical definitions for peripheral psu_ipi_2 */
+#define  XPAR_XIPIPSU_2_DEVICE_ID	XPAR_PSU_IPI_2_DEVICE_ID
+#define  XPAR_XIPIPSU_2_BASE_ADDRESS	XPAR_PSU_IPI_2_BASE_ADDRESS
+#define  XPAR_XIPIPSU_2_BIT_MASK	XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPSU_2_BUFFER_INDEX	XPAR_PSU_IPI_2_BUFFER_INDEX
+#define  XPAR_XIPIPSU_2_INT_ID	XPAR_PSU_IPI_2_INT_ID
+
 #define  XPAR_XIPIPSU_NUM_TARGETS  11
 
 #define  XPAR_PSU_IPI_0_BIT_MASK  0x00000001
@@ -695,15 +719,31 @@
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1
@@ -715,14 +755,18 @@
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2
 
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6
 
 /* Definitions for driver QSPIPSU */
 #define XPAR_XQSPIPSU_NUM_INSTANCES 1
@@ -1010,14 +1054,14 @@
 #define XPAR_PSU_WDT_0_DEVICE_ID 0
 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
 
 
 /* Definitions for peripheral PSU_WDT_1 */
 #define XPAR_PSU_WDT_1_DEVICE_ID 1
 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
@@ -1026,13 +1070,13 @@
 #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
 #define XPAR_XWDTPS_0_BASEADDR 0xFF150000
 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
 
 /* Canonical definitions for peripheral PSU_WDT_1 */
 #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
 #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
index a33878ef5..2bd473dd5 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c
index b45c5b2d6..4063a44eb 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c
index b3fb65f5b..09e7f739a 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c
index 6a7cc7866..db734b924 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
index 597b38a12..38a5b9355 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c
index 50f1c1413..f449e0ed6 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
index 6d32d1dc7..7845cb5b7 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
@@ -101,5 +101,117 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] =
 				XPAR_PSU_IPI_10_BUFFER_INDEX
 			}
 		}
+	},
+
+	{
+		XPAR_PSU_IPI_1_DEVICE_ID,
+		XPAR_PSU_IPI_1_BASE_ADDRESS,
+		XPAR_PSU_IPI_1_BIT_MASK,
+		XPAR_PSU_IPI_1_BUFFER_INDEX,
+		XPAR_PSU_IPI_1_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	},
+
+	{
+		XPAR_PSU_IPI_2_DEVICE_ID,
+		XPAR_PSU_IPI_2_BASE_ADDRESS,
+		XPAR_PSU_IPI_2_BIT_MASK,
+		XPAR_PSU_IPI_2_BUFFER_INDEX,
+		XPAR_PSU_IPI_2_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
 	}
 };
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
index daa5bde27..969fa96b0 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
index 8dc37775a..5913cd8d4 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c
index 2acea2b51..ff1955d3a 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c
index b5d2e4be8..34c589039 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
index 4dd178f04..8671e3fbe 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
index ace39e369..b692531ad 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
index 10c16eb02..28d356092 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
index 94aaf5b2e..d4a8e5ab9 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
index 5147be676..6ea6b192b 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c
index 33202264d..194aac12e 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
index fb6114afc..bcd6d1ada 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
@@ -496,6 +496,23 @@ void vFullDemoTickHook( void )
 
 	/* Call the code that 'gives' a task notification from an ISR. */
 	xNotifyTaskFromISR();
+
+	/* Test flop alignment in interrupts - calling printf from an interrupt
+	is BAD! */
+	#if( configASSERT_DEFINED == 1 )
+	{
+	char cBuf[ 20 ];
+	UBaseType_t uxSavedInterruptStatus;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			sprintf( cBuf, "%1.3f", 1.234 );
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		configASSERT( strcmp( cBuf, "1.234" ) == 0 );
+	}
+	#endif /* configASSERT_DEFINED */
 }
 
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
index 25054143d..d73fe8014 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="org.eclipse.cdt.core.default.config.750804140">
-			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.750804140" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+		<cconfiguration id="org.eclipse.cdt.core.default.config.887738538">
+			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.887738538" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
 				<externalSettings/>
 				<extensions/>
 			</storageModule>
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project
index be846c648..ed0ff0ff0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
 	<name>RTOSDemo_R5_bsp</name>
-	<comment>Created by SDK v2016.1</comment>
+	<comment>Created by SDK v2016.4</comment>
 	<projects>
 	</projects>
 	<buildSpec>
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile
index 91c3fcf13..071f646d1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile
@@ -21,11 +21,11 @@ $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
 
 %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
 	@echo "Running Make include in $(subst /make.include,,$@)"
-	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16"
+	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5"
 
 %/make.libs: include
 	@echo "Running Make libs in $(subst /make.libs,,$@)"
-	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16"
+	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5"
 
 clean:
 	rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
index 7e9e79ff2..efc88f158 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
@@ -13,6 +13,9 @@
 
 /******************************************************************/
 
+ /* Definition for PSS REF CLK FREQUENCY */
+#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U
+
 #include "xparameters_ps.h"
 
 /******************************************************************/
@@ -27,6 +30,10 @@
 
 /******************************************************************/
 
+
+/* Number of Fabric Resets */
+#define XPAR_NUM_FABRIC_RESETS 1
+
 #define STDIN_BASEADDRESS 0xFF000000
 #define STDOUT_BASEADDRESS 0xFF000000
 
@@ -260,6 +267,28 @@
 #define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0
 
 
+/******************************************************************/
+
+/* Definitions for driver DDRCPSU */
+#define XPAR_XDDRCPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_DDRC_0 */
+#define XPAR_PSU_DDRC_0_DEVICE_ID 0
+#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000
+#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF
+#define XPAR_PSU_DDRC_0_HAS_ECC 0
+#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_DDRC_0 */
+#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID
+#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000
+#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF
+#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002
+
+
 /******************************************************************/
 
 /* Definitions for driver EMACPS */
@@ -270,12 +299,12 @@
 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
 
 
 /******************************************************************/
@@ -285,12 +314,12 @@
 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
 
 
 /******************************************************************/
@@ -336,11 +365,6 @@
 #define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF
 
 
-/* Definitions for peripheral PSU_BBRAM_0 */
-#define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000
-#define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF
-
-
 /* Definitions for peripheral PSU_CCI_GPV */
 #define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000
 #define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF
@@ -406,11 +430,6 @@
 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF
 
 
-/* Definitions for peripheral PSU_DDRC_0 */
-#define XPAR_PSU_DDRC_0_S_AXI_BASEADDR 0xFD070000
-#define XPAR_PSU_DDRC_0_S_AXI_HIGHADDR 0xFD070FFF
-
-
 /* Definitions for peripheral PSU_DP */
 #define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000
 #define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF
@@ -456,11 +475,6 @@
 #define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF
 
 
-/* Definitions for peripheral PSU_IOU_S */
-#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000
-#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF
-
-
 /* Definitions for peripheral PSU_IOU_SCNTR */
 #define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000
 #define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF
@@ -516,11 +530,6 @@
 #define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF
 
 
-/* Definitions for peripheral PSU_OCM_RAM_1 */
-#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
-#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
-
-
 /* Definitions for peripheral PSU_OCM_XMPU_CFG */
 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000
 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF
@@ -541,6 +550,11 @@
 #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF
 
 
+/* Definitions for peripheral PSU_PCIE_LOW */
+#define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000
+#define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF
+
+
 /* Definitions for peripheral PSU_PMU_GLOBAL_0 */
 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000
 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF
@@ -551,44 +565,19 @@
 #define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF
 
 
-/* Definitions for peripheral PSU_PMU_RAM */
-#define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000
-#define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF
-
-
 /* Definitions for peripheral PSU_QSPI_LINEAR_0 */
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF
 
 
 /* Definitions for peripheral PSU_R5_0_ATCM */
-#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0xFFE00000
-#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0xFFE0FFFF
-
-
-/* Definitions for peripheral PSU_R5_0_ATCM_LOCKSTEP */
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE10000
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE1FFFF
+#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000
+#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF
 
 
 /* Definitions for peripheral PSU_R5_0_BTCM */
-#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0xFFE20000
-#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0xFFE2FFFF
-
-
-/* Definitions for peripheral PSU_R5_0_BTCM_LOCKSTEP */
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE30000
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE3FFFF
-
-
-/* Definitions for peripheral PSU_R5_1_ATCM */
-#define XPAR_PSU_R5_1_ATCM_S_AXI_BASEADDR 0xFFE90000
-#define XPAR_PSU_R5_1_ATCM_S_AXI_HIGHADDR 0xFFE9FFFF
-
-
-/* Definitions for peripheral PSU_R5_1_BTCM */
-#define XPAR_PSU_R5_1_BTCM_S_AXI_BASEADDR 0xFFEB0000
-#define XPAR_PSU_R5_1_BTCM_S_AXI_HIGHADDR 0xFFEBFFFF
+#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000
+#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF
 
 
 /* Definitions for peripheral PSU_R5_DDR_0 */
@@ -598,7 +587,7 @@
 
 /* Definitions for peripheral PSU_R5_TCM_RAM_0 */
 #define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000
-#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x00020000
+#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
 
 
 /* Definitions for peripheral PSU_RPU */
@@ -636,11 +625,6 @@
 #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF
 
 
-/* Definitions for peripheral PSU_USB_0 */
-#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFE200000
-#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFE20FFFF
-
-
 /******************************************************************/
 
 /* Definitions for driver GPIOPS */
@@ -754,15 +738,31 @@
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1
@@ -774,14 +774,18 @@
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2
 
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6
 
 /* Definitions for driver QSPIPSU */
 #define XPAR_XQSPIPSU_NUM_INSTANCES 1
@@ -858,6 +862,9 @@
 #define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006
 #define XPAR_PSU_SD_1_HAS_CD 1
 #define XPAR_PSU_SD_1_HAS_WP 1
+#define XPAR_PSU_SD_1_BUS_WIDTH 4
+#define XPAR_PSU_SD_1_MIO_BANK 1
+#define XPAR_PSU_SD_1_HAS_EMIO 0
 
 
 /******************************************************************/
@@ -869,6 +876,9 @@
 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006
 #define XPAR_XSDPS_0_HAS_CD 1
 #define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 4
+#define XPAR_XSDPS_0_MIO_BANK 1
+#define XPAR_XSDPS_0_HAS_EMIO 0
 
 
 /******************************************************************/
@@ -1060,6 +1070,25 @@
 #define XPAR_XUARTPS_1_HAS_MODEM 0
 
 
+/******************************************************************/
+
+/* Definitions for driver USBPSU */
+#define XPAR_XUSBPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_USB_0 */
+#define XPAR_PSU_USB_0_DEVICE_ID 0
+#define XPAR_PSU_USB_0_BASEADDR 0xFE200000
+#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_USB_0 */
+#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID
+#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000
+#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF
+
+
 /******************************************************************/
 
 /* Definitions for driver WDTPS */
@@ -1069,14 +1098,14 @@
 #define XPAR_PSU_WDT_0_DEVICE_ID 0
 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
 
 
 /* Definitions for peripheral PSU_WDT_1 */
 #define XPAR_PSU_WDT_1_DEVICE_ID 1
 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
@@ -1085,13 +1114,13 @@
 #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
 #define XPAR_XWDTPS_0_BASEADDR 0xFF150000
 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
 
 /* Canonical definitions for peripheral PSU_WDT_1 */
 #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
 #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile
deleted file mode 100644
index 926b20c4e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-
-libs:
-	echo "Compiling axipmon"
-	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
-	make clean
-
-include:
-	 ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OUTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c
deleted file mode 100644
index fbb867839..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c
+++ /dev/null
@@ -1,2123 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xaxipmon.c
-* @addtogroup axipmon_v6_3
-* @{
-*
-* This file contains the driver API functions that can be used to access
-* the AXI Performance Monitor device.
-*
-* Refer to the xaxipmon.h header file for more information about this driver.
-*
-* @note 	None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.00a bss   02/27/12  First release
-* 2.00a bss   06/23/12  Updated to support v2_00a version of IP.
-* 3.00a bss   09/03/12  Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
-*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
-*			to support v2_01a version of IP.
-* 3.01a bss   10/25/12  Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
-*			APIs (CR #683799).
-*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
-*			APIs (CR #683801).
-*			Added XAxiPmon_GetMetricName API (CR #683803).
-*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
-*			(CR #683746)
-*			Added XAxiPmon_EnableEventLog,
-*			XAxiPmon_DisableMetricsCounter,
-*			XAxiPmon_EnableMetricsCounter APIs to replace macros.
-*			Added XAxiPmon_SetMetricCounterCutOff,
-*			XAxiPmon_GetMetricCounterCutOff,
-*			XAxiPmon_EnableExternalTrigger and
-*			XAxiPmon_DisableExternalTrigger APIs to support new
-*			version of IP.
-* 4.00a bss   01/17/13  To support new version of IP:
-* 			Added XAxiPmon_SetLogEnableRanges,
-*	  		XAxiPmon_GetLogEnableRanges,
-*			XAxiPmon_EnableMetricCounterTrigger,
-*			XAxiPmon_DisableMetricCounterTrigger,
-*			XAxiPmon_EnableEventLogTrigger,
-*			XAxiPmon_DisableEventLogTrigger,
-*			XAxiPmon_SetWriteLatencyId,
-*			XAxiPmon_SetReadLatencyId,
-*			XAxiPmon_GetWriteLatencyId,
-*			XAxiPmon_GetReadLatencyId APIs and removed
-*			XAxiPmon_SetMetricCounterCutOff,
-*			XAxiPmon_GetMetricCounterCutOff,
-*			XAxiPmon_EnableExternalTrigger and
-*			XAxiPmon_DisableExternalTrigger APIs
-* 5.00a bss   08/26/13  To support new version of IP:
-*			Modified XAxiPmon_CfgInitialize to add Mode of APM and
-*			ScaleFactor parameter.
-*			Modified Assert functions depending on Mode.
-*			Modified XAxiPmon_GetMetricCounter and
-*			XAxiPmon_GetSampledMetricCounter to include
-*			new Counters.
-*			Modified XAxiPmon_SetSampleInterval and
-*			XAxiPmon_GetSampleInterval to remove higher 32 bit
-*			value of SampleInterval since Sample Interval Register
-*			is only 32 bit.
-*			Added XAxiPmon_SetWrLatencyStart,
-*			XAxiPmon_SetWrLatencyEnd, XAxiPmon_SetRdLatencyStart
-*			XAxiPmon_SetRdLatencyEnd, XAxiPmon_GetWrLatencyStart,
-*			XAxiPmon_GetWrLatencyEnd, XAxiPmon_GetRdLatencyStart,
-*			XAxiPmon_GetRdLatencyEnd, XAxiPmon_SetWriteIdMask,
-*			XAxiPmon_SetReadIdMask,
-*			XAxiPmon_GetWriteIdMask and
-*			XAxiPmon_GetReadIdMask APIs.
-*			Renamed:
-*			XAxiPmon_SetWriteLatencyId to XAxiPmon_SetWriteId
-*			XAxiPmon_SetReadLatencyId to XAxiPmon_SetReadId
-*			XAxiPmon_GetWriteLatencyId to XAxiPmon_GetWriteId
-*			XAxiPmon_SetReadLatencyId to XAxiPmon_GetReadId.
-* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize to Reset counters
-*			and FIFOs based on Modes(CR#782671). And if both
-*			profile and trace modes are present set mode as
-*			Advanced.
-* 6.2	bss  03/02/15	Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
-*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
-*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
-*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
-*						functions to support Zynq MP APM.
-* 6.3	kvn  07/02/15	Modified code according to MISRA-C:2012 guidelines.
-* 6.4   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
-*                     Changed the prototype of XAxiPmon_CfgInitialize API.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xaxipmon.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a specific XAxiPmon device/instance. This function
-* must be called prior to using the AXI Performance Monitor device.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	ConfigPtr points to the XAxiPmon device configuration structure.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. If the address translation is not used then the
-*		physical address is passed.
-*		Unexpected errors may occur if the address mapping is changed
-*		after this function is invoked.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*
-* @note		The user needs to first call the XAxiPmon_LookupConfig() API
-*		which returns the Configuration structure pointer which is
-*		passed as a parameter to the XAxiPmon_CfgInitialize() API.
-*
-******************************************************************************/
-s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
-						UINTPTR EffectiveAddr)
-{
-	/*
-	 * Assert the input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	/*
-	 * Set the values read from the device config and the base address.
-	 */
-	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-	InstancePtr->Config.GlobalClkCounterWidth =
-				ConfigPtr->GlobalClkCounterWidth;
-	InstancePtr->Config.MetricSampleCounterWidth =
-				ConfigPtr->MetricSampleCounterWidth;
-	InstancePtr->Config.IsEventCount =
-				ConfigPtr->IsEventCount;
-	InstancePtr->Config.NumberofSlots =
-				ConfigPtr->NumberofSlots;
-	InstancePtr->Config.NumberofCounters =
-				ConfigPtr->NumberofCounters;
-	InstancePtr->Config.HaveSampledCounters =
-				ConfigPtr->HaveSampledCounters;
-	InstancePtr->Config.IsEventLog =
-				ConfigPtr->IsEventLog;
-	InstancePtr->Config.FifoDepth =
-				ConfigPtr->FifoDepth;
-	InstancePtr->Config.FifoWidth =
-				ConfigPtr->FifoWidth;
-	InstancePtr->Config.TidWidth =
-				ConfigPtr->TidWidth;
-	InstancePtr->Config.Is32BitFiltering = ConfigPtr->Is32BitFiltering;
-
-	InstancePtr->Config.ScaleFactor = ConfigPtr->ScaleFactor;
-
-	if ((ConfigPtr->ModeProfile == ConfigPtr->ModeTrace)
-			|| (ConfigPtr->ModeAdvanced == 1U))
-	{
-		InstancePtr->Mode = XAPM_MODE_ADVANCED;
-	} else if (ConfigPtr->ModeTrace == 1U) {
-		InstancePtr->Mode = XAPM_MODE_TRACE;
-	} else {
-		InstancePtr->Mode = XAPM_MODE_PROFILE;
-	}
-
-	/*
-	 * Indicate the instance is now ready to use, initialized without error.
-	 */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-	/*
-	 * Reset the Counters and FIFO based on Modes.
-	 */
-
-	/* Advanced and Profile */
-	if((InstancePtr->Mode == XAPM_MODE_ADVANCED) ||
-			(InstancePtr->Mode == XAPM_MODE_PROFILE))
-	{
-		(void)XAxiPmon_ResetMetricCounter(InstancePtr);
-	}
-	/* Advanced */
-	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
-	{
-		XAxiPmon_ResetGlobalClkCounter(InstancePtr);
-	}
-	/* Advanced and Trace */
-	if((InstancePtr->Mode == XAPM_MODE_ADVANCED) ||
-			(InstancePtr->Mode == XAPM_MODE_TRACE))
-	{
-		(void)XAxiPmon_ResetFifo(InstancePtr);
-	}
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function resets all Metric Counters and Sampled Metric Counters of
-* AXI Performance Monitor.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	XST_SUCCESS
-*
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr)
-{
-
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
-
-	/*
-	 * Write the reset value to the Control register to reset
-	 * Metric counters
-	 */
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							 XAPM_CTL_OFFSET);
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-					(RegValue | XAPM_CR_MCNTR_RESET_MASK));
-	/*
-	 * Release from Reset
-	 */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				(RegValue & ~(XAPM_CR_MCNTR_RESET_MASK)));
-	return XST_SUCCESS;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function resets Global Clock Counter of AXI Performance Monitor
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr)
-{
-
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
-
-	/*
-	 * Write the reset value to the Control register to reset
-	 * Global Clock Counter
-	 */
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							 XAPM_CTL_OFFSET);
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-					(RegValue | XAPM_CR_GCC_RESET_MASK));
-
-	/*
-	 * Release from Reset
-	 */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				(RegValue & ~(XAPM_CR_GCC_RESET_MASK)));
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function resets Streaming FIFO of AXI Performance Monitor
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	XST_SUCCESS
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr)
-{
-
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_PROFILE);
-
-	/* Check Event Logging is enabled in Hardware */
-	if((InstancePtr->Config.IsEventLog == 0U) &&
-			(InstancePtr->Mode == XAPM_MODE_ADVANCED))
-	{
-		/*Event logging not enabled in Hardware*/
-		return XST_SUCCESS;
-	}
-	/*
-	 * Write the reset value to the Control register to reset
-	 * FIFO
-	 */
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							 XAPM_CTL_OFFSET);
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-					(RegValue | XAPM_CR_FIFO_RESET_MASK));
-	/*
-	 * Release from Reset
-	 */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				(RegValue & ~(XAPM_CR_FIFO_RESET_MASK)));
-
-	return XST_SUCCESS;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets Ranges for Incrementers depending on parameters passed.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	IncrementerNum specifies the Incrementer for which Ranges
-*		need to be set
-* @param 	RangeUpper specifies the Upper limit in 32 bit Register
-* @param 	RangeLower specifies the Lower limit in 32 bit Register
-*
-* @return	None.
-*
-* @note		None
-*
-*****************************************************************************/
-void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
-					u16 RangeUpper,	u16 RangeLower)
- {
-
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
-	Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS);
-
-	/*
-	 * Write to the specified Range register
-	 */
-	RegValue = (u32)RangeUpper << 16;
-	RegValue |= RangeLower;
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16)),
-			RegValue);
- }
-
-/****************************************************************************/
-/**
-*
-* This function returns the Ranges of Incrementers Registers.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	IncrementerNum specifies the Incrementer for which Ranges
-*		need to be returned.
-* @param 	RangeUpper specifies the user reference variable which returns
-*		the Upper Range Value of the specified Incrementer.
-* @param 	RangeLower specifies the user reference variable which returns
-*		the Lower Range Value of the specified Incrementer.
-*
-* @return	None.
-*
-* @note		None
-*
-*****************************************************************************/
-void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
-				u16 *RangeUpper, u16 *RangeLower)
- {
-
-	u32 RegValue;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
-	Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS);
-
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-				((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16)));
-
-	*RangeLower = (u16)(RegValue & 0x0000FFFFU);
-	*RangeUpper = (u16)((RegValue >> 16) & 0x0000FFFFU);
- }
-
-/****************************************************************************/
-/**
-*
-* This function sets the Sample Interval Register
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	SampleInterval is the Sample Interval value to be set
-*
-* @return	None
-*
-* @note		None.
-*
-*****************************************************************************/
-void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval)
-{
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
-
-	/*
-	 * Set Sample Interval Lower
-	 */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-		XAPM_SI_LOW_OFFSET, SampleInterval);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of Sample Interval Register
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	SampleInterval is a pointer where the Sample Interval
-*		Counter value is returned.
-*
-* @return 	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval)
-{
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
-
-	/*
-	 * Set Sample Interval Lower
-	 */
-	*SampleInterval = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-				XAPM_SI_LOW_OFFSET);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets Metrics for specified Counter in the corresponding
-* Metric Selector Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Slot is the slot ID for which specified counter has to
-*		be connected.
-* @param	Metrics is one of the Metric Sets. User has to use
-*		XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter
-* @param	CounterNum is the Counter Number.
-*		The valid values are 0 to 9.
-*
-* @return	XST_SUCCESS if Success
-*		XST_FAILURE if Failure
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
-						u8 CounterNum)
-{
-	u32 RegValue;
-	u32 Mask;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
-	Xil_AssertNonvoid(Slot < XAPM_MAX_AGENTS);
-	Xil_AssertNonvoid((Metrics <= XAPM_METRIC_SET_22) ||
-			(Metrics == XAPM_METRIC_SET_30));
-	Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS);
-
-	/* Find Mask value to force zero in counternum byte range */
-	if ((CounterNum == 0U) || (CounterNum == 4U) || (CounterNum == 8U)) {
-		Mask = 0xFFFFFF00U;
-	}
-	else if ((CounterNum == 1U) || (CounterNum == 5U) || (CounterNum == 9U)) {
-		Mask = 0xFFFF00FFU;
-	}
-	else if ((CounterNum == 2U) || (CounterNum == 6U)) {
-		Mask = 0xFF00FFFFU;
-	}
-	else {
-		Mask = 0x00FFFFFFU;
-	}
-
-	if(CounterNum <= 3U) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-					    XAPM_MSR0_OFFSET);
-
-		RegValue = RegValue & Mask;
-		RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
-		RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					(u32)XAPM_MSR0_OFFSET,RegValue);
-	}
-	else if((CounterNum >= 4U) && (CounterNum <= 7U)) {
-		CounterNum = CounterNum - 4U;
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-					    (u32)XAPM_MSR1_OFFSET);
-
-		RegValue = RegValue & Mask;
-		RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
-		RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_MSR1_OFFSET,RegValue);
-	}
-	else {
-		CounterNum = CounterNum - 8U;
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-					    XAPM_MSR2_OFFSET);
-
-		RegValue = RegValue & Mask;
-		RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
-		RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_MSR2_OFFSET,RegValue);
-	}
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns Metrics in the specified Counter from the corresponding
-* Metric Selector Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	CounterNum is the Counter Number.
-*		The valid values are 0 to 9.
-* @param	Metrics is a reference parameter from application where metrics
-*		of specified counter is filled.
-* @praram	Slot is a reference parameter in which slot Id of
-*		specified counter is filled
-* @return	XST_SUCCESS if Success
-*		XST_FAILURE if Failure
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
-								u8 *Slot)
-{
-	u32 RegValue;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
-	Xil_AssertNonvoid(CounterNum <= XAPM_MAX_COUNTERS);
-
-	if(CounterNum <= 3U) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-					XAPM_MSR0_OFFSET);
-		*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
-		*Slot 	= (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
-
-	}
-	else if((CounterNum >= 4U) && (CounterNum <= 7U)) {
-		CounterNum = CounterNum - 4U;
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-					XAPM_MSR1_OFFSET);
-		*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
-		*Slot 	= (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
-	}
-	else {
-		CounterNum = CounterNum - 8U;
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-					XAPM_MSR2_OFFSET);
-		*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
-		*Slot 	= (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
-	}
-	return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the Global Clock Counter Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	CntHighValue is the user space pointer with which upper 32 bits
-*		of Global Clock Counter has to be filled
-* @param	CntLowValue is the user space pointer with which lower 32 bits
-*		of Global Clock Counter has to be filled
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
-							u32 *CntLowValue)
-{
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
-
-	*CntHighValue = 0x0U;
-	*CntLowValue  = 0x0U;
-
-	/*
-	 * If Counter width is 64 bit then Counter Value has to be
-	 * filled at CntHighValue address also.
-	 */
-	if(InstancePtr->Config.GlobalClkCounterWidth == 64) {
-
-		/* Bits[63:32] exists at XAPM_GCC_HIGH_OFFSET */
-		*CntHighValue = XAxiPmon_ReadReg(InstancePtr->
-				Config.BaseAddress, XAPM_GCC_HIGH_OFFSET);
-	}
-	/* Bits[31:0] exists at XAPM_GCC_LOW_OFFSET */
-	*CntLowValue = XAxiPmon_ReadReg(InstancePtr->
-				Config.BaseAddress, XAPM_GCC_LOW_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the Metric Counter Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	CounterNum is the number of the Metric Counter to be read.
-*		Use the XAPM_METRIC_COUNTER* defines for the counter number in
-*		xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to
-*		47(XAPM_METRIC_COUNTER_47).
-* @return	RegValue is the content of specified Metric Counter.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum)
-{
-
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
-	Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE);
-
-	if (CounterNum < 10U ) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_MC0_OFFSET + (CounterNum * (u32)16)));
-	}
-	else if ((CounterNum >= 10U) && (CounterNum < 12U)) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_MC10_OFFSET + ((CounterNum - (u32)10) * (u32)16)));
-	}
-	else if ((CounterNum >= 12U) && (CounterNum < 24U)) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_MC12_OFFSET + ((CounterNum - (u32)12) * (u32)16)));
-	}
-	else if ((CounterNum >= 24U) && (CounterNum < 36U)) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_MC24_OFFSET + ((CounterNum - (u32)24) * (u32)16)));
-	}
-	else {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_MC36_OFFSET + ((CounterNum - (u32)36) * (u32)16)));
-	}
-
-	return RegValue;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the Sampled Metric Counter Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	CounterNum is the number of the Sampled Metric Counter to read.
-*		Use the XAPM_METRIC_COUNTER* defines for the counter number in
-*		xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to
-*		47(XAPM_METRIC_COUNTER_47).
-*
-* @return	RegValue is the content of specified Sampled Metric Counter.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum)
-{
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
-	Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE);
-	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
-		((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-			(InstancePtr->Config.HaveSampledCounters == 1U)));
-
-	if (CounterNum < 10U ) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_SMC0_OFFSET + (CounterNum * (u32)16)));
-	}
-	else if ((CounterNum >= 10U) && (CounterNum < 12U)) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_SMC10_OFFSET + ((CounterNum - (u32)10) * (u32)16)));
-	}
-	else if ((CounterNum >= 12U) && (CounterNum < 24U)) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_SMC12_OFFSET + ((CounterNum - (u32)12) * (u32)16)));
-	}
-	else if ((CounterNum >= 24U) && (CounterNum < 36U)) {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_SMC24_OFFSET + ((CounterNum - (u32)24) * (u32)16)));
-	}
-	else {
-		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_SMC36_OFFSET + ((CounterNum - (u32)36) * (u32)16)));
-	}
-
-	return RegValue;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the Incrementer Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	IncrementerNum is the number of the Incrementer register to
-*		read.Use the XAPM_INCREMENTER_* defines for the Incrementer
-*		number.The valid values are 0 (XAPM_INCREMENTER_0) to
-*		9 (XAPM_INCREMENTER_9).
-* @param	IncrementerNum is the number of the specified Incrementer
-*		register
-* @return	RegValue is content of specified Metric Incrementer register.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum)
-{
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U));
-	Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS);
-
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)XAPM_INC0_OFFSET + (IncrementerNum * (u32)16)));
-
-	return RegValue;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the Sampled Incrementer Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	IncrementerNum is the number of the Sampled Incrementer
-*		register to read.Use the XAPM_INCREMENTER_* defines for the
-*		Incrementer number.The valid values are 0 (XAPM_INCREMENTER_0)
-*		to 9 (XAPM_INCREMENTER_9).
-* @param	IncrementerNum is the number of the specified Sampled
-*		Incrementer register
-* @return	RegValue is content of specified Sampled Incrementer register.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum)
-{
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U) &&
-				(InstancePtr->Config.HaveSampledCounters == 1U));
-	Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS);
-
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-				((u32)XAPM_SINC0_OFFSET + (IncrementerNum * (u32)16)));
-	return RegValue;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets Software-written Data Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	SwData is the Software written Data.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData)
-{
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Set Software-written Data Register
-	 */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_SWD_OFFSET,
-								SwData);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns contents of Software-written Data Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	SwData.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr)
-{
-	 u32 SwData;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Set Metric Selector Register
-	 */
-	SwData = (u32)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-						XAPM_SWD_OFFSET);
-	return SwData;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables the following in the AXI Performance Monitor:
-*   - Event logging
-*
-* @param        InstancePtr is a pointer to the XAxiPmon instance.
-* @param        FlagEnables is a value to write to the flag enables
-*               register defined by XAPM_FEC_OFFSET. It is recommended
-*               to use the XAPM_FEC_*_MASK mask bits to generate.
-*               A value of 0x0 will disable all events to the event
-*               log streaming FIFO.
-*
-* @return       XST_SUCCESS
-*
-* @note         None
-*
-******************************************************************************/
-s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables)
-{
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
-				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-			(InstancePtr->Config.IsEventLog == 1U)));
-
-	/* Read current register value */
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-	/* Flag Enable register is present only in Advanced Mode */
-	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
-	{
-		/* Now write to flag enables register */
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-				(u32)XAPM_FEC_OFFSET, FlagEnables);
-	}
-
-	/* Write the new value to the Control register to
-	 *	enable event logging */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
-		                  RegValue | XAPM_CR_EVENTLOG_ENABLE_MASK);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function disables the following in the AXI Performance Monitor:
-*   - Event logging
-*
-* @param        InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return       XST_SUCCESS
-*
-* @note         None
-*
-******************************************************************************/
-s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr)
-{
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
-			((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-			(InstancePtr->Config.IsEventLog == 1U)));
-
-	/* Read current register value */
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-						(u32)XAPM_CTL_OFFSET);
-
-	/* Write the new value to the Control register to disable
-	 * event logging */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
-	                    RegValue & ~XAPM_CR_EVENTLOG_ENABLE_MASK);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables the following in the AXI Performance Monitor:
-*   - Global clock counter
-*   - All metric counters
-*   - All sampled metric counters
-*
-* @param    InstancePtr is a pointer to the XAxiPmon instance.
-*           SampleInterval is the sample interval for the sampled metric
-*           counters
-*
-* @return   XST_SUCCESS
-*
-* @note	    None
-******************************************************************************/
-s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval)
-{
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
-				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U)));
-
-	/* Read current register value */
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-	/* Globlal Clock Counter is present in Advanced mode only */
-	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
-	{
-		RegValue = RegValue | XAPM_CR_GCC_ENABLE_MASK;
-	}
-
-	/*
-	 * Write the new value to the Control register to enable
-	 * global clock counter and metric counters
-	 */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
-              RegValue | XAPM_CR_MCNTR_ENABLE_MASK);
-
-	/* Set, enable, and load sampled counters */
-	XAxiPmon_SetSampleInterval(InstancePtr, SampleInterval);
-	XAxiPmon_LoadSampleIntervalCounter(InstancePtr);
-	XAxiPmon_EnableSampleIntervalCounter(InstancePtr);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function disables the following in the AXI Performance Monitor:
-*   - Global clock counter
-*   - All metric counters
-*
-* @param        InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return       XST_SUCCESS
-*
-* @note         None
-*
-******************************************************************************/
-s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr)
-{
-	u32 RegValue;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
-				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U)));
-
-	/* Read current register value */
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-	/* Globlal Clock Counter is present in Advanced mode only */
-	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
-	{
-		RegValue = RegValue & ~XAPM_CR_GCC_ENABLE_MASK;
-	}
-
-	/*
-	 * Write the new value to the Control register to disable
-	 * global clock counter and metric counters
-	 */
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
-			RegValue & ~XAPM_CR_MCNTR_ENABLE_MASK);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables Metric Counters.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		None
-*
-*******************************************************************************/
-void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
-				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U)));
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-						XAPM_CTL_OFFSET);
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-					RegVal | XAPM_CR_MCNTR_ENABLE_MASK);
-}
-/****************************************************************************/
-/**
-*
-* This function disables the Metric Counters.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		None
-*
-*****************************************************************************/
-void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
-				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U)));
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
-					RegVal & ~(XAPM_CR_MCNTR_ENABLE_MASK));
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Upper and Lower Ranges for specified Metric Counter
-* Log Enable Register.Event Logging starts when corresponding Metric Counter
-* value falls in between these ranges
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	CounterNum is the Metric Counter number for which
-*		Ranges are to be assigned.Use the XAPM_METRIC_COUNTER*
-*		defines for the counter number in xaxipmon.h.
-*		The valid values are 0 (XAPM_METRIC_COUNTER_0) to
-*		9 (XAPM_METRIC_COUNTER_9).
-* @param 	RangeUpper specifies the Upper limit in 32 bit Register
-* @param 	RangeLower specifies the Lower limit in 32 bit Register
-* @return	None
-*
-* @note		None.
-*
-*****************************************************************************/
-void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
-					u16 RangeUpper, u16 RangeLower)
-{
-	u32 RegValue;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS);
-	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U));
-
-
-	/*
-	 * Write the specified Ranges to corresponding Metric Counter Log
-	 * Enable Register
-	 */
-	RegValue = (u32)RangeUpper << 16;
-	RegValue |= RangeLower;
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16)), RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the Ranges of specified Metric Counter Log
-* Enable Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	CounterNum is the Metric Counter number for which
-*		Ranges are to be returned.Use the XAPM_METRIC_COUNTER*
-*		defines for the counter number in xaxipmon.h.
-*		The valid values are 0 (XAPM_METRIC_COUNTER_0) to
-*		9 (XAPM_METRIC_COUNTER_9).
-*
-* @param 	RangeUpper specifies the user reference variable which returns
-*		the Upper Range Value of the specified Metric Counter
-*		Log Enable Register.
-* @param 	RangeLower specifies the user reference variable which returns
-*		the Lower Range Value of the specified Metric Counter
-*		Log Enable Register.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
-					u16 *RangeUpper, u16 *RangeLower)
-{
-	u32 RegValue;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS);
-	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventCount == 1U));
-
-
-	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-				((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16)));
-
-	*RangeLower = (u16)RegValue & 0xFFFFU;
-	*RangeUpper = (u16)(RegValue >> 16) & 0xFFFFU;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables Event Logging.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		None
-*
-*******************************************************************************/
-void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
-				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
-				(InstancePtr->Config.IsEventLog == 1U)));
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				RegVal | XAPM_CR_EVENTLOG_ENABLE_MASK);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables External trigger pulse so that Metric Counters can be
-* started on external trigger pulse for a Slot.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		None
-*
-*******************************************************************************/
-void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				RegVal | XAPM_CR_MCNTR_EXTTRIGGER_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the External trigger pulse used to start Metric
-* Counters on external trigger pulse for a Slot.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		None
-*
-*****************************************************************************/
-void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				RegVal & ~(XAPM_CR_MCNTR_EXTTRIGGER_MASK));
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables External trigger pulse for Event Log
-* so that Event Logging can be started on external trigger pulse for a Slot.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		None
-*
-*******************************************************************************/
-void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				RegVal | XAPM_CR_EVTLOG_EXTTRIGGER_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the External trigger pulse used to start Event
-* Log on external trigger pulse for a Slot.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		None
-*
-*****************************************************************************/
-void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-
-	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
-				RegVal & ~(XAPM_CR_EVTLOG_EXTTRIGGER_MASK));
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns a name for a given Metric.
-*
-* @param        Metrics is one of the Metric Sets. User has to use
-*               XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter
-*
-* @return       const char *
-*
-* @note         None
-*
-*****************************************************************************/
-const char * XAxiPmon_GetMetricName(u8 Metrics)
-{
-	if (Metrics == XAPM_METRIC_SET_0 ){
-		return "Write Transaction Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_1 ){
-			return "Read Transaction Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_2 ){
-			return "Write Byte Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_3 ){
-			return "Read Byte Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_4 ){
-			return "Write Beat Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_5 ){
-			return "Total Read Latency";
-	}
-	if (Metrics == XAPM_METRIC_SET_6 ){
-			return "Total Write Latency";
-	}
-	if (Metrics == XAPM_METRIC_SET_7 ){
-		return "Slv_Wr_Idle_Cnt";
-	}
-	if (Metrics == XAPM_METRIC_SET_8 ){
-			return "Mst_Rd_Idle_Cnt";
-	}
-	if (Metrics == XAPM_METRIC_SET_9 ){
-			return "Num_BValids";
-	}
-	if (Metrics == XAPM_METRIC_SET_10){
-		return "Num_WLasts";
-	}
-	if (Metrics == XAPM_METRIC_SET_11){
-			return "Num_RLasts";
-	}
-	if (Metrics == XAPM_METRIC_SET_12){
-			return "Minimum Write Latency";
-	}
-	if (Metrics == XAPM_METRIC_SET_13){
-			return "Maximum Write Latency";
-	}
-	if (Metrics == XAPM_METRIC_SET_14){
-			return "Minimum Read Latency";
-	}
-	if (Metrics == XAPM_METRIC_SET_15){
-			return "Maximum Read Latency";
-	}
-	if (Metrics == XAPM_METRIC_SET_16){
-			return "Transfer Cycle Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_17){
-			return "Packet Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_18){
-			return "Data Byte Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_19){
-			return "Position Byte Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_20){
-			return "Null Byte Count";
-	}
-	if (Metrics == XAPM_METRIC_SET_21){
-			return "Slv_Idle_Cnt";
-	}
-	if (Metrics == XAPM_METRIC_SET_22){
-			return "Mst_Idle_Cnt";
-	}
-	if (Metrics == XAPM_METRIC_SET_30){
-			return "External event count";
-	}
-	return "Unsupported";
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets Write ID in ID register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	WriteId is the Write ID to be written in ID register.
-*
-* @return	None.
-*
-* @note
-*			If ID filtering for write is of 32 bits(for Zynq MP APM) width then
-*			WriteID is written to XAPM_ID_OFFSET or if it is 16 bit width
-*			then lower 16 bits of WriteID are written to XAPM_ID_OFFSET.
-*
-*****************************************************************************/
-void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId)
-{
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_ID_OFFSET);
-		RegVal = RegVal & ~(XAPM_ID_WID_MASK);
-		RegVal = RegVal | WriteId;
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_ID_OFFSET, RegVal);
-	} else {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_ID_OFFSET, WriteId);
-	}
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets Read ID in ID register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	ReadId is the Read ID to be written in ID register.
-*
-* @return	None.
-*
-* @note
-*			If ID filtering for read is of 32 bits(for Zynq MP APM) width then
-*			ReadId is written to XAPM_RID_OFFSET or if it is 16 bit width
-*			then lower 16 bits of ReadId are written to XAPM_ID_OFFSET.
-*
-*****************************************************************************/
-void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId)
-{
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_ID_OFFSET);
-		RegVal = RegVal & ~(XAPM_ID_RID_MASK);
-		RegVal = RegVal | (ReadId << 16);
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_ID_OFFSET, RegVal);
-	} else {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_RID_OFFSET, ReadId);
-	}
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns Write ID in ID register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	WriteId is the required Write ID in ID register.
-*
-* @note		None.
-*			If ID filtering for write is of 32 bits(for Zynq MP APM) width then
-*			32 bit XAPM_ID_OFFSET contents are returned or if it is 16 bit
-*			width then lower 16 bits of XAPM_ID_OFFSET register are returned.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr)
-{
-
-	u32 WriteId;
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_ID_OFFSET);
-		WriteId = RegVal & XAPM_ID_WID_MASK;
-	} else {
-		WriteId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_ID_OFFSET);
-	}
-
-	return WriteId;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns Read ID in ID register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	ReadId is the required Read ID in ID register.
-*
-* @note		None.
-*			If ID filtering for write is of 32 bits(for Zynq MP APM) width then
-*			32 bit XAPM_RID_OFFSET contents are returned or if it is 16 bit
-*			width then higher 16 bits of XAPM_ID_OFFSET register are returned.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr)
-{
-
-	u32 ReadId;
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_ID_OFFSET);
-		RegVal = RegVal & XAPM_ID_RID_MASK;
-		ReadId = RegVal >> 16;
-	} else {
-		ReadId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_RID_OFFSET);
-	}
-
-	return ReadId;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets Latency Start point to calculate write latency.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT
-*		in xaxipmon.h.
-* @return	None
-*
-* @note		Param can be 0 - XAPM_LATENCY_ADDR_ISSUE
-*		or 1 - XAPM_LATENCY_ADDR_ACCEPT
-*
-*******************************************************************************/
-void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-	if (Param == XAPM_LATENCY_ADDR_ACCEPT) {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_START_MASK);
-	}
-	else {
-		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET,
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_START_MASK));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets Latency End point to calculate write latency.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Param is XAPM_LATENCY_LASTWR or XAPM_LATENCY_FIRSTWR
-* 		in xaxipmon.h.
-*
-* @return	None
-*
-* @note		Param can be 0 - XAPM_LATENCY_LASTWR
-*		or 1 - XAPM_LATENCY_FIRSTWR
-*
-*******************************************************************************/
-void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-	if (Param == XAPM_LATENCY_FIRSTWR) {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_END_MASK);
-	}
-	else {
-		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET,
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_END_MASK));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets Latency Start point to calculate read latency.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT
-*		in xaxipmon.h.
-*
-* @return	None
-*
-* @note		Param can be 0 - XAPM_LATENCY_ADDR_ISSUE
-*		or 1 - XAPM_LATENCY_ADDR_ACCEPT
-*
-*******************************************************************************/
-void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-	if (Param == XAPM_LATENCY_ADDR_ACCEPT) {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_START_MASK);
-	}
-	else {
-		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET,
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_START_MASK));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets Latency End point to calculate read latency.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Param is XAPM_LATENCY_LASTRD or XAPM_LATENCY_FIRSTRD
-* 		in xaxipmon.h.
-*
-* @return	None
-*
-* @note		Param can be 0 - XAPM_LATENCY_LASTRD
-*		or 1 - XAPM_LATENCY_FIRSTRD
-*
-*******************************************************************************/
-void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param)
-{
-	u32 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_CTL_OFFSET);
-	if (Param == XAPM_LATENCY_FIRSTRD) {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_END_MASK);
-	}
-	else {
-		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET,
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
-			XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_END_MASK));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns Write Latency Start point.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	Returns 0 - XAPM_LATENCY_ADDR_ISSUE or
-*			1 - XAPM_LATENCY_ADDR_ACCEPT
-*
-* @note		None
-*
-*******************************************************************************/
-u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr)
-{
-	u8 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-	RegVal = RegVal & XAPM_CR_WRLATENCY_START_MASK;
-	if (RegVal != XAPM_LATENCY_ADDR_ISSUE) {
-		return (u8)XAPM_LATENCY_ADDR_ACCEPT;
-	}
-	else {
-		return (u8)XAPM_LATENCY_ADDR_ISSUE;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns Write Latency End point.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	Returns 0 - XAPM_LATENCY_LASTWR or
-*			1 - XAPM_LATENCY_FIRSTWR.
-*
-* @note		None
-*
-*******************************************************************************/
-u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr)
-{
-	u8 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-	RegVal = RegVal & XAPM_CR_WRLATENCY_END_MASK;
-	if (RegVal != XAPM_LATENCY_LASTWR) {
-		return (u8)XAPM_LATENCY_FIRSTWR;
-	}
-	else {
-		return (u8)XAPM_LATENCY_LASTWR;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns read Latency Start point.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	Returns 0 - XAPM_LATENCY_ADDR_ISSUE or
-*			1 - XAPM_LATENCY_ADDR_ACCEPT
-*
-* @note		None
-*
-*******************************************************************************/
-u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr)
-{
-	u8 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-	RegVal = RegVal & XAPM_CR_RDLATENCY_START_MASK;
-
-	if (RegVal != XAPM_LATENCY_ADDR_ISSUE) {
-		return	(u8)XAPM_LATENCY_ADDR_ACCEPT;
-	}
-	else {
-		return (u8)XAPM_LATENCY_ADDR_ISSUE;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns Read Latency End point.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	Returns 0 - XAPM_LATENCY_LASTRD or
-*			1 - XAPM_LATENCY_FIRSTRD.
-*
-* @note		None
-*
-*******************************************************************************/
-u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr)
-{
-	u8 RegVal;
-
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							(u32)XAPM_CTL_OFFSET);
-	RegVal = RegVal & XAPM_CR_RDLATENCY_END_MASK;
-	if (RegVal != XAPM_LATENCY_LASTRD) {
-		return (u8)XAPM_LATENCY_FIRSTRD;
-	}
-	else {
-		return (u8)XAPM_LATENCY_LASTRD;
-	}
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets Write ID Mask in ID Mask register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	WrMask is the Write ID mask to be written in ID register.
-*
-* @return	None.
-*
-* @note
-*			If ID masking for write is of 32 bits(for Zynq MP APM) width then
-*			WrMask is written to XAPM_IDMASK_OFFSET or if it is 16 bit width
-*			then lower 16 bits of WrMask are written to XAPM_IDMASK_OFFSET.
-*
-*****************************************************************************/
-void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask)
-{
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_IDMASK_OFFSET);
-		RegVal = RegVal & ~(XAPM_MASKID_WID_MASK);
-		RegVal = RegVal | WrMask;
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-							XAPM_IDMASK_OFFSET, RegVal);
-	} else {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-							XAPM_IDMASK_OFFSET, WrMask);
-	}
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets Read ID Mask in ID Mask register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	RdMask is the Read ID mask to be written in ID Mask register.
-*
-* @return	None.
-*
-* @note
-*			If ID masking for read is of 32 bits(for Zynq MP APM) width then
-*			RdMask is written to XAPM_RIDMASK_OFFSET or if it is 16 bit width
-*			then lower 16 bits of RdMask are written to XAPM_IDMASK_OFFSET.
-*
-*****************************************************************************/
-void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask)
-{
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_IDMASK_OFFSET);
-		RegVal = RegVal & ~(XAPM_MASKID_RID_MASK);
-		RegVal = RegVal | (RdMask << 16);
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_IDMASK_OFFSET, RegVal);
-	} else {
-		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
-					XAPM_RIDMASK_OFFSET, RdMask);
-	}
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns Write ID Mask in ID Mask register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	WrMask is the required Write ID Mask in ID Mask register.
-*
-* @note
-*			If ID masking for write is of 32 bits(for Zynq MP APM) width then
-*			32 bit XAPM_IDMASK_OFFSET contents are returned or if it is 16 bit
-*			width then lower 16 bits of XAPM_IDMASK_OFFSET register
-*			are returned.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr)
-{
-
-	u32 WrMask;
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_IDMASK_OFFSET);
-		WrMask = RegVal & XAPM_MASKID_WID_MASK;
-	} else {
-		WrMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_IDMASK_OFFSET);
-	}
-
-	return WrMask;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns Read ID Mask in ID Mask register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	RdMask is the required Read ID Mask in ID Mask register.
-*
-* @note
-*			If ID masking for read is of 32 bits(for Zynq MP APM) width then
-*			32 bit XAPM_RIDMASK_OFFSET contents are returned or if it is 16 bit
-*			width then higher 16 bits of XAPM_IDMASK_OFFSET register
-*			are returned.
-*
-*****************************************************************************/
-u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr)
-{
-
-	u32 RdMask;
-	u32 RegVal;
-	/*
-	 * Assert the arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->Config.Is32BitFiltering == 0U)
-	{
-		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-							XAPM_IDMASK_OFFSET);
-		RegVal = RegVal & XAPM_MASKID_RID_MASK;
-		RdMask = RegVal >> 16;
-	} else {
-		RdMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
-								XAPM_RIDMASK_OFFSET);
-	}
-
-	return RdMask;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h
deleted file mode 100644
index f8d4d6467..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h
+++ /dev/null
@@ -1,938 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2007 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xaxipmon.h
-* @addtogroup axipmon_v6_3
-* @{
-* @details
-*
-* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device.
-*
-* The AXI Performance Monitor device provides following features:
-*
-*	Configurable number of Metric Counters and Incrementers
-* 	Computes performance metrics for Agents connected to
-*	monitor slots (Up to 8 slots)
-*
-* The following Metrics can be computed:
-*
-* Metrics computed for an AXI4 MM agent:
-*	Write Request Count: Total number of write requests by/to the agent.
-*	Read Request Count: Total number of read requests given by/to the
-*			    agent.
-*	Read Latency: It is defined as the time from the start of read address
-*       	      transaction to the beginning of the read data service.
-*	Write Latency: It is defined as the period needed a master completes
-*        	       write data transaction, i.e. from write address
-*        	       transaction to write response from slave.
-*	Write Byte Count: Total number of bytes written by/to the agent.
-*        		  This metric is helpful when calculating the
-*        		  throughput of the system.
-*	Read Byte Count: Total number of bytes read from/by the agent.
-*	Average Write Latency: Average write latency seen by the agent.
-*        		       It can be derived from total write latency
-*        		       and the write request count.
-*	Average Read Latency: Average read latency seen by the agent. It can be
-*        		      derived from total read latency and the read
-*        		      request count.
-*	Master Write Idle Cycle Count: Number of idle cycles caused by the
-*        			       masters during write transactions to
-*        			       the slave.
-*	Slave Write Idle Cycle Count: Number of idle cycles caused by this slave
-*        			      during write transactions to the slave.
-*	Master Read Idle Cycle Count: Number of idle cycles caused by the
-*        			      master during read transactions to the
-*        			      slave.
-*	Slave Read Idle Cycle Count: Number of idle cycles caused by this slave
-*        			     during read transactions to the slave.
-*
-* Metrics computed for an AXI4-Stream agent:
-*
-*	Transfer Cycle Count: Total number of writes by/to the agent.
-*	Data Byte Count: Total number of data bytes written by/to the agent.
-*			 This metric helps in calculating the throughput
-*			 of the system.
-*	Position Byte Count: Total number of position bytes transferred.
-*	Null Byte Count: Total number of null bytes transferred.
-*	Packet Count: Total number of packets transferred.
-*
-* There are three modes : Advanced, Profile and Trace.
-* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors
-*   and Sampled Incrementors.
-* - Profile mode has only 47 Metric Counters and Sampled Metric Counters.
-* - Trace mode has no Counters.
-* User should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the AXI Performance Monitor device.
-*
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the AXI Performance Monitor device.
-*
-* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor
-* device. The user needs to first call the XAxiPmon_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XAxiPmon_CfgInitialize() API.
-*
-*
-* <b>Interrupts</b>
-*
-* The AXI Performance Monitor does not support Interrupts
-*
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* <b> Building the driver </b>
-*
-* The XAxiPmon driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <b> Limitations of the driver </b>
-*
-*
-* <br><br>
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.00a bss    02/27/12 First release
-* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
-* 3.00a bss    09/03/12 To support v2_01_a version of IP:
-*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
-*			added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
-*			XAPM_FLAG_EVNTSTOP.
-*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
-*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
-*			in xaxipmon.c
-*			Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
-* 3.01a bss    10/25/12 To support new version of IP:
-*			Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
-*			Added XAxiPmon_SetMetricCounterCutOff,
-*			XAxiPmon_GetMetricCounterCutOff,
-*			XAxiPmon_EnableExternalTrigger and
-*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
-*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
-*			(CR #683746) in xaxipmon.c
-*			Added XAxiPmon_EnableEventLog,
-*			XAxiPmon_DisableMetricsCounter,
-*			XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
-*			replace macros in this file.
-*			Added XAPM_FLAG_XXX macros.
-*			Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
-*			APIs (CR #683799).
-*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
-*			APIs (CR #683801).
-*			Added XAxiPmon_GetMetricName API (CR #683803).
-*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
-*			declarations (CR #677337)
-* 4.00a bss    01/17/13 To support new version of IP:
-*			Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
-*			Added XAxiPmon_SetLogEnableRanges,
-*	  		XAxiPmon_GetLogEnableRanges,
-*			XAxiPmon_EnableMetricCounterTrigger,
-*			XAxiPmon_DisableMetricCounterTrigger,
-*			XAxiPmon_EnableEventLogTrigger,
-*			XAxiPmon_DisableEventLogTrigger,
-*			XAxiPmon_SetWriteLatencyId,
-*			XAxiPmon_SetReadLatencyId,
-*			XAxiPmon_GetWriteLatencyId,
-*			XAxiPmon_GetReadLatencyId APIs and removed
-*			XAxiPmon_SetMetricCounterCutOff,
-*			XAxiPmon_GetMetricCounterCutOff,
-*			XAxiPmon_EnableExternalTrigger and
-*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
-*			Added XAPM_LATENCYID_OFFSET,
-*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
-*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
-*			xaxipmon_hw.h
-* 5.00a bss   08/26/13  To support new version of IP:
-*			XAxiPmon_SampleMetrics Macro.
-*			Modified XAxiPmon_CfgInitialize, Assert functions
-*			Added XAxiPmon_GetMetricCounter,
-*			XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
-*			XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
-*			XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
-*			XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
-*			XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
-*			XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
-*			XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
-*			Renamed :
-*			XAxiPmon_SetWriteLatencyId to
-*			XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
-*			XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
-*			XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
-*			XAxiPmon_GetReadId. in xaxipmon.c
-*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
-*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
-*			XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
-*			XAPM_CR_WRLATENCY_START_MASK,
-*			XAPM_CR_WRLATENCY_END_MASK,
-*			XAPM_CR_RDLATENCY_START_MASK,
-*			XAPM_CR_RDLATENCY_END_MASK and
-*			XAPM_MAX_COUNTERS_PROFILE.
-*			Renamed:
-*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
-*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
-*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
-*			in xaxipmon_hw.h.
-*			Modified driver tcl to generate new parameters
-*			ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
-*			in Config structure.
-* 6.0   adk  19/12/13 Updated as per the New Tcl API's
-* 6.1   adk  16/04/14 Updated the driver tcl for the newly added parameters in
-* 		      The Axi pmon IP.
-* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
-*			counters and FIFOs based on Modes(CR#782671). And if
-*			both profile and trace modes are present set mode as
-*			Advanced.
-* 6.2	bss  03/02/15	To support Zynq MP APM:
-*						Added Is32BitFiltering in XAxiPmon_Config structure.
-*						Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
-*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
-*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
-*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
-*						functions in xaxipmon.c.
-*						Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
-*						xaxipmon_hw.h
-*
-* 6.3	kvn  07/02/15	Modified code according to MISRA-C:2012 guidelines.
-* 6.4   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
-*                     Changed the prototype of XAxiPmon_CfgInitialize API.
-* </pre>
-*
-*****************************************************************************/
-#ifndef XAXIPMON_H /* Prevent circular inclusions */
-#define XAXIPMON_H /* by using protection macros  */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xaxipmon_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Macro for Maximum number of Counters
- *
- * @{
- */
-#define XAPM_MAX_COUNTERS		10U /**< Maximum number of Counters */
-#define XAPM_MAX_COUNTERS_PROFILE	48U /**< Maximum number of Counters */
-
-/*@}*/
-
-
-/**
- * @name Indices for Metric Counters and Sampled Metric Coounters used with
- * 	 XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs
- * @{
- */
-
-#define XAPM_METRIC_COUNTER_0	0U /**< Metric Counter 0 Register Index */
-#define XAPM_METRIC_COUNTER_1	1U /**< Metric Counter 1 Register Index */
-#define XAPM_METRIC_COUNTER_2	2U /**< Metric Counter 2 Register Index */
-#define XAPM_METRIC_COUNTER_3	3U /**< Metric Counter 3 Register Index */
-#define XAPM_METRIC_COUNTER_4	4U /**< Metric Counter 4 Register Index */
-#define XAPM_METRIC_COUNTER_5	5U /**< Metric Counter 5 Register Index */
-#define XAPM_METRIC_COUNTER_6	6U /**< Metric Counter 6 Register Index */
-#define XAPM_METRIC_COUNTER_7	7U /**< Metric Counter 7 Register Index */
-#define XAPM_METRIC_COUNTER_8	8U /**< Metric Counter 8 Register Index */
-#define XAPM_METRIC_COUNTER_9	9U /**< Metric Counter 9 Register Index */
-
-/*@}*/
-
-/**
- * @name Indices for Incrementers and Sampled Incrementers used with
- * 	 XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs
- * @{
- */
-
-#define XAPM_INCREMENTER_0	0U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_1	1U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_2	2U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_3	3U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_4	4U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_5	5U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_6	6U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_7	7U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_8	8U /**< Metric Counter 0 Register Index */
-#define XAPM_INCREMENTER_9	9U /**< Metric Counter 0 Register Index */
-
-/*@}*/
-
-/**
- * @name Macros for Metric Selector Settings
- * @{
- */
-
-#define XAPM_METRIC_SET_0		0U /**< Write Transaction Count */
-#define XAPM_METRIC_SET_1		1U /**< Read Transaction Count */
-#define XAPM_METRIC_SET_2		2U /**< Write Byte Count */
-#define XAPM_METRIC_SET_3		3U /**< Read Byte Count */
-#define XAPM_METRIC_SET_4		4U /**< Write Beat Count */
-#define XAPM_METRIC_SET_5		5U /**< Total Read Latency */
-#define XAPM_METRIC_SET_6		6U /**< Total Write Latency */
-#define XAPM_METRIC_SET_7		7U /**< Slv_Wr_Idle_Cnt */
-#define XAPM_METRIC_SET_8		8U /**< Mst_Rd_Idle_Cnt */
-#define XAPM_METRIC_SET_9		9U /**< Num_BValids */
-#define XAPM_METRIC_SET_10		10U /**< Num_WLasts */
-#define XAPM_METRIC_SET_11		11U /**< Num_RLasts */
-#define XAPM_METRIC_SET_12		12U /**< Minimum Write Latency */
-#define XAPM_METRIC_SET_13		13U /**< Maximum Write Latency */
-#define XAPM_METRIC_SET_14		14U /**< Minimum Read Latency */
-#define XAPM_METRIC_SET_15		15U /**< Maximum Read Latency */
-#define XAPM_METRIC_SET_16		16U /**< Transfer Cycle Count */
-#define XAPM_METRIC_SET_17		17U /**< Packet Count */
-#define XAPM_METRIC_SET_18		18U /**< Data Byte Count */
-#define XAPM_METRIC_SET_19		19U /**< Position Byte Count */
-#define XAPM_METRIC_SET_20		20U /**< Null Byte Count */
-#define XAPM_METRIC_SET_21		21U /**< Slv_Idle_Cnt */
-#define XAPM_METRIC_SET_22		22U /**< Mst_Idle_Cnt */
-#define XAPM_METRIC_SET_30		30U /**< External event count */
-
-
-/*@}*/
-
-
-/**
- * @name Macros for Maximum number of Agents
- * @{
- */
-
-#define XAPM_MAX_AGENTS 	8U /**< Maximum number of Agents */
-
-/*@}*/
-
-/**
- * @name Macros for Flags in Flag Enable Control Register
- * @{
- */
-
-#define XAPM_FLAG_WRADDR	0x00000001 /**< Write Address Flag */
-#define XAPM_FLAG_FIRSTWR	0x00000002 /**< First Write Flag */
-#define XAPM_FLAG_LASTWR	0x00000004 /**< Last Write Flag */
-#define XAPM_FLAG_RESPONSE	0x00000008 /**< Response Flag */
-#define XAPM_FLAG_RDADDR	0x00000010 /**< Read Address Flag */
-#define XAPM_FLAG_FIRSTRD	0x00000020 /**< First Read Flag */
-#define XAPM_FLAG_LASTRD	0x00000040 /**< Last Read Flag */
-#define XAPM_FLAG_SWDATA	0x00010000 /**< Software-written Data Flag */
-#define XAPM_FLAG_EVENT		0x00020000 /**< Last Read Flag */
-#define XAPM_FLAG_EVNTSTOP	0x00040000 /**< Last Read Flag */
-#define XAPM_FLAG_EVNTSTART	0x00080000 /**< Last Read Flag */
-#define XAPM_FLAG_GCCOVF	0x00100000 /**< Global Clock Counter Overflow
-					     *  Flag */
-#define XAPM_FLAG_SCLAPSE	0x00200000 /**< Sample Counter Lapse Flag */
-#define XAPM_FLAG_MC0		0x00400000U /**< Metric Counter 0 Flag */
-#define XAPM_FLAG_MC1		0x00800000U /**< Metric Counter 1 Flag */
-#define XAPM_FLAG_MC2		0x01000000U /**< Metric Counter 2 Flag */
-#define XAPM_FLAG_MC3		0x02000000U /**< Metric Counter 3 Flag */
-#define XAPM_FLAG_MC4		0x04000000U /**< Metric Counter 4 Flag */
-#define XAPM_FLAG_MC5		0x08000000U /**< Metric Counter 5 Flag */
-#define XAPM_FLAG_MC6		0x10000000U /**< Metric Counter 6 Flag */
-#define XAPM_FLAG_MC7		0x20000000U /**< Metric Counter 7 Flag */
-#define XAPM_FLAG_MC8		0x40000000U /**< Metric Counter 8 Flag */
-#define XAPM_FLAG_MC9		0x80000000U /**< Metric Counter 9 Flag */
-
-/*@}*/
-
-/**
- * @name Macros for Read/Write Latency Start and End points
- * @{
- */
-#define XAPM_LATENCY_ADDR_ISSUE		0U /**< Address Issue as start
-					point for Latency calculation*/
-#define XAPM_LATENCY_ADDR_ACCEPT	1U /**< Address Acceptance as start
-					point for Latency calculation*/
-#define XAPM_LATENCY_LASTRD		0U /**< Last Read as end point for
-					Latency calculation */
-#define XAPM_LATENCY_LASTWR		0U /**< Last Write as end point for
-					Latency calculation */
-#define XAPM_LATENCY_FIRSTRD		1U /**< First Read as end point for
-					Latency calculation */
-#define XAPM_LATENCY_FIRSTWR		1U /**< First Write as end point for
-					Latency calculation */
-
-/*@}*/
-
-/**
- * @name Macros for Modes of APM
- * @{
- */
-
-#define XAPM_MODE_TRACE			2U /**< APM in Trace mode */
-
-#define XAPM_MODE_PROFILE		1U /**< APM in Profile mode */
-
-#define XAPM_MODE_ADVANCED		0U /**< APM in Advanced mode */
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the AXI Performance
- * Monitor device.
- */
-typedef struct {
-	u16 DeviceId;			/**< Unique ID of device */
-	UINTPTR BaseAddress;		/**< Device base address */
-	s32 GlobalClkCounterWidth;	/**< Global Clock Counter Width */
-	s32 MetricSampleCounterWidth ;	/**< Metric Sample Counters Width */
-	u8  IsEventCount;		/**< Event Count Enabled 1 - enabled
-							   0 - not enabled */
-	u8  NumberofSlots;		/**< Number of Monitor Slots */
-	u8  NumberofCounters;		/**< Number of Counters */
-	u8  HaveSampledCounters;	/**< Have Sampled Counters 1 - present
-							    0 - Not present */
-	u8 IsEventLog;			/**< Event Logging Enabled 1 - enabled
-							    0 - Not enabled */
-	u32 FifoDepth;			/**< Event Log FIFO Depth */
-	u32 FifoWidth;			/**< Event Log FIFO Width */
-	u32 TidWidth; 			/**< Streaming Interface TID Width */
-	u8  ScaleFactor;		/**< Event Count Scaling factor */
-	u8  ModeAdvanced;		/**< Advanced Mode */
-	u8  ModeProfile;		/**< Profile Mode */
-	u8  ModeTrace;			/**< Trace Mode */
-	u8  Is32BitFiltering;   /**< 32 bit filtering enabled */
-} XAxiPmon_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every AXI Performance Monitor device in system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XAxiPmon_Config Config;	/**< XAxiPmon_Config of current device */
-	u32  IsReady;		/**< Device is initialized and ready  */
-	u8   Mode;		/**< APM Mode */
-} XAxiPmon;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/****************************************************************************/
-/**
-*
-* This routine enables the Global Interrupt.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_IntrGlobalEnable(InstancePtr)			\
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, 	\
-			XAPM_GIE_OFFSET, 1)
-
-
-/****************************************************************************/
-/**
-*
-* This routine disables the Global Interrupt.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_IntrGlobalDisable(InstancePtr)				\
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, 		\
-				XAPM_GIE_OFFSET, 0)
-
-
-/****************************************************************************/
-/**
-*
-* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in
-* xaxipmon_hw.h to create the bit-mask to enable interrupts.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Mask is the mask to enable. Bit positions of 1 will be enabled.
-*		Bit positions of 0 will keep the previous setting. This mask is
-*		formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XAxiPmon_IntrEnable(InstancePtr, Mask)				     \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_IE_OFFSET) | (Mask));
-
-
-/****************************************************************************/
-/**
-*
-* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in
-* xaxipmon_hw.h to create the bit-mask to disable interrupts.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Mask is the mask to disable. Bit positions of 1 will be
-*		disabled. Bit positions of 0 will keep the previous setting.
-*		This mask is formed by OR'ing XAPM_IXR_* bits defined in
-*		xaxipmon_hw.h.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XAxiPmon_IntrDisable(InstancePtr, Mask)				     \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_IE_OFFSET) | (Mask));
-
-/****************************************************************************/
-/**
-*
-* This routine clears the specified interrupt(s).
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param	Mask is the mask to clear. Bit positions of 1 will be cleared.
-*		This mask is formed by OR'ing XAPM_IXR_* bits defined in
-*		xaxipmon_hw.h.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XAxiPmon_IntrClear(InstancePtr, Mask)				     \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_IS_OFFSET) | (Mask));
-
-/****************************************************************************/
-/**
-*
-* This routine returns the Interrupt Status Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	Interrupt Status Register contents
-*
-* @note		C-Style signature:
-*		void XAxiPmon_IntrClear(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_IntrGetStatus(InstancePtr)				     \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_IS_OFFSET);
-
-/****************************************************************************/
-/**
-*
-* This function enables the Global Clock Counter.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK);
-
-/****************************************************************************/
-/**
-*
-* This function disbles the Global Clock Counter.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK));
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified flag in Flag Control Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param 	Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_EnableFlag(InstancePtr, Flag) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_FEC_OFFSET) | (Flag));
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified flag in Flag Control Register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-* @param 	Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_DisableFlag(InstancePtr, Flag) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_FEC_OFFSET) & ~(Flag));
-
-/****************************************************************************/
-/**
-*
-* This function loads the sample interval register value into the sample
-* interval counter.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \
-       XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
-							XAPM_SICR_LOAD_MASK);
-
-
-
-/****************************************************************************/
-/**
-*
-* This enables the down count of the sample interval counter.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*	   void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
-							XAPM_SICR_ENABLE_MASK);
-
-
-/****************************************************************************/
-/**
-*
-* This disables the down count of the sample interval counter.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*	    void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK));
-
-/****************************************************************************/
-/**
-*
-* This enables Reset of Metric Counters when Sample Interval Counter lapses.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
-						XAPM_SICR_MCNTR_RST_MASK);
-
-/****************************************************************************/
-/**
-*
-* This disables the down count of the sample interval counter.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \
-       XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK));
-
-/****************************************************************************/
-/**
-*
-* This function enables the ID Filter Masking.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_EnableIDFilter(InstancePtr) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK);
-
-/****************************************************************************/
-/**
-*
-* This function disbles the ID Filter masking.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_DisableIDFilter(InstancePtr) \
-	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
-			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
-			XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK));
-
-/****************************************************************************/
-/**
-*
-* This function samples Metric Counters to Sampled Metric Counters by
-* reading Sample Register and also returns interval. i.e. the number of
-* clocks in between previous read to the current read of sample register.
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return	Interval. i.e. the number of clocks in between previous
-*		read to the current read of sample register.
-*
-* @note		C-Style signature:
-*		u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr)
-*
-*****************************************************************************/
-#define XAxiPmon_SampleMetrics(InstancePtr) \
-       XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-/**
- * Functions in xaxipmon_sinit.c
- */
-XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xaxipmon.c
- */
-s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr,
-		XAxiPmon_Config *ConfigPtr, UINTPTR EffectiveAddr);
-
-s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr);
-
-void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr);
-
-s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr);
-
-void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
-					u16 RangeUpper,	u16 RangeLower);
-
-void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
-				u16 *RangeUpper, u16 *RangeLower);
-
-void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval);
-
-void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval);
-
-s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
-							u8 CounterNum);
-
-s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
-								u8 *Slot);
-void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
-							u32 *CntLowValue);
-
-u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
-
-u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
-
-u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
-
-u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
-
-void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData);
-
-u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr);
-
-s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables);
-
-s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr);
-
-s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval);
-
-s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr);
-
-void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr);
-
-void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr);
-
-void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
-					u16 RangeUpper, u16 RangeLower);
-
-void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
-					u16 *RangeUpper, u16 *RangeLower);
-
-void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr);
-
-void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr);
-
-void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr);
-
-void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr);
-
-void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr);
-
-const char * XAxiPmon_GetMetricName(u8 Metrics);
-
-void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId);
-
-void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId);
-
-u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr);
-
-u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr);
-
-void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param);
-
-void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
-
-void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param);
-
-void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
-
-u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr);
-
-u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr);
-
-u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr);
-
-u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr);
-
-void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask);
-
-void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask);
-
-u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr);
-
-u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr);
-
-
-/**
- * Functions in xaxipmon_selftest.c
- */
-s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* End of protection macro. */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
deleted file mode 100644
index a33878ef5..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
+++ /dev/null
@@ -1,127 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xaxipmon.h"
-
-/*
-* The configuration table for devices
-*/
-
-XAxiPmon_Config XAxiPmon_ConfigTable[] =
-{
-	{
-		XPAR_PSU_APM_0_DEVICE_ID,
-		XPAR_PSU_APM_0_BASEADDR,
-		XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH,
-		XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH,
-		XPAR_PSU_APM_0_ENABLE_EVENT_COUNT,
-		XPAR_PSU_APM_0_NUM_MONITOR_SLOTS,
-		XPAR_PSU_APM_0_NUM_OF_COUNTERS,
-		XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT,
-		XPAR_PSU_APM_0_ENABLE_EVENT_LOG,
-		XPAR_PSU_APM_0_FIFO_AXIS_DEPTH,
-		XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH,
-		XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH,
-		XPAR_PSU_APM_0_METRIC_COUNT_SCALE,
-		XPAR_PSU_APM_0_ENABLE_ADVANCED,
-		XPAR_PSU_APM_0_ENABLE_PROFILE,
-		XPAR_PSU_APM_0_ENABLE_TRACE,
-		XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID
-	},
-	{
-		XPAR_PSU_APM_1_DEVICE_ID,
-		XPAR_PSU_APM_1_BASEADDR,
-		XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH,
-		XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH,
-		XPAR_PSU_APM_1_ENABLE_EVENT_COUNT,
-		XPAR_PSU_APM_1_NUM_MONITOR_SLOTS,
-		XPAR_PSU_APM_1_NUM_OF_COUNTERS,
-		XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT,
-		XPAR_PSU_APM_1_ENABLE_EVENT_LOG,
-		XPAR_PSU_APM_1_FIFO_AXIS_DEPTH,
-		XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH,
-		XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH,
-		XPAR_PSU_APM_1_METRIC_COUNT_SCALE,
-		XPAR_PSU_APM_1_ENABLE_ADVANCED,
-		XPAR_PSU_APM_1_ENABLE_PROFILE,
-		XPAR_PSU_APM_1_ENABLE_TRACE,
-		XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID
-	},
-	{
-		XPAR_PSU_APM_2_DEVICE_ID,
-		XPAR_PSU_APM_2_BASEADDR,
-		XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH,
-		XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH,
-		XPAR_PSU_APM_2_ENABLE_EVENT_COUNT,
-		XPAR_PSU_APM_2_NUM_MONITOR_SLOTS,
-		XPAR_PSU_APM_2_NUM_OF_COUNTERS,
-		XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT,
-		XPAR_PSU_APM_2_ENABLE_EVENT_LOG,
-		XPAR_PSU_APM_2_FIFO_AXIS_DEPTH,
-		XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH,
-		XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH,
-		XPAR_PSU_APM_2_METRIC_COUNT_SCALE,
-		XPAR_PSU_APM_2_ENABLE_ADVANCED,
-		XPAR_PSU_APM_2_ENABLE_PROFILE,
-		XPAR_PSU_APM_2_ENABLE_TRACE,
-		XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID
-	},
-	{
-		XPAR_PSU_APM_5_DEVICE_ID,
-		XPAR_PSU_APM_5_BASEADDR,
-		XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH,
-		XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH,
-		XPAR_PSU_APM_5_ENABLE_EVENT_COUNT,
-		XPAR_PSU_APM_5_NUM_MONITOR_SLOTS,
-		XPAR_PSU_APM_5_NUM_OF_COUNTERS,
-		XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT,
-		XPAR_PSU_APM_5_ENABLE_EVENT_LOG,
-		XPAR_PSU_APM_5_FIFO_AXIS_DEPTH,
-		XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH,
-		XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH,
-		XPAR_PSU_APM_5_METRIC_COUNT_SCALE,
-		XPAR_PSU_APM_5_ENABLE_ADVANCED,
-		XPAR_PSU_APM_5_ENABLE_PROFILE,
-		XPAR_PSU_APM_5_ENABLE_TRACE,
-		XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h
deleted file mode 100644
index 68ed57aaf..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xaxipmon_hw.h
-* @addtogroup axipmon_v6_3
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the AXI Performance Monitor.
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note	 None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.00a bss    02/27/12 First release
-* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
-* 3.00a bss    09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
-*			v2_01a version of IP.
-* 3.01a bss    10/25/12 To support new version of IP:
-*			Added XAPM_MCXLOGEN_OFFSET and
-*			XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
-* 4.00a bss    01/17/13 To support new version of IP:
-*			Added XAPM_LATENCYID_OFFSET,
-*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
-*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
-* 5.00a bss   08/26/13  To support new version of IP:
-*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
-*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
-*			Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
-*			Added XAPM_CR_IDFILTER_ENABLE_MASK,
-*			XAPM_CR_WRLATENCY_START_MASK,
-*			XAPM_CR_WRLATENCY_END_MASK,
-*			XAPM_CR_RDLATENCY_START_MASK,
-*			XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
-*			and XAPM_MASKID_WID_MASK macros.
-*			Renamed:
-*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
-*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
-*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
-*
-* 6.2  bss  03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
-*					 Zynq MP APM.
-*
-* 6.3  kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
-* </pre>
-*
-*****************************************************************************/
-#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */
-#define XAXIPMON_HW_H /* by using protection macros  */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of AXIMONITOR in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * AXI PERFORMANCE MONITOR device.
- * @{
- */
-
-#define XAPM_GCC_HIGH_OFFSET		0x00000000U	/**< Global Clock Counter
-							32 to 63 bits  */
-#define XAPM_GCC_LOW_OFFSET		0x00000004U	/**< Global Clock Counter Lower
-							0-31 bits  */
-#define XAPM_SI_HIGH_OFFSET		0x00000020U	/**< Sample Interval MSB */
-#define XAPM_SI_LOW_OFFSET		0x00000024U	/**< Sample Interval LSB */
-#define XAPM_SICR_OFFSET		0x00000028U	/**< Sample Interval Control
-							Register */
-#define XAPM_SR_OFFSET			0x0000002CU	/**< Sample Register */
-#define XAPM_GIE_OFFSET			0x00000030U	/**< Global Interrupt Enable
-							Register */
-#define XAPM_IE_OFFSET			0x00000034U	/**< Interrupt Enable Register */
-#define XAPM_IS_OFFSET			0x00000038U	/**< Interrupt Status Register */
-
-#define XAPM_MSR0_OFFSET		0x00000044U	/**< Metric Selector 0 Register */
-#define XAPM_MSR1_OFFSET		0x00000048U	/**< Metric Selector 1 Register */
-#define XAPM_MSR2_OFFSET		0x0000004CU	/**< Metric Selector 2 Register */
-
-#define XAPM_MC0_OFFSET			0x00000100U	/**< Metric Counter 0 Register */
-#define XAPM_INC0_OFFSET		0x00000104U	/**< Incrementer 0 Register */
-#define XAPM_RANGE0_OFFSET		0x00000108U	/**< Range 0 Register */
-#define XAPM_MC0LOGEN_OFFSET		0x0000010CU	/**< Metric Counter 0
-							Log Enable Register */
-#define XAPM_MC1_OFFSET			0x00000110U	/**< Metric Counter 1 Register */
-#define XAPM_INC1_OFFSET		0x00000114U	/**< Incrementer 1 Register */
-#define XAPM_RANGE1_OFFSET		0x00000118U	/**< Range 1 Register */
-#define XAPM_MC1LOGEN_OFFSET		0x0000011CU	/**< Metric Counter 1
-							Log Enable Register */
-#define XAPM_MC2_OFFSET			0x00000120U	/**< Metric Counter 2 Register */
-#define XAPM_INC2_OFFSET		0x00000124U	/**< Incrementer 2 Register */
-#define XAPM_RANGE2_OFFSET		0x00000128U	/**< Range 2 Register */
-#define XAPM_MC2LOGEN_OFFSET		0x0000012CU	/**< Metric Counter 2
-							Log Enable Register */
-#define XAPM_MC3_OFFSET			0x00000130U	/**< Metric Counter 3 Register */
-#define XAPM_INC3_OFFSET		0x00000134U	/**< Incrementer 3 Register */
-#define XAPM_RANGE3_OFFSET		0x00000138U	/**< Range 3 Register */
-#define XAPM_MC3LOGEN_OFFSET		0x0000013CU	/**< Metric Counter 3
-							Log Enable Register */
-#define XAPM_MC4_OFFSET			0x00000140U	/**< Metric Counter 4 Register */
-#define XAPM_INC4_OFFSET		0x00000144U	/**< Incrementer 4 Register */
-#define XAPM_RANGE4_OFFSET		0x00000148U	/**< Range 4 Register */
-#define XAPM_MC4LOGEN_OFFSET		0x0000014CU	/**< Metric Counter 4
-							Log Enable Register */
-#define XAPM_MC5_OFFSET			0x00000150U	/**< Metric Counter 5
-							Register */
-#define XAPM_INC5_OFFSET		0x00000154U	/**< Incrementer 5 Register */
-#define XAPM_RANGE5_OFFSET		0x00000158U	/**< Range 5 Register */
-#define XAPM_MC5LOGEN_OFFSET		0x0000015CU	/**< Metric Counter 5
-							Log Enable Register */
-#define XAPM_MC6_OFFSET			0x00000160U	/**< Metric Counter 6
-							Register */
-#define XAPM_INC6_OFFSET		0x00000164U	/**< Incrementer 6 Register */
-#define XAPM_RANGE6_OFFSET		0x00000168U	/**< Range 6 Register */
-#define XAPM_MC6LOGEN_OFFSET		0x0000016CU	/**< Metric Counter 6
-							Log Enable Register */
-#define XAPM_MC7_OFFSET			0x00000170U	/**< Metric Counter 7
-							Register */
-#define XAPM_INC7_OFFSET		0x00000174U	/**< Incrementer 7 Register */
-#define XAPM_RANGE7_OFFSET		0x00000178U	/**< Range 7 Register */
-#define XAPM_MC7LOGEN_OFFSET		0x0000017CU	/**< Metric Counter 7
-							Log Enable Register */
-#define XAPM_MC8_OFFSET			0x00000180U	/**< Metric Counter 8
-							Register */
-#define XAPM_INC8_OFFSET		0x00000184U	/**< Incrementer 8 Register */
-#define XAPM_RANGE8_OFFSET		0x00000188U	/**< Range 8 Register */
-#define XAPM_MC8LOGEN_OFFSET		0x0000018CU	/**< Metric Counter 8
-							Log Enable Register */
-#define XAPM_MC9_OFFSET			0x00000190U	/**< Metric Counter 9
-							Register */
-#define XAPM_INC9_OFFSET		0x00000194U	/**< Incrementer 9 Register */
-#define XAPM_RANGE9_OFFSET		0x00000198U	/**< Range 9 Register */
-#define XAPM_MC9LOGEN_OFFSET		0x0000019CU	/**< Metric Counter 9
-							Log Enable Register */
-#define XAPM_SMC0_OFFSET		0x00000200U	/**< Sampled Metric Counter
-							0 Register */
-#define XAPM_SINC0_OFFSET		0x00000204U	/**< Sampled Incrementer
-							0 Register */
-#define XAPM_SMC1_OFFSET		0x00000210U	/**< Sampled Metric Counter
-							1 Register */
-#define XAPM_SINC1_OFFSET		0x00000214U	/**< Sampled Incrementer
-							1 Register */
-#define XAPM_SMC2_OFFSET		0x00000220U	/**< Sampled Metric Counter
-							2 Register */
-#define XAPM_SINC2_OFFSET		0x00000224U	/**< Sampled Incrementer
-							2 Register */
-#define XAPM_SMC3_OFFSET		0x00000230U	/**< Sampled Metric Counter
-							3 Register */
-#define XAPM_SINC3_OFFSET		0x00000234U	/**< Sampled Incrementer
-							3 Register */
-#define XAPM_SMC4_OFFSET		0x00000240U	/**< Sampled Metric Counter
-							4 Register */
-#define XAPM_SINC4_OFFSET		0x00000244U	/**< Sampled Incrementer
-							4 Register */
-#define XAPM_SMC5_OFFSET		0x00000250U	/**< Sampled Metric Counter
-							5 Register */
-#define XAPM_SINC5_OFFSET		0x00000254U	/**< Sampled Incrementer
-							5 Register */
-#define XAPM_SMC6_OFFSET		0x00000260U	/**< Sampled Metric Counter
-							6 Register */
-#define XAPM_SINC6_OFFSET		0x00000264U	/**< Sampled Incrementer
-							6 Register */
-#define XAPM_SMC7_OFFSET		0x00000270U	/**< Sampled Metric Counter
-							7 Register */
-#define XAPM_SINC7_OFFSET		0x00000274U	/**< Sampled Incrementer
-							7 Register */
-#define XAPM_SMC8_OFFSET		0x00000280U	/**< Sampled Metric Counter
-							8 Register */
-#define XAPM_SINC8_OFFSET		0x00000284U	/**< Sampled Incrementer
-							8 Register */
-#define XAPM_SMC9_OFFSET		0x00000290U	/**< Sampled Metric Counter
-							9 Register */
-#define XAPM_SINC9_OFFSET		0x00000294U	/**< Sampled Incrementer
-							9 Register */
-
-#define XAPM_MC10_OFFSET		0x000001A0U	/**< Metric Counter 10
-							Register */
-#define XAPM_MC11_OFFSET		0x000001B0U	/**< Metric Counter 11
-							Register */
-#define XAPM_MC12_OFFSET		0x00000500U	/**< Metric Counter 12
-							Register */
-#define XAPM_MC13_OFFSET		0x00000510U	/**< Metric Counter 13
-							Register */
-#define XAPM_MC14_OFFSET		0x00000520U	/**< Metric Counter 14
-							Register */
-#define XAPM_MC15_OFFSET		0x00000530U	/**< Metric Counter 15
-							Register */
-#define XAPM_MC16_OFFSET		0x00000540U	/**< Metric Counter 16
-							Register */
-#define XAPM_MC17_OFFSET		0x00000550U	/**< Metric Counter 17
-							Register */
-#define XAPM_MC18_OFFSET		0x00000560U	/**< Metric Counter 18
-							Register */
-#define XAPM_MC19_OFFSET		0x00000570U	/**< Metric Counter 19
-							Register */
-#define XAPM_MC20_OFFSET		0x00000580U	/**< Metric Counter 20
-							Register */
-#define XAPM_MC21_OFFSET		0x00000590U	/**< Metric Counter 21
-							Register */
-#define XAPM_MC22_OFFSET		0x000005A0U	/**< Metric Counter 22
-							Register */
-#define XAPM_MC23_OFFSET		0x000005B0U	/**< Metric Counter 23
-							Register */
-#define XAPM_MC24_OFFSET		0x00000700U	/**< Metric Counter 24
-							Register */
-#define XAPM_MC25_OFFSET		0x00000710U	/**< Metric Counter 25
-							Register */
-#define XAPM_MC26_OFFSET		0x00000720U	/**< Metric Counter 26
-							Register */
-#define XAPM_MC27_OFFSET		0x00000730U	/**< Metric Counter 27
-							Register */
-#define XAPM_MC28_OFFSET		0x00000740U	/**< Metric Counter 28
-							Register */
-#define XAPM_MC29_OFFSET		0x00000750U	/**< Metric Counter 29
-							Register */
-#define XAPM_MC30_OFFSET		0x00000760U	/**< Metric Counter 30
-							Register */
-#define XAPM_MC31_OFFSET		0x00000770U	/**< Metric Counter 31
-							Register */
-#define XAPM_MC32_OFFSET		0x00000780U	/**< Metric Counter 32
-							Register */
-#define XAPM_MC33_OFFSET		0x00000790U	/**< Metric Counter 33
-							Register */
-#define XAPM_MC34_OFFSET		0x000007A0U	/**< Metric Counter 34
-							Register */
-#define XAPM_MC35_OFFSET		0x000007B0U	/**< Metric Counter 35
-							Register */
-#define XAPM_MC36_OFFSET		0x00000900U	/**< Metric Counter 36
-							Register */
-#define XAPM_MC37_OFFSET		0x00000910U	/**< Metric Counter 37
-							Register */
-#define XAPM_MC38_OFFSET		0x00000920U	/**< Metric Counter 38
-							Register */
-#define XAPM_MC39_OFFSET		0x00000930U	/**< Metric Counter 39
-							Register */
-#define XAPM_MC40_OFFSET		0x00000940U	/**< Metric Counter 40
-							Register */
-#define XAPM_MC41_OFFSET		0x00000950U	/**< Metric Counter 41
-							Register */
-#define XAPM_MC42_OFFSET		0x00000960U	/**< Metric Counter 42
-							Register */
-#define XAPM_MC43_OFFSET		0x00000970U	/**< Metric Counter 43
-							Register */
-#define XAPM_MC44_OFFSET		0x00000980U	/**< Metric Counter 44
-							Register */
-#define XAPM_MC45_OFFSET		0x00000990U	/**< Metric Counter 45
-							Register */
-#define XAPM_MC46_OFFSET		0x000009A0U	/**< Metric Counter 46
-							Register */
-#define XAPM_MC47_OFFSET		0x000009B0U	/**< Metric Counter 47
-							Register */
-
-#define XAPM_SMC10_OFFSET		0x000002A0U	/**< Sampled Metric Counter
-							10 Register */
-#define XAPM_SMC11_OFFSET		0x000002B0U	/**< Sampled Metric Counter
-							11 Register */
-#define XAPM_SMC12_OFFSET		0x00000600U	/**< Sampled Metric Counter
-							12 Register */
-#define XAPM_SMC13_OFFSET		0x00000610U	/**< Sampled Metric Counter
-							13 Register */
-#define XAPM_SMC14_OFFSET		0x00000620U	/**< Sampled Metric Counter
-							14 Register */
-#define XAPM_SMC15_OFFSET		0x00000630U	/**< Sampled Metric Counter
-							15 Register */
-#define XAPM_SMC16_OFFSET		0x00000640U	/**< Sampled Metric Counter
-							16 Register */
-#define XAPM_SMC17_OFFSET		0x00000650U	/**< Sampled Metric Counter
-							17 Register */
-#define XAPM_SMC18_OFFSET		0x00000660U	/**< Sampled Metric Counter
-							18 Register */
-#define XAPM_SMC19_OFFSET		0x00000670U	/**< Sampled Metric Counter
-							19 Register */
-#define XAPM_SMC20_OFFSET		0x00000680U	/**< Sampled Metric Counter
-							20 Register */
-#define XAPM_SMC21_OFFSET		0x00000690U	/**< Sampled Metric Counter
-							21 Register */
-#define XAPM_SMC22_OFFSET		0x000006A0U	/**< Sampled Metric Counter
-							22 Register */
-#define XAPM_SMC23_OFFSET		0x000006B0U	/**< Sampled Metric Counter
-							23 Register */
-#define XAPM_SMC24_OFFSET		0x00000800U	/**< Sampled Metric Counter
-							24 Register */
-#define XAPM_SMC25_OFFSET		0x00000810U	/**< Sampled Metric Counter
-							25 Register */
-#define XAPM_SMC26_OFFSET		0x00000820U	/**< Sampled Metric Counter
-							26 Register */
-#define XAPM_SMC27_OFFSET		0x00000830U	/**< Sampled Metric Counter
-							27 Register */
-#define XAPM_SMC28_OFFSET		0x00000840U	/**< Sampled Metric Counter
-							28 Register */
-#define XAPM_SMC29_OFFSET		0x00000850U	/**< Sampled Metric Counter
-							29 Register */
-#define XAPM_SMC30_OFFSET		0x00000860U	/**< Sampled Metric Counter
-							30 Register */
-#define XAPM_SMC31_OFFSET		0x00000870U	/**< Sampled Metric Counter
-							31 Register */
-#define XAPM_SMC32_OFFSET		0x00000880U	/**< Sampled Metric Counter
-							32 Register */
-#define XAPM_SMC33_OFFSET		0x00000890U	/**< Sampled Metric Counter
-							33 Register */
-#define XAPM_SMC34_OFFSET		0x000008A0U	/**< Sampled Metric Counter
-							34 Register */
-#define XAPM_SMC35_OFFSET		0x000008B0U	/**< Sampled Metric Counter
-							35 Register */
-#define XAPM_SMC36_OFFSET		0x00000A00U	/**< Sampled Metric Counter
-							36 Register */
-#define XAPM_SMC37_OFFSET		0x00000A10U	/**< Sampled Metric Counter
-							37 Register */
-#define XAPM_SMC38_OFFSET		0x00000A20U	/**< Sampled Metric Counter
-							38 Register */
-#define XAPM_SMC39_OFFSET		0x00000A30U	/**< Sampled Metric Counter
-							39 Register */
-#define XAPM_SMC40_OFFSET		0x00000A40U	/**< Sampled Metric Counter
-							40 Register */
-#define XAPM_SMC41_OFFSET		0x00000A50U	/**< Sampled Metric Counter
-							41 Register */
-#define XAPM_SMC42_OFFSET		0x00000A60U	/**< Sampled Metric Counter
-							42 Register */
-#define XAPM_SMC43_OFFSET		0x00000A70U	/**< Sampled Metric Counter
-							43 Register */
-#define XAPM_SMC44_OFFSET		0x00000A80U	/**< Sampled Metric Counter
-							44 Register */
-#define XAPM_SMC45_OFFSET		0x00000A90U	/**< Sampled Metric Counter
-							45 Register */
-#define XAPM_SMC46_OFFSET		0x00000AA0U	/**< Sampled Metric Counter
-							46 Register */
-#define XAPM_SMC47_OFFSET		0x00000AB0U	/**< Sampled Metric Counter
-							47 Register */
-
-#define XAPM_CTL_OFFSET		 	0x00000300U	/**< Control Register */
-
-#define XAPM_ID_OFFSET			0x00000304U	/**< Latency ID Register */
-
-#define XAPM_IDMASK_OFFSET		0x00000308U	/**< ID Mask Register */
-
-#define XAPM_RID_OFFSET			0x0000030CU	/**< Latency Write ID Register */
-
-#define XAPM_RIDMASK_OFFSET		0x00000310U	/**< Read ID Mask Register */
-
-#define XAPM_FEC_OFFSET			0x00000400U	/**< Flag Enable
-							Control Register */
-
-#define XAPM_SWD_OFFSET			0x00000404U	/**< Software-written
-							Data Register */
-
-/* @} */
-
-/**
- * @name AXI Monitor Sample Interval Control Register mask(s)
- * @{
- */
-
-#define XAPM_SICR_MCNTR_RST_MASK	0x00000100U /**< Enable the Metric
-							Counter Reset */
-#define XAPM_SICR_LOAD_MASK		0x00000002U /**< Load the Sample Interval
-							*  Register Value into the
-							*  counter */
-#define XAPM_SICR_ENABLE_MASK		0x00000001U /**< Enable the downcounter */
-
-/*@}*/
-
-
-/** @name Interrupt Status/Enable Register Bit Definitions and Masks
- *  @{
- */
-
-#define XAPM_IXR_MC9_OVERFLOW_MASK	0x00001000U	/**< Metric Counter 9
-							  *  Overflow> */
-#define XAPM_IXR_MC8_OVERFLOW_MASK	0x00000800U	/**< Metric Counter 8
-							  *  Overflow> */
-#define XAPM_IXR_MC7_OVERFLOW_MASK   	0x00000400U	/**< Metric Counter 7
-							  *  Overflow> */
-#define XAPM_IXR_MC6_OVERFLOW_MASK   	0x00000200U	/**< Metric Counter 6
-							  *  Overflow> */
-#define XAPM_IXR_MC5_OVERFLOW_MASK   	0x00000100U	/**< Metric Counter 5
-							  *  Overflow> */
-#define XAPM_IXR_MC4_OVERFLOW_MASK   	0x00000080U	/**< Metric Counter 4
-							  *  Overflow> */
-#define XAPM_IXR_MC3_OVERFLOW_MASK   	0x00000040U	/**< Metric Counter 3
-							  *  Overflow> */
-#define XAPM_IXR_MC2_OVERFLOW_MASK   	0x00000020U	/**< Metric Counter 2
-							  *  Overflow> */
-#define XAPM_IXR_MC1_OVERFLOW_MASK   	0x00000010U	/**< Metric Counter 1
-							  *  Overflow> */
-#define XAPM_IXR_MC0_OVERFLOW_MASK   	0x00000008U	/**< Metric Counter 0
-							  *  Overflow> */
-#define XAPM_IXR_FIFO_FULL_MASK   	0x00000004U	/**< Event Log FIFO
-							  *  full> */
-#define XAPM_IXR_SIC_OVERFLOW_MASK   	0x00000002U	/**< Sample Interval
-							  * Counter Overflow> */
-#define XAPM_IXR_GCC_OVERFLOW_MASK	0x00000001U	/**< Global Clock Counter
-						          *  Overflow> */
-#define XAPM_IXR_ALL_MASK		(XAPM_IXR_SIC_OVERFLOW_MASK | \
-					XAPM_IXR_GCC_OVERFLOW_MASK |  \
-					XAPM_IXR_FIFO_FULL_MASK | \
-					XAPM_IXR_MC0_OVERFLOW_MASK | \
-					XAPM_IXR_MC1_OVERFLOW_MASK | \
-					XAPM_IXR_MC2_OVERFLOW_MASK | \
-					XAPM_IXR_MC3_OVERFLOW_MASK | \
-					XAPM_IXR_MC4_OVERFLOW_MASK | \
-					XAPM_IXR_MC5_OVERFLOW_MASK | \
-					XAPM_IXR_MC6_OVERFLOW_MASK | \
-					XAPM_IXR_MC7_OVERFLOW_MASK | \
-					XAPM_IXR_MC8_OVERFLOW_MASK | \
-					XAPM_IXR_MC9_OVERFLOW_MASK)
-/* @} */
-
-/**
- * @name AXI Monitor Control Register mask(s)
- * @{
- */
-
-#define XAPM_CR_FIFO_RESET_MASK			0x02000000U
-						/**< FIFO Reset */
-#define XAPM_CR_GCC_RESET_MASK			0x00020000U
-						/**< Global Clk
-						  Counter Reset */
-#define XAPM_CR_GCC_ENABLE_MASK			0x00010000U
-						/**< Global Clk
-						   Counter Enable */
-#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK  	0x00000200U
-						/**< Enable External trigger
-						to start event Log */
-#define XAPM_CR_EVENTLOG_ENABLE_MASK  		0x00000100U
-						/**< Event Log Enable */
-
-#define XAPM_CR_RDLATENCY_END_MASK  		0x00000080U
-						/**< Write Latency
-							End point */
-#define XAPM_CR_RDLATENCY_START_MASK  		0x00000040U
-						/**< Read Latency
-							Start point */
-#define XAPM_CR_WRLATENCY_END_MASK  		0x00000020U
-						/**< Write Latency
-							End point */
-#define XAPM_CR_WRLATENCY_START_MASK  		0x00000010U
-						/**< Write Latency
-							Start point */
-#define XAPM_CR_IDFILTER_ENABLE_MASK  		0x00000008U
-						/**< ID Filter Enable */
-
-#define XAPM_CR_MCNTR_EXTTRIGGER_MASK  	 	0x00000004U
-						/**< Enable External
-						   trigger to start
-						   Metric Counters  */
-#define XAPM_CR_MCNTR_RESET_MASK   		0x00000002U
-						/**< Metrics Counter
-						   Reset */
-#define XAPM_CR_MCNTR_ENABLE_MASK  		0x00000001U
-						/**< Metrics Counter
-					           Enable */
-/*@}*/
-
-/**
- * @name AXI Monitor ID Register mask(s)
- * @{
- */
-
-#define XAPM_ID_RID_MASK			0xFFFF0000U /**< Read ID */
-
-#define XAPM_ID_WID_MASK			0x0000FFFFU /**< Write ID */
-
-/*@}*/
-
-/**
- * @name AXI Monitor ID Mask Register mask(s)
- * @{
- */
-
-#define XAPM_MASKID_RID_MASK			0xFFFF0000U /**< Read ID Mask */
-
-#define XAPM_MASKID_WID_MASK			0x0000FFFFU /**< Write ID Mask*/
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-*
-* Read a register of the AXI Performance Monitor device. This macro provides
-* register access to all registers using the register offsets defined above.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset is the offset of the register to read.
-*
-* @return	The contents of the register.
-*
-* @note		C-style Signature:
-*		u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset);
-*
-******************************************************************************/
-#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \
-		(Xil_In32((BaseAddress) + (RegOffset)))
-
-/*****************************************************************************/
-/**
-*
-* Write a register of the AXI Performance Monitor device. This macro provides
-* register access to all registers using the register offsets defined above.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset is the offset of the register to write.
-* @param	Data is the value to write to the register.
-*
-* @return	None.
-*
-* @note 	C-style Signature:
-*		void XAxiPmon_WriteReg(u32 BaseAddress,
-*					u32 RegOffset,u32 Data)
-*
-******************************************************************************/
-#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \
-		(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* End of protection macro. */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c
deleted file mode 100644
index df2a9da66..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xaxipmon_selftest.c
-* @addtogroup axipmon_v6_3
-* @{
-*
-* This file contains a diagnostic self test function for the XAxiPmon driver.
-* The self test function does a simple read/write test of the Alarm Threshold
-* Register.
-*
-* See XAxiPmon.h for more information.
-*
-* @note	None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.00a bss  02/24/12 First release
-* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
-* 6.3   kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xaxipmon.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constant defines the test value to be written
- * to the Range Registers of Incrementers
- */
-
-#define XAPM_TEST_RANGEUPPER_VALUE	16U /**< Test Value for Upper Range */
-#define XAPM_TEST_RANGELOWER_VALUE	 8U /**< Test Value for Lower Range */
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. The test
-*	- Resets the device,
-*	- Writes a value into the Range Registers of Incrementer 0 and reads
-*	  it back for comparison.
-*	- Resets the device again.
-*
-*
-* @param	InstancePtr is a pointer to the XAxiPmon instance.
-*
-* @return
-*		- XST_SUCCESS if the value read from the Range Register of
-*		  Incrementer 0 is the same as the value written.
-*		- XST_FAILURE Otherwise
-*
-* @note		This is a destructive test in that resets of the device are
-*		performed. Refer to the device specification for the
-*		device status after the reset operation.
-*
-******************************************************************************/
-s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr)
-{
-	s32 Status;
-	u16 RangeUpper = 0U;
-	u16 RangeLower = 0U;
-
-	/*
-	 * Assert the argument
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
-	/*
-	 * Reset the device to get it back to its default state
-	 */
-	(void)XAxiPmon_ResetMetricCounter(InstancePtr);
-	XAxiPmon_ResetGlobalClkCounter(InstancePtr);
-
-	/*
-	 * Write a value into the Incrementer register and
-	 * read it back, and do the comparison
-	 */
-	XAxiPmon_SetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0,
-					XAPM_TEST_RANGEUPPER_VALUE,
-					XAPM_TEST_RANGELOWER_VALUE);
-
-	XAxiPmon_GetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0,
-					&RangeUpper, &RangeLower);
-
-	if ((RangeUpper == XAPM_TEST_RANGEUPPER_VALUE) &&
-			(RangeLower == XAPM_TEST_RANGELOWER_VALUE)) {
-		Status = XST_SUCCESS;
-	} else {
-		Status = XST_FAILURE;
-	}
-
-	/*
-	 * Reset the device again to its default state.
-	 */
-	(void)XAxiPmon_ResetMetricCounter(InstancePtr);
-	XAxiPmon_ResetGlobalClkCounter(InstancePtr);
-
-	/*
-	 * Return the test result.
-	 */
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c
deleted file mode 100644
index 737d80b48..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xaxipmon_sinit.c
-* @addtogroup axipmon_v6_3
-* @{
-*
-* This file contains the implementation of the XAxiPmon driver's static
-* initialization functionality.
-*
-* @note	None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.00a bss  02/27/12 First release
-* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
-* 6.3   kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xaxipmon.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XAxiPmon_Config XAxiPmon_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* This function looks up the device configuration based on the unique device ID.
-* The table XAxiPmon_ConfigTable contains the configuration info for each device
-* in the system.
-*
-* @param	DeviceId contains the ID of the device for which the
-*		device configuration pointer is to be returned.
-*
-* @return
-*		- A pointer to the configuration found.
-*		- NULL if the specified device ID was not found.
-*
-* @note		None.
-*
-******************************************************************************/
-XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId)
-{
-	XAxiPmon_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index=0U; Index < (u32)XPAR_XAXIPMON_NUM_INSTANCES; Index++) {
-		if (XAxiPmon_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XAxiPmon_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XAxiPmon_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile
new file mode 100644
index 000000000..926b20c4e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile
@@ -0,0 +1,27 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+
+libs:
+	echo "Compiling axipmon"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	 ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OUTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c
new file mode 100644
index 000000000..fbb867839
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c
@@ -0,0 +1,2123 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xaxipmon.c
+* @addtogroup axipmon_v6_3
+* @{
+*
+* This file contains the driver API functions that can be used to access
+* the AXI Performance Monitor device.
+*
+* Refer to the xaxipmon.h header file for more information about this driver.
+*
+* @note 	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss   02/27/12  First release
+* 2.00a bss   06/23/12  Updated to support v2_00a version of IP.
+* 3.00a bss   09/03/12  Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
+*			to support v2_01a version of IP.
+* 3.01a bss   10/25/12  Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
+*			APIs (CR #683799).
+*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
+*			APIs (CR #683801).
+*			Added XAxiPmon_GetMetricName API (CR #683803).
+*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
+*			(CR #683746)
+*			Added XAxiPmon_EnableEventLog,
+*			XAxiPmon_DisableMetricsCounter,
+*			XAxiPmon_EnableMetricsCounter APIs to replace macros.
+*			Added XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs to support new
+*			version of IP.
+* 4.00a bss   01/17/13  To support new version of IP:
+* 			Added XAxiPmon_SetLogEnableRanges,
+*	  		XAxiPmon_GetLogEnableRanges,
+*			XAxiPmon_EnableMetricCounterTrigger,
+*			XAxiPmon_DisableMetricCounterTrigger,
+*			XAxiPmon_EnableEventLogTrigger,
+*			XAxiPmon_DisableEventLogTrigger,
+*			XAxiPmon_SetWriteLatencyId,
+*			XAxiPmon_SetReadLatencyId,
+*			XAxiPmon_GetWriteLatencyId,
+*			XAxiPmon_GetReadLatencyId APIs and removed
+*			XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs
+* 5.00a bss   08/26/13  To support new version of IP:
+*			Modified XAxiPmon_CfgInitialize to add Mode of APM and
+*			ScaleFactor parameter.
+*			Modified Assert functions depending on Mode.
+*			Modified XAxiPmon_GetMetricCounter and
+*			XAxiPmon_GetSampledMetricCounter to include
+*			new Counters.
+*			Modified XAxiPmon_SetSampleInterval and
+*			XAxiPmon_GetSampleInterval to remove higher 32 bit
+*			value of SampleInterval since Sample Interval Register
+*			is only 32 bit.
+*			Added XAxiPmon_SetWrLatencyStart,
+*			XAxiPmon_SetWrLatencyEnd, XAxiPmon_SetRdLatencyStart
+*			XAxiPmon_SetRdLatencyEnd, XAxiPmon_GetWrLatencyStart,
+*			XAxiPmon_GetWrLatencyEnd, XAxiPmon_GetRdLatencyStart,
+*			XAxiPmon_GetRdLatencyEnd, XAxiPmon_SetWriteIdMask,
+*			XAxiPmon_SetReadIdMask,
+*			XAxiPmon_GetWriteIdMask and
+*			XAxiPmon_GetReadIdMask APIs.
+*			Renamed:
+*			XAxiPmon_SetWriteLatencyId to XAxiPmon_SetWriteId
+*			XAxiPmon_SetReadLatencyId to XAxiPmon_SetReadId
+*			XAxiPmon_GetWriteLatencyId to XAxiPmon_GetWriteId
+*			XAxiPmon_SetReadLatencyId to XAxiPmon_GetReadId.
+* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize to Reset counters
+*			and FIFOs based on Modes(CR#782671). And if both
+*			profile and trace modes are present set mode as
+*			Advanced.
+* 6.2	bss  03/02/15	Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
+*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
+*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
+*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
+*						functions to support Zynq MP APM.
+* 6.3	kvn  07/02/15	Modified code according to MISRA-C:2012 guidelines.
+* 6.4   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototype of XAxiPmon_CfgInitialize API.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xaxipmon.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAxiPmon device/instance. This function
+* must be called prior to using the AXI Performance Monitor device.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	ConfigPtr points to the XAxiPmon device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XAxiPmon_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XAxiPmon_CfgInitialize() API.
+*
+******************************************************************************/
+s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
+						UINTPTR EffectiveAddr)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set the values read from the device config and the base address.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.GlobalClkCounterWidth =
+				ConfigPtr->GlobalClkCounterWidth;
+	InstancePtr->Config.MetricSampleCounterWidth =
+				ConfigPtr->MetricSampleCounterWidth;
+	InstancePtr->Config.IsEventCount =
+				ConfigPtr->IsEventCount;
+	InstancePtr->Config.NumberofSlots =
+				ConfigPtr->NumberofSlots;
+	InstancePtr->Config.NumberofCounters =
+				ConfigPtr->NumberofCounters;
+	InstancePtr->Config.HaveSampledCounters =
+				ConfigPtr->HaveSampledCounters;
+	InstancePtr->Config.IsEventLog =
+				ConfigPtr->IsEventLog;
+	InstancePtr->Config.FifoDepth =
+				ConfigPtr->FifoDepth;
+	InstancePtr->Config.FifoWidth =
+				ConfigPtr->FifoWidth;
+	InstancePtr->Config.TidWidth =
+				ConfigPtr->TidWidth;
+	InstancePtr->Config.Is32BitFiltering = ConfigPtr->Is32BitFiltering;
+
+	InstancePtr->Config.ScaleFactor = ConfigPtr->ScaleFactor;
+
+	if ((ConfigPtr->ModeProfile == ConfigPtr->ModeTrace)
+			|| (ConfigPtr->ModeAdvanced == 1U))
+	{
+		InstancePtr->Mode = XAPM_MODE_ADVANCED;
+	} else if (ConfigPtr->ModeTrace == 1U) {
+		InstancePtr->Mode = XAPM_MODE_TRACE;
+	} else {
+		InstancePtr->Mode = XAPM_MODE_PROFILE;
+	}
+
+	/*
+	 * Indicate the instance is now ready to use, initialized without error.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the Counters and FIFO based on Modes.
+	 */
+
+	/* Advanced and Profile */
+	if((InstancePtr->Mode == XAPM_MODE_ADVANCED) ||
+			(InstancePtr->Mode == XAPM_MODE_PROFILE))
+	{
+		(void)XAxiPmon_ResetMetricCounter(InstancePtr);
+	}
+	/* Advanced */
+	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
+	{
+		XAxiPmon_ResetGlobalClkCounter(InstancePtr);
+	}
+	/* Advanced and Trace */
+	if((InstancePtr->Mode == XAPM_MODE_ADVANCED) ||
+			(InstancePtr->Mode == XAPM_MODE_TRACE))
+	{
+		(void)XAxiPmon_ResetFifo(InstancePtr);
+	}
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets all Metric Counters and Sampled Metric Counters of
+* AXI Performance Monitor.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	XST_SUCCESS
+*
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr)
+{
+
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
+
+	/*
+	 * Write the reset value to the Control register to reset
+	 * Metric counters
+	 */
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							 XAPM_CTL_OFFSET);
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+					(RegValue | XAPM_CR_MCNTR_RESET_MASK));
+	/*
+	 * Release from Reset
+	 */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				(RegValue & ~(XAPM_CR_MCNTR_RESET_MASK)));
+	return XST_SUCCESS;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets Global Clock Counter of AXI Performance Monitor
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr)
+{
+
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
+
+	/*
+	 * Write the reset value to the Control register to reset
+	 * Global Clock Counter
+	 */
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							 XAPM_CTL_OFFSET);
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+					(RegValue | XAPM_CR_GCC_RESET_MASK));
+
+	/*
+	 * Release from Reset
+	 */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				(RegValue & ~(XAPM_CR_GCC_RESET_MASK)));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets Streaming FIFO of AXI Performance Monitor
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	XST_SUCCESS
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr)
+{
+
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_PROFILE);
+
+	/* Check Event Logging is enabled in Hardware */
+	if((InstancePtr->Config.IsEventLog == 0U) &&
+			(InstancePtr->Mode == XAPM_MODE_ADVANCED))
+	{
+		/*Event logging not enabled in Hardware*/
+		return XST_SUCCESS;
+	}
+	/*
+	 * Write the reset value to the Control register to reset
+	 * FIFO
+	 */
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							 XAPM_CTL_OFFSET);
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+					(RegValue | XAPM_CR_FIFO_RESET_MASK));
+	/*
+	 * Release from Reset
+	 */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				(RegValue & ~(XAPM_CR_FIFO_RESET_MASK)));
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets Ranges for Incrementers depending on parameters passed.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	IncrementerNum specifies the Incrementer for which Ranges
+*		need to be set
+* @param 	RangeUpper specifies the Upper limit in 32 bit Register
+* @param 	RangeLower specifies the Lower limit in 32 bit Register
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
+					u16 RangeUpper,	u16 RangeLower)
+ {
+
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
+	Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS);
+
+	/*
+	 * Write to the specified Range register
+	 */
+	RegValue = (u32)RangeUpper << 16;
+	RegValue |= RangeLower;
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16)),
+			RegValue);
+ }
+
+/****************************************************************************/
+/**
+*
+* This function returns the Ranges of Incrementers Registers.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	IncrementerNum specifies the Incrementer for which Ranges
+*		need to be returned.
+* @param 	RangeUpper specifies the user reference variable which returns
+*		the Upper Range Value of the specified Incrementer.
+* @param 	RangeLower specifies the user reference variable which returns
+*		the Lower Range Value of the specified Incrementer.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
+				u16 *RangeUpper, u16 *RangeLower)
+ {
+
+	u32 RegValue;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
+	Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS);
+
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+				((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16)));
+
+	*RangeLower = (u16)(RegValue & 0x0000FFFFU);
+	*RangeUpper = (u16)((RegValue >> 16) & 0x0000FFFFU);
+ }
+
+/****************************************************************************/
+/**
+*
+* This function sets the Sample Interval Register
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	SampleInterval is the Sample Interval value to be set
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval)
+{
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
+
+	/*
+	 * Set Sample Interval Lower
+	 */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+		XAPM_SI_LOW_OFFSET, SampleInterval);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of Sample Interval Register
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	SampleInterval is a pointer where the Sample Interval
+*		Counter value is returned.
+*
+* @return 	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
+
+	/*
+	 * Set Sample Interval Lower
+	 */
+	*SampleInterval = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+				XAPM_SI_LOW_OFFSET);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets Metrics for specified Counter in the corresponding
+* Metric Selector Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Slot is the slot ID for which specified counter has to
+*		be connected.
+* @param	Metrics is one of the Metric Sets. User has to use
+*		XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter
+* @param	CounterNum is the Counter Number.
+*		The valid values are 0 to 9.
+*
+* @return	XST_SUCCESS if Success
+*		XST_FAILURE if Failure
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
+						u8 CounterNum)
+{
+	u32 RegValue;
+	u32 Mask;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
+	Xil_AssertNonvoid(Slot < XAPM_MAX_AGENTS);
+	Xil_AssertNonvoid((Metrics <= XAPM_METRIC_SET_22) ||
+			(Metrics == XAPM_METRIC_SET_30));
+	Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS);
+
+	/* Find Mask value to force zero in counternum byte range */
+	if ((CounterNum == 0U) || (CounterNum == 4U) || (CounterNum == 8U)) {
+		Mask = 0xFFFFFF00U;
+	}
+	else if ((CounterNum == 1U) || (CounterNum == 5U) || (CounterNum == 9U)) {
+		Mask = 0xFFFF00FFU;
+	}
+	else if ((CounterNum == 2U) || (CounterNum == 6U)) {
+		Mask = 0xFF00FFFFU;
+	}
+	else {
+		Mask = 0x00FFFFFFU;
+	}
+
+	if(CounterNum <= 3U) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+					    XAPM_MSR0_OFFSET);
+
+		RegValue = RegValue & Mask;
+		RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
+		RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					(u32)XAPM_MSR0_OFFSET,RegValue);
+	}
+	else if((CounterNum >= 4U) && (CounterNum <= 7U)) {
+		CounterNum = CounterNum - 4U;
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+					    (u32)XAPM_MSR1_OFFSET);
+
+		RegValue = RegValue & Mask;
+		RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
+		RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_MSR1_OFFSET,RegValue);
+	}
+	else {
+		CounterNum = CounterNum - 8U;
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+					    XAPM_MSR2_OFFSET);
+
+		RegValue = RegValue & Mask;
+		RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
+		RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_MSR2_OFFSET,RegValue);
+	}
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns Metrics in the specified Counter from the corresponding
+* Metric Selector Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	CounterNum is the Counter Number.
+*		The valid values are 0 to 9.
+* @param	Metrics is a reference parameter from application where metrics
+*		of specified counter is filled.
+* @praram	Slot is a reference parameter in which slot Id of
+*		specified counter is filled
+* @return	XST_SUCCESS if Success
+*		XST_FAILURE if Failure
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
+								u8 *Slot)
+{
+	u32 RegValue;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
+	Xil_AssertNonvoid(CounterNum <= XAPM_MAX_COUNTERS);
+
+	if(CounterNum <= 3U) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+					XAPM_MSR0_OFFSET);
+		*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
+		*Slot 	= (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
+
+	}
+	else if((CounterNum >= 4U) && (CounterNum <= 7U)) {
+		CounterNum = CounterNum - 4U;
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+					XAPM_MSR1_OFFSET);
+		*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
+		*Slot 	= (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
+	}
+	else {
+		CounterNum = CounterNum - 8U;
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+					XAPM_MSR2_OFFSET);
+		*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
+		*Slot 	= (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
+	}
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the Global Clock Counter Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	CntHighValue is the user space pointer with which upper 32 bits
+*		of Global Clock Counter has to be filled
+* @param	CntLowValue is the user space pointer with which lower 32 bits
+*		of Global Clock Counter has to be filled
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
+							u32 *CntLowValue)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
+
+	*CntHighValue = 0x0U;
+	*CntLowValue  = 0x0U;
+
+	/*
+	 * If Counter width is 64 bit then Counter Value has to be
+	 * filled at CntHighValue address also.
+	 */
+	if(InstancePtr->Config.GlobalClkCounterWidth == 64) {
+
+		/* Bits[63:32] exists at XAPM_GCC_HIGH_OFFSET */
+		*CntHighValue = XAxiPmon_ReadReg(InstancePtr->
+				Config.BaseAddress, XAPM_GCC_HIGH_OFFSET);
+	}
+	/* Bits[31:0] exists at XAPM_GCC_LOW_OFFSET */
+	*CntLowValue = XAxiPmon_ReadReg(InstancePtr->
+				Config.BaseAddress, XAPM_GCC_LOW_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the Metric Counter Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	CounterNum is the number of the Metric Counter to be read.
+*		Use the XAPM_METRIC_COUNTER* defines for the counter number in
+*		xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to
+*		47(XAPM_METRIC_COUNTER_47).
+* @return	RegValue is the content of specified Metric Counter.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum)
+{
+
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
+	Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE);
+
+	if (CounterNum < 10U ) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_MC0_OFFSET + (CounterNum * (u32)16)));
+	}
+	else if ((CounterNum >= 10U) && (CounterNum < 12U)) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_MC10_OFFSET + ((CounterNum - (u32)10) * (u32)16)));
+	}
+	else if ((CounterNum >= 12U) && (CounterNum < 24U)) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_MC12_OFFSET + ((CounterNum - (u32)12) * (u32)16)));
+	}
+	else if ((CounterNum >= 24U) && (CounterNum < 36U)) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_MC24_OFFSET + ((CounterNum - (u32)24) * (u32)16)));
+	}
+	else {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_MC36_OFFSET + ((CounterNum - (u32)36) * (u32)16)));
+	}
+
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the Sampled Metric Counter Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	CounterNum is the number of the Sampled Metric Counter to read.
+*		Use the XAPM_METRIC_COUNTER* defines for the counter number in
+*		xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to
+*		47(XAPM_METRIC_COUNTER_47).
+*
+* @return	RegValue is the content of specified Sampled Metric Counter.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
+	Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE);
+	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
+		((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+			(InstancePtr->Config.HaveSampledCounters == 1U)));
+
+	if (CounterNum < 10U ) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_SMC0_OFFSET + (CounterNum * (u32)16)));
+	}
+	else if ((CounterNum >= 10U) && (CounterNum < 12U)) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_SMC10_OFFSET + ((CounterNum - (u32)10) * (u32)16)));
+	}
+	else if ((CounterNum >= 12U) && (CounterNum < 24U)) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_SMC12_OFFSET + ((CounterNum - (u32)12) * (u32)16)));
+	}
+	else if ((CounterNum >= 24U) && (CounterNum < 36U)) {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_SMC24_OFFSET + ((CounterNum - (u32)24) * (u32)16)));
+	}
+	else {
+		RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_SMC36_OFFSET + ((CounterNum - (u32)36) * (u32)16)));
+	}
+
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the Incrementer Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	IncrementerNum is the number of the Incrementer register to
+*		read.Use the XAPM_INCREMENTER_* defines for the Incrementer
+*		number.The valid values are 0 (XAPM_INCREMENTER_0) to
+*		9 (XAPM_INCREMENTER_9).
+* @param	IncrementerNum is the number of the specified Incrementer
+*		register
+* @return	RegValue is content of specified Metric Incrementer register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U));
+	Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS);
+
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)XAPM_INC0_OFFSET + (IncrementerNum * (u32)16)));
+
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the Sampled Incrementer Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	IncrementerNum is the number of the Sampled Incrementer
+*		register to read.Use the XAPM_INCREMENTER_* defines for the
+*		Incrementer number.The valid values are 0 (XAPM_INCREMENTER_0)
+*		to 9 (XAPM_INCREMENTER_9).
+* @param	IncrementerNum is the number of the specified Sampled
+*		Incrementer register
+* @return	RegValue is content of specified Sampled Incrementer register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U) &&
+				(InstancePtr->Config.HaveSampledCounters == 1U));
+	Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS);
+
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+				((u32)XAPM_SINC0_OFFSET + (IncrementerNum * (u32)16)));
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets Software-written Data Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	SwData is the Software written Data.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set Software-written Data Register
+	 */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_SWD_OFFSET,
+								SwData);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns contents of Software-written Data Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	SwData.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr)
+{
+	 u32 SwData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set Metric Selector Register
+	 */
+	SwData = (u32)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+						XAPM_SWD_OFFSET);
+	return SwData;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables the following in the AXI Performance Monitor:
+*   - Event logging
+*
+* @param        InstancePtr is a pointer to the XAxiPmon instance.
+* @param        FlagEnables is a value to write to the flag enables
+*               register defined by XAPM_FEC_OFFSET. It is recommended
+*               to use the XAPM_FEC_*_MASK mask bits to generate.
+*               A value of 0x0 will disable all events to the event
+*               log streaming FIFO.
+*
+* @return       XST_SUCCESS
+*
+* @note         None
+*
+******************************************************************************/
+s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
+				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+			(InstancePtr->Config.IsEventLog == 1U)));
+
+	/* Read current register value */
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+	/* Flag Enable register is present only in Advanced Mode */
+	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
+	{
+		/* Now write to flag enables register */
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+				(u32)XAPM_FEC_OFFSET, FlagEnables);
+	}
+
+	/* Write the new value to the Control register to
+	 *	enable event logging */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
+		                  RegValue | XAPM_CR_EVENTLOG_ENABLE_MASK);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the following in the AXI Performance Monitor:
+*   - Event logging
+*
+* @param        InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return       XST_SUCCESS
+*
+* @note         None
+*
+******************************************************************************/
+s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
+			((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+			(InstancePtr->Config.IsEventLog == 1U)));
+
+	/* Read current register value */
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+						(u32)XAPM_CTL_OFFSET);
+
+	/* Write the new value to the Control register to disable
+	 * event logging */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
+	                    RegValue & ~XAPM_CR_EVENTLOG_ENABLE_MASK);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables the following in the AXI Performance Monitor:
+*   - Global clock counter
+*   - All metric counters
+*   - All sampled metric counters
+*
+* @param    InstancePtr is a pointer to the XAxiPmon instance.
+*           SampleInterval is the sample interval for the sampled metric
+*           counters
+*
+* @return   XST_SUCCESS
+*
+* @note	    None
+******************************************************************************/
+s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
+				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U)));
+
+	/* Read current register value */
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+	/* Globlal Clock Counter is present in Advanced mode only */
+	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
+	{
+		RegValue = RegValue | XAPM_CR_GCC_ENABLE_MASK;
+	}
+
+	/*
+	 * Write the new value to the Control register to enable
+	 * global clock counter and metric counters
+	 */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
+              RegValue | XAPM_CR_MCNTR_ENABLE_MASK);
+
+	/* Set, enable, and load sampled counters */
+	XAxiPmon_SetSampleInterval(InstancePtr, SampleInterval);
+	XAxiPmon_LoadSampleIntervalCounter(InstancePtr);
+	XAxiPmon_EnableSampleIntervalCounter(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the following in the AXI Performance Monitor:
+*   - Global clock counter
+*   - All metric counters
+*
+* @param        InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return       XST_SUCCESS
+*
+* @note         None
+*
+******************************************************************************/
+s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
+				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U)));
+
+	/* Read current register value */
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+	/* Globlal Clock Counter is present in Advanced mode only */
+	if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
+	{
+		RegValue = RegValue & ~XAPM_CR_GCC_ENABLE_MASK;
+	}
+
+	/*
+	 * Write the new value to the Control register to disable
+	 * global clock counter and metric counters
+	 */
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
+			RegValue & ~XAPM_CR_MCNTR_ENABLE_MASK);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables Metric Counters.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		None
+*
+*******************************************************************************/
+void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
+				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U)));
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+						XAPM_CTL_OFFSET);
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+					RegVal | XAPM_CR_MCNTR_ENABLE_MASK);
+}
+/****************************************************************************/
+/**
+*
+* This function disables the Metric Counters.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
+				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U)));
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
+					RegVal & ~(XAPM_CR_MCNTR_ENABLE_MASK));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Upper and Lower Ranges for specified Metric Counter
+* Log Enable Register.Event Logging starts when corresponding Metric Counter
+* value falls in between these ranges
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	CounterNum is the Metric Counter number for which
+*		Ranges are to be assigned.Use the XAPM_METRIC_COUNTER*
+*		defines for the counter number in xaxipmon.h.
+*		The valid values are 0 (XAPM_METRIC_COUNTER_0) to
+*		9 (XAPM_METRIC_COUNTER_9).
+* @param 	RangeUpper specifies the Upper limit in 32 bit Register
+* @param 	RangeLower specifies the Lower limit in 32 bit Register
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
+					u16 RangeUpper, u16 RangeLower)
+{
+	u32 RegValue;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS);
+	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U));
+
+
+	/*
+	 * Write the specified Ranges to corresponding Metric Counter Log
+	 * Enable Register
+	 */
+	RegValue = (u32)RangeUpper << 16;
+	RegValue |= RangeLower;
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16)), RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the Ranges of specified Metric Counter Log
+* Enable Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	CounterNum is the Metric Counter number for which
+*		Ranges are to be returned.Use the XAPM_METRIC_COUNTER*
+*		defines for the counter number in xaxipmon.h.
+*		The valid values are 0 (XAPM_METRIC_COUNTER_0) to
+*		9 (XAPM_METRIC_COUNTER_9).
+*
+* @param 	RangeUpper specifies the user reference variable which returns
+*		the Upper Range Value of the specified Metric Counter
+*		Log Enable Register.
+* @param 	RangeLower specifies the user reference variable which returns
+*		the Lower Range Value of the specified Metric Counter
+*		Log Enable Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
+					u16 *RangeUpper, u16 *RangeLower)
+{
+	u32 RegValue;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS);
+	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventCount == 1U));
+
+
+	RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+				((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16)));
+
+	*RangeLower = (u16)RegValue & 0xFFFFU;
+	*RangeUpper = (u16)(RegValue >> 16) & 0xFFFFU;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables Event Logging.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		None
+*
+*******************************************************************************/
+void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
+				((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
+				(InstancePtr->Config.IsEventLog == 1U)));
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				RegVal | XAPM_CR_EVENTLOG_ENABLE_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables External trigger pulse so that Metric Counters can be
+* started on external trigger pulse for a Slot.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		None
+*
+*******************************************************************************/
+void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				RegVal | XAPM_CR_MCNTR_EXTTRIGGER_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the External trigger pulse used to start Metric
+* Counters on external trigger pulse for a Slot.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				RegVal & ~(XAPM_CR_MCNTR_EXTTRIGGER_MASK));
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables External trigger pulse for Event Log
+* so that Event Logging can be started on external trigger pulse for a Slot.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		None
+*
+*******************************************************************************/
+void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				RegVal | XAPM_CR_EVTLOG_EXTTRIGGER_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the External trigger pulse used to start Event
+* Log on external trigger pulse for a Slot.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+
+	XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
+				RegVal & ~(XAPM_CR_EVTLOG_EXTTRIGGER_MASK));
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns a name for a given Metric.
+*
+* @param        Metrics is one of the Metric Sets. User has to use
+*               XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter
+*
+* @return       const char *
+*
+* @note         None
+*
+*****************************************************************************/
+const char * XAxiPmon_GetMetricName(u8 Metrics)
+{
+	if (Metrics == XAPM_METRIC_SET_0 ){
+		return "Write Transaction Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_1 ){
+			return "Read Transaction Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_2 ){
+			return "Write Byte Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_3 ){
+			return "Read Byte Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_4 ){
+			return "Write Beat Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_5 ){
+			return "Total Read Latency";
+	}
+	if (Metrics == XAPM_METRIC_SET_6 ){
+			return "Total Write Latency";
+	}
+	if (Metrics == XAPM_METRIC_SET_7 ){
+		return "Slv_Wr_Idle_Cnt";
+	}
+	if (Metrics == XAPM_METRIC_SET_8 ){
+			return "Mst_Rd_Idle_Cnt";
+	}
+	if (Metrics == XAPM_METRIC_SET_9 ){
+			return "Num_BValids";
+	}
+	if (Metrics == XAPM_METRIC_SET_10){
+		return "Num_WLasts";
+	}
+	if (Metrics == XAPM_METRIC_SET_11){
+			return "Num_RLasts";
+	}
+	if (Metrics == XAPM_METRIC_SET_12){
+			return "Minimum Write Latency";
+	}
+	if (Metrics == XAPM_METRIC_SET_13){
+			return "Maximum Write Latency";
+	}
+	if (Metrics == XAPM_METRIC_SET_14){
+			return "Minimum Read Latency";
+	}
+	if (Metrics == XAPM_METRIC_SET_15){
+			return "Maximum Read Latency";
+	}
+	if (Metrics == XAPM_METRIC_SET_16){
+			return "Transfer Cycle Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_17){
+			return "Packet Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_18){
+			return "Data Byte Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_19){
+			return "Position Byte Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_20){
+			return "Null Byte Count";
+	}
+	if (Metrics == XAPM_METRIC_SET_21){
+			return "Slv_Idle_Cnt";
+	}
+	if (Metrics == XAPM_METRIC_SET_22){
+			return "Mst_Idle_Cnt";
+	}
+	if (Metrics == XAPM_METRIC_SET_30){
+			return "External event count";
+	}
+	return "Unsupported";
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets Write ID in ID register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	WriteId is the Write ID to be written in ID register.
+*
+* @return	None.
+*
+* @note
+*			If ID filtering for write is of 32 bits(for Zynq MP APM) width then
+*			WriteID is written to XAPM_ID_OFFSET or if it is 16 bit width
+*			then lower 16 bits of WriteID are written to XAPM_ID_OFFSET.
+*
+*****************************************************************************/
+void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId)
+{
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_ID_OFFSET);
+		RegVal = RegVal & ~(XAPM_ID_WID_MASK);
+		RegVal = RegVal | WriteId;
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_ID_OFFSET, RegVal);
+	} else {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_ID_OFFSET, WriteId);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets Read ID in ID register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	ReadId is the Read ID to be written in ID register.
+*
+* @return	None.
+*
+* @note
+*			If ID filtering for read is of 32 bits(for Zynq MP APM) width then
+*			ReadId is written to XAPM_RID_OFFSET or if it is 16 bit width
+*			then lower 16 bits of ReadId are written to XAPM_ID_OFFSET.
+*
+*****************************************************************************/
+void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId)
+{
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_ID_OFFSET);
+		RegVal = RegVal & ~(XAPM_ID_RID_MASK);
+		RegVal = RegVal | (ReadId << 16);
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_ID_OFFSET, RegVal);
+	} else {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_RID_OFFSET, ReadId);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns Write ID in ID register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	WriteId is the required Write ID in ID register.
+*
+* @note		None.
+*			If ID filtering for write is of 32 bits(for Zynq MP APM) width then
+*			32 bit XAPM_ID_OFFSET contents are returned or if it is 16 bit
+*			width then lower 16 bits of XAPM_ID_OFFSET register are returned.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr)
+{
+
+	u32 WriteId;
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_ID_OFFSET);
+		WriteId = RegVal & XAPM_ID_WID_MASK;
+	} else {
+		WriteId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_ID_OFFSET);
+	}
+
+	return WriteId;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns Read ID in ID register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	ReadId is the required Read ID in ID register.
+*
+* @note		None.
+*			If ID filtering for write is of 32 bits(for Zynq MP APM) width then
+*			32 bit XAPM_RID_OFFSET contents are returned or if it is 16 bit
+*			width then higher 16 bits of XAPM_ID_OFFSET register are returned.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr)
+{
+
+	u32 ReadId;
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_ID_OFFSET);
+		RegVal = RegVal & XAPM_ID_RID_MASK;
+		ReadId = RegVal >> 16;
+	} else {
+		ReadId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_RID_OFFSET);
+	}
+
+	return ReadId;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets Latency Start point to calculate write latency.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT
+*		in xaxipmon.h.
+* @return	None
+*
+* @note		Param can be 0 - XAPM_LATENCY_ADDR_ISSUE
+*		or 1 - XAPM_LATENCY_ADDR_ACCEPT
+*
+*******************************************************************************/
+void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+	if (Param == XAPM_LATENCY_ADDR_ACCEPT) {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_START_MASK);
+	}
+	else {
+		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET,
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_START_MASK));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets Latency End point to calculate write latency.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Param is XAPM_LATENCY_LASTWR or XAPM_LATENCY_FIRSTWR
+* 		in xaxipmon.h.
+*
+* @return	None
+*
+* @note		Param can be 0 - XAPM_LATENCY_LASTWR
+*		or 1 - XAPM_LATENCY_FIRSTWR
+*
+*******************************************************************************/
+void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+	if (Param == XAPM_LATENCY_FIRSTWR) {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_END_MASK);
+	}
+	else {
+		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET,
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_END_MASK));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets Latency Start point to calculate read latency.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT
+*		in xaxipmon.h.
+*
+* @return	None
+*
+* @note		Param can be 0 - XAPM_LATENCY_ADDR_ISSUE
+*		or 1 - XAPM_LATENCY_ADDR_ACCEPT
+*
+*******************************************************************************/
+void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+	if (Param == XAPM_LATENCY_ADDR_ACCEPT) {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_START_MASK);
+	}
+	else {
+		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET,
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_START_MASK));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets Latency End point to calculate read latency.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Param is XAPM_LATENCY_LASTRD or XAPM_LATENCY_FIRSTRD
+* 		in xaxipmon.h.
+*
+* @return	None
+*
+* @note		Param can be 0 - XAPM_LATENCY_LASTRD
+*		or 1 - XAPM_LATENCY_FIRSTRD
+*
+*******************************************************************************/
+void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param)
+{
+	u32 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_CTL_OFFSET);
+	if (Param == XAPM_LATENCY_FIRSTRD) {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+		  XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_END_MASK);
+	}
+	else {
+		XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET,
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress,
+			XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_END_MASK));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns Write Latency Start point.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	Returns 0 - XAPM_LATENCY_ADDR_ISSUE or
+*			1 - XAPM_LATENCY_ADDR_ACCEPT
+*
+* @note		None
+*
+*******************************************************************************/
+u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr)
+{
+	u8 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+	RegVal = RegVal & XAPM_CR_WRLATENCY_START_MASK;
+	if (RegVal != XAPM_LATENCY_ADDR_ISSUE) {
+		return (u8)XAPM_LATENCY_ADDR_ACCEPT;
+	}
+	else {
+		return (u8)XAPM_LATENCY_ADDR_ISSUE;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns Write Latency End point.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	Returns 0 - XAPM_LATENCY_LASTWR or
+*			1 - XAPM_LATENCY_FIRSTWR.
+*
+* @note		None
+*
+*******************************************************************************/
+u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr)
+{
+	u8 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+	RegVal = RegVal & XAPM_CR_WRLATENCY_END_MASK;
+	if (RegVal != XAPM_LATENCY_LASTWR) {
+		return (u8)XAPM_LATENCY_FIRSTWR;
+	}
+	else {
+		return (u8)XAPM_LATENCY_LASTWR;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns read Latency Start point.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	Returns 0 - XAPM_LATENCY_ADDR_ISSUE or
+*			1 - XAPM_LATENCY_ADDR_ACCEPT
+*
+* @note		None
+*
+*******************************************************************************/
+u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr)
+{
+	u8 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+	RegVal = RegVal & XAPM_CR_RDLATENCY_START_MASK;
+
+	if (RegVal != XAPM_LATENCY_ADDR_ISSUE) {
+		return	(u8)XAPM_LATENCY_ADDR_ACCEPT;
+	}
+	else {
+		return (u8)XAPM_LATENCY_ADDR_ISSUE;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns Read Latency End point.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	Returns 0 - XAPM_LATENCY_LASTRD or
+*			1 - XAPM_LATENCY_FIRSTRD.
+*
+* @note		None
+*
+*******************************************************************************/
+u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr)
+{
+	u8 RegVal;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							(u32)XAPM_CTL_OFFSET);
+	RegVal = RegVal & XAPM_CR_RDLATENCY_END_MASK;
+	if (RegVal != XAPM_LATENCY_LASTRD) {
+		return (u8)XAPM_LATENCY_FIRSTRD;
+	}
+	else {
+		return (u8)XAPM_LATENCY_LASTRD;
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets Write ID Mask in ID Mask register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	WrMask is the Write ID mask to be written in ID register.
+*
+* @return	None.
+*
+* @note
+*			If ID masking for write is of 32 bits(for Zynq MP APM) width then
+*			WrMask is written to XAPM_IDMASK_OFFSET or if it is 16 bit width
+*			then lower 16 bits of WrMask are written to XAPM_IDMASK_OFFSET.
+*
+*****************************************************************************/
+void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask)
+{
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_IDMASK_OFFSET);
+		RegVal = RegVal & ~(XAPM_MASKID_WID_MASK);
+		RegVal = RegVal | WrMask;
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+							XAPM_IDMASK_OFFSET, RegVal);
+	} else {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+							XAPM_IDMASK_OFFSET, WrMask);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets Read ID Mask in ID Mask register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	RdMask is the Read ID mask to be written in ID Mask register.
+*
+* @return	None.
+*
+* @note
+*			If ID masking for read is of 32 bits(for Zynq MP APM) width then
+*			RdMask is written to XAPM_RIDMASK_OFFSET or if it is 16 bit width
+*			then lower 16 bits of RdMask are written to XAPM_IDMASK_OFFSET.
+*
+*****************************************************************************/
+void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask)
+{
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_IDMASK_OFFSET);
+		RegVal = RegVal & ~(XAPM_MASKID_RID_MASK);
+		RegVal = RegVal | (RdMask << 16);
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_IDMASK_OFFSET, RegVal);
+	} else {
+		XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
+					XAPM_RIDMASK_OFFSET, RdMask);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns Write ID Mask in ID Mask register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	WrMask is the required Write ID Mask in ID Mask register.
+*
+* @note
+*			If ID masking for write is of 32 bits(for Zynq MP APM) width then
+*			32 bit XAPM_IDMASK_OFFSET contents are returned or if it is 16 bit
+*			width then lower 16 bits of XAPM_IDMASK_OFFSET register
+*			are returned.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr)
+{
+
+	u32 WrMask;
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_IDMASK_OFFSET);
+		WrMask = RegVal & XAPM_MASKID_WID_MASK;
+	} else {
+		WrMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_IDMASK_OFFSET);
+	}
+
+	return WrMask;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns Read ID Mask in ID Mask register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	RdMask is the required Read ID Mask in ID Mask register.
+*
+* @note
+*			If ID masking for read is of 32 bits(for Zynq MP APM) width then
+*			32 bit XAPM_RIDMASK_OFFSET contents are returned or if it is 16 bit
+*			width then higher 16 bits of XAPM_IDMASK_OFFSET register
+*			are returned.
+*
+*****************************************************************************/
+u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr)
+{
+
+	u32 RdMask;
+	u32 RegVal;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->Config.Is32BitFiltering == 0U)
+	{
+		RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+							XAPM_IDMASK_OFFSET);
+		RegVal = RegVal & XAPM_MASKID_RID_MASK;
+		RdMask = RegVal >> 16;
+	} else {
+		RdMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
+								XAPM_RIDMASK_OFFSET);
+	}
+
+	return RdMask;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h
new file mode 100644
index 000000000..f8d4d6467
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h
@@ -0,0 +1,938 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xaxipmon.h
+* @addtogroup axipmon_v6_3
+* @{
+* @details
+*
+* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device.
+*
+* The AXI Performance Monitor device provides following features:
+*
+*	Configurable number of Metric Counters and Incrementers
+* 	Computes performance metrics for Agents connected to
+*	monitor slots (Up to 8 slots)
+*
+* The following Metrics can be computed:
+*
+* Metrics computed for an AXI4 MM agent:
+*	Write Request Count: Total number of write requests by/to the agent.
+*	Read Request Count: Total number of read requests given by/to the
+*			    agent.
+*	Read Latency: It is defined as the time from the start of read address
+*       	      transaction to the beginning of the read data service.
+*	Write Latency: It is defined as the period needed a master completes
+*        	       write data transaction, i.e. from write address
+*        	       transaction to write response from slave.
+*	Write Byte Count: Total number of bytes written by/to the agent.
+*        		  This metric is helpful when calculating the
+*        		  throughput of the system.
+*	Read Byte Count: Total number of bytes read from/by the agent.
+*	Average Write Latency: Average write latency seen by the agent.
+*        		       It can be derived from total write latency
+*        		       and the write request count.
+*	Average Read Latency: Average read latency seen by the agent. It can be
+*        		      derived from total read latency and the read
+*        		      request count.
+*	Master Write Idle Cycle Count: Number of idle cycles caused by the
+*        			       masters during write transactions to
+*        			       the slave.
+*	Slave Write Idle Cycle Count: Number of idle cycles caused by this slave
+*        			      during write transactions to the slave.
+*	Master Read Idle Cycle Count: Number of idle cycles caused by the
+*        			      master during read transactions to the
+*        			      slave.
+*	Slave Read Idle Cycle Count: Number of idle cycles caused by this slave
+*        			     during read transactions to the slave.
+*
+* Metrics computed for an AXI4-Stream agent:
+*
+*	Transfer Cycle Count: Total number of writes by/to the agent.
+*	Data Byte Count: Total number of data bytes written by/to the agent.
+*			 This metric helps in calculating the throughput
+*			 of the system.
+*	Position Byte Count: Total number of position bytes transferred.
+*	Null Byte Count: Total number of null bytes transferred.
+*	Packet Count: Total number of packets transferred.
+*
+* There are three modes : Advanced, Profile and Trace.
+* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors
+*   and Sampled Incrementors.
+* - Profile mode has only 47 Metric Counters and Sampled Metric Counters.
+* - Trace mode has no Counters.
+* User should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the AXI Performance Monitor device.
+*
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the AXI Performance Monitor device.
+*
+* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor
+* device. The user needs to first call the XAxiPmon_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAxiPmon_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The AXI Performance Monitor does not support Interrupts
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XAxiPmon driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <b> Limitations of the driver </b>
+*
+*
+* <br><br>
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 To support v2_01_a version of IP:
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
+*			XAPM_FLAG_EVNTSTOP.
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
+*			in xaxipmon.c
+*			Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
+*			Added XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
+*			(CR #683746) in xaxipmon.c
+*			Added XAxiPmon_EnableEventLog,
+*			XAxiPmon_DisableMetricsCounter,
+*			XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
+*			replace macros in this file.
+*			Added XAPM_FLAG_XXX macros.
+*			Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
+*			APIs (CR #683799).
+*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
+*			APIs (CR #683801).
+*			Added XAxiPmon_GetMetricName API (CR #683803).
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
+*			declarations (CR #677337)
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
+*			Added XAxiPmon_SetLogEnableRanges,
+*	  		XAxiPmon_GetLogEnableRanges,
+*			XAxiPmon_EnableMetricCounterTrigger,
+*			XAxiPmon_DisableMetricCounterTrigger,
+*			XAxiPmon_EnableEventLogTrigger,
+*			XAxiPmon_DisableEventLogTrigger,
+*			XAxiPmon_SetWriteLatencyId,
+*			XAxiPmon_SetReadLatencyId,
+*			XAxiPmon_GetWriteLatencyId,
+*			XAxiPmon_GetReadLatencyId APIs and removed
+*			XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
+*			xaxipmon_hw.h
+* 5.00a bss   08/26/13  To support new version of IP:
+*			XAxiPmon_SampleMetrics Macro.
+*			Modified XAxiPmon_CfgInitialize, Assert functions
+*			Added XAxiPmon_GetMetricCounter,
+*			XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
+*			XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
+*			XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
+*			XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
+*			XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
+*			XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
+*			XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
+*			Renamed :
+*			XAxiPmon_SetWriteLatencyId to
+*			XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
+*			XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_GetReadId. in xaxipmon.c
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
+*			XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK and
+*			XAPM_MAX_COUNTERS_PROFILE.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*			in xaxipmon_hw.h.
+*			Modified driver tcl to generate new parameters
+*			ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
+*			in Config structure.
+* 6.0   adk  19/12/13 Updated as per the New Tcl API's
+* 6.1   adk  16/04/14 Updated the driver tcl for the newly added parameters in
+* 		      The Axi pmon IP.
+* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
+*			counters and FIFOs based on Modes(CR#782671). And if
+*			both profile and trace modes are present set mode as
+*			Advanced.
+* 6.2	bss  03/02/15	To support Zynq MP APM:
+*						Added Is32BitFiltering in XAxiPmon_Config structure.
+*						Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
+*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
+*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
+*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
+*						functions in xaxipmon.c.
+*						Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
+*						xaxipmon_hw.h
+*
+* 6.3	kvn  07/02/15	Modified code according to MISRA-C:2012 guidelines.
+* 6.4   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototype of XAxiPmon_CfgInitialize API.
+* </pre>
+*
+*****************************************************************************/
+#ifndef XAXIPMON_H /* Prevent circular inclusions */
+#define XAXIPMON_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xaxipmon_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Macro for Maximum number of Counters
+ *
+ * @{
+ */
+#define XAPM_MAX_COUNTERS		10U /**< Maximum number of Counters */
+#define XAPM_MAX_COUNTERS_PROFILE	48U /**< Maximum number of Counters */
+
+/*@}*/
+
+
+/**
+ * @name Indices for Metric Counters and Sampled Metric Coounters used with
+ * 	 XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs
+ * @{
+ */
+
+#define XAPM_METRIC_COUNTER_0	0U /**< Metric Counter 0 Register Index */
+#define XAPM_METRIC_COUNTER_1	1U /**< Metric Counter 1 Register Index */
+#define XAPM_METRIC_COUNTER_2	2U /**< Metric Counter 2 Register Index */
+#define XAPM_METRIC_COUNTER_3	3U /**< Metric Counter 3 Register Index */
+#define XAPM_METRIC_COUNTER_4	4U /**< Metric Counter 4 Register Index */
+#define XAPM_METRIC_COUNTER_5	5U /**< Metric Counter 5 Register Index */
+#define XAPM_METRIC_COUNTER_6	6U /**< Metric Counter 6 Register Index */
+#define XAPM_METRIC_COUNTER_7	7U /**< Metric Counter 7 Register Index */
+#define XAPM_METRIC_COUNTER_8	8U /**< Metric Counter 8 Register Index */
+#define XAPM_METRIC_COUNTER_9	9U /**< Metric Counter 9 Register Index */
+
+/*@}*/
+
+/**
+ * @name Indices for Incrementers and Sampled Incrementers used with
+ * 	 XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs
+ * @{
+ */
+
+#define XAPM_INCREMENTER_0	0U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_1	1U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_2	2U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_3	3U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_4	4U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_5	5U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_6	6U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_7	7U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_8	8U /**< Metric Counter 0 Register Index */
+#define XAPM_INCREMENTER_9	9U /**< Metric Counter 0 Register Index */
+
+/*@}*/
+
+/**
+ * @name Macros for Metric Selector Settings
+ * @{
+ */
+
+#define XAPM_METRIC_SET_0		0U /**< Write Transaction Count */
+#define XAPM_METRIC_SET_1		1U /**< Read Transaction Count */
+#define XAPM_METRIC_SET_2		2U /**< Write Byte Count */
+#define XAPM_METRIC_SET_3		3U /**< Read Byte Count */
+#define XAPM_METRIC_SET_4		4U /**< Write Beat Count */
+#define XAPM_METRIC_SET_5		5U /**< Total Read Latency */
+#define XAPM_METRIC_SET_6		6U /**< Total Write Latency */
+#define XAPM_METRIC_SET_7		7U /**< Slv_Wr_Idle_Cnt */
+#define XAPM_METRIC_SET_8		8U /**< Mst_Rd_Idle_Cnt */
+#define XAPM_METRIC_SET_9		9U /**< Num_BValids */
+#define XAPM_METRIC_SET_10		10U /**< Num_WLasts */
+#define XAPM_METRIC_SET_11		11U /**< Num_RLasts */
+#define XAPM_METRIC_SET_12		12U /**< Minimum Write Latency */
+#define XAPM_METRIC_SET_13		13U /**< Maximum Write Latency */
+#define XAPM_METRIC_SET_14		14U /**< Minimum Read Latency */
+#define XAPM_METRIC_SET_15		15U /**< Maximum Read Latency */
+#define XAPM_METRIC_SET_16		16U /**< Transfer Cycle Count */
+#define XAPM_METRIC_SET_17		17U /**< Packet Count */
+#define XAPM_METRIC_SET_18		18U /**< Data Byte Count */
+#define XAPM_METRIC_SET_19		19U /**< Position Byte Count */
+#define XAPM_METRIC_SET_20		20U /**< Null Byte Count */
+#define XAPM_METRIC_SET_21		21U /**< Slv_Idle_Cnt */
+#define XAPM_METRIC_SET_22		22U /**< Mst_Idle_Cnt */
+#define XAPM_METRIC_SET_30		30U /**< External event count */
+
+
+/*@}*/
+
+
+/**
+ * @name Macros for Maximum number of Agents
+ * @{
+ */
+
+#define XAPM_MAX_AGENTS 	8U /**< Maximum number of Agents */
+
+/*@}*/
+
+/**
+ * @name Macros for Flags in Flag Enable Control Register
+ * @{
+ */
+
+#define XAPM_FLAG_WRADDR	0x00000001 /**< Write Address Flag */
+#define XAPM_FLAG_FIRSTWR	0x00000002 /**< First Write Flag */
+#define XAPM_FLAG_LASTWR	0x00000004 /**< Last Write Flag */
+#define XAPM_FLAG_RESPONSE	0x00000008 /**< Response Flag */
+#define XAPM_FLAG_RDADDR	0x00000010 /**< Read Address Flag */
+#define XAPM_FLAG_FIRSTRD	0x00000020 /**< First Read Flag */
+#define XAPM_FLAG_LASTRD	0x00000040 /**< Last Read Flag */
+#define XAPM_FLAG_SWDATA	0x00010000 /**< Software-written Data Flag */
+#define XAPM_FLAG_EVENT		0x00020000 /**< Last Read Flag */
+#define XAPM_FLAG_EVNTSTOP	0x00040000 /**< Last Read Flag */
+#define XAPM_FLAG_EVNTSTART	0x00080000 /**< Last Read Flag */
+#define XAPM_FLAG_GCCOVF	0x00100000 /**< Global Clock Counter Overflow
+					     *  Flag */
+#define XAPM_FLAG_SCLAPSE	0x00200000 /**< Sample Counter Lapse Flag */
+#define XAPM_FLAG_MC0		0x00400000U /**< Metric Counter 0 Flag */
+#define XAPM_FLAG_MC1		0x00800000U /**< Metric Counter 1 Flag */
+#define XAPM_FLAG_MC2		0x01000000U /**< Metric Counter 2 Flag */
+#define XAPM_FLAG_MC3		0x02000000U /**< Metric Counter 3 Flag */
+#define XAPM_FLAG_MC4		0x04000000U /**< Metric Counter 4 Flag */
+#define XAPM_FLAG_MC5		0x08000000U /**< Metric Counter 5 Flag */
+#define XAPM_FLAG_MC6		0x10000000U /**< Metric Counter 6 Flag */
+#define XAPM_FLAG_MC7		0x20000000U /**< Metric Counter 7 Flag */
+#define XAPM_FLAG_MC8		0x40000000U /**< Metric Counter 8 Flag */
+#define XAPM_FLAG_MC9		0x80000000U /**< Metric Counter 9 Flag */
+
+/*@}*/
+
+/**
+ * @name Macros for Read/Write Latency Start and End points
+ * @{
+ */
+#define XAPM_LATENCY_ADDR_ISSUE		0U /**< Address Issue as start
+					point for Latency calculation*/
+#define XAPM_LATENCY_ADDR_ACCEPT	1U /**< Address Acceptance as start
+					point for Latency calculation*/
+#define XAPM_LATENCY_LASTRD		0U /**< Last Read as end point for
+					Latency calculation */
+#define XAPM_LATENCY_LASTWR		0U /**< Last Write as end point for
+					Latency calculation */
+#define XAPM_LATENCY_FIRSTRD		1U /**< First Read as end point for
+					Latency calculation */
+#define XAPM_LATENCY_FIRSTWR		1U /**< First Write as end point for
+					Latency calculation */
+
+/*@}*/
+
+/**
+ * @name Macros for Modes of APM
+ * @{
+ */
+
+#define XAPM_MODE_TRACE			2U /**< APM in Trace mode */
+
+#define XAPM_MODE_PROFILE		1U /**< APM in Profile mode */
+
+#define XAPM_MODE_ADVANCED		0U /**< APM in Advanced mode */
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the AXI Performance
+ * Monitor device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID of device */
+	UINTPTR BaseAddress;		/**< Device base address */
+	s32 GlobalClkCounterWidth;	/**< Global Clock Counter Width */
+	s32 MetricSampleCounterWidth ;	/**< Metric Sample Counters Width */
+	u8  IsEventCount;		/**< Event Count Enabled 1 - enabled
+							   0 - not enabled */
+	u8  NumberofSlots;		/**< Number of Monitor Slots */
+	u8  NumberofCounters;		/**< Number of Counters */
+	u8  HaveSampledCounters;	/**< Have Sampled Counters 1 - present
+							    0 - Not present */
+	u8 IsEventLog;			/**< Event Logging Enabled 1 - enabled
+							    0 - Not enabled */
+	u32 FifoDepth;			/**< Event Log FIFO Depth */
+	u32 FifoWidth;			/**< Event Log FIFO Width */
+	u32 TidWidth; 			/**< Streaming Interface TID Width */
+	u8  ScaleFactor;		/**< Event Count Scaling factor */
+	u8  ModeAdvanced;		/**< Advanced Mode */
+	u8  ModeProfile;		/**< Profile Mode */
+	u8  ModeTrace;			/**< Trace Mode */
+	u8  Is32BitFiltering;   /**< 32 bit filtering enabled */
+} XAxiPmon_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every AXI Performance Monitor device in system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAxiPmon_Config Config;	/**< XAxiPmon_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+	u8   Mode;		/**< APM Mode */
+} XAxiPmon;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/****************************************************************************/
+/**
+*
+* This routine enables the Global Interrupt.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_IntrGlobalEnable(InstancePtr)			\
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, 	\
+			XAPM_GIE_OFFSET, 1)
+
+
+/****************************************************************************/
+/**
+*
+* This routine disables the Global Interrupt.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_IntrGlobalDisable(InstancePtr)				\
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, 		\
+				XAPM_GIE_OFFSET, 0)
+
+
+/****************************************************************************/
+/**
+*
+* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in
+* xaxipmon_hw.h to create the bit-mask to enable interrupts.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Mask is the mask to enable. Bit positions of 1 will be enabled.
+*		Bit positions of 0 will keep the previous setting. This mask is
+*		formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XAxiPmon_IntrEnable(InstancePtr, Mask)				     \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_IE_OFFSET) | (Mask));
+
+
+/****************************************************************************/
+/**
+*
+* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in
+* xaxipmon_hw.h to create the bit-mask to disable interrupts.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Mask is the mask to disable. Bit positions of 1 will be
+*		disabled. Bit positions of 0 will keep the previous setting.
+*		This mask is formed by OR'ing XAPM_IXR_* bits defined in
+*		xaxipmon_hw.h.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XAxiPmon_IntrDisable(InstancePtr, Mask)				     \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_IE_OFFSET) | (Mask));
+
+/****************************************************************************/
+/**
+*
+* This routine clears the specified interrupt(s).
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param	Mask is the mask to clear. Bit positions of 1 will be cleared.
+*		This mask is formed by OR'ing XAPM_IXR_* bits defined in
+*		xaxipmon_hw.h.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XAxiPmon_IntrClear(InstancePtr, Mask)				     \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_IS_OFFSET) | (Mask));
+
+/****************************************************************************/
+/**
+*
+* This routine returns the Interrupt Status Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	Interrupt Status Register contents
+*
+* @note		C-Style signature:
+*		void XAxiPmon_IntrClear(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_IntrGetStatus(InstancePtr)				     \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_IS_OFFSET);
+
+/****************************************************************************/
+/**
+*
+* This function enables the Global Clock Counter.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK);
+
+/****************************************************************************/
+/**
+*
+* This function disbles the Global Clock Counter.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK));
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified flag in Flag Control Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param 	Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_EnableFlag(InstancePtr, Flag) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_FEC_OFFSET) | (Flag));
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified flag in Flag Control Register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+* @param 	Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_DisableFlag(InstancePtr, Flag) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_FEC_OFFSET) & ~(Flag));
+
+/****************************************************************************/
+/**
+*
+* This function loads the sample interval register value into the sample
+* interval counter.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \
+       XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
+							XAPM_SICR_LOAD_MASK);
+
+
+
+/****************************************************************************/
+/**
+*
+* This enables the down count of the sample interval counter.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*	   void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
+							XAPM_SICR_ENABLE_MASK);
+
+
+/****************************************************************************/
+/**
+*
+* This disables the down count of the sample interval counter.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*	    void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK));
+
+/****************************************************************************/
+/**
+*
+* This enables Reset of Metric Counters when Sample Interval Counter lapses.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
+						XAPM_SICR_MCNTR_RST_MASK);
+
+/****************************************************************************/
+/**
+*
+* This disables the down count of the sample interval counter.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \
+       XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK));
+
+/****************************************************************************/
+/**
+*
+* This function enables the ID Filter Masking.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_EnableIDFilter(InstancePtr) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK);
+
+/****************************************************************************/
+/**
+*
+* This function disbles the ID Filter masking.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	None
+*
+* @note		C-Style signature:
+*		void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_DisableIDFilter(InstancePtr) \
+	XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
+			XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK));
+
+/****************************************************************************/
+/**
+*
+* This function samples Metric Counters to Sampled Metric Counters by
+* reading Sample Register and also returns interval. i.e. the number of
+* clocks in between previous read to the current read of sample register.
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return	Interval. i.e. the number of clocks in between previous
+*		read to the current read of sample register.
+*
+* @note		C-Style signature:
+*		u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr)
+*
+*****************************************************************************/
+#define XAxiPmon_SampleMetrics(InstancePtr) \
+       XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+/**
+ * Functions in xaxipmon_sinit.c
+ */
+XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xaxipmon.c
+ */
+s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr,
+		XAxiPmon_Config *ConfigPtr, UINTPTR EffectiveAddr);
+
+s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr);
+
+void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr);
+
+s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr);
+
+void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
+					u16 RangeUpper,	u16 RangeLower);
+
+void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
+				u16 *RangeUpper, u16 *RangeLower);
+
+void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval);
+
+void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval);
+
+s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
+							u8 CounterNum);
+
+s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
+								u8 *Slot);
+void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
+							u32 *CntLowValue);
+
+u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
+
+u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
+
+u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
+
+u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
+
+void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData);
+
+u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr);
+
+s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables);
+
+s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr);
+
+s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval);
+
+s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr);
+
+void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr);
+
+void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr);
+
+void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
+					u16 RangeUpper, u16 RangeLower);
+
+void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
+					u16 *RangeUpper, u16 *RangeLower);
+
+void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr);
+
+void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr);
+
+void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr);
+
+void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr);
+
+void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr);
+
+const char * XAxiPmon_GetMetricName(u8 Metrics);
+
+void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId);
+
+void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId);
+
+u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr);
+
+u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr);
+
+void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param);
+
+void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
+
+void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param);
+
+void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
+
+u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr);
+
+u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr);
+
+u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr);
+
+u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr);
+
+void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask);
+
+void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask);
+
+u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr);
+
+u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr);
+
+
+/**
+ * Functions in xaxipmon_selftest.c
+ */
+s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c
new file mode 100644
index 000000000..2bd473dd5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c
@@ -0,0 +1,127 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xaxipmon.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAxiPmon_Config XAxiPmon_ConfigTable[] =
+{
+	{
+		XPAR_PSU_APM_0_DEVICE_ID,
+		XPAR_PSU_APM_0_BASEADDR,
+		XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH,
+		XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH,
+		XPAR_PSU_APM_0_ENABLE_EVENT_COUNT,
+		XPAR_PSU_APM_0_NUM_MONITOR_SLOTS,
+		XPAR_PSU_APM_0_NUM_OF_COUNTERS,
+		XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT,
+		XPAR_PSU_APM_0_ENABLE_EVENT_LOG,
+		XPAR_PSU_APM_0_FIFO_AXIS_DEPTH,
+		XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH,
+		XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH,
+		XPAR_PSU_APM_0_METRIC_COUNT_SCALE,
+		XPAR_PSU_APM_0_ENABLE_ADVANCED,
+		XPAR_PSU_APM_0_ENABLE_PROFILE,
+		XPAR_PSU_APM_0_ENABLE_TRACE,
+		XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID
+	},
+	{
+		XPAR_PSU_APM_1_DEVICE_ID,
+		XPAR_PSU_APM_1_BASEADDR,
+		XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH,
+		XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH,
+		XPAR_PSU_APM_1_ENABLE_EVENT_COUNT,
+		XPAR_PSU_APM_1_NUM_MONITOR_SLOTS,
+		XPAR_PSU_APM_1_NUM_OF_COUNTERS,
+		XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT,
+		XPAR_PSU_APM_1_ENABLE_EVENT_LOG,
+		XPAR_PSU_APM_1_FIFO_AXIS_DEPTH,
+		XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH,
+		XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH,
+		XPAR_PSU_APM_1_METRIC_COUNT_SCALE,
+		XPAR_PSU_APM_1_ENABLE_ADVANCED,
+		XPAR_PSU_APM_1_ENABLE_PROFILE,
+		XPAR_PSU_APM_1_ENABLE_TRACE,
+		XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID
+	},
+	{
+		XPAR_PSU_APM_2_DEVICE_ID,
+		XPAR_PSU_APM_2_BASEADDR,
+		XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH,
+		XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH,
+		XPAR_PSU_APM_2_ENABLE_EVENT_COUNT,
+		XPAR_PSU_APM_2_NUM_MONITOR_SLOTS,
+		XPAR_PSU_APM_2_NUM_OF_COUNTERS,
+		XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT,
+		XPAR_PSU_APM_2_ENABLE_EVENT_LOG,
+		XPAR_PSU_APM_2_FIFO_AXIS_DEPTH,
+		XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH,
+		XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH,
+		XPAR_PSU_APM_2_METRIC_COUNT_SCALE,
+		XPAR_PSU_APM_2_ENABLE_ADVANCED,
+		XPAR_PSU_APM_2_ENABLE_PROFILE,
+		XPAR_PSU_APM_2_ENABLE_TRACE,
+		XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID
+	},
+	{
+		XPAR_PSU_APM_5_DEVICE_ID,
+		XPAR_PSU_APM_5_BASEADDR,
+		XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH,
+		XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH,
+		XPAR_PSU_APM_5_ENABLE_EVENT_COUNT,
+		XPAR_PSU_APM_5_NUM_MONITOR_SLOTS,
+		XPAR_PSU_APM_5_NUM_OF_COUNTERS,
+		XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT,
+		XPAR_PSU_APM_5_ENABLE_EVENT_LOG,
+		XPAR_PSU_APM_5_FIFO_AXIS_DEPTH,
+		XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH,
+		XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH,
+		XPAR_PSU_APM_5_METRIC_COUNT_SCALE,
+		XPAR_PSU_APM_5_ENABLE_ADVANCED,
+		XPAR_PSU_APM_5_ENABLE_PROFILE,
+		XPAR_PSU_APM_5_ENABLE_TRACE,
+		XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h
new file mode 100644
index 000000000..68ed57aaf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h
@@ -0,0 +1,571 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xaxipmon_hw.h
+* @addtogroup axipmon_v6_3
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the AXI Performance Monitor.
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
+*			v2_01a version of IP.
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET and
+*			XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
+* 5.00a bss   08/26/13  To support new version of IP:
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
+*			Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
+*			Added XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
+*			and XAPM_MASKID_WID_MASK macros.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*
+* 6.2  bss  03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
+*					 Zynq MP APM.
+*
+* 6.3  kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
+* </pre>
+*
+*****************************************************************************/
+#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */
+#define XAXIPMON_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of AXIMONITOR in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * AXI PERFORMANCE MONITOR device.
+ * @{
+ */
+
+#define XAPM_GCC_HIGH_OFFSET		0x00000000U	/**< Global Clock Counter
+							32 to 63 bits  */
+#define XAPM_GCC_LOW_OFFSET		0x00000004U	/**< Global Clock Counter Lower
+							0-31 bits  */
+#define XAPM_SI_HIGH_OFFSET		0x00000020U	/**< Sample Interval MSB */
+#define XAPM_SI_LOW_OFFSET		0x00000024U	/**< Sample Interval LSB */
+#define XAPM_SICR_OFFSET		0x00000028U	/**< Sample Interval Control
+							Register */
+#define XAPM_SR_OFFSET			0x0000002CU	/**< Sample Register */
+#define XAPM_GIE_OFFSET			0x00000030U	/**< Global Interrupt Enable
+							Register */
+#define XAPM_IE_OFFSET			0x00000034U	/**< Interrupt Enable Register */
+#define XAPM_IS_OFFSET			0x00000038U	/**< Interrupt Status Register */
+
+#define XAPM_MSR0_OFFSET		0x00000044U	/**< Metric Selector 0 Register */
+#define XAPM_MSR1_OFFSET		0x00000048U	/**< Metric Selector 1 Register */
+#define XAPM_MSR2_OFFSET		0x0000004CU	/**< Metric Selector 2 Register */
+
+#define XAPM_MC0_OFFSET			0x00000100U	/**< Metric Counter 0 Register */
+#define XAPM_INC0_OFFSET		0x00000104U	/**< Incrementer 0 Register */
+#define XAPM_RANGE0_OFFSET		0x00000108U	/**< Range 0 Register */
+#define XAPM_MC0LOGEN_OFFSET		0x0000010CU	/**< Metric Counter 0
+							Log Enable Register */
+#define XAPM_MC1_OFFSET			0x00000110U	/**< Metric Counter 1 Register */
+#define XAPM_INC1_OFFSET		0x00000114U	/**< Incrementer 1 Register */
+#define XAPM_RANGE1_OFFSET		0x00000118U	/**< Range 1 Register */
+#define XAPM_MC1LOGEN_OFFSET		0x0000011CU	/**< Metric Counter 1
+							Log Enable Register */
+#define XAPM_MC2_OFFSET			0x00000120U	/**< Metric Counter 2 Register */
+#define XAPM_INC2_OFFSET		0x00000124U	/**< Incrementer 2 Register */
+#define XAPM_RANGE2_OFFSET		0x00000128U	/**< Range 2 Register */
+#define XAPM_MC2LOGEN_OFFSET		0x0000012CU	/**< Metric Counter 2
+							Log Enable Register */
+#define XAPM_MC3_OFFSET			0x00000130U	/**< Metric Counter 3 Register */
+#define XAPM_INC3_OFFSET		0x00000134U	/**< Incrementer 3 Register */
+#define XAPM_RANGE3_OFFSET		0x00000138U	/**< Range 3 Register */
+#define XAPM_MC3LOGEN_OFFSET		0x0000013CU	/**< Metric Counter 3
+							Log Enable Register */
+#define XAPM_MC4_OFFSET			0x00000140U	/**< Metric Counter 4 Register */
+#define XAPM_INC4_OFFSET		0x00000144U	/**< Incrementer 4 Register */
+#define XAPM_RANGE4_OFFSET		0x00000148U	/**< Range 4 Register */
+#define XAPM_MC4LOGEN_OFFSET		0x0000014CU	/**< Metric Counter 4
+							Log Enable Register */
+#define XAPM_MC5_OFFSET			0x00000150U	/**< Metric Counter 5
+							Register */
+#define XAPM_INC5_OFFSET		0x00000154U	/**< Incrementer 5 Register */
+#define XAPM_RANGE5_OFFSET		0x00000158U	/**< Range 5 Register */
+#define XAPM_MC5LOGEN_OFFSET		0x0000015CU	/**< Metric Counter 5
+							Log Enable Register */
+#define XAPM_MC6_OFFSET			0x00000160U	/**< Metric Counter 6
+							Register */
+#define XAPM_INC6_OFFSET		0x00000164U	/**< Incrementer 6 Register */
+#define XAPM_RANGE6_OFFSET		0x00000168U	/**< Range 6 Register */
+#define XAPM_MC6LOGEN_OFFSET		0x0000016CU	/**< Metric Counter 6
+							Log Enable Register */
+#define XAPM_MC7_OFFSET			0x00000170U	/**< Metric Counter 7
+							Register */
+#define XAPM_INC7_OFFSET		0x00000174U	/**< Incrementer 7 Register */
+#define XAPM_RANGE7_OFFSET		0x00000178U	/**< Range 7 Register */
+#define XAPM_MC7LOGEN_OFFSET		0x0000017CU	/**< Metric Counter 7
+							Log Enable Register */
+#define XAPM_MC8_OFFSET			0x00000180U	/**< Metric Counter 8
+							Register */
+#define XAPM_INC8_OFFSET		0x00000184U	/**< Incrementer 8 Register */
+#define XAPM_RANGE8_OFFSET		0x00000188U	/**< Range 8 Register */
+#define XAPM_MC8LOGEN_OFFSET		0x0000018CU	/**< Metric Counter 8
+							Log Enable Register */
+#define XAPM_MC9_OFFSET			0x00000190U	/**< Metric Counter 9
+							Register */
+#define XAPM_INC9_OFFSET		0x00000194U	/**< Incrementer 9 Register */
+#define XAPM_RANGE9_OFFSET		0x00000198U	/**< Range 9 Register */
+#define XAPM_MC9LOGEN_OFFSET		0x0000019CU	/**< Metric Counter 9
+							Log Enable Register */
+#define XAPM_SMC0_OFFSET		0x00000200U	/**< Sampled Metric Counter
+							0 Register */
+#define XAPM_SINC0_OFFSET		0x00000204U	/**< Sampled Incrementer
+							0 Register */
+#define XAPM_SMC1_OFFSET		0x00000210U	/**< Sampled Metric Counter
+							1 Register */
+#define XAPM_SINC1_OFFSET		0x00000214U	/**< Sampled Incrementer
+							1 Register */
+#define XAPM_SMC2_OFFSET		0x00000220U	/**< Sampled Metric Counter
+							2 Register */
+#define XAPM_SINC2_OFFSET		0x00000224U	/**< Sampled Incrementer
+							2 Register */
+#define XAPM_SMC3_OFFSET		0x00000230U	/**< Sampled Metric Counter
+							3 Register */
+#define XAPM_SINC3_OFFSET		0x00000234U	/**< Sampled Incrementer
+							3 Register */
+#define XAPM_SMC4_OFFSET		0x00000240U	/**< Sampled Metric Counter
+							4 Register */
+#define XAPM_SINC4_OFFSET		0x00000244U	/**< Sampled Incrementer
+							4 Register */
+#define XAPM_SMC5_OFFSET		0x00000250U	/**< Sampled Metric Counter
+							5 Register */
+#define XAPM_SINC5_OFFSET		0x00000254U	/**< Sampled Incrementer
+							5 Register */
+#define XAPM_SMC6_OFFSET		0x00000260U	/**< Sampled Metric Counter
+							6 Register */
+#define XAPM_SINC6_OFFSET		0x00000264U	/**< Sampled Incrementer
+							6 Register */
+#define XAPM_SMC7_OFFSET		0x00000270U	/**< Sampled Metric Counter
+							7 Register */
+#define XAPM_SINC7_OFFSET		0x00000274U	/**< Sampled Incrementer
+							7 Register */
+#define XAPM_SMC8_OFFSET		0x00000280U	/**< Sampled Metric Counter
+							8 Register */
+#define XAPM_SINC8_OFFSET		0x00000284U	/**< Sampled Incrementer
+							8 Register */
+#define XAPM_SMC9_OFFSET		0x00000290U	/**< Sampled Metric Counter
+							9 Register */
+#define XAPM_SINC9_OFFSET		0x00000294U	/**< Sampled Incrementer
+							9 Register */
+
+#define XAPM_MC10_OFFSET		0x000001A0U	/**< Metric Counter 10
+							Register */
+#define XAPM_MC11_OFFSET		0x000001B0U	/**< Metric Counter 11
+							Register */
+#define XAPM_MC12_OFFSET		0x00000500U	/**< Metric Counter 12
+							Register */
+#define XAPM_MC13_OFFSET		0x00000510U	/**< Metric Counter 13
+							Register */
+#define XAPM_MC14_OFFSET		0x00000520U	/**< Metric Counter 14
+							Register */
+#define XAPM_MC15_OFFSET		0x00000530U	/**< Metric Counter 15
+							Register */
+#define XAPM_MC16_OFFSET		0x00000540U	/**< Metric Counter 16
+							Register */
+#define XAPM_MC17_OFFSET		0x00000550U	/**< Metric Counter 17
+							Register */
+#define XAPM_MC18_OFFSET		0x00000560U	/**< Metric Counter 18
+							Register */
+#define XAPM_MC19_OFFSET		0x00000570U	/**< Metric Counter 19
+							Register */
+#define XAPM_MC20_OFFSET		0x00000580U	/**< Metric Counter 20
+							Register */
+#define XAPM_MC21_OFFSET		0x00000590U	/**< Metric Counter 21
+							Register */
+#define XAPM_MC22_OFFSET		0x000005A0U	/**< Metric Counter 22
+							Register */
+#define XAPM_MC23_OFFSET		0x000005B0U	/**< Metric Counter 23
+							Register */
+#define XAPM_MC24_OFFSET		0x00000700U	/**< Metric Counter 24
+							Register */
+#define XAPM_MC25_OFFSET		0x00000710U	/**< Metric Counter 25
+							Register */
+#define XAPM_MC26_OFFSET		0x00000720U	/**< Metric Counter 26
+							Register */
+#define XAPM_MC27_OFFSET		0x00000730U	/**< Metric Counter 27
+							Register */
+#define XAPM_MC28_OFFSET		0x00000740U	/**< Metric Counter 28
+							Register */
+#define XAPM_MC29_OFFSET		0x00000750U	/**< Metric Counter 29
+							Register */
+#define XAPM_MC30_OFFSET		0x00000760U	/**< Metric Counter 30
+							Register */
+#define XAPM_MC31_OFFSET		0x00000770U	/**< Metric Counter 31
+							Register */
+#define XAPM_MC32_OFFSET		0x00000780U	/**< Metric Counter 32
+							Register */
+#define XAPM_MC33_OFFSET		0x00000790U	/**< Metric Counter 33
+							Register */
+#define XAPM_MC34_OFFSET		0x000007A0U	/**< Metric Counter 34
+							Register */
+#define XAPM_MC35_OFFSET		0x000007B0U	/**< Metric Counter 35
+							Register */
+#define XAPM_MC36_OFFSET		0x00000900U	/**< Metric Counter 36
+							Register */
+#define XAPM_MC37_OFFSET		0x00000910U	/**< Metric Counter 37
+							Register */
+#define XAPM_MC38_OFFSET		0x00000920U	/**< Metric Counter 38
+							Register */
+#define XAPM_MC39_OFFSET		0x00000930U	/**< Metric Counter 39
+							Register */
+#define XAPM_MC40_OFFSET		0x00000940U	/**< Metric Counter 40
+							Register */
+#define XAPM_MC41_OFFSET		0x00000950U	/**< Metric Counter 41
+							Register */
+#define XAPM_MC42_OFFSET		0x00000960U	/**< Metric Counter 42
+							Register */
+#define XAPM_MC43_OFFSET		0x00000970U	/**< Metric Counter 43
+							Register */
+#define XAPM_MC44_OFFSET		0x00000980U	/**< Metric Counter 44
+							Register */
+#define XAPM_MC45_OFFSET		0x00000990U	/**< Metric Counter 45
+							Register */
+#define XAPM_MC46_OFFSET		0x000009A0U	/**< Metric Counter 46
+							Register */
+#define XAPM_MC47_OFFSET		0x000009B0U	/**< Metric Counter 47
+							Register */
+
+#define XAPM_SMC10_OFFSET		0x000002A0U	/**< Sampled Metric Counter
+							10 Register */
+#define XAPM_SMC11_OFFSET		0x000002B0U	/**< Sampled Metric Counter
+							11 Register */
+#define XAPM_SMC12_OFFSET		0x00000600U	/**< Sampled Metric Counter
+							12 Register */
+#define XAPM_SMC13_OFFSET		0x00000610U	/**< Sampled Metric Counter
+							13 Register */
+#define XAPM_SMC14_OFFSET		0x00000620U	/**< Sampled Metric Counter
+							14 Register */
+#define XAPM_SMC15_OFFSET		0x00000630U	/**< Sampled Metric Counter
+							15 Register */
+#define XAPM_SMC16_OFFSET		0x00000640U	/**< Sampled Metric Counter
+							16 Register */
+#define XAPM_SMC17_OFFSET		0x00000650U	/**< Sampled Metric Counter
+							17 Register */
+#define XAPM_SMC18_OFFSET		0x00000660U	/**< Sampled Metric Counter
+							18 Register */
+#define XAPM_SMC19_OFFSET		0x00000670U	/**< Sampled Metric Counter
+							19 Register */
+#define XAPM_SMC20_OFFSET		0x00000680U	/**< Sampled Metric Counter
+							20 Register */
+#define XAPM_SMC21_OFFSET		0x00000690U	/**< Sampled Metric Counter
+							21 Register */
+#define XAPM_SMC22_OFFSET		0x000006A0U	/**< Sampled Metric Counter
+							22 Register */
+#define XAPM_SMC23_OFFSET		0x000006B0U	/**< Sampled Metric Counter
+							23 Register */
+#define XAPM_SMC24_OFFSET		0x00000800U	/**< Sampled Metric Counter
+							24 Register */
+#define XAPM_SMC25_OFFSET		0x00000810U	/**< Sampled Metric Counter
+							25 Register */
+#define XAPM_SMC26_OFFSET		0x00000820U	/**< Sampled Metric Counter
+							26 Register */
+#define XAPM_SMC27_OFFSET		0x00000830U	/**< Sampled Metric Counter
+							27 Register */
+#define XAPM_SMC28_OFFSET		0x00000840U	/**< Sampled Metric Counter
+							28 Register */
+#define XAPM_SMC29_OFFSET		0x00000850U	/**< Sampled Metric Counter
+							29 Register */
+#define XAPM_SMC30_OFFSET		0x00000860U	/**< Sampled Metric Counter
+							30 Register */
+#define XAPM_SMC31_OFFSET		0x00000870U	/**< Sampled Metric Counter
+							31 Register */
+#define XAPM_SMC32_OFFSET		0x00000880U	/**< Sampled Metric Counter
+							32 Register */
+#define XAPM_SMC33_OFFSET		0x00000890U	/**< Sampled Metric Counter
+							33 Register */
+#define XAPM_SMC34_OFFSET		0x000008A0U	/**< Sampled Metric Counter
+							34 Register */
+#define XAPM_SMC35_OFFSET		0x000008B0U	/**< Sampled Metric Counter
+							35 Register */
+#define XAPM_SMC36_OFFSET		0x00000A00U	/**< Sampled Metric Counter
+							36 Register */
+#define XAPM_SMC37_OFFSET		0x00000A10U	/**< Sampled Metric Counter
+							37 Register */
+#define XAPM_SMC38_OFFSET		0x00000A20U	/**< Sampled Metric Counter
+							38 Register */
+#define XAPM_SMC39_OFFSET		0x00000A30U	/**< Sampled Metric Counter
+							39 Register */
+#define XAPM_SMC40_OFFSET		0x00000A40U	/**< Sampled Metric Counter
+							40 Register */
+#define XAPM_SMC41_OFFSET		0x00000A50U	/**< Sampled Metric Counter
+							41 Register */
+#define XAPM_SMC42_OFFSET		0x00000A60U	/**< Sampled Metric Counter
+							42 Register */
+#define XAPM_SMC43_OFFSET		0x00000A70U	/**< Sampled Metric Counter
+							43 Register */
+#define XAPM_SMC44_OFFSET		0x00000A80U	/**< Sampled Metric Counter
+							44 Register */
+#define XAPM_SMC45_OFFSET		0x00000A90U	/**< Sampled Metric Counter
+							45 Register */
+#define XAPM_SMC46_OFFSET		0x00000AA0U	/**< Sampled Metric Counter
+							46 Register */
+#define XAPM_SMC47_OFFSET		0x00000AB0U	/**< Sampled Metric Counter
+							47 Register */
+
+#define XAPM_CTL_OFFSET		 	0x00000300U	/**< Control Register */
+
+#define XAPM_ID_OFFSET			0x00000304U	/**< Latency ID Register */
+
+#define XAPM_IDMASK_OFFSET		0x00000308U	/**< ID Mask Register */
+
+#define XAPM_RID_OFFSET			0x0000030CU	/**< Latency Write ID Register */
+
+#define XAPM_RIDMASK_OFFSET		0x00000310U	/**< Read ID Mask Register */
+
+#define XAPM_FEC_OFFSET			0x00000400U	/**< Flag Enable
+							Control Register */
+
+#define XAPM_SWD_OFFSET			0x00000404U	/**< Software-written
+							Data Register */
+
+/* @} */
+
+/**
+ * @name AXI Monitor Sample Interval Control Register mask(s)
+ * @{
+ */
+
+#define XAPM_SICR_MCNTR_RST_MASK	0x00000100U /**< Enable the Metric
+							Counter Reset */
+#define XAPM_SICR_LOAD_MASK		0x00000002U /**< Load the Sample Interval
+							*  Register Value into the
+							*  counter */
+#define XAPM_SICR_ENABLE_MASK		0x00000001U /**< Enable the downcounter */
+
+/*@}*/
+
+
+/** @name Interrupt Status/Enable Register Bit Definitions and Masks
+ *  @{
+ */
+
+#define XAPM_IXR_MC9_OVERFLOW_MASK	0x00001000U	/**< Metric Counter 9
+							  *  Overflow> */
+#define XAPM_IXR_MC8_OVERFLOW_MASK	0x00000800U	/**< Metric Counter 8
+							  *  Overflow> */
+#define XAPM_IXR_MC7_OVERFLOW_MASK   	0x00000400U	/**< Metric Counter 7
+							  *  Overflow> */
+#define XAPM_IXR_MC6_OVERFLOW_MASK   	0x00000200U	/**< Metric Counter 6
+							  *  Overflow> */
+#define XAPM_IXR_MC5_OVERFLOW_MASK   	0x00000100U	/**< Metric Counter 5
+							  *  Overflow> */
+#define XAPM_IXR_MC4_OVERFLOW_MASK   	0x00000080U	/**< Metric Counter 4
+							  *  Overflow> */
+#define XAPM_IXR_MC3_OVERFLOW_MASK   	0x00000040U	/**< Metric Counter 3
+							  *  Overflow> */
+#define XAPM_IXR_MC2_OVERFLOW_MASK   	0x00000020U	/**< Metric Counter 2
+							  *  Overflow> */
+#define XAPM_IXR_MC1_OVERFLOW_MASK   	0x00000010U	/**< Metric Counter 1
+							  *  Overflow> */
+#define XAPM_IXR_MC0_OVERFLOW_MASK   	0x00000008U	/**< Metric Counter 0
+							  *  Overflow> */
+#define XAPM_IXR_FIFO_FULL_MASK   	0x00000004U	/**< Event Log FIFO
+							  *  full> */
+#define XAPM_IXR_SIC_OVERFLOW_MASK   	0x00000002U	/**< Sample Interval
+							  * Counter Overflow> */
+#define XAPM_IXR_GCC_OVERFLOW_MASK	0x00000001U	/**< Global Clock Counter
+						          *  Overflow> */
+#define XAPM_IXR_ALL_MASK		(XAPM_IXR_SIC_OVERFLOW_MASK | \
+					XAPM_IXR_GCC_OVERFLOW_MASK |  \
+					XAPM_IXR_FIFO_FULL_MASK | \
+					XAPM_IXR_MC0_OVERFLOW_MASK | \
+					XAPM_IXR_MC1_OVERFLOW_MASK | \
+					XAPM_IXR_MC2_OVERFLOW_MASK | \
+					XAPM_IXR_MC3_OVERFLOW_MASK | \
+					XAPM_IXR_MC4_OVERFLOW_MASK | \
+					XAPM_IXR_MC5_OVERFLOW_MASK | \
+					XAPM_IXR_MC6_OVERFLOW_MASK | \
+					XAPM_IXR_MC7_OVERFLOW_MASK | \
+					XAPM_IXR_MC8_OVERFLOW_MASK | \
+					XAPM_IXR_MC9_OVERFLOW_MASK)
+/* @} */
+
+/**
+ * @name AXI Monitor Control Register mask(s)
+ * @{
+ */
+
+#define XAPM_CR_FIFO_RESET_MASK			0x02000000U
+						/**< FIFO Reset */
+#define XAPM_CR_GCC_RESET_MASK			0x00020000U
+						/**< Global Clk
+						  Counter Reset */
+#define XAPM_CR_GCC_ENABLE_MASK			0x00010000U
+						/**< Global Clk
+						   Counter Enable */
+#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK  	0x00000200U
+						/**< Enable External trigger
+						to start event Log */
+#define XAPM_CR_EVENTLOG_ENABLE_MASK  		0x00000100U
+						/**< Event Log Enable */
+
+#define XAPM_CR_RDLATENCY_END_MASK  		0x00000080U
+						/**< Write Latency
+							End point */
+#define XAPM_CR_RDLATENCY_START_MASK  		0x00000040U
+						/**< Read Latency
+							Start point */
+#define XAPM_CR_WRLATENCY_END_MASK  		0x00000020U
+						/**< Write Latency
+							End point */
+#define XAPM_CR_WRLATENCY_START_MASK  		0x00000010U
+						/**< Write Latency
+							Start point */
+#define XAPM_CR_IDFILTER_ENABLE_MASK  		0x00000008U
+						/**< ID Filter Enable */
+
+#define XAPM_CR_MCNTR_EXTTRIGGER_MASK  	 	0x00000004U
+						/**< Enable External
+						   trigger to start
+						   Metric Counters  */
+#define XAPM_CR_MCNTR_RESET_MASK   		0x00000002U
+						/**< Metrics Counter
+						   Reset */
+#define XAPM_CR_MCNTR_ENABLE_MASK  		0x00000001U
+						/**< Metrics Counter
+					           Enable */
+/*@}*/
+
+/**
+ * @name AXI Monitor ID Register mask(s)
+ * @{
+ */
+
+#define XAPM_ID_RID_MASK			0xFFFF0000U /**< Read ID */
+
+#define XAPM_ID_WID_MASK			0x0000FFFFU /**< Write ID */
+
+/*@}*/
+
+/**
+ * @name AXI Monitor ID Mask Register mask(s)
+ * @{
+ */
+
+#define XAPM_MASKID_RID_MASK			0xFFFF0000U /**< Read ID Mask */
+
+#define XAPM_MASKID_WID_MASK			0x0000FFFFU /**< Write ID Mask*/
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the AXI Performance Monitor device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \
+		(Xil_In32((BaseAddress) + (RegOffset)))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the AXI Performance Monitor device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAxiPmon_WriteReg(u32 BaseAddress,
+*					u32 RegOffset,u32 Data)
+*
+******************************************************************************/
+#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \
+		(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c
new file mode 100644
index 000000000..df2a9da66
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c
@@ -0,0 +1,152 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxipmon_selftest.c
+* @addtogroup axipmon_v6_3
+* @{
+*
+* This file contains a diagnostic self test function for the XAxiPmon driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See XAxiPmon.h for more information.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss  02/24/12 First release
+* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
+* 6.3   kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xaxipmon.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Range Registers of Incrementers
+ */
+
+#define XAPM_TEST_RANGEUPPER_VALUE	16U /**< Test Value for Upper Range */
+#define XAPM_TEST_RANGELOWER_VALUE	 8U /**< Test Value for Lower Range */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Resets the device,
+*	- Writes a value into the Range Registers of Incrementer 0 and reads
+*	  it back for comparison.
+*	- Resets the device again.
+*
+*
+* @param	InstancePtr is a pointer to the XAxiPmon instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the Range Register of
+*		  Incrementer 0 is the same as the value written.
+*		- XST_FAILURE Otherwise
+*
+* @note		This is a destructive test in that resets of the device are
+*		performed. Refer to the device specification for the
+*		device status after the reset operation.
+*
+******************************************************************************/
+s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr)
+{
+	s32 Status;
+	u16 RangeUpper = 0U;
+	u16 RangeLower = 0U;
+
+	/*
+	 * Assert the argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Reset the device to get it back to its default state
+	 */
+	(void)XAxiPmon_ResetMetricCounter(InstancePtr);
+	XAxiPmon_ResetGlobalClkCounter(InstancePtr);
+
+	/*
+	 * Write a value into the Incrementer register and
+	 * read it back, and do the comparison
+	 */
+	XAxiPmon_SetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0,
+					XAPM_TEST_RANGEUPPER_VALUE,
+					XAPM_TEST_RANGELOWER_VALUE);
+
+	XAxiPmon_GetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0,
+					&RangeUpper, &RangeLower);
+
+	if ((RangeUpper == XAPM_TEST_RANGEUPPER_VALUE) &&
+			(RangeLower == XAPM_TEST_RANGELOWER_VALUE)) {
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Reset the device again to its default state.
+	 */
+	(void)XAxiPmon_ResetMetricCounter(InstancePtr);
+	XAxiPmon_ResetGlobalClkCounter(InstancePtr);
+
+	/*
+	 * Return the test result.
+	 */
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c
new file mode 100644
index 000000000..737d80b48
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxipmon_sinit.c
+* @addtogroup axipmon_v6_3
+* @{
+*
+* This file contains the implementation of the XAxiPmon driver's static
+* initialization functionality.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss  02/27/12 First release
+* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
+* 6.3   kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xaxipmon.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XAxiPmon_Config XAxiPmon_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks up the device configuration based on the unique device ID.
+* The table XAxiPmon_ConfigTable contains the configuration info for each device
+* in the system.
+*
+* @param	DeviceId contains the ID of the device for which the
+*		device configuration pointer is to be returned.
+*
+* @return
+*		- A pointer to the configuration found.
+*		- NULL if the specified device ID was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId)
+{
+	XAxiPmon_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0U; Index < (u32)XPAR_XAXIPMON_NUM_INSTANCES; Index++) {
+		if (XAxiPmon_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XAxiPmon_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XAxiPmon_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile
deleted file mode 100644
index 55565709b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xcanps_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling canps"
-
-xcanps_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xcanps_includes
-
-xcanps_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c
deleted file mode 100644
index 243b3a81b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c
+++ /dev/null
@@ -1,1205 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcanps.c
-* @addtogroup canps_v3_0
-* @{
-*
-* Functions in this file are the minimum required functions for the XCanPs
-* driver. See xcanps.h for a detailed description of the driver.
-*
-* @note 	None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00a xd/sv  01/12/10 First release
-* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
-* 			XCanPs_GetTxIntrWatermark.
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcanps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void);
-
-/*****************************************************************************/
-/*
-*
-* This function initializes a XCanPs instance/driver.
-*
-* The initialization entails:
-* - Initialize all members of the XCanPs structure.
-* - Reset the CAN device. The CAN device will enter Configuration Mode
-*   immediately after the reset is finished.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	ConfigPtr points to the XCanPs device configuration structure.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. If the address translation is not used then the
-*		physical address is passed.
-*		Unexpected errors may occur if the address mapping is changed
-*		after this function is invoked.
-*
-* @return	XST_SUCCESS always.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
-				u32 EffectiveAddr)
-{
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	/*
-	 * Set some default values for instance data, don't indicate the device
-	 * is ready to use until everything has been initialized successfully.
-	 */
-	InstancePtr->IsReady = 0U;
-	InstancePtr->CanConfig.BaseAddr = EffectiveAddr;
-	InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId;
-
-	/*
-	 * Set all handlers to stub values, let user configure this data later.
-	 */
-	InstancePtr->SendHandler = (XCanPs_SendRecvHandler) StubHandler;
-	InstancePtr->RecvHandler = (XCanPs_SendRecvHandler) StubHandler;
-	InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) StubHandler;
-	InstancePtr->EventHandler = (XCanPs_EventHandler) StubHandler;
-
-	/*
-	 * Indicate the component is now ready to use.
-	 */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-	/*
-	 * Reset the device to get it into its initial state.
-	 */
-	XCanPs_Reset(InstancePtr);
-
-	Status = XST_SUCCESS;
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function resets the CAN device. Calling this function resets the device
-* immediately, and any pending transmission or reception is terminated at once.
-* Both Object Layer and Transfer Layer are reset. This function does not reset
-* the Physical Layer. All registers are reset to the default values, and no
-* previous status will be restored. TX FIFO, RX FIFO and TX High Priority
-* Buffer are also reset.
-*
-* When a reset is required due to an internal error, the driver notifies the
-* upper layer software of this need through the error status code or interrupts.
-* The upper layer software is responsible for calling this Reset function and
-* then re-configuring the device.
-*
-* The CAN device will be in Configuration Mode immediately after this function
-* returns.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_Reset(XCanPs *InstancePtr)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_SRR_OFFSET, \
-			   XCANPS_SRR_SRST_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This routine returns the current operation mode of the CAN device.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return
-* 		- XCANPS_MODE_CONFIG if the device is in Configuration Mode.
-* 		- XCANPS_MODE_SLEEP if the device is in Sleep Mode.
-* 		- XCANPS_MODE_NORMAL if the device is in Normal Mode.
-* 		- XCANPS_MODE_LOOPBACK if the device is in Loop Back Mode.
-* 		- XCANPS_MODE_SNOOP if the device is in Snoop Mode.
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XCanPs_GetMode(XCanPs *InstancePtr)
-{
-	u32 StatusReg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	StatusReg = XCanPs_GetStatus(InstancePtr);
-
-	if ((StatusReg & XCANPS_SR_CONFIG_MASK) != (u32)0) {
-		return (u8)XCANPS_MODE_CONFIG;
-
-	}
-	else if ((StatusReg & XCANPS_SR_SLEEP_MASK) != (u32)0) {
-		return (u8)XCANPS_MODE_SLEEP;
-
-	}
-	else if ((StatusReg & XCANPS_SR_NORMAL_MASK) != (u32)0) {
-		if ((StatusReg & XCANPS_SR_SNOOP_MASK) != (u32)0) {
-			return (u8)XCANPS_MODE_SNOOP;
-		} else {
-			return (u8)XCANPS_MODE_NORMAL;
-		}
-	}
-	else {
-		/*
-		 * If this line is reached, the device is in Loop Back Mode.
-		 */
-		return (u8)XCANPS_MODE_LOOPBACK;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function allows the CAN device to enter one of the following operation
-* modes:
-*	- Configuration Mode: Pass in parameter XCANPS_MODE_CONFIG
-*	- Sleep Mode: Pass in parameter XCANPS_MODE_SLEEP
-*	- Normal Mode: Pass in parameter XCANPS_MODE_NORMAL
-*	- Loop Back Mode: Pass in parameter XCANPS_MODE_LOOPBACK.
-*	- Snoop Mode: Pass in parameter XCANPS_MODE_SNOOP.
-*
-* Read the xcanps.h file and device specification for detailed description of
-* each operation mode.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	OperationMode specify which operation mode to enter. Valid value
-*		is any of XCANPS_MODE_* defined in xcanps.h. Multiple modes
-*		can not be entered at the same time.
-*
-* @return	None.
-*
-* @note
-*
-* This function does NOT ensure CAN device enters the specified operation mode
-* before it returns the control to the caller. The caller is responsible for
-* checking current operation mode using XCanPs_GetMode().
-*
-******************************************************************************/
-void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode)
-{
-	u8 CurrentMode;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((OperationMode == (u8)XCANPS_MODE_CONFIG) ||
-			(OperationMode == (u8)XCANPS_MODE_SLEEP) ||
-			(OperationMode == (u8)XCANPS_MODE_NORMAL) ||
-			(OperationMode == (u8)XCANPS_MODE_LOOPBACK) ||
-			(OperationMode == (u8)XCANPS_MODE_SNOOP));
-
-	CurrentMode = XCanPs_GetMode(InstancePtr);
-
-	/*
-	 * If current mode is Normal Mode and the mode to enter is Sleep Mode,
-	 * or if current mode is Sleep Mode and the mode to enter is Normal
-	 * Mode, no transition through Configuration Mode is needed.
-	 */
-	if ((CurrentMode == (u8)XCANPS_MODE_NORMAL) &&
-		(OperationMode == (u8)XCANPS_MODE_SLEEP)) {
-		/*
-		 * Normal Mode ---> Sleep Mode
-		 */
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
-		return;
-
-	} else if ((CurrentMode == (u8)XCANPS_MODE_SLEEP) &&
-		 (OperationMode == (u8)XCANPS_MODE_NORMAL)) {
-		/*
-		 * Sleep Mode ---> Normal Mode
-		 */
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_MSR_OFFSET, 0U);
-		return;
-	}
-	else {
-		/*This else was made for misra-c compliance*/
-		;
-	}
-
-	/*
-	 * If the mode transition is not any of the two cases above, CAN must
-	 * enter Configuration Mode before switching into the target operation
-	 * mode.
-	 */
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_SRR_OFFSET, 0U);
-
-	/*
-	 * Check if the device has entered Configuration Mode, if not, return to
-	 * the caller.
-	 */
-	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
-		return;
-	}
-
-	switch (OperationMode) {
-		case XCANPS_MODE_CONFIG:
-			/*
-			 * As CAN is in Configuration Mode already.
-			 * Nothing is needed to be done here.
-			 */
-			break;
-
-		case XCANPS_MODE_SLEEP:
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-			break;
-
-		case XCANPS_MODE_NORMAL:
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_MSR_OFFSET, 0U);
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-			break;
-
-		case XCANPS_MODE_LOOPBACK:
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK);
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-			break;
-
-		case XCANPS_MODE_SNOOP:
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK);
-			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-			break;
-
-		default:
-			/*This default was made for misra-c compliance*/
-			break;
-
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns Status value from Status Register (SR). Use the
-* XCANPS_SR_* constants defined in xcanps_hw.h to interpret the returned
-* value.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	The 32-bit value read from Status Register.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XCanPs_GetStatus(XCanPs *InstancePtr)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_SR_OFFSET);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function reads Receive and Transmit error counters.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	RxErrorCount is a pointer to data in which the Receive Error
-*		counter value is returned.
-* @param	TxErrorCount is a pointer to data in which the Transmit Error
-*		counter value is returned.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
-				 u8 *TxErrorCount)
-{
-	u32 ErrorCount;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(RxErrorCount != NULL);
-	Xil_AssertVoid(TxErrorCount != NULL);
-	/*
-	 * Read Error Counter Register and parse it.
-	 */
-	ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_ECR_OFFSET);
-	*RxErrorCount = (u8)((ErrorCount & XCANPS_ECR_REC_MASK) >>
-				XCANPS_ECR_REC_SHIFT);
-	*TxErrorCount = (u8)(ErrorCount & XCANPS_ECR_TEC_MASK);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function reads Error Status value from Error Status Register (ESR). Use
-* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the
-* returned value.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	The 32-bit value read from Error Status Register.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_ESR_OFFSET);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function clears Error Status bit(s) previously set in Error
-* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h
-* to create the value to pass in. If a bit was cleared in Error Status Register
-* before this function is called, it will not be modified.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @param	Mask is he 32-bit mask used to clear bits in Error Status
-*		Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear
-*		multiple bits.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_ESR_OFFSET, Mask);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sends a CAN Frame. If the TX FIFO is not full then the given
-* frame is written into the the TX FIFO otherwise, it returns an error code
-* immediately.
-* This function does not wait for the given frame being sent to CAN bus.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	FramePtr is a pointer to a 32-bit aligned buffer containing the
-*		CAN frame to be sent.
-*
-* @return
-*		- XST_SUCCESS if TX FIFO was not full and the given frame was
-*		written into the FIFO.
-*		- XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the
-*		given frame.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr)
-{
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(FramePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) {
-		Status = XST_FIFO_NO_ROOM;
-	} else {
-
-		/*
-		 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
-		 */
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXFIFO_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2]));
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXFIFO_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3]));
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function receives a CAN Frame. This function first checks if RX FIFO is
-* empty, if not, it then reads a frame from the RX FIFO into the given buffer.
-* This function returns error code immediately if there is no frame in the RX
-* FIFO.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	FramePtr is a pointer to a 32-bit aligned buffer where the CAN
-*		frame to be written.
-*
-* @return
-*		- XST_SUCCESS if RX FIFO was not empty and a frame was read from
-*		RX FIFO successfully and written into the given buffer.
-*		- XST_NO_DATA if there is no frame to be received from the FIFO.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
-{
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(FramePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) {
-		Status = XST_NO_DATA;
-	} else {
-
-		/*
-		 * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device.
-		 */
-		FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						XCANPS_RXFIFO_ID_OFFSET);
-		FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						XCANPS_RXFIFO_DLC_OFFSET);
-		FramePtr[2] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						XCANPS_RXFIFO_DW1_OFFSET));
-		FramePtr[3] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						XCANPS_RXFIFO_DW2_OFFSET));
-
-		/*
-		 * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call
-		 * returns correct RX FIFO occupancy/empty condition.
-		 */
-		XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK);
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine sends a CAN High Priority frame. This function first checks if
-* TX High Priority Buffer is empty. If yes, it then writes the given frame into
-* the Buffer. If not, this function returns immediately. This function does not
-* wait for the given frame being sent to CAN bus.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	FramePtr is a pointer to a 32-bit aligned buffer containing the
-*		CAN High Priority frame to be sent.
-*
-* @return
-*		- XST_SUCCESS if TX High Priority Buffer was not full and the
-*		given frame was written into the buffer.
-*		- XST_FIFO_NO_ROOM if there is no room in the TX High Priority
-*		Buffer for this frame.
-*
-* @note
-*
-* If the frame needs to be sent immediately and not delayed by processor's
-* interrupt handling, the caller should disable interrupt at processor
-* level before invoking this function.
-*
-******************************************************************************/
-s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr)
-{
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(FramePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) {
-		Status = XST_FIFO_NO_ROOM;
-	} else {
-
-		/*
-		 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
-		 */
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXHPB_ID_OFFSET, FramePtr[0]);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXHPB_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2]));
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_TXHPB_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3]));
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine enables individual acceptance filters. Up to 4 filters could
-* be enabled.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	FilterIndexes specifies which filter(s) to enable. Use
-*		any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or"
-*		multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
-*		to be enabled. Any filter not specified in this parameter will
-*		keep its previous enable/disable setting.
-*
-* @return	None.
-*
-* @note		None.
-*
-*
-******************************************************************************/
-void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes)
-{
-	u32 EnabledFilters;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 *  Calculate the new value and write to AFR.
-	 */
-	EnabledFilters =  XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						XCANPS_AFR_OFFSET);
-	EnabledFilters |= FilterIndexes;
-	EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK;
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
-			EnabledFilters);
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine disables individual acceptance filters. Up to 4 filters could
-* be disabled. If all acceptance filters are disabled then all the received
-* frames are stored in the RX FIFO.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	FilterIndexes specifies which filter(s) to disable. Use
-*		any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or"
-*		multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
-* 		to be disabled. Any filter not specified in this parameter will
-*		keep its previous enable/disable setting. If all acceptance
-*		filters are disabled then all received frames are stored in the
-*		RX FIFO.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes)
-{
-	u32 EnabledFilters;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 *  Calculate the new value and write to AFR.
-	 */
-	EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_AFR_OFFSET);
-	EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
-			   EnabledFilters);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK
-* defined in xcanps_hw.h to interpret the returned value. If no acceptance
-* filters are enabled then all received frames are stored in the RX FIFO.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	The value stored in Acceptance Filter Register.
-*
-* @note		None.
-*
-*
-******************************************************************************/
-u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFR_OFFSET);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets values to the Acceptance Filter Mask Register (AFMR) and
-* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter.
-* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the
-* filter. Read the xcanps.h file and device specification for details.
-*
-* This function should be called only after:
-*   - The given filter is disabled by calling XCanPs_AcceptFilterDisable()
-*   - And the CAN device is ready to accept writes to AFMR and AFIR, i.e.,
-*	 XCanPs_IsAcceptFilterBusy() returns FALSE.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	FilterIndex defines which Acceptance Filter Mask and ID Register
-*		to set. Use any single XCANPS_AFR_UAF*_MASK value.
-* @param	MaskValue is the value to write to the chosen Acceptance Filter
-*		Mask Register.
-* @param	IdValue is the value to write to the chosen Acceptance Filter
-*		ID Register.
-*
-* @return
-*		- XST_SUCCESS if the values were set successfully.
-*		- XST_FAILURE if the given filter was not disabled, or the CAN
-*		device was not ready to accept writes to AFMR and AFIR.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
-			 u32 MaskValue, u32 IdValue)
-{
-	u32 EnabledFilters;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) ||
-			(FilterIndex == XCANPS_AFR_UAF3_MASK) ||
-			(FilterIndex == XCANPS_AFR_UAF2_MASK) ||
-			(FilterIndex == XCANPS_AFR_UAF1_MASK));
-
-	/*
-	 * Return an error if the given filter is currently enabled.
-	 */
-	EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr);
-	if ((EnabledFilters & FilterIndex) == FilterIndex) {
-		Status = XST_FAILURE;
-	} else {
-
-		/*
-		 * If the CAN device is not ready to accept writes to AFMR and AFIR,
-		 * return error code.
-		 */
-		if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) {
-			Status = XST_FAILURE;
-		} else {
-
-			/*
-			 * Write to the AFMR and AFIR of the specified filter.
-			 */
-			switch (FilterIndex) {
-				case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
-
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFMR1_OFFSET, MaskValue);
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFIR1_OFFSET, IdValue);
-					break;
-
-				case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFMR2_OFFSET, MaskValue);
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFIR2_OFFSET, IdValue);
-					break;
-
-				case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFMR3_OFFSET, MaskValue);
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFIR3_OFFSET, IdValue);
-					break;
-
-				case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFMR4_OFFSET, MaskValue);
-					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-							XCANPS_AFIR4_OFFSET, IdValue);
-					break;
-
-				default:
-					/*This default was made for misra-c compliance*/
-					break;
-			}
-
-			Status = XST_SUCCESS;
-		}
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function reads the values of the Acceptance Filter Mask and ID Register
-* for the specified Acceptance Filter. Use XCANPS_IDR_* defined in xcanps_hw.h
-* to interpret the values. Read the xcanps.h file and device specification for
-* details.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	FilterIndex defines which Acceptance Filter Mask Register to get
-*		Mask and ID from. Use any single XCANPS_FILTER_* value.
-* @param	MaskValue is a pointer to the data in which the Mask value read
-*		from the chosen Acceptance Filter Mask Register is returned.
-* @param	IdValue is a pointer to the data in which the ID value read
-*		from the chosen Acceptance Filter ID Register is returned.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
-			  u32 *MaskValue, u32 *IdValue)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((FilterIndex == XCANPS_AFR_UAF4_MASK) ||
-			 (FilterIndex == XCANPS_AFR_UAF3_MASK) ||
-			 (FilterIndex == XCANPS_AFR_UAF2_MASK) ||
-			 (FilterIndex == XCANPS_AFR_UAF1_MASK));
-	Xil_AssertVoid(MaskValue != NULL);
-	Xil_AssertVoid(IdValue != NULL);
-
-	/*
-	 * Read from the AFMR and AFIR of the specified filter.
-	 */
-	switch (FilterIndex) {
-		case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
-			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFMR1_OFFSET);
-			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFIR1_OFFSET);
-			break;
-
-		case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
-			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFMR2_OFFSET);
-			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFIR2_OFFSET);
-			break;
-
-		case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
-			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFMR3_OFFSET);
-			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFIR3_OFFSET);
-			break;
-
-		case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
-			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFMR4_OFFSET);
-			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-						  XCANPS_AFIR4_OFFSET);
-			break;
-
-		default:
-			/*This default was made for misra-c compliance*/
-			break;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine sets Baud Rate Prescaler value. The system clock for the CAN
-* controller is divided by (Prescaler + 1) to generate the quantum clock
-* needed for sampling and synchronization. Read the device specification
-* for details.
-*
-* Baud Rate Prescaler can be set only if the CAN device is in Configuration
-* Mode. Call XCanPs_EnterMode() to enter Configuration Mode before using this
-* function.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	Prescaler is the value to set. Valid values are from 0 to 255.
-*
-* @return
-*		- XST_SUCCESS if the Baud Rate Prescaler value is set
-*		successfully.
-*		- XST_FAILURE if CAN device is not in Configuration Mode.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler)
-{
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
-		Status = XST_FAILURE;
-	} else {
-
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET,
-					(u32)Prescaler);
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine gets Baud Rate Prescaler value. The system clock for the CAN
-* controller is divided by (Prescaler + 1) to generate the quantum clock
-* needed for sampling and synchronization. Read the device specification for
-* details.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	Current used Baud Rate Prescaler value. The value's range is
-*		from 0 to 255.
-*
-* @note		None.
-*
-******************************************************************************/
-u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr)
-{
-	u32 ReadValue;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	ReadValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_BRPR_OFFSET);
-	return ((u8)ReadValue);
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine sets Bit time. Time segment 1, Time segment 2 and
-* Synchronization Jump Width are set in this function. Device specification
-* requires the values passed into this function be one less than the actual
-* values of these fields. Read the device specification for details.
-*
-* Bit time can be set only if the CAN device is in Configuration Mode.
-* Call XCanPs_EnterMode() to enter Configuration Mode before using this
-* function.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	SyncJumpWidth is the Synchronization Jump Width value to set.
-*		Valid values are from 0 to 3.
-* @param	TimeSegment2 is the Time Segment 2 value to set. Valid values
-*		are from 0 to 7.
-* @param	TimeSegment1 is the Time Segment 1 value to set. Valid values
-*		are from 0 to 15.
-*
-* @return
-*		- XST_SUCCESS if the Bit time is set successfully.
-*		- XST_FAILURE if CAN device is not in Configuration Mode.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
-			  u8 TimeSegment2, u8 TimeSegment1)
-{
-	u32 Value;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(SyncJumpWidth <= (u8)3U);
-	Xil_AssertNonvoid(TimeSegment2 <= (u8)7U);
-	Xil_AssertNonvoid(TimeSegment1 <= (u8)15U );
-
-	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
-		Status = XST_FAILURE;
-	} else {
-
-		Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK;
-		Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) &
-			XCANPS_BTR_TS2_MASK;
-		Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) &
-			XCANPS_BTR_SJW_MASK;
-
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_BTR_OFFSET, Value);
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine gets Bit time. Time segment 1, Time segment 2 and
-* Synchronization Jump Width values are read in this function. According to
-* device specification, the actual value of each of these fields is one
-* more than the value read. Read the device specification for details.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	SyncJumpWidth will store the Synchronization Jump Width value
-*		after this function returns. Its value ranges from 0 to 3.
-* @param	TimeSegment2 will store the Time Segment 2 value after this
-*		function returns. Its value ranges from 0 to 7.
-* @param	TimeSegment1 will store the Time Segment 1 value after this
-*		function returns. Its value ranges from 0 to 15.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
-			   u8 *TimeSegment2, u8 *TimeSegment1)
-{
-	u32 Value;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(SyncJumpWidth != NULL);
-	Xil_AssertVoid(TimeSegment2 != NULL);
-	Xil_AssertVoid(TimeSegment1 != NULL);
-
-	Value = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_BTR_OFFSET);
-
-	*TimeSegment1 = (u8) (Value & XCANPS_BTR_TS1_MASK);
-	*TimeSegment2 =
-		(u8) ((Value & XCANPS_BTR_TS2_MASK) >> XCANPS_BTR_TS2_SHIFT);
-	*SyncJumpWidth =
-		(u8) ((Value & XCANPS_BTR_SJW_MASK) >> XCANPS_BTR_SJW_SHIFT);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This routine sets the Rx Full threshold in the Watermark Interrupt Register.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	Threshold is the threshold to be set. The valid values are
-*		from 1 to 63.
-*
-* @return
-*		- XST_FAILURE - If the CAN device is not in Configuration Mode.
-*		- XST_SUCCESS - If the Rx Full threshold is set in Watermark
-*		Interrupt Register.
-*
-* @note		The threshold can only be set when the CAN device is in the
-*		configuration mode.
-*
-*****************************************************************************/
-s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
-{
-
-	u32 ThrReg;
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Threshold <= (u8)63);
-
-	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
-		Status = XST_FAILURE;
-	} else {
-
-		ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_WIR_OFFSET);
-
-		ThrReg &= XCANPS_WIR_EW_MASK;
-		ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_WIR_OFFSET, ThrReg);
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This routine gets the Rx Full threshold from the Watermark Interrupt Register.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	The Rx FIFO full watermark threshold value. The valid values
-*		are 1 to 63.
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
-	return (u8) (XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_WIR_OFFSET) &
-					XCANPS_WIR_FW_MASK);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This routine sets the Tx Empty Threshold in the Watermark Interrupt Register.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	Threshold is the threshold to be set. The valid values are
-*		from 1 to 63.
-*
-* @return
-*		- XST_FAILURE - If the CAN device is not in Configuration Mode.
-*		- XST_SUCCESS - If the threshold is set in Watermark
-*		Interrupt Register.
-*
-* @note		The threshold can only be set when the CAN device is in the
-*		configuration mode.
-*
-*****************************************************************************/
-s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
-{
-	u32 ThrReg;
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Threshold <= (u8)63);
-
-	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
-		Status = XST_FAILURE;
-	} else {
-
-		ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_WIR_OFFSET);
-
-		ThrReg &= XCANPS_WIR_FW_MASK;
-		ThrReg |= (((u32)Threshold << XCANPS_WIR_EW_SHIFT)
-				& XCANPS_WIR_EW_MASK);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_WIR_OFFSET, ThrReg);
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This routine gets the Tx Empty threshold from Watermark Interrupt Register.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	The Tx Empty FIFO threshold value. The valid values are 1 to 63.
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
-	return (u8) ((XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_WIR_OFFSET) & XCANPS_WIR_EW_MASK) >>
-					XCANPS_WIR_EW_SHIFT);
-}
-
-
-
-/******************************************************************************/
-/*
- * This routine is a stub for the asynchronous callbacks. The stub is here in
- * case the upper layer forgot to set the handler(s). On initialization, all
- * handlers are set to this callback. It is considered an error for this handler
- * to be invoked.
- *
- ******************************************************************************/
-static void StubHandler(void)
-{
-	Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h
deleted file mode 100644
index b180e37ec..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcanps.h
-* @addtogroup canps_v3_0
-* @{
-* @details
-*
-* The Xilinx CAN driver component.  This component supports the Xilinx
-* CAN Controller.
-*
-* The CAN Controller supports the following features:
-*	- Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
-*	- Supports both Standard (11 bit Identifier) and Extended (29 bit
-*	  Identifier) frames.
-*	- Supports Bit Rates up to 1 Mbps.
-*	- Transmit message object FIFO with a user configurable depth of
-*	  up to 64 message objects.
-*	- Transmit prioritization through one TX High Priority Buffer.
-*	- Receive message object FIFO with a user configurable depth of
-*	  up to 64 message objects.
-*	- Watermark interrupts for Rx FIFO with configurable Watermark.
-*	- Acceptance filtering with 4 acceptance filters.
-*	- Sleep mode with automatic wake up.
-*	- Loop Back mode for diagnostic applications.
-*	- Snoop mode for diagnostic applications.
-*	- Maskable Error and Status Interrupts.
-*	- Readable Error Counters.
-*	- External PHY chip required.
-*	- Receive Timestamp.
-*
-* The device driver supports all the features listed above, if applicable.
-*
-* <b>Driver Description</b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the CAN. The driver handles transmission and reception of
-* CAN frames, as well as configuration of the controller. The driver is simply a
-* pass-through mechanism between a protocol stack and the CAN. A single device
-* driver can support multiple CANs.
-*
-* Since the driver is a simple pass-through mechanism between a protocol stack
-* and the CAN, no assembly or disassembly of CAN frames is done at the
-* driver-level. This assumes that the protocol stack passes a correctly
-* formatted CAN frame to the driver for transmission, and that the driver
-* does not validate the contents of an incoming frame
-*
-* <b>Operation Modes</b>
-*
-* The CAN controller supports the following modes of operation:
-*   - <b>Configuration Mode</b>: In this mode the CAN timing parameters and
-*	 Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
-*	 controller loses synchronization with the CAN bus and drives a
-*	 constant recessive bit on the bus line. The Error Counter Register are
-*	 reset. The CAN controller does not receive or transmit any messages
-*	 even if there are pending transmit requests from the TX FIFO or the TX
-*	 High Priority Buffer. The Storage FIFOs and the CAN configuration
-*	 registers are still accessible.
-*   - <b>Normal Mode</b>:In Normal Mode the CAN controller participates in bus
-*	 communication, by transmitting and receiving messages.
-*   - <b>Sleep Mode</b>: In Sleep Mode the CAN Controller does not transmit any
-*	 messages. However, if any other node transmits a message, then the CAN
-*	 Controller receives the transmitted message and exits from Sleep Mode.
-*	 If there are new transmission requests from either the TX FIFO or the
-*	 TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
-*	 requests are not serviced, and the CAN Controller continues to remain
-*	 in Sleep Mode. Interrupts are generated when the CAN controller enters
-*	Sleep mode or Wakes up from Sleep mode.
-*   - <b>Loop Back Mode</b>: In Loop Back mode, the CAN controller transmits a
-*	 recessive bit stream on to the CAN Bus. Any message that is transmitted
-*	 is looped back to the �Rx� line and acknowledged. The CAN controller
-*	 thus receives any message that it transmits. It does not participate in
-*	 normal bus communication and does not receive any messages that are
-*	 transmitted by other CAN nodes. This mode is used for diagnostic
-*	 purposes.
-*   - <b>Snoop Mode</b>: In Snoop mode, the CAN controller transmits a
-*	 recessive bit stream on to the CAN Bus and does not participate
-*	 in normal bus communication but receives messages that are transmitted
-*	 by other CAN nodes. This mode is used for diagnostic purposes.
-*
-*
-* <b>Buffer Alignment</b>
-*
-* It is important to note that frame buffers passed to the driver must be
-* 32-bit aligned.
-*
-* <b>Receive Address Filtering</b>
-*
-* The device can be set to accept frames whose Identifiers match any of the
-* 4 filters set in the Acceptance Filter Mask/ID registers.
-*
-* The incoming Identifier is masked with the bits in the Acceptance Filter Mask
-* Register. This value is compared with the result of masking the bits in the
-* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If
-* both these values are equal, the message will be stored in the RX FIFO.
-*
-* Acceptance Filtering is performed by each of the defined acceptance filters.
-* If the incoming identifier passes through any acceptance filter then the
-* frame is stored in the RX FIFO.
-*
-* If the Accpetance Filters are not set up then all the received messages are
-* stroed in the RX FIFO.
-*
-* <b>PHY Communication</b>
-*
-* This driver does not provide any mechanism for directly programming PHY.
-*
-* <b>Interrupts</b>
-*
-* The driver has no dependencies on the interrupt controller. The driver
-* provides an interrupt handler. User of this driver needs to provide
-* callback functions. An interrupt handler example is available with
-* the driver.
-*
-* <b>Threads</b>
-*
-* This driver is not thread safe.  Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b>Device Reset</b>
-*
-* Bus Off interrupt that can occur in the device requires a device reset.
-* The user is responsible for resetting the device and re-configuring it
-* based on its needs (the driver does not save the current configuration).
-* When integrating into an RTOS, these reset and re-configure obligations are
-* taken care of by the OS adapter software if it exists for that RTOS.
-*
-* <b>Device Configuration</b>
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xcanps_g.c files.
-* A table is defined where each entry contains configuration information
-* for a CAN device.  This information includes such things as the base address
-* of the memory-mapped device.
-*
-* <b>Asserts</b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b>Building the driver</b>
-*
-* The XCanPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-* <br><br>
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00a xd/sv  01/12/10 First release
-* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
-* 			XCanPs_GetTxIntrWatermark.
-*			Updated the Register/bit definitions
-*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
-*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
-*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
-*			Changed XCANPS_IXR_RXFLL_MASK to
-*			XCANPS_IXR_RXFWMFLL_MASK
-* 			Changed
-*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
-* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
-*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
-*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
-* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
-*			SDK claims a 40kbps baud rate but it's not.
-* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.Also code
-*			modified for MISRA-C:2012 compliance.
-* 3.1 adk     10/11/15  Fixed CR#911958 Add support for Tx Watermark example.
-*			Data mismatch while sending data less than 8 bytes.
-* 3.1 nsk     12/21/15  Updated XCanPs_IntrHandler in xcanps_intr.c to handle
-*			error interrupts correctly. CR#925615
-* </pre>
-*
-******************************************************************************/
-#ifndef XCANPS_H			/* prevent circular inclusions */
-#define XCANPS_H			/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xcanps_hw.h"
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name CAN operation modes
- *  @{
- */
-#define XCANPS_MODE_CONFIG	0x00000001U /**< Configuration mode */
-#define XCANPS_MODE_NORMAL	0x00000002U /**< Normal mode */
-#define XCANPS_MODE_LOOPBACK	0x00000004U /**< Loop Back mode */
-#define XCANPS_MODE_SLEEP	0x00000008U /**< Sleep mode */
-#define XCANPS_MODE_SNOOP	0x00000010U /**< Snoop mode */
-/* @} */
-
-/** @name Callback identifiers used as parameters to XCanPs_SetHandler()
- *  @{
- */
-#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */
-#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/
-#define XCANPS_HANDLER_ERROR  3U /**< Handler type for error interrupt */
-#define XCANPS_HANDLER_EVENT  4U /**< Handler type for all other interrupts */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID of device */
-	u32 BaseAddr;		/**< Register base address */
-} XCanPs_Config;
-
-/******************************************************************************/
-/**
- * Callback type for frame sending and reception interrupts.
- *
- * @param 	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the callback functions, and passed back to the
- *		upper layer when the callback is invoked.
-*******************************************************************************/
-typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef);
-
-/******************************************************************************/
-/**
- * Callback type for error interrupt.
- *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the callback functions, and passed back to the
- *		upper layer when the callback is invoked.
- * @param	ErrorMask is a bit mask indicating the cause of the error. Its
- *		value equals 'OR'ing one or more XCANPS_ESR_* values defined in
- *		xcanps_hw.h
-*******************************************************************************/
-typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
-
-/******************************************************************************/
-/**
- * Callback type for all kinds of interrupts except sending frame interrupt,
- * receiving frame interrupt, and error interrupt.
- *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the callback functions, and passed back to the
- *		upper layer when the callback is invoked.
- * @param	Mask is a bit mask indicating the pending interrupts. Its value
- *		equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h
-*******************************************************************************/
-typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask);
-
-/**
- * The XCanPs driver instance data. The user is required to allocate a
- * variable of this type for every CAN device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XCanPs_Config CanConfig; 	/**< Device configuration */
-	u32 IsReady;			/**< Device is initialized and ready */
-
-	/**
-	 * Callback and callback reference for TXOK interrupt.
-	 */
-	XCanPs_SendRecvHandler SendHandler;
-	void *SendRef;
-
-	/**
-	 * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts.
-	 */
-	XCanPs_SendRecvHandler RecvHandler;
-	void *RecvRef;
-
-	/**
-	 * Callback and callback reference for ERROR interrupt.
-	 */
-	XCanPs_ErrorHandler ErrorHandler;
-	void *ErrorRef;
-
-	/**
-	 * Callback  and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/
-	 * Wakeup/Sleep/Bus off/ARBLST interrupts.
-	 */
-	XCanPs_EventHandler EventHandler;
-	void *EventRef;
-
-} XCanPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the transmission is complete.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return
-*		- TRUE if the transmission is done.
-*		- FALSE if the transmission is not done.
-*
-* @note		C-Style signature:
-*		int XCanPs_IsTxDone(XCanPs *InstancePtr)
-*
-*******************************************************************************/
-#define XCanPs_IsTxDone(InstancePtr) \
-	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),		\
-		XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE)
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the transmission FIFO is full.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return
-*		- TRUE if TX FIFO is full.
-*		- FALSE if the TX FIFO is NOT full.
-*
-* @note		C-Style signature:
-*		int XCanPs_IsTxFifoFull(XCanPs *InstancePtr)
-*
-*****************************************************************************/
-#define XCanPs_IsTxFifoFull(InstancePtr) \
-	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE)
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the Transmission High Priority Buffer is full.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return
-*		- TRUE if the TX High Priority Buffer is full.
-*		- FALSE if the TX High Priority Buffer is NOT full.
-*
-* @note		C-Style signature:
-*		int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr)
-*
-*****************************************************************************/
-#define XCanPs_IsHighPriorityBufFull(InstancePtr) \
-	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE)
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the receive FIFO is empty.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return
-*		- TRUE if RX FIFO is empty.
-*		- FALSE if the RX FIFO is NOT empty.
-*
-* @note		C-Style signature:
-*		int XCanPs_IsRxEmpty(XCanPs *InstancePtr)
-*
-*****************************************************************************/
-#define XCanPs_IsRxEmpty(InstancePtr) \
-	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE)
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the CAN device is ready for the driver to change
-* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask
-* Registers (AFMR).
-*
-* AFIR and AFMR for a filter are changeable only after the filter is disabled
-* and this routine returns FALSE. The filter can be disabled using the
-* XCanPs_AcceptFilterDisable function.
-*
-* Use the XCanPs_Accept_* functions for configuring the acceptance filters.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return
-*		- TRUE if the device is busy and NOT ready to accept writes to
-*		AFIR and AFMR.
-*		- FALSE if the device is ready to accept writes to AFIR and
-*		AFMR.
-*
-* @note		C-Style signature:
-*		int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr)
-*
-*****************************************************************************/
-#define XCanPs_IsAcceptFilterBusy(InstancePtr) 		\
-	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE)
-
-
-/****************************************************************************/
-/**
-*
-* This macro calculates CAN message identifier value given identifier field
-* values.
-*
-* @param	StandardId contains Standard Message ID value.
-* @param	SubRemoteTransReq contains Substitute Remote Transmission
-*		Request value.
-* @param	IdExtension contains Identifier Extension value.
-* @param	ExtendedId contains Extended Message ID value.
-* @param	RemoteTransReq contains Remote Transmission Request value.
-*
-* @return	Message Identifier value.
-*
-* @note		C-Style signature:
-*		u32 XCanPs_CreateIdValue(u32 StandardId,
-*					u32 SubRemoteTransReq,
-*					u32 IdExtension, u32 ExtendedId,
-*					u32 RemoteTransReq)
-*
-*		Read the CAN specification for meaning of each parameter.
-*
-*****************************************************************************/
-#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \
-		ExtendedId, RemoteTransReq) 				\
- ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) |	\
- (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\
- (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) |	\
- (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) |	\
- ((RemoteTransReq) & XCANPS_IDR_RTR_MASK))
-
-
-/****************************************************************************/
-/**
-*
-* This macro calculates value for Data Length Code register given Data
-* Length Code value.
-*
-* @param	DataLengCode indicates Data Length Code value.
-*
-* @return	Value that can be assigned to Data Length Code register.
-*
-* @note		C-Style signature:
-*		u32 XCanPs_CreateDlcValue(u32 DataLengCode)
-*
-*		Read the CAN specification for meaning of Data Length Code.
-*
-*****************************************************************************/
-#define XCanPs_CreateDlcValue(DataLengCode) \
-	(((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK)
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the timestamp in the Timestamp Control Register.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XCanPs_ClearTimestamp(XCanPs *InstancePtr)
-*
-*****************************************************************************/
-#define XCanPs_ClearTimestamp(InstancePtr) 			\
-	XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, 		\
-				XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions in xcanps.c
- */
-s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
-				u32 EffectiveAddr);
-
-void XCanPs_Reset(XCanPs *InstancePtr);
-u8 XCanPs_GetMode(XCanPs *InstancePtr);
-void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode);
-u32 XCanPs_GetStatus(XCanPs *InstancePtr);
-void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
-				 u8 *TxErrorCount);
-u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
-void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
-s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
-s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
-s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
-void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
-void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
-u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
-s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
-			 u32 MaskValue, u32 IdValue);
-void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
-			  u32 *MaskValue, u32 *IdValue);
-
-s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
-u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
-s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
-			  u8 TimeSegment2, u8 TimeSegment1);
-void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
-			   u8 *TimeSegment2, u8 *TimeSegment1);
-
-s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
-u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
-s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
-u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr);
-
-/*
- * Diagnostic functions in xcanps_selftest.c
- */
-s32 XCanPs_SelfTest(XCanPs *InstancePtr);
-
-/*
- * Functions in xcanps_intr.c
- */
-void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask);
-void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask);
-u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
-u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
-void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
-void XCanPs_IntrHandler(void *InstancePtr);
-s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
-			void *CallBackFunc, void *CallBackRef);
-
-/*
- * Functions in xcanps_sinit.c
- */
-XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c
deleted file mode 100644
index b45c5b2d6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xcanps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XCanPs_Config XCanPs_ConfigTable[] =
-{
-	{
-		XPAR_PSU_CAN_1_DEVICE_ID,
-		XPAR_PSU_CAN_1_BASEADDR
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c
deleted file mode 100644
index bbb96120a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcanps_hw.c
-* @addtogroup canps_v3_0
-* @{
-*
-* This file contains the implementation of the canps interface reset sequence
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.02a adk  08/08/13 First release
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcanps_hw.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* This function resets the CAN device. Calling this function resets the device
-* immediately, and any pending transmission or reception is terminated at once.
-* Both Object Layer and Transfer Layer are reset. This function does not reset
-* the Physical Layer. All registers are reset to the default values, and no
-* previous status will be restored. TX FIFO, RX FIFO and TX High Priority
-* Buffer are also reset.
-*
-* The CAN device will be in Configuration Mode immediately after this function
-* returns.
-*
-* @param	BaseAddr is the baseaddress of the interface.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_ResetHw(u32 BaseAddr)
-{
-	XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \
-			   XCANPS_SRR_SRST_MASK);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h
deleted file mode 100644
index 9fe681aaf..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcanps_hw.h
-* @addtogroup canps_v3_0
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xcanps.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00a xd/sv  01/12/10 First release
-* 1.01a sbs    12/27/11 Updated the Register/bit definitions
-*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
-*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
-*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
-*			Changed XCANPS_IXR_RXFLL_MASK to
-*			XCANPS_IXR_RXFWMFLL_MASK
-* 			Changed
-*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
-* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
-*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
-*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
-* 1.02a adk   08/08/13  Updated for inclding the function prototype
-* 3.00  kvn   02/13/15  Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XCANPS_HW_H		/* prevent circular inclusions */
-#define XCANPS_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the CAN. Each register is 32 bits.
- *  @{
- */
-#define XCANPS_SRR_OFFSET	  	0x00000000U /**< Software Reset Register */
-#define XCANPS_MSR_OFFSET	  	0x00000004U /**< Mode Select Register */
-#define XCANPS_BRPR_OFFSET	  	0x00000008U /**< Baud Rate Prescaler */
-#define XCANPS_BTR_OFFSET	  	0x0000000CU /**< Bit Timing Register */
-#define XCANPS_ECR_OFFSET	  	0x00000010U /**< Error Counter Register */
-#define XCANPS_ESR_OFFSET	  	0x00000014U /**< Error Status Register */
-#define XCANPS_SR_OFFSET	  	0x00000018U /**< Status Register */
-
-#define XCANPS_ISR_OFFSET	  	0x0000001CU /**< Interrupt Status Register */
-#define XCANPS_IER_OFFSET	  	0x00000020U /**< Interrupt Enable Register */
-#define XCANPS_ICR_OFFSET	  	0x00000024U /**< Interrupt Clear Register */
-#define XCANPS_TCR_OFFSET	  	0x00000028U /**< Timestamp Control Register */
-#define XCANPS_WIR_OFFSET	  	0x0000002CU /**< Watermark Interrupt Reg */
-
-#define XCANPS_TXFIFO_ID_OFFSET  	0x00000030U /**< TX FIFO ID */
-#define XCANPS_TXFIFO_DLC_OFFSET 	0x00000034U /**< TX FIFO DLC */
-#define XCANPS_TXFIFO_DW1_OFFSET	0x00000038U /**< TX FIFO Data Word 1 */
-#define XCANPS_TXFIFO_DW2_OFFSET 	0x0000003CU /**< TX FIFO Data Word 2 */
-
-#define XCANPS_TXHPB_ID_OFFSET   	0x00000040U /**< TX High Priority Buffer ID */
-#define XCANPS_TXHPB_DLC_OFFSET  	0x00000044U /**< TX High Priority Buffer DLC */
-#define XCANPS_TXHPB_DW1_OFFSET  	0x00000048U /**< TX High Priority Buf Data 1 */
-#define XCANPS_TXHPB_DW2_OFFSET  	0x0000004CU /**< TX High Priority Buf Data Word 2 */
-
-#define XCANPS_RXFIFO_ID_OFFSET  	0x00000050U /**< RX FIFO ID */
-#define XCANPS_RXFIFO_DLC_OFFSET 	0x00000054U /**< RX FIFO DLC */
-#define XCANPS_RXFIFO_DW1_OFFSET 	0x00000058U /**< RX FIFO Data Word 1 */
-#define XCANPS_RXFIFO_DW2_OFFSET 	0x0000005CU /**< RX FIFO Data Word 2 */
-
-#define XCANPS_AFR_OFFSET	  	0x00000060U /**< Acceptance Filter Register */
-#define XCANPS_AFMR1_OFFSET	  	0x00000064U /**< Acceptance Filter Mask 1 */
-#define XCANPS_AFIR1_OFFSET	  	0x00000068U /**< Acceptance Filter ID  1 */
-#define XCANPS_AFMR2_OFFSET	  	0x0000006CU /**< Acceptance Filter Mask  2 */
-#define XCANPS_AFIR2_OFFSET	  	0x00000070U /**< Acceptance Filter ID 2 */
-#define XCANPS_AFMR3_OFFSET	  	0x00000074U /**< Acceptance Filter Mask 3 */
-#define XCANPS_AFIR3_OFFSET	  	0x00000078U /**< Acceptance Filter ID 3 */
-#define XCANPS_AFMR4_OFFSET	  	0x0000007CU /**< Acceptance Filter Mask  4 */
-#define XCANPS_AFIR4_OFFSET	  	0x00000080U /**< Acceptance Filter ID 4 */
-/* @} */
-
-/** @name Software Reset Register (SRR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_SRR_CEN_MASK		0x00000002U  /**< Can Enable */
-#define XCANPS_SRR_SRST_MASK	0x00000001U  /**< Reset */
-/* @} */
-
-/** @name Mode Select Register (MSR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_MSR_SNOOP_MASK	0x00000004U /**< Snoop Mode Select */
-#define XCANPS_MSR_LBACK_MASK	0x00000002U /**< Loop Back Mode Select */
-#define XCANPS_MSR_SLEEP_MASK	0x00000001U /**< Sleep Mode Select */
-/* @} */
-
-/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_BRPR_BRP_MASK	0x000000FFU /**< Baud Rate Prescaler */
-/* @} */
-
-/** @name Bit Timing Register (BTR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_BTR_SJW_MASK	0x00000180U /**< Synchronization Jump Width */
-#define XCANPS_BTR_SJW_SHIFT	7U
-#define XCANPS_BTR_TS2_MASK	0x00000070U /**< Time Segment 2 */
-#define XCANPS_BTR_TS2_SHIFT	4U
-#define XCANPS_BTR_TS1_MASK	0x0000000FU /**< Time Segment 1 */
-/* @} */
-
-/** @name Error Counter Register (ECR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_ECR_REC_MASK	0x0000FF00U /**< Receive Error Counter */
-#define XCANPS_ECR_REC_SHIFT		 8U
-#define XCANPS_ECR_TEC_MASK	0x000000FFU /**< Transmit Error Counter */
-/* @} */
-
-/** @name Error Status Register (ESR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_ESR_ACKER_MASK	0x00000010U /**< ACK Error */
-#define XCANPS_ESR_BERR_MASK	0x00000008U /**< Bit Error */
-#define XCANPS_ESR_STER_MASK	0x00000004U /**< Stuff Error */
-#define XCANPS_ESR_FMER_MASK	0x00000002U /**< Form Error */
-#define XCANPS_ESR_CRCER_MASK	0x00000001U /**< CRC Error */
-/* @} */
-
-/** @name Status Register (SR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_SR_SNOOP_MASK	0x00001000U /**< Snoop Mask */
-#define XCANPS_SR_ACFBSY_MASK	0x00000800U /**< Acceptance Filter busy */
-#define XCANPS_SR_TXFLL_MASK	0x00000400U /**< TX FIFO is full */
-#define XCANPS_SR_TXBFLL_MASK	0x00000200U /**< TX High Priority Buffer full */
-#define XCANPS_SR_ESTAT_MASK	0x00000180U /**< Error Status */
-#define XCANPS_SR_ESTAT_SHIFT			 7U
-#define XCANPS_SR_ERRWRN_MASK	0x00000040U /**< Error Warning */
-#define XCANPS_SR_BBSY_MASK		0x00000020U /**< Bus Busy */
-#define XCANPS_SR_BIDLE_MASK	0x00000010U /**< Bus Idle */
-#define XCANPS_SR_NORMAL_MASK	0x00000008U /**< Normal Mode */
-#define XCANPS_SR_SLEEP_MASK	0x00000004U /**< Sleep Mode */
-#define XCANPS_SR_LBACK_MASK	0x00000002U /**< Loop Back Mode */
-#define XCANPS_SR_CONFIG_MASK	0x00000001U /**< Configuration Mode */
-/* @} */
-
-/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_IXR_TXFEMP_MASK   0x00004000U /**< Tx Fifo Empty Interrupt */
-#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */
-#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */
-#define XCANPS_IXR_WKUP_MASK	 0x00000800U /**< Wake up Interrupt */
-#define XCANPS_IXR_SLP_MASK		0x00000400U /**< Sleep Interrupt */
-#define XCANPS_IXR_BSOFF_MASK	0x00000200U /**< Bus Off Interrupt */
-#define XCANPS_IXR_ERROR_MASK	0x00000100U /**< Error Interrupt */
-#define XCANPS_IXR_RXNEMP_MASK	0x00000080U /**< RX FIFO Not Empty Interrupt */
-#define XCANPS_IXR_RXOFLW_MASK	0x00000040U /**< RX FIFO Overflow Interrupt */
-#define XCANPS_IXR_RXUFLW_MASK	0x00000020U /**< RX FIFO Underflow Interrupt */
-#define XCANPS_IXR_RXOK_MASK	0x00000010U /**< New Message Received Intr */
-#define XCANPS_IXR_TXBFLL_MASK	0x00000008U /**< TX High Priority Buf Full */
-#define XCANPS_IXR_TXFLL_MASK	0x00000004U /**< TX FIFO Full Interrupt */
-#define XCANPS_IXR_TXOK_MASK	0x00000002U /**< TX Successful Interrupt */
-#define XCANPS_IXR_ARBLST_MASK	0x00000001U /**< Arbitration Lost Interrupt */
-#define XCANPS_IXR_ALL		((u32)XCANPS_IXR_RXFWMFLL_MASK | \
-				(u32)XCANPS_IXR_WKUP_MASK   | \
-				(u32)XCANPS_IXR_SLP_MASK	| \
-				(u32)XCANPS_IXR_BSOFF_MASK  | \
-				(u32)XCANPS_IXR_ERROR_MASK  | \
-				(u32)XCANPS_IXR_RXNEMP_MASK | \
-				(u32)XCANPS_IXR_RXOFLW_MASK | \
-				(u32)XCANPS_IXR_RXUFLW_MASK | \
-				(u32)XCANPS_IXR_RXOK_MASK   | \
-				(u32)XCANPS_IXR_TXBFLL_MASK | \
-				(u32)XCANPS_IXR_TXFLL_MASK  | \
-				(u32)XCANPS_IXR_TXOK_MASK   | \
-				(u32)XCANPS_IXR_ARBLST_MASK)
-/* @} */
-
-/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_TCR_CTS_MASK	0x00000001U /**< Clear Timestamp counter mask */
-/* @} */
-
-/** @name CAN Watermark Register (WIR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_WIR_FW_MASK   	0x0000003FU /**< Rx Full Threshold mask */
-#define XCANPS_WIR_EW_MASK 	0x00003F00U /**< Tx Empty Threshold mask */
-#define XCANPS_WIR_EW_SHIFT 	0x00000008U /**< Tx Empty Threshold shift */
-
-/* @} */
-
-/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
-				Mask/Acceptance Filter ID)
- *  @{
- */
-#define XCANPS_IDR_ID1_MASK	0xFFE00000U /**< Standard Messg Identifier */
-#define XCANPS_IDR_ID1_SHIFT	21U
-#define XCANPS_IDR_SRR_MASK	0x00100000U /**< Substitute Remote TX Req */
-#define XCANPS_IDR_SRR_SHIFT	20U
-#define XCANPS_IDR_IDE_MASK	0x00080000U /**< Identifier Extension */
-#define XCANPS_IDR_IDE_SHIFT	19U
-#define XCANPS_IDR_ID2_MASK	0x0007FFFEU /**< Extended Message Ident */
-#define XCANPS_IDR_ID2_SHIFT	1U
-#define XCANPS_IDR_RTR_MASK	0x00000001U /**< Remote TX Request */
-/* @} */
-
-/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
- *  @{
- */
-#define XCANPS_DLCR_DLC_MASK	 0xF0000000U	/**< Data Length Code */
-#define XCANPS_DLCR_DLC_SHIFT	 28U
-#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU	/**< Timestamp Mask (Rx only) */
-
-/* @} */
-
-/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
- *  @{
- */
-#define XCANPS_DW1R_DB0_MASK	0xFF000000U /**< Data Byte 0 */
-#define XCANPS_DW1R_DB0_SHIFT	24U
-#define XCANPS_DW1R_DB1_MASK	0x00FF0000U /**< Data Byte 1 */
-#define XCANPS_DW1R_DB1_SHIFT	16U
-#define XCANPS_DW1R_DB2_MASK	0x0000FF00U /**< Data Byte 2 */
-#define XCANPS_DW1R_DB2_SHIFT	8U
-#define XCANPS_DW1R_DB3_MASK	0x000000FFU /**< Data Byte 3 */
-/* @} */
-
-/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
- *  @{
- */
-#define XCANPS_DW2R_DB4_MASK	0xFF000000U /**< Data Byte 4 */
-#define XCANPS_DW2R_DB4_SHIFT	24U
-#define XCANPS_DW2R_DB5_MASK	0x00FF0000U /**< Data Byte 5 */
-#define XCANPS_DW2R_DB5_SHIFT	16U
-#define XCANPS_DW2R_DB6_MASK	0x0000FF00U /**< Data Byte 6 */
-#define XCANPS_DW2R_DB6_SHIFT	8U
-#define XCANPS_DW2R_DB7_MASK	0x000000FFU /**< Data Byte 7 */
-/* @} */
-
-/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
- *  @{
- */
-#define XCANPS_AFR_UAF4_MASK	0x00000008U /**< Use Acceptance Filter No.4 */
-#define XCANPS_AFR_UAF3_MASK	0x00000004U /**< Use Acceptance Filter No.3 */
-#define XCANPS_AFR_UAF2_MASK	0x00000002U /**< Use Acceptance Filter No.2 */
-#define XCANPS_AFR_UAF1_MASK	0x00000001U /**< Use Acceptance Filter No.1 */
-#define XCANPS_AFR_UAF_ALL_MASK	((u32)XCANPS_AFR_UAF4_MASK | \
-					(u32)XCANPS_AFR_UAF3_MASK | \
-					(u32)XCANPS_AFR_UAF2_MASK | \
-					(u32)XCANPS_AFR_UAF1_MASK)
-/* @} */
-
-/** @name CAN frame length constants
- *  @{
- */
-#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */
-/* @} */
-
-/* For backwards compatibilty */
-#define XCANPS_TXBUF_ID_OFFSET   XCANPS_TXHPB_ID_OFFSET
-#define XCANPS_TXBUF_DLC_OFFSET  XCANPS_TXHPB_DLC_OFFSET
-#define XCANPS_TXBUF_DW1_OFFSET  XCANPS_TXHPB_DW1_OFFSET
-#define XCANPS_TXBUF_DW2_OFFSET  XCANPS_TXHPB_DW2_OFFSET
-
-#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK
-#define XCANPS_RXWIR_OFFSET 	 XCANPS_WIR_OFFSET
-#define XCANPS_IXR_RXFLL_MASK 	 XCANPS_IXR_RXFWMFLL_MASK
-
-
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param	BaseAddr is the base address of the device.
-* @param	RegOffset is the register offset to be read.
-*
-* @return	The 32-bit value of the register
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XCanPs_ReadReg(BaseAddr, RegOffset) \
-		Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param	BaseAddr is the base address of the device.
-* @param	RegOffset is the register offset to be written.
-* @param	Data is the 32-bit value to write to the register.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
-		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the CanPs interface
- */
-void XCanPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c
deleted file mode 100644
index f6721ca75..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcanps_intr.c
-* @addtogroup canps_v3_0
-* @{
-*
-* This file contains functions related to CAN interrupt handling.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00a xd/sv  01/12/10 First release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1   nsk    12/21/15 Updated XCanPs_IntrHandler to handle error
-*			interrupts correctly. CR#925615
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcanps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/****************************************************************************/
-/**
-*
-* This routine enables interrupt(s). Use the XCANPS_IXR_* constants defined in
-* xcanps_hw.h to create the bit-mask to enable interrupts.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	Mask is the mask to enable. Bit positions of 1 will be enabled.
-*		Bit positions of 0 will keep the previous setting. This mask is
-*		formed by OR'ing XCANPS_IXR_* bits defined in xcanps_hw.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask)
-{
-	u32 IntrValue;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Write to the IER to enable the specified interrupts.
-	 */
-	IntrValue = XCanPs_IntrGetEnabled(InstancePtr);
-	IntrValue |= Mask;
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_IER_OFFSET, IntrValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This routine disables interrupt(s). Use the XCANPS_IXR_* constants defined in
-* xcanps_hw.h to create the bit-mask to disable interrupt(s).
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	Mask is the mask to disable. Bit positions of 1 will be
-*		disabled. Bit positions of 0 will keep the previous setting.
-*		This mask is formed by OR'ing XCANPS_IXR_* bits defined in
-*		xcanps_hw.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask)
-{
-	u32 IntrValue;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Write to the IER to disable the specified interrupts.
-	 */
-	IntrValue = XCanPs_IntrGetEnabled(InstancePtr);
-	IntrValue &= ~Mask;
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_IER_OFFSET, IntrValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This routine returns enabled interrupt(s). Use the XCANPS_IXR_* constants
-* defined in xcanps_hw.h to interpret the returned value.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	Enabled interrupt(s) in a 32-bit format.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_IER_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This routine returns interrupt status read from Interrupt Status Register.
-* Use the XCANPS_IXR_* constants defined in xcanps_hw.h to interpret the
-* returned value.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return	The value stored in Interrupt Status Register.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr)
-{
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_ISR_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears interrupt(s). Every bit set in Interrupt Status
-* Register indicates that a specific type of interrupt is occurring, and this
-* function clears one or more interrupts by writing a bit mask to Interrupt
-* Clear Register.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	Mask is the mask to clear. Bit positions of 1 will be cleared.
-*		Bit positions of 0 will not change the previous interrupt
-*		status. This mask is formed by OR'ing XCANPS_IXR_* bits defined
-* 		in xcanps_hw.h.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask)
-{
-	u32 IntrValue;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Clear the currently pending interrupts.
-	 */
-	IntrValue = XCanPs_IntrGetStatus(InstancePtr);
-	IntrValue &= Mask;
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_ICR_OFFSET,
-				IntrValue);
-}
-
-/*****************************************************************************/
-/**
-*
-* This routine is the interrupt handler for the CAN driver.
-*
-* This handler reads the interrupt status from the ISR, determines the source of
-* the interrupts, calls according callbacks, and finally clears the interrupts.
-*
-* Application beyond this driver is responsible for providing callbacks to
-* handle interrupts and installing the callbacks using XCanPs_SetHandler()
-* during initialization phase. An example delivered with this driver
-* demonstrates how this could be done.
-*
-* @param	InstancePtr is a pointer to the XCanPs instance that just
-*		interrupted.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCanPs_IntrHandler(void *InstancePtr)
-{
-	u32 PendingIntr;
-	u32 EventIntr;
-	u32 ErrorStatus;
-	XCanPs *CanPtr = (XCanPs *) ((void *)InstancePtr);
-
-	Xil_AssertVoid(CanPtr != NULL);
-	Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	PendingIntr = XCanPs_IntrGetStatus(CanPtr);
-	PendingIntr &= XCanPs_IntrGetEnabled(CanPtr);
-
-	/*
-	 * Clear all pending interrupts.
-	 * Rising Edge interrupt
-	 */
-	XCanPs_IntrClear(CanPtr, PendingIntr);
-
-	/*
-	 * An error interrupt is occurring.
-	 */
-	if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) &&
-		(CanPtr->ErrorHandler != NULL)) {
-			ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr);
-			CanPtr->ErrorHandler(CanPtr->ErrorRef,ErrorStatus);
-		/*
-		 * Clear Error Status Register.
-		 */
-		XCanPs_ClearBusErrorStatus(CanPtr,ErrorStatus);
-	}
-
-	/*
-	 * Check if any following event interrupt is pending:
-	 *	  - RX FIFO Overflow
-	 *	  - RX FIFO Underflow
-	 *	  - TX High Priority Buffer full
-	 *	  - TX FIFO Full
-	 *	  - Wake up from sleep mode
-	 *	  - Enter sleep mode
-	 *	  - Enter Bus off status
-	 *	  - Arbitration is lost
-	 *
-	 * If so, call event callback provided by upper level.
-	 */
-	EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK |
-				(u32)XCANPS_IXR_RXUFLW_MASK |
-				(u32)XCANPS_IXR_TXBFLL_MASK |
-				(u32)XCANPS_IXR_TXFLL_MASK |
-				(u32)XCANPS_IXR_WKUP_MASK |
-				(u32)XCANPS_IXR_SLP_MASK |
-				(u32)XCANPS_IXR_BSOFF_MASK |
-				(u32)XCANPS_IXR_ARBLST_MASK);
-	if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) {
-		CanPtr->EventHandler(CanPtr->EventRef, EventIntr);
-
-		if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) {
-			/*
-			 * Event callback should reset whole device if "Enter
-			 * Bus Off Status" interrupt occurred. All pending
-			 * interrupts are cleared and no further checking and
-			 * handling of other interrupts is needed any more.
-			 */
-			return;
-		} else {
-			/*This else was made for misra-c compliance*/
-			;
-		}
-	}
-
-
-	if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK |
-			XCANPS_IXR_RXNEMP_MASK)) != (u32)0) &&
-		(CanPtr->RecvHandler != NULL)) {
-
-		/*
-		 * This case happens when
-		 * A number of frames depending on the Rx FIFO Watermark
-		 * threshold are received.
-		 * And  also when frame was received and is sitting in RX FIFO.
-		 *
-		 * XCANPS_IXR_RXOK_MASK is not used because the bit is set
-		 * just once even if there are multiple frames sitting
-		 * in the RX FIFO.
-		 *
-		 * XCANPS_IXR_RXNEMP_MASK is used because the bit can be
-		 * set again and again automatically as long as there is
-		 * at least one frame in RX FIFO.
-		 */
-		CanPtr->RecvHandler(CanPtr->RecvRef);
-	}
-
-	/*
-	 * A frame was transmitted successfully.
-	 */
-	if (((PendingIntr & (XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK)) != (u32)0) &&
-		(CanPtr->SendHandler != NULL)) {
-		CanPtr->SendHandler(CanPtr->SendRef);
-	}
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This routine installs an asynchronous callback function for the given
-* HandlerType:
-*
-* <pre>
-* HandlerType			Callback Function Type
-* -----------------------	------------------------
-* XCANPS_HANDLER_SEND		XCanPs_SendRecvHandler
-* XCANPS_HANDLER_RECV		XCanPs_SendRecvHandler
-* XCANPS_HANDLER_ERROR		XCanPs_ErrorHandler
-* XCANPS_HANDLER_EVENT		XCanPs_EventHandler
-*
-* HandlerType			Invoked by this driver when:
-* -------------------------------------------------------------------------
-* XCANPS_HANDLER_SEND		A frame transmitted by a call to
-*				XCanPs_Send() has been sent successfully.
-*
-* XCANPS_HANDLER_RECV		A frame(s) has been received and is sitting in
-*				the RX FIFO.
-*
-* XCANPS_HANDLER_ERROR		An error interrupt is occurring.
-*
-* XCANPS_HANDLER_EVENT		Any other kind of interrupt is occurring.
-* </pre>
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-* @param	HandlerType specifies which handler is to be attached.
-* @param	CallBackFunc is the address of the callback function.
-* @param	CallBackRef is a user data item that will be passed to the
-*		callback function when it is invoked.
-*
-* @return
-*		- XST_SUCCESS when handler is installed.
-*		- XST_INVALID_PARAM when HandlerType is invalid.
-*
-* @note
-* Invoking this function for a handler that already has been installed replaces
-* it with the new handler.
-*
-******************************************************************************/
-s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
-			void *CallBackFunc, void *CallBackRef)
-{
-	s32 Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	switch (HandlerType) {
-		case XCANPS_HANDLER_SEND:
-			InstancePtr->SendHandler =
-				(XCanPs_SendRecvHandler) CallBackFunc;
-			InstancePtr->SendRef = CallBackRef;
-			Status = XST_SUCCESS;
-			break;
-
-		case XCANPS_HANDLER_RECV:
-			InstancePtr->RecvHandler =
-				(XCanPs_SendRecvHandler) CallBackFunc;
-			InstancePtr->RecvRef = CallBackRef;
-			Status = XST_SUCCESS;
-			break;
-
-		case XCANPS_HANDLER_ERROR:
-			InstancePtr->ErrorHandler =
-				(XCanPs_ErrorHandler) CallBackFunc;
-			InstancePtr->ErrorRef = CallBackRef;
-			Status = XST_SUCCESS;
-			break;
-
-		case XCANPS_HANDLER_EVENT:
-			InstancePtr->EventHandler =
-				(XCanPs_EventHandler) CallBackFunc;
-			InstancePtr->EventRef = CallBackRef;
-			Status = XST_SUCCESS;
-			break;
-
-		default:
-			Status = XST_INVALID_PARAM;
-			break;
-	}
-	return Status;
-}
-
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c
deleted file mode 100644
index 8bc77d7f4..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcanps_selftest.c
-* @addtogroup canps_v3_0
-* @{
-*
-* This file contains a diagnostic self-test function for the XCanPs driver.
-*
-* Read xcanps.h file for more information.
-*
-* @note
-* The  Baud Rate Prescaler Register (BRPR) and Bit Timing Register(BTR)
-* are setup such that CAN baud rate equals 40Kbps, given the CAN clock
-* equal to 24MHz. These need to be changed based on the desired baudrate
-* and CAN clock frequency.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00a xd/sv  01/12/10 First release
-* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
-*						 SDK claims a 40kbps baud rate but it's not.
-* 3.00  kvn    02/13/15 Modified code for MISRA_C:2012 compliance.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xcanps.h"
-
-/************************** Constant Definitions ****************************/
-
-#define XCANPS_MAX_FRAME_SIZE_IN_WORDS ((XCANPS_MAX_FRAME_SIZE) / (sizeof(u32)))
-
-#define FRAME_DATA_LENGTH	8U /* Frame Data field length */
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/*
- * Buffers to hold frames to send and receive. These are declared as global so
- * that they are not on the stack.
- */
-static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS];
-static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS];
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function runs a self-test on the CAN driver/device. The test resets
-* the device, sets up the Loop Back mode, sends a standard frame, receives the
-* frame, verifies the contents, and resets the device again.
-*
-* Note that this is a destructive test in that resets of the device are
-* performed. Refer the device specification for the device status after
-* the reset operation.
-*
-*
-* @param	InstancePtr is a pointer to the XCanPs instance.
-*
-* @return
-*		- XST_SUCCESS if the self-test passed. i.e., the frame
-*		  received via the internal loop back has the same contents as
-*		  the frame sent.
-* 		- XST_FAILURE   Otherwise.
-*
-* @note
-*
-* If the CAN device does not work properly, this function may enter an
-* infinite loop and will never return to the caller.
-* <br><br>
-* If XST_FAILURE is returned, the device is not reset so that the caller could
-* have a chance to check reason(s) causing the failure.
-*
-******************************************************************************/
-s32 XCanPs_SelfTest(XCanPs *InstancePtr)
-{
-	u8 *FramePtr;
-	s32 Status;
-	u32 Index;
-	u8 GetModeResult;
-	u32 RxEmptyResult;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	XCanPs_Reset(InstancePtr);
-
-	/*
-	 * The device should enter Configuration Mode immediately after
-	 * reset above is finished. Now check the mode and return error code if
-	 * it is not Configuration Mode.
-	 */
-	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) {
-		Status = XST_FAILURE;
-		return Status;
-	}
-
-	/*
-	 * Setup Baud Rate Prescaler Register (BRPR) and Bit Timing Register
-	 * (BTR) such that CAN baud rate equals 40Kbps, given the CAN clock
-	 * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B,
-	 * ISO 11898-1 specifications.
-	 */
-	(void)XCanPs_SetBaudRatePrescaler(InstancePtr, (u8)29U);
-	(void)XCanPs_SetBitTiming(InstancePtr, (u8)3U, (u8)2U, (u8)15U);
-
-	/*
-	 * Enter the loop back mode.
-	 */
-	XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK);
-	GetModeResult = XCanPs_GetMode(InstancePtr);
-	while (GetModeResult != ((u8)XCANPS_MODE_LOOPBACK)) {
-		GetModeResult = XCanPs_GetMode(InstancePtr);
-	}
-
-	/*
-	 * Create a frame to send with known values so we can verify them
-	 * on receive.
-	 */
-	TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U);
-	TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8U);
-
-	FramePtr = (u8 *)((void *)(&TxFrame[2]));
-	for (Index = 0U; Index < 8U; Index++) {
-		if(*FramePtr != 0U) {
-			*FramePtr = (u8)Index;
-			*FramePtr++;
-		}
-	}
-
-	/*
-	 * Send the frame.
-	 */
-	Status = XCanPs_Send(InstancePtr, TxFrame);
-	if (Status != (s32)XST_SUCCESS) {
-		Status = XST_FAILURE;
-		return Status;
-	}
-
-	/*
-	 * Wait until the frame arrives RX FIFO via internal loop back.
-	 */
-	RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
-			XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
-
-	while (RxEmptyResult == (u32)0U) {
-		RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
-				XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
-	}
-
-	/*
-	 * Receive the frame.
-	 */
-	Status = XCanPs_Recv(InstancePtr, RxFrame);
-	if (Status != (s32)XST_SUCCESS) {
-		Status = XST_FAILURE;
-		return Status;
-	}
-
-	/*
-	 * Verify Identifier and Data Length Code.
-	 */
-	if (RxFrame[0] !=
-		(u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U)) {
-		Status = XST_FAILURE;
-		return Status;
-	}
-
-	if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) {
-		Status = XST_FAILURE;
-		return Status;
-	}
-
-
-	for (Index = 2U; Index < (XCANPS_MAX_FRAME_SIZE_IN_WORDS); Index++) {
-		if (RxFrame[Index] != TxFrame[Index]) {
-			Status = XST_FAILURE;
-			return Status;
-		}
-	}
-
-	/*
-	 * Reset device again before returning to the caller.
-	 */
-	XCanPs_Reset(InstancePtr);
-
-	Status = XST_SUCCESS;
-	return Status;
-}
-
-
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c
deleted file mode 100644
index 230c429b3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcanps_sinit.c
-* @addtogroup canps_v3_0
-* @{
-*
-* This file contains the implementation of the XCanPs driver's static
-* initialization functionality.
-*
-* @note		None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00a xd/sv  01/12/10 First release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcanps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* This function looks for the device configuration based on the unique device
-* ID. The table XCanPs_ConfigTable[] contains the configuration information for
-* each device in the system.
-*
-* @param	DeviceId is the unique device ID of the device being looked up.
-*
-* @return	A pointer to the configuration table entry corresponding to the
-*		given device ID, or NULL if no match is found.
-*
-* @note		None.
-*
-******************************************************************************/
-XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId)
-{
-	XCanPs_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index = 0U; Index < (u32)XPAR_XCANPS_NUM_INSTANCES; Index++) {
-		if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XCanPs_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XCanPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/Makefile
new file mode 100644
index 000000000..55565709b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xcanps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling canps"
+
+xcanps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xcanps_includes
+
+xcanps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c
new file mode 100644
index 000000000..243b3a81b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c
@@ -0,0 +1,1205 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps.c
+* @addtogroup canps_v3_0
+* @{
+*
+* Functions in this file are the minimum required functions for the XCanPs
+* driver. See xcanps.h for a detailed description of the driver.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XCanPs instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XCanPs structure.
+* - Reset the CAN device. The CAN device will enter Configuration Mode
+*   immediately after the reset is finished.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	ConfigPtr points to the XCanPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->CanConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId;
+
+	/*
+	 * Set all handlers to stub values, let user configure this data later.
+	 */
+	InstancePtr->SendHandler = (XCanPs_SendRecvHandler) StubHandler;
+	InstancePtr->RecvHandler = (XCanPs_SendRecvHandler) StubHandler;
+	InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) StubHandler;
+	InstancePtr->EventHandler = (XCanPs_EventHandler) StubHandler;
+
+	/*
+	 * Indicate the component is now ready to use.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the device to get it into its initial state.
+	 */
+	XCanPs_Reset(InstancePtr);
+
+	Status = XST_SUCCESS;
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the CAN device. Calling this function resets the device
+* immediately, and any pending transmission or reception is terminated at once.
+* Both Object Layer and Transfer Layer are reset. This function does not reset
+* the Physical Layer. All registers are reset to the default values, and no
+* previous status will be restored. TX FIFO, RX FIFO and TX High Priority
+* Buffer are also reset.
+*
+* When a reset is required due to an internal error, the driver notifies the
+* upper layer software of this need through the error status code or interrupts.
+* The upper layer software is responsible for calling this Reset function and
+* then re-configuring the device.
+*
+* The CAN device will be in Configuration Mode immediately after this function
+* returns.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_Reset(XCanPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_SRR_OFFSET, \
+			   XCANPS_SRR_SRST_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This routine returns the current operation mode of the CAN device.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* 		- XCANPS_MODE_CONFIG if the device is in Configuration Mode.
+* 		- XCANPS_MODE_SLEEP if the device is in Sleep Mode.
+* 		- XCANPS_MODE_NORMAL if the device is in Normal Mode.
+* 		- XCANPS_MODE_LOOPBACK if the device is in Loop Back Mode.
+* 		- XCANPS_MODE_SNOOP if the device is in Snoop Mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XCanPs_GetMode(XCanPs *InstancePtr)
+{
+	u32 StatusReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	StatusReg = XCanPs_GetStatus(InstancePtr);
+
+	if ((StatusReg & XCANPS_SR_CONFIG_MASK) != (u32)0) {
+		return (u8)XCANPS_MODE_CONFIG;
+
+	}
+	else if ((StatusReg & XCANPS_SR_SLEEP_MASK) != (u32)0) {
+		return (u8)XCANPS_MODE_SLEEP;
+
+	}
+	else if ((StatusReg & XCANPS_SR_NORMAL_MASK) != (u32)0) {
+		if ((StatusReg & XCANPS_SR_SNOOP_MASK) != (u32)0) {
+			return (u8)XCANPS_MODE_SNOOP;
+		} else {
+			return (u8)XCANPS_MODE_NORMAL;
+		}
+	}
+	else {
+		/*
+		 * If this line is reached, the device is in Loop Back Mode.
+		 */
+		return (u8)XCANPS_MODE_LOOPBACK;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function allows the CAN device to enter one of the following operation
+* modes:
+*	- Configuration Mode: Pass in parameter XCANPS_MODE_CONFIG
+*	- Sleep Mode: Pass in parameter XCANPS_MODE_SLEEP
+*	- Normal Mode: Pass in parameter XCANPS_MODE_NORMAL
+*	- Loop Back Mode: Pass in parameter XCANPS_MODE_LOOPBACK.
+*	- Snoop Mode: Pass in parameter XCANPS_MODE_SNOOP.
+*
+* Read the xcanps.h file and device specification for detailed description of
+* each operation mode.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	OperationMode specify which operation mode to enter. Valid value
+*		is any of XCANPS_MODE_* defined in xcanps.h. Multiple modes
+*		can not be entered at the same time.
+*
+* @return	None.
+*
+* @note
+*
+* This function does NOT ensure CAN device enters the specified operation mode
+* before it returns the control to the caller. The caller is responsible for
+* checking current operation mode using XCanPs_GetMode().
+*
+******************************************************************************/
+void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode)
+{
+	u8 CurrentMode;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((OperationMode == (u8)XCANPS_MODE_CONFIG) ||
+			(OperationMode == (u8)XCANPS_MODE_SLEEP) ||
+			(OperationMode == (u8)XCANPS_MODE_NORMAL) ||
+			(OperationMode == (u8)XCANPS_MODE_LOOPBACK) ||
+			(OperationMode == (u8)XCANPS_MODE_SNOOP));
+
+	CurrentMode = XCanPs_GetMode(InstancePtr);
+
+	/*
+	 * If current mode is Normal Mode and the mode to enter is Sleep Mode,
+	 * or if current mode is Sleep Mode and the mode to enter is Normal
+	 * Mode, no transition through Configuration Mode is needed.
+	 */
+	if ((CurrentMode == (u8)XCANPS_MODE_NORMAL) &&
+		(OperationMode == (u8)XCANPS_MODE_SLEEP)) {
+		/*
+		 * Normal Mode ---> Sleep Mode
+		 */
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
+		return;
+
+	} else if ((CurrentMode == (u8)XCANPS_MODE_SLEEP) &&
+		 (OperationMode == (u8)XCANPS_MODE_NORMAL)) {
+		/*
+		 * Sleep Mode ---> Normal Mode
+		 */
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, 0U);
+		return;
+	}
+	else {
+		/*This else was made for misra-c compliance*/
+		;
+	}
+
+	/*
+	 * If the mode transition is not any of the two cases above, CAN must
+	 * enter Configuration Mode before switching into the target operation
+	 * mode.
+	 */
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_SRR_OFFSET, 0U);
+
+	/*
+	 * Check if the device has entered Configuration Mode, if not, return to
+	 * the caller.
+	 */
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		return;
+	}
+
+	switch (OperationMode) {
+		case XCANPS_MODE_CONFIG:
+			/*
+			 * As CAN is in Configuration Mode already.
+			 * Nothing is needed to be done here.
+			 */
+			break;
+
+		case XCANPS_MODE_SLEEP:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
+
+		case XCANPS_MODE_NORMAL:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, 0U);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
+
+		case XCANPS_MODE_LOOPBACK:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
+
+		case XCANPS_MODE_SNOOP:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
+
+		default:
+			/*This default was made for misra-c compliance*/
+			break;
+
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns Status value from Status Register (SR). Use the
+* XCANPS_SR_* constants defined in xcanps_hw.h to interpret the returned
+* value.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	The 32-bit value read from Status Register.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XCanPs_GetStatus(XCanPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_SR_OFFSET);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads Receive and Transmit error counters.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	RxErrorCount is a pointer to data in which the Receive Error
+*		counter value is returned.
+* @param	TxErrorCount is a pointer to data in which the Transmit Error
+*		counter value is returned.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
+				 u8 *TxErrorCount)
+{
+	u32 ErrorCount;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(RxErrorCount != NULL);
+	Xil_AssertVoid(TxErrorCount != NULL);
+	/*
+	 * Read Error Counter Register and parse it.
+	 */
+	ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_ECR_OFFSET);
+	*RxErrorCount = (u8)((ErrorCount & XCANPS_ECR_REC_MASK) >>
+				XCANPS_ECR_REC_SHIFT);
+	*TxErrorCount = (u8)(ErrorCount & XCANPS_ECR_TEC_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads Error Status value from Error Status Register (ESR). Use
+* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the
+* returned value.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	The 32-bit value read from Error Status Register.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_ESR_OFFSET);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears Error Status bit(s) previously set in Error
+* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h
+* to create the value to pass in. If a bit was cleared in Error Status Register
+* before this function is called, it will not be modified.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @param	Mask is he 32-bit mask used to clear bits in Error Status
+*		Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear
+*		multiple bits.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+			XCANPS_ESR_OFFSET, Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends a CAN Frame. If the TX FIFO is not full then the given
+* frame is written into the the TX FIFO otherwise, it returns an error code
+* immediately.
+* This function does not wait for the given frame being sent to CAN bus.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	FramePtr is a pointer to a 32-bit aligned buffer containing the
+*		CAN frame to be sent.
+*
+* @return
+*		- XST_SUCCESS if TX FIFO was not full and the given frame was
+*		written into the FIFO.
+*		- XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the
+*		given frame.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FramePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) {
+		Status = XST_FIFO_NO_ROOM;
+	} else {
+
+		/*
+		 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
+		 */
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2]));
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3]));
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function receives a CAN Frame. This function first checks if RX FIFO is
+* empty, if not, it then reads a frame from the RX FIFO into the given buffer.
+* This function returns error code immediately if there is no frame in the RX
+* FIFO.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	FramePtr is a pointer to a 32-bit aligned buffer where the CAN
+*		frame to be written.
+*
+* @return
+*		- XST_SUCCESS if RX FIFO was not empty and a frame was read from
+*		RX FIFO successfully and written into the given buffer.
+*		- XST_NO_DATA if there is no frame to be received from the FIFO.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FramePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) {
+		Status = XST_NO_DATA;
+	} else {
+
+		/*
+		 * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device.
+		 */
+		FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_ID_OFFSET);
+		FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_DLC_OFFSET);
+		FramePtr[2] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_DW1_OFFSET));
+		FramePtr[3] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_DW2_OFFSET));
+
+		/*
+		 * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call
+		 * returns correct RX FIFO occupancy/empty condition.
+		 */
+		XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine sends a CAN High Priority frame. This function first checks if
+* TX High Priority Buffer is empty. If yes, it then writes the given frame into
+* the Buffer. If not, this function returns immediately. This function does not
+* wait for the given frame being sent to CAN bus.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	FramePtr is a pointer to a 32-bit aligned buffer containing the
+*		CAN High Priority frame to be sent.
+*
+* @return
+*		- XST_SUCCESS if TX High Priority Buffer was not full and the
+*		given frame was written into the buffer.
+*		- XST_FIFO_NO_ROOM if there is no room in the TX High Priority
+*		Buffer for this frame.
+*
+* @note
+*
+* If the frame needs to be sent immediately and not delayed by processor's
+* interrupt handling, the caller should disable interrupt at processor
+* level before invoking this function.
+*
+******************************************************************************/
+s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FramePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) {
+		Status = XST_FIFO_NO_ROOM;
+	} else {
+
+		/*
+		 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
+		 */
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_ID_OFFSET, FramePtr[0]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2]));
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3]));
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine enables individual acceptance filters. Up to 4 filters could
+* be enabled.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	FilterIndexes specifies which filter(s) to enable. Use
+*		any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or"
+*		multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
+*		to be enabled. Any filter not specified in this parameter will
+*		keep its previous enable/disable setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+******************************************************************************/
+void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes)
+{
+	u32 EnabledFilters;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Calculate the new value and write to AFR.
+	 */
+	EnabledFilters =  XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_AFR_OFFSET);
+	EnabledFilters |= FilterIndexes;
+	EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK;
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
+			EnabledFilters);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine disables individual acceptance filters. Up to 4 filters could
+* be disabled. If all acceptance filters are disabled then all the received
+* frames are stored in the RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	FilterIndexes specifies which filter(s) to disable. Use
+*		any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or"
+*		multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
+* 		to be disabled. Any filter not specified in this parameter will
+*		keep its previous enable/disable setting. If all acceptance
+*		filters are disabled then all received frames are stored in the
+*		RX FIFO.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes)
+{
+	u32 EnabledFilters;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Calculate the new value and write to AFR.
+	 */
+	EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_AFR_OFFSET);
+	EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes);
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
+			   EnabledFilters);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK
+* defined in xcanps_hw.h to interpret the returned value. If no acceptance
+* filters are enabled then all received frames are stored in the RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	The value stored in Acceptance Filter Register.
+*
+* @note		None.
+*
+*
+******************************************************************************/
+u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_AFR_OFFSET);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets values to the Acceptance Filter Mask Register (AFMR) and
+* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter.
+* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the
+* filter. Read the xcanps.h file and device specification for details.
+*
+* This function should be called only after:
+*   - The given filter is disabled by calling XCanPs_AcceptFilterDisable()
+*   - And the CAN device is ready to accept writes to AFMR and AFIR, i.e.,
+*	 XCanPs_IsAcceptFilterBusy() returns FALSE.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	FilterIndex defines which Acceptance Filter Mask and ID Register
+*		to set. Use any single XCANPS_AFR_UAF*_MASK value.
+* @param	MaskValue is the value to write to the chosen Acceptance Filter
+*		Mask Register.
+* @param	IdValue is the value to write to the chosen Acceptance Filter
+*		ID Register.
+*
+* @return
+*		- XST_SUCCESS if the values were set successfully.
+*		- XST_FAILURE if the given filter was not disabled, or the CAN
+*		device was not ready to accept writes to AFMR and AFIR.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
+			 u32 MaskValue, u32 IdValue)
+{
+	u32 EnabledFilters;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) ||
+			(FilterIndex == XCANPS_AFR_UAF3_MASK) ||
+			(FilterIndex == XCANPS_AFR_UAF2_MASK) ||
+			(FilterIndex == XCANPS_AFR_UAF1_MASK));
+
+	/*
+	 * Return an error if the given filter is currently enabled.
+	 */
+	EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr);
+	if ((EnabledFilters & FilterIndex) == FilterIndex) {
+		Status = XST_FAILURE;
+	} else {
+
+		/*
+		 * If the CAN device is not ready to accept writes to AFMR and AFIR,
+		 * return error code.
+		 */
+		if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) {
+			Status = XST_FAILURE;
+		} else {
+
+			/*
+			 * Write to the AFMR and AFIR of the specified filter.
+			 */
+			switch (FilterIndex) {
+				case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
+
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR1_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR1_OFFSET, IdValue);
+					break;
+
+				case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR2_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR2_OFFSET, IdValue);
+					break;
+
+				case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR3_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR3_OFFSET, IdValue);
+					break;
+
+				case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR4_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR4_OFFSET, IdValue);
+					break;
+
+				default:
+					/*This default was made for misra-c compliance*/
+					break;
+			}
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads the values of the Acceptance Filter Mask and ID Register
+* for the specified Acceptance Filter. Use XCANPS_IDR_* defined in xcanps_hw.h
+* to interpret the values. Read the xcanps.h file and device specification for
+* details.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	FilterIndex defines which Acceptance Filter Mask Register to get
+*		Mask and ID from. Use any single XCANPS_FILTER_* value.
+* @param	MaskValue is a pointer to the data in which the Mask value read
+*		from the chosen Acceptance Filter Mask Register is returned.
+* @param	IdValue is a pointer to the data in which the ID value read
+*		from the chosen Acceptance Filter ID Register is returned.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
+			  u32 *MaskValue, u32 *IdValue)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((FilterIndex == XCANPS_AFR_UAF4_MASK) ||
+			 (FilterIndex == XCANPS_AFR_UAF3_MASK) ||
+			 (FilterIndex == XCANPS_AFR_UAF2_MASK) ||
+			 (FilterIndex == XCANPS_AFR_UAF1_MASK));
+	Xil_AssertVoid(MaskValue != NULL);
+	Xil_AssertVoid(IdValue != NULL);
+
+	/*
+	 * Read from the AFMR and AFIR of the specified filter.
+	 */
+	switch (FilterIndex) {
+		case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR1_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR1_OFFSET);
+			break;
+
+		case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR2_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR2_OFFSET);
+			break;
+
+		case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR3_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR3_OFFSET);
+			break;
+
+		case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR4_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR4_OFFSET);
+			break;
+
+		default:
+			/*This default was made for misra-c compliance*/
+			break;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine sets Baud Rate Prescaler value. The system clock for the CAN
+* controller is divided by (Prescaler + 1) to generate the quantum clock
+* needed for sampling and synchronization. Read the device specification
+* for details.
+*
+* Baud Rate Prescaler can be set only if the CAN device is in Configuration
+* Mode. Call XCanPs_EnterMode() to enter Configuration Mode before using this
+* function.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	Prescaler is the value to set. Valid values are from 0 to 255.
+*
+* @return
+*		- XST_SUCCESS if the Baud Rate Prescaler value is set
+*		successfully.
+*		- XST_FAILURE if CAN device is not in Configuration Mode.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
+
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET,
+					(u32)Prescaler);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine gets Baud Rate Prescaler value. The system clock for the CAN
+* controller is divided by (Prescaler + 1) to generate the quantum clock
+* needed for sampling and synchronization. Read the device specification for
+* details.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	Current used Baud Rate Prescaler value. The value's range is
+*		from 0 to 255.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr)
+{
+	u32 ReadValue;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ReadValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_BRPR_OFFSET);
+	return ((u8)ReadValue);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine sets Bit time. Time segment 1, Time segment 2 and
+* Synchronization Jump Width are set in this function. Device specification
+* requires the values passed into this function be one less than the actual
+* values of these fields. Read the device specification for details.
+*
+* Bit time can be set only if the CAN device is in Configuration Mode.
+* Call XCanPs_EnterMode() to enter Configuration Mode before using this
+* function.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	SyncJumpWidth is the Synchronization Jump Width value to set.
+*		Valid values are from 0 to 3.
+* @param	TimeSegment2 is the Time Segment 2 value to set. Valid values
+*		are from 0 to 7.
+* @param	TimeSegment1 is the Time Segment 1 value to set. Valid values
+*		are from 0 to 15.
+*
+* @return
+*		- XST_SUCCESS if the Bit time is set successfully.
+*		- XST_FAILURE if CAN device is not in Configuration Mode.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
+			  u8 TimeSegment2, u8 TimeSegment1)
+{
+	u32 Value;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(SyncJumpWidth <= (u8)3U);
+	Xil_AssertNonvoid(TimeSegment2 <= (u8)7U);
+	Xil_AssertNonvoid(TimeSegment1 <= (u8)15U );
+
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
+
+		Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK;
+		Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) &
+			XCANPS_BTR_TS2_MASK;
+		Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) &
+			XCANPS_BTR_SJW_MASK;
+
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_BTR_OFFSET, Value);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine gets Bit time. Time segment 1, Time segment 2 and
+* Synchronization Jump Width values are read in this function. According to
+* device specification, the actual value of each of these fields is one
+* more than the value read. Read the device specification for details.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	SyncJumpWidth will store the Synchronization Jump Width value
+*		after this function returns. Its value ranges from 0 to 3.
+* @param	TimeSegment2 will store the Time Segment 2 value after this
+*		function returns. Its value ranges from 0 to 7.
+* @param	TimeSegment1 will store the Time Segment 1 value after this
+*		function returns. Its value ranges from 0 to 15.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
+			   u8 *TimeSegment2, u8 *TimeSegment1)
+{
+	u32 Value;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(SyncJumpWidth != NULL);
+	Xil_AssertVoid(TimeSegment2 != NULL);
+	Xil_AssertVoid(TimeSegment1 != NULL);
+
+	Value = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_BTR_OFFSET);
+
+	*TimeSegment1 = (u8) (Value & XCANPS_BTR_TS1_MASK);
+	*TimeSegment2 =
+		(u8) ((Value & XCANPS_BTR_TS2_MASK) >> XCANPS_BTR_TS2_SHIFT);
+	*SyncJumpWidth =
+		(u8) ((Value & XCANPS_BTR_SJW_MASK) >> XCANPS_BTR_SJW_SHIFT);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This routine sets the Rx Full threshold in the Watermark Interrupt Register.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	Threshold is the threshold to be set. The valid values are
+*		from 1 to 63.
+*
+* @return
+*		- XST_FAILURE - If the CAN device is not in Configuration Mode.
+*		- XST_SUCCESS - If the Rx Full threshold is set in Watermark
+*		Interrupt Register.
+*
+* @note		The threshold can only be set when the CAN device is in the
+*		configuration mode.
+*
+*****************************************************************************/
+s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
+{
+
+	u32 ThrReg;
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Threshold <= (u8)63);
+
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
+
+		ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET);
+
+		ThrReg &= XCANPS_WIR_EW_MASK;
+		ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET, ThrReg);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This routine gets the Rx Full threshold from the Watermark Interrupt Register.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	The Rx FIFO full watermark threshold value. The valid values
+*		are 1 to 63.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	return (u8) (XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_WIR_OFFSET) &
+					XCANPS_WIR_FW_MASK);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This routine sets the Tx Empty Threshold in the Watermark Interrupt Register.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	Threshold is the threshold to be set. The valid values are
+*		from 1 to 63.
+*
+* @return
+*		- XST_FAILURE - If the CAN device is not in Configuration Mode.
+*		- XST_SUCCESS - If the threshold is set in Watermark
+*		Interrupt Register.
+*
+* @note		The threshold can only be set when the CAN device is in the
+*		configuration mode.
+*
+*****************************************************************************/
+s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
+{
+	u32 ThrReg;
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Threshold <= (u8)63);
+
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
+
+		ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET);
+
+		ThrReg &= XCANPS_WIR_FW_MASK;
+		ThrReg |= (((u32)Threshold << XCANPS_WIR_EW_SHIFT)
+				& XCANPS_WIR_EW_MASK);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET, ThrReg);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This routine gets the Tx Empty threshold from Watermark Interrupt Register.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	The Tx Empty FIFO threshold value. The valid values are 1 to 63.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	return (u8) ((XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET) & XCANPS_WIR_EW_MASK) >>
+					XCANPS_WIR_EW_SHIFT);
+}
+
+
+
+/******************************************************************************/
+/*
+ * This routine is a stub for the asynchronous callbacks. The stub is here in
+ * case the upper layer forgot to set the handler(s). On initialization, all
+ * handlers are set to this callback. It is considered an error for this handler
+ * to be invoked.
+ *
+ ******************************************************************************/
+static void StubHandler(void)
+{
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h
new file mode 100644
index 000000000..b180e37ec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps.h
+* @addtogroup canps_v3_0
+* @{
+* @details
+*
+* The Xilinx CAN driver component.  This component supports the Xilinx
+* CAN Controller.
+*
+* The CAN Controller supports the following features:
+*	- Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
+*	- Supports both Standard (11 bit Identifier) and Extended (29 bit
+*	  Identifier) frames.
+*	- Supports Bit Rates up to 1 Mbps.
+*	- Transmit message object FIFO with a user configurable depth of
+*	  up to 64 message objects.
+*	- Transmit prioritization through one TX High Priority Buffer.
+*	- Receive message object FIFO with a user configurable depth of
+*	  up to 64 message objects.
+*	- Watermark interrupts for Rx FIFO with configurable Watermark.
+*	- Acceptance filtering with 4 acceptance filters.
+*	- Sleep mode with automatic wake up.
+*	- Loop Back mode for diagnostic applications.
+*	- Snoop mode for diagnostic applications.
+*	- Maskable Error and Status Interrupts.
+*	- Readable Error Counters.
+*	- External PHY chip required.
+*	- Receive Timestamp.
+*
+* The device driver supports all the features listed above, if applicable.
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the CAN. The driver handles transmission and reception of
+* CAN frames, as well as configuration of the controller. The driver is simply a
+* pass-through mechanism between a protocol stack and the CAN. A single device
+* driver can support multiple CANs.
+*
+* Since the driver is a simple pass-through mechanism between a protocol stack
+* and the CAN, no assembly or disassembly of CAN frames is done at the
+* driver-level. This assumes that the protocol stack passes a correctly
+* formatted CAN frame to the driver for transmission, and that the driver
+* does not validate the contents of an incoming frame
+*
+* <b>Operation Modes</b>
+*
+* The CAN controller supports the following modes of operation:
+*   - <b>Configuration Mode</b>: In this mode the CAN timing parameters and
+*	 Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
+*	 controller loses synchronization with the CAN bus and drives a
+*	 constant recessive bit on the bus line. The Error Counter Register are
+*	 reset. The CAN controller does not receive or transmit any messages
+*	 even if there are pending transmit requests from the TX FIFO or the TX
+*	 High Priority Buffer. The Storage FIFOs and the CAN configuration
+*	 registers are still accessible.
+*   - <b>Normal Mode</b>:In Normal Mode the CAN controller participates in bus
+*	 communication, by transmitting and receiving messages.
+*   - <b>Sleep Mode</b>: In Sleep Mode the CAN Controller does not transmit any
+*	 messages. However, if any other node transmits a message, then the CAN
+*	 Controller receives the transmitted message and exits from Sleep Mode.
+*	 If there are new transmission requests from either the TX FIFO or the
+*	 TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
+*	 requests are not serviced, and the CAN Controller continues to remain
+*	 in Sleep Mode. Interrupts are generated when the CAN controller enters
+*	Sleep mode or Wakes up from Sleep mode.
+*   - <b>Loop Back Mode</b>: In Loop Back mode, the CAN controller transmits a
+*	 recessive bit stream on to the CAN Bus. Any message that is transmitted
+*	 is looped back to the �Rx� line and acknowledged. The CAN controller
+*	 thus receives any message that it transmits. It does not participate in
+*	 normal bus communication and does not receive any messages that are
+*	 transmitted by other CAN nodes. This mode is used for diagnostic
+*	 purposes.
+*   - <b>Snoop Mode</b>: In Snoop mode, the CAN controller transmits a
+*	 recessive bit stream on to the CAN Bus and does not participate
+*	 in normal bus communication but receives messages that are transmitted
+*	 by other CAN nodes. This mode is used for diagnostic purposes.
+*
+*
+* <b>Buffer Alignment</b>
+*
+* It is important to note that frame buffers passed to the driver must be
+* 32-bit aligned.
+*
+* <b>Receive Address Filtering</b>
+*
+* The device can be set to accept frames whose Identifiers match any of the
+* 4 filters set in the Acceptance Filter Mask/ID registers.
+*
+* The incoming Identifier is masked with the bits in the Acceptance Filter Mask
+* Register. This value is compared with the result of masking the bits in the
+* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If
+* both these values are equal, the message will be stored in the RX FIFO.
+*
+* Acceptance Filtering is performed by each of the defined acceptance filters.
+* If the incoming identifier passes through any acceptance filter then the
+* frame is stored in the RX FIFO.
+*
+* If the Accpetance Filters are not set up then all the received messages are
+* stroed in the RX FIFO.
+*
+* <b>PHY Communication</b>
+*
+* This driver does not provide any mechanism for directly programming PHY.
+*
+* <b>Interrupts</b>
+*
+* The driver has no dependencies on the interrupt controller. The driver
+* provides an interrupt handler. User of this driver needs to provide
+* callback functions. An interrupt handler example is available with
+* the driver.
+*
+* <b>Threads</b>
+*
+* This driver is not thread safe.  Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b>Device Reset</b>
+*
+* Bus Off interrupt that can occur in the device requires a device reset.
+* The user is responsible for resetting the device and re-configuring it
+* based on its needs (the driver does not save the current configuration).
+* When integrating into an RTOS, these reset and re-configure obligations are
+* taken care of by the OS adapter software if it exists for that RTOS.
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xcanps_g.c files.
+* A table is defined where each entry contains configuration information
+* for a CAN device.  This information includes such things as the base address
+* of the memory-mapped device.
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>Building the driver</b>
+*
+* The XCanPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*			SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.1 adk     10/11/15  Fixed CR#911958 Add support for Tx Watermark example.
+*			Data mismatch while sending data less than 8 bytes.
+* 3.1 nsk     12/21/15  Updated XCanPs_IntrHandler in xcanps_intr.c to handle
+*			error interrupts correctly. CR#925615
+* </pre>
+*
+******************************************************************************/
+#ifndef XCANPS_H			/* prevent circular inclusions */
+#define XCANPS_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xcanps_hw.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name CAN operation modes
+ *  @{
+ */
+#define XCANPS_MODE_CONFIG	0x00000001U /**< Configuration mode */
+#define XCANPS_MODE_NORMAL	0x00000002U /**< Normal mode */
+#define XCANPS_MODE_LOOPBACK	0x00000004U /**< Loop Back mode */
+#define XCANPS_MODE_SLEEP	0x00000008U /**< Sleep mode */
+#define XCANPS_MODE_SNOOP	0x00000010U /**< Snoop mode */
+/* @} */
+
+/** @name Callback identifiers used as parameters to XCanPs_SetHandler()
+ *  @{
+ */
+#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */
+#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/
+#define XCANPS_HANDLER_ERROR  3U /**< Handler type for error interrupt */
+#define XCANPS_HANDLER_EVENT  4U /**< Handler type for all other interrupts */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XCanPs_Config;
+
+/******************************************************************************/
+/**
+ * Callback type for frame sending and reception interrupts.
+ *
+ * @param 	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions, and passed back to the
+ *		upper layer when the callback is invoked.
+*******************************************************************************/
+typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef);
+
+/******************************************************************************/
+/**
+ * Callback type for error interrupt.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions, and passed back to the
+ *		upper layer when the callback is invoked.
+ * @param	ErrorMask is a bit mask indicating the cause of the error. Its
+ *		value equals 'OR'ing one or more XCANPS_ESR_* values defined in
+ *		xcanps_hw.h
+*******************************************************************************/
+typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
+
+/******************************************************************************/
+/**
+ * Callback type for all kinds of interrupts except sending frame interrupt,
+ * receiving frame interrupt, and error interrupt.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions, and passed back to the
+ *		upper layer when the callback is invoked.
+ * @param	Mask is a bit mask indicating the pending interrupts. Its value
+ *		equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h
+*******************************************************************************/
+typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask);
+
+/**
+ * The XCanPs driver instance data. The user is required to allocate a
+ * variable of this type for every CAN device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XCanPs_Config CanConfig; 	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+
+	/**
+	 * Callback and callback reference for TXOK interrupt.
+	 */
+	XCanPs_SendRecvHandler SendHandler;
+	void *SendRef;
+
+	/**
+	 * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts.
+	 */
+	XCanPs_SendRecvHandler RecvHandler;
+	void *RecvRef;
+
+	/**
+	 * Callback and callback reference for ERROR interrupt.
+	 */
+	XCanPs_ErrorHandler ErrorHandler;
+	void *ErrorRef;
+
+	/**
+	 * Callback  and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/
+	 * Wakeup/Sleep/Bus off/ARBLST interrupts.
+	 */
+	XCanPs_EventHandler EventHandler;
+	void *EventRef;
+
+} XCanPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the transmission is complete.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+*		- TRUE if the transmission is done.
+*		- FALSE if the transmission is not done.
+*
+* @note		C-Style signature:
+*		int XCanPs_IsTxDone(XCanPs *InstancePtr)
+*
+*******************************************************************************/
+#define XCanPs_IsTxDone(InstancePtr) \
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),		\
+		XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the transmission FIFO is full.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+*		- TRUE if TX FIFO is full.
+*		- FALSE if the TX FIFO is NOT full.
+*
+* @note		C-Style signature:
+*		int XCanPs_IsTxFifoFull(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsTxFifoFull(InstancePtr) \
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the Transmission High Priority Buffer is full.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+*		- TRUE if the TX High Priority Buffer is full.
+*		- FALSE if the TX High Priority Buffer is NOT full.
+*
+* @note		C-Style signature:
+*		int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsHighPriorityBufFull(InstancePtr) \
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the receive FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+*		- TRUE if RX FIFO is empty.
+*		- FALSE if the RX FIFO is NOT empty.
+*
+* @note		C-Style signature:
+*		int XCanPs_IsRxEmpty(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsRxEmpty(InstancePtr) \
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the CAN device is ready for the driver to change
+* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask
+* Registers (AFMR).
+*
+* AFIR and AFMR for a filter are changeable only after the filter is disabled
+* and this routine returns FALSE. The filter can be disabled using the
+* XCanPs_AcceptFilterDisable function.
+*
+* Use the XCanPs_Accept_* functions for configuring the acceptance filters.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+*		- TRUE if the device is busy and NOT ready to accept writes to
+*		AFIR and AFMR.
+*		- FALSE if the device is ready to accept writes to AFIR and
+*		AFMR.
+*
+* @note		C-Style signature:
+*		int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsAcceptFilterBusy(InstancePtr) 		\
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro calculates CAN message identifier value given identifier field
+* values.
+*
+* @param	StandardId contains Standard Message ID value.
+* @param	SubRemoteTransReq contains Substitute Remote Transmission
+*		Request value.
+* @param	IdExtension contains Identifier Extension value.
+* @param	ExtendedId contains Extended Message ID value.
+* @param	RemoteTransReq contains Remote Transmission Request value.
+*
+* @return	Message Identifier value.
+*
+* @note		C-Style signature:
+*		u32 XCanPs_CreateIdValue(u32 StandardId,
+*					u32 SubRemoteTransReq,
+*					u32 IdExtension, u32 ExtendedId,
+*					u32 RemoteTransReq)
+*
+*		Read the CAN specification for meaning of each parameter.
+*
+*****************************************************************************/
+#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \
+		ExtendedId, RemoteTransReq) 				\
+ ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) |	\
+ (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\
+ (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) |	\
+ (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) |	\
+ ((RemoteTransReq) & XCANPS_IDR_RTR_MASK))
+
+
+/****************************************************************************/
+/**
+*
+* This macro calculates value for Data Length Code register given Data
+* Length Code value.
+*
+* @param	DataLengCode indicates Data Length Code value.
+*
+* @return	Value that can be assigned to Data Length Code register.
+*
+* @note		C-Style signature:
+*		u32 XCanPs_CreateDlcValue(u32 DataLengCode)
+*
+*		Read the CAN specification for meaning of Data Length Code.
+*
+*****************************************************************************/
+#define XCanPs_CreateDlcValue(DataLengCode) \
+	(((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the timestamp in the Timestamp Control Register.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XCanPs_ClearTimestamp(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_ClearTimestamp(InstancePtr) 			\
+	XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, 		\
+				XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xcanps.c
+ */
+s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+void XCanPs_Reset(XCanPs *InstancePtr);
+u8 XCanPs_GetMode(XCanPs *InstancePtr);
+void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode);
+u32 XCanPs_GetStatus(XCanPs *InstancePtr);
+void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
+				 u8 *TxErrorCount);
+u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
+void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
+s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
+void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
+void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
+u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
+s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
+			 u32 MaskValue, u32 IdValue);
+void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
+			  u32 *MaskValue, u32 *IdValue);
+
+s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
+u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
+s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
+			  u8 TimeSegment2, u8 TimeSegment1);
+void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
+			   u8 *TimeSegment2, u8 *TimeSegment1);
+
+s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
+s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr);
+
+/*
+ * Diagnostic functions in xcanps_selftest.c
+ */
+s32 XCanPs_SelfTest(XCanPs *InstancePtr);
+
+/*
+ * Functions in xcanps_intr.c
+ */
+void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask);
+void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask);
+u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
+u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
+void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
+void XCanPs_IntrHandler(void *InstancePtr);
+s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
+			void *CallBackFunc, void *CallBackRef);
+
+/*
+ * Functions in xcanps_sinit.c
+ */
+XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
new file mode 100644
index 000000000..4063a44eb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xcanps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XCanPs_Config XCanPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_CAN_1_DEVICE_ID,
+		XPAR_PSU_CAN_1_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c
new file mode 100644
index 000000000..bbb96120a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_hw.c
+* @addtogroup canps_v3_0
+* @{
+*
+* This file contains the implementation of the canps interface reset sequence
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.02a adk  08/08/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function resets the CAN device. Calling this function resets the device
+* immediately, and any pending transmission or reception is terminated at once.
+* Both Object Layer and Transfer Layer are reset. This function does not reset
+* the Physical Layer. All registers are reset to the default values, and no
+* previous status will be restored. TX FIFO, RX FIFO and TX High Priority
+* Buffer are also reset.
+*
+* The CAN device will be in Configuration Mode immediately after this function
+* returns.
+*
+* @param	BaseAddr is the baseaddress of the interface.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_ResetHw(u32 BaseAddr)
+{
+	XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \
+			   XCANPS_SRR_SRST_MASK);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h
new file mode 100644
index 000000000..9fe681aaf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h
@@ -0,0 +1,369 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_hw.h
+* @addtogroup canps_v3_0
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xcanps.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+* 3.00  kvn   02/13/15  Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XCANPS_HW_H		/* prevent circular inclusions */
+#define XCANPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the CAN. Each register is 32 bits.
+ *  @{
+ */
+#define XCANPS_SRR_OFFSET	  	0x00000000U /**< Software Reset Register */
+#define XCANPS_MSR_OFFSET	  	0x00000004U /**< Mode Select Register */
+#define XCANPS_BRPR_OFFSET	  	0x00000008U /**< Baud Rate Prescaler */
+#define XCANPS_BTR_OFFSET	  	0x0000000CU /**< Bit Timing Register */
+#define XCANPS_ECR_OFFSET	  	0x00000010U /**< Error Counter Register */
+#define XCANPS_ESR_OFFSET	  	0x00000014U /**< Error Status Register */
+#define XCANPS_SR_OFFSET	  	0x00000018U /**< Status Register */
+
+#define XCANPS_ISR_OFFSET	  	0x0000001CU /**< Interrupt Status Register */
+#define XCANPS_IER_OFFSET	  	0x00000020U /**< Interrupt Enable Register */
+#define XCANPS_ICR_OFFSET	  	0x00000024U /**< Interrupt Clear Register */
+#define XCANPS_TCR_OFFSET	  	0x00000028U /**< Timestamp Control Register */
+#define XCANPS_WIR_OFFSET	  	0x0000002CU /**< Watermark Interrupt Reg */
+
+#define XCANPS_TXFIFO_ID_OFFSET  	0x00000030U /**< TX FIFO ID */
+#define XCANPS_TXFIFO_DLC_OFFSET 	0x00000034U /**< TX FIFO DLC */
+#define XCANPS_TXFIFO_DW1_OFFSET	0x00000038U /**< TX FIFO Data Word 1 */
+#define XCANPS_TXFIFO_DW2_OFFSET 	0x0000003CU /**< TX FIFO Data Word 2 */
+
+#define XCANPS_TXHPB_ID_OFFSET   	0x00000040U /**< TX High Priority Buffer ID */
+#define XCANPS_TXHPB_DLC_OFFSET  	0x00000044U /**< TX High Priority Buffer DLC */
+#define XCANPS_TXHPB_DW1_OFFSET  	0x00000048U /**< TX High Priority Buf Data 1 */
+#define XCANPS_TXHPB_DW2_OFFSET  	0x0000004CU /**< TX High Priority Buf Data Word 2 */
+
+#define XCANPS_RXFIFO_ID_OFFSET  	0x00000050U /**< RX FIFO ID */
+#define XCANPS_RXFIFO_DLC_OFFSET 	0x00000054U /**< RX FIFO DLC */
+#define XCANPS_RXFIFO_DW1_OFFSET 	0x00000058U /**< RX FIFO Data Word 1 */
+#define XCANPS_RXFIFO_DW2_OFFSET 	0x0000005CU /**< RX FIFO Data Word 2 */
+
+#define XCANPS_AFR_OFFSET	  	0x00000060U /**< Acceptance Filter Register */
+#define XCANPS_AFMR1_OFFSET	  	0x00000064U /**< Acceptance Filter Mask 1 */
+#define XCANPS_AFIR1_OFFSET	  	0x00000068U /**< Acceptance Filter ID  1 */
+#define XCANPS_AFMR2_OFFSET	  	0x0000006CU /**< Acceptance Filter Mask  2 */
+#define XCANPS_AFIR2_OFFSET	  	0x00000070U /**< Acceptance Filter ID 2 */
+#define XCANPS_AFMR3_OFFSET	  	0x00000074U /**< Acceptance Filter Mask 3 */
+#define XCANPS_AFIR3_OFFSET	  	0x00000078U /**< Acceptance Filter ID 3 */
+#define XCANPS_AFMR4_OFFSET	  	0x0000007CU /**< Acceptance Filter Mask  4 */
+#define XCANPS_AFIR4_OFFSET	  	0x00000080U /**< Acceptance Filter ID 4 */
+/* @} */
+
+/** @name Software Reset Register (SRR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_SRR_CEN_MASK		0x00000002U  /**< Can Enable */
+#define XCANPS_SRR_SRST_MASK	0x00000001U  /**< Reset */
+/* @} */
+
+/** @name Mode Select Register (MSR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_MSR_SNOOP_MASK	0x00000004U /**< Snoop Mode Select */
+#define XCANPS_MSR_LBACK_MASK	0x00000002U /**< Loop Back Mode Select */
+#define XCANPS_MSR_SLEEP_MASK	0x00000001U /**< Sleep Mode Select */
+/* @} */
+
+/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_BRPR_BRP_MASK	0x000000FFU /**< Baud Rate Prescaler */
+/* @} */
+
+/** @name Bit Timing Register (BTR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_BTR_SJW_MASK	0x00000180U /**< Synchronization Jump Width */
+#define XCANPS_BTR_SJW_SHIFT	7U
+#define XCANPS_BTR_TS2_MASK	0x00000070U /**< Time Segment 2 */
+#define XCANPS_BTR_TS2_SHIFT	4U
+#define XCANPS_BTR_TS1_MASK	0x0000000FU /**< Time Segment 1 */
+/* @} */
+
+/** @name Error Counter Register (ECR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_ECR_REC_MASK	0x0000FF00U /**< Receive Error Counter */
+#define XCANPS_ECR_REC_SHIFT		 8U
+#define XCANPS_ECR_TEC_MASK	0x000000FFU /**< Transmit Error Counter */
+/* @} */
+
+/** @name Error Status Register (ESR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_ESR_ACKER_MASK	0x00000010U /**< ACK Error */
+#define XCANPS_ESR_BERR_MASK	0x00000008U /**< Bit Error */
+#define XCANPS_ESR_STER_MASK	0x00000004U /**< Stuff Error */
+#define XCANPS_ESR_FMER_MASK	0x00000002U /**< Form Error */
+#define XCANPS_ESR_CRCER_MASK	0x00000001U /**< CRC Error */
+/* @} */
+
+/** @name Status Register (SR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_SR_SNOOP_MASK	0x00001000U /**< Snoop Mask */
+#define XCANPS_SR_ACFBSY_MASK	0x00000800U /**< Acceptance Filter busy */
+#define XCANPS_SR_TXFLL_MASK	0x00000400U /**< TX FIFO is full */
+#define XCANPS_SR_TXBFLL_MASK	0x00000200U /**< TX High Priority Buffer full */
+#define XCANPS_SR_ESTAT_MASK	0x00000180U /**< Error Status */
+#define XCANPS_SR_ESTAT_SHIFT			 7U
+#define XCANPS_SR_ERRWRN_MASK	0x00000040U /**< Error Warning */
+#define XCANPS_SR_BBSY_MASK		0x00000020U /**< Bus Busy */
+#define XCANPS_SR_BIDLE_MASK	0x00000010U /**< Bus Idle */
+#define XCANPS_SR_NORMAL_MASK	0x00000008U /**< Normal Mode */
+#define XCANPS_SR_SLEEP_MASK	0x00000004U /**< Sleep Mode */
+#define XCANPS_SR_LBACK_MASK	0x00000002U /**< Loop Back Mode */
+#define XCANPS_SR_CONFIG_MASK	0x00000001U /**< Configuration Mode */
+/* @} */
+
+/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_IXR_TXFEMP_MASK   0x00004000U /**< Tx Fifo Empty Interrupt */
+#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */
+#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */
+#define XCANPS_IXR_WKUP_MASK	 0x00000800U /**< Wake up Interrupt */
+#define XCANPS_IXR_SLP_MASK		0x00000400U /**< Sleep Interrupt */
+#define XCANPS_IXR_BSOFF_MASK	0x00000200U /**< Bus Off Interrupt */
+#define XCANPS_IXR_ERROR_MASK	0x00000100U /**< Error Interrupt */
+#define XCANPS_IXR_RXNEMP_MASK	0x00000080U /**< RX FIFO Not Empty Interrupt */
+#define XCANPS_IXR_RXOFLW_MASK	0x00000040U /**< RX FIFO Overflow Interrupt */
+#define XCANPS_IXR_RXUFLW_MASK	0x00000020U /**< RX FIFO Underflow Interrupt */
+#define XCANPS_IXR_RXOK_MASK	0x00000010U /**< New Message Received Intr */
+#define XCANPS_IXR_TXBFLL_MASK	0x00000008U /**< TX High Priority Buf Full */
+#define XCANPS_IXR_TXFLL_MASK	0x00000004U /**< TX FIFO Full Interrupt */
+#define XCANPS_IXR_TXOK_MASK	0x00000002U /**< TX Successful Interrupt */
+#define XCANPS_IXR_ARBLST_MASK	0x00000001U /**< Arbitration Lost Interrupt */
+#define XCANPS_IXR_ALL		((u32)XCANPS_IXR_RXFWMFLL_MASK | \
+				(u32)XCANPS_IXR_WKUP_MASK   | \
+				(u32)XCANPS_IXR_SLP_MASK	| \
+				(u32)XCANPS_IXR_BSOFF_MASK  | \
+				(u32)XCANPS_IXR_ERROR_MASK  | \
+				(u32)XCANPS_IXR_RXNEMP_MASK | \
+				(u32)XCANPS_IXR_RXOFLW_MASK | \
+				(u32)XCANPS_IXR_RXUFLW_MASK | \
+				(u32)XCANPS_IXR_RXOK_MASK   | \
+				(u32)XCANPS_IXR_TXBFLL_MASK | \
+				(u32)XCANPS_IXR_TXFLL_MASK  | \
+				(u32)XCANPS_IXR_TXOK_MASK   | \
+				(u32)XCANPS_IXR_ARBLST_MASK)
+/* @} */
+
+/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_TCR_CTS_MASK	0x00000001U /**< Clear Timestamp counter mask */
+/* @} */
+
+/** @name CAN Watermark Register (WIR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_WIR_FW_MASK   	0x0000003FU /**< Rx Full Threshold mask */
+#define XCANPS_WIR_EW_MASK 	0x00003F00U /**< Tx Empty Threshold mask */
+#define XCANPS_WIR_EW_SHIFT 	0x00000008U /**< Tx Empty Threshold shift */
+
+/* @} */
+
+/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
+				Mask/Acceptance Filter ID)
+ *  @{
+ */
+#define XCANPS_IDR_ID1_MASK	0xFFE00000U /**< Standard Messg Identifier */
+#define XCANPS_IDR_ID1_SHIFT	21U
+#define XCANPS_IDR_SRR_MASK	0x00100000U /**< Substitute Remote TX Req */
+#define XCANPS_IDR_SRR_SHIFT	20U
+#define XCANPS_IDR_IDE_MASK	0x00080000U /**< Identifier Extension */
+#define XCANPS_IDR_IDE_SHIFT	19U
+#define XCANPS_IDR_ID2_MASK	0x0007FFFEU /**< Extended Message Ident */
+#define XCANPS_IDR_ID2_SHIFT	1U
+#define XCANPS_IDR_RTR_MASK	0x00000001U /**< Remote TX Request */
+/* @} */
+
+/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
+ *  @{
+ */
+#define XCANPS_DLCR_DLC_MASK	 0xF0000000U	/**< Data Length Code */
+#define XCANPS_DLCR_DLC_SHIFT	 28U
+#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU	/**< Timestamp Mask (Rx only) */
+
+/* @} */
+
+/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
+ *  @{
+ */
+#define XCANPS_DW1R_DB0_MASK	0xFF000000U /**< Data Byte 0 */
+#define XCANPS_DW1R_DB0_SHIFT	24U
+#define XCANPS_DW1R_DB1_MASK	0x00FF0000U /**< Data Byte 1 */
+#define XCANPS_DW1R_DB1_SHIFT	16U
+#define XCANPS_DW1R_DB2_MASK	0x0000FF00U /**< Data Byte 2 */
+#define XCANPS_DW1R_DB2_SHIFT	8U
+#define XCANPS_DW1R_DB3_MASK	0x000000FFU /**< Data Byte 3 */
+/* @} */
+
+/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
+ *  @{
+ */
+#define XCANPS_DW2R_DB4_MASK	0xFF000000U /**< Data Byte 4 */
+#define XCANPS_DW2R_DB4_SHIFT	24U
+#define XCANPS_DW2R_DB5_MASK	0x00FF0000U /**< Data Byte 5 */
+#define XCANPS_DW2R_DB5_SHIFT	16U
+#define XCANPS_DW2R_DB6_MASK	0x0000FF00U /**< Data Byte 6 */
+#define XCANPS_DW2R_DB6_SHIFT	8U
+#define XCANPS_DW2R_DB7_MASK	0x000000FFU /**< Data Byte 7 */
+/* @} */
+
+/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
+ *  @{
+ */
+#define XCANPS_AFR_UAF4_MASK	0x00000008U /**< Use Acceptance Filter No.4 */
+#define XCANPS_AFR_UAF3_MASK	0x00000004U /**< Use Acceptance Filter No.3 */
+#define XCANPS_AFR_UAF2_MASK	0x00000002U /**< Use Acceptance Filter No.2 */
+#define XCANPS_AFR_UAF1_MASK	0x00000001U /**< Use Acceptance Filter No.1 */
+#define XCANPS_AFR_UAF_ALL_MASK	((u32)XCANPS_AFR_UAF4_MASK | \
+					(u32)XCANPS_AFR_UAF3_MASK | \
+					(u32)XCANPS_AFR_UAF2_MASK | \
+					(u32)XCANPS_AFR_UAF1_MASK)
+/* @} */
+
+/** @name CAN frame length constants
+ *  @{
+ */
+#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */
+/* @} */
+
+/* For backwards compatibilty */
+#define XCANPS_TXBUF_ID_OFFSET   XCANPS_TXHPB_ID_OFFSET
+#define XCANPS_TXBUF_DLC_OFFSET  XCANPS_TXHPB_DLC_OFFSET
+#define XCANPS_TXBUF_DW1_OFFSET  XCANPS_TXHPB_DW1_OFFSET
+#define XCANPS_TXBUF_DW2_OFFSET  XCANPS_TXHPB_DW2_OFFSET
+
+#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK
+#define XCANPS_RXWIR_OFFSET 	 XCANPS_WIR_OFFSET
+#define XCANPS_IXR_RXFLL_MASK 	 XCANPS_IXR_RXFWMFLL_MASK
+
+
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XCanPs_ReadReg(BaseAddr, RegOffset) \
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the CanPs interface
+ */
+void XCanPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c
new file mode 100644
index 000000000..f6721ca75
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c
@@ -0,0 +1,421 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_intr.c
+* @addtogroup canps_v3_0
+* @{
+*
+* This file contains functions related to CAN interrupt handling.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   nsk    12/21/15 Updated XCanPs_IntrHandler to handle error
+*			interrupts correctly. CR#925615
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+*
+* This routine enables interrupt(s). Use the XCANPS_IXR_* constants defined in
+* xcanps_hw.h to create the bit-mask to enable interrupts.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	Mask is the mask to enable. Bit positions of 1 will be enabled.
+*		Bit positions of 0 will keep the previous setting. This mask is
+*		formed by OR'ing XCANPS_IXR_* bits defined in xcanps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask)
+{
+	u32 IntrValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write to the IER to enable the specified interrupts.
+	 */
+	IntrValue = XCanPs_IntrGetEnabled(InstancePtr);
+	IntrValue |= Mask;
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+			XCANPS_IER_OFFSET, IntrValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This routine disables interrupt(s). Use the XCANPS_IXR_* constants defined in
+* xcanps_hw.h to create the bit-mask to disable interrupt(s).
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	Mask is the mask to disable. Bit positions of 1 will be
+*		disabled. Bit positions of 0 will keep the previous setting.
+*		This mask is formed by OR'ing XCANPS_IXR_* bits defined in
+*		xcanps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask)
+{
+	u32 IntrValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write to the IER to disable the specified interrupts.
+	 */
+	IntrValue = XCanPs_IntrGetEnabled(InstancePtr);
+	IntrValue &= ~Mask;
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+			XCANPS_IER_OFFSET, IntrValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This routine returns enabled interrupt(s). Use the XCANPS_IXR_* constants
+* defined in xcanps_hw.h to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	Enabled interrupt(s) in a 32-bit format.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_IER_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This routine returns interrupt status read from Interrupt Status Register.
+* Use the XCANPS_IXR_* constants defined in xcanps_hw.h to interpret the
+* returned value.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return	The value stored in Interrupt Status Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_ISR_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears interrupt(s). Every bit set in Interrupt Status
+* Register indicates that a specific type of interrupt is occurring, and this
+* function clears one or more interrupts by writing a bit mask to Interrupt
+* Clear Register.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	Mask is the mask to clear. Bit positions of 1 will be cleared.
+*		Bit positions of 0 will not change the previous interrupt
+*		status. This mask is formed by OR'ing XCANPS_IXR_* bits defined
+* 		in xcanps_hw.h.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask)
+{
+	u32 IntrValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Clear the currently pending interrupts.
+	 */
+	IntrValue = XCanPs_IntrGetStatus(InstancePtr);
+	IntrValue &= Mask;
+	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_ICR_OFFSET,
+				IntrValue);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is the interrupt handler for the CAN driver.
+*
+* This handler reads the interrupt status from the ISR, determines the source of
+* the interrupts, calls according callbacks, and finally clears the interrupts.
+*
+* Application beyond this driver is responsible for providing callbacks to
+* handle interrupts and installing the callbacks using XCanPs_SetHandler()
+* during initialization phase. An example delivered with this driver
+* demonstrates how this could be done.
+*
+* @param	InstancePtr is a pointer to the XCanPs instance that just
+*		interrupted.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCanPs_IntrHandler(void *InstancePtr)
+{
+	u32 PendingIntr;
+	u32 EventIntr;
+	u32 ErrorStatus;
+	XCanPs *CanPtr = (XCanPs *) ((void *)InstancePtr);
+
+	Xil_AssertVoid(CanPtr != NULL);
+	Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PendingIntr = XCanPs_IntrGetStatus(CanPtr);
+	PendingIntr &= XCanPs_IntrGetEnabled(CanPtr);
+
+	/*
+	 * Clear all pending interrupts.
+	 * Rising Edge interrupt
+	 */
+	XCanPs_IntrClear(CanPtr, PendingIntr);
+
+	/*
+	 * An error interrupt is occurring.
+	 */
+	if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) &&
+		(CanPtr->ErrorHandler != NULL)) {
+			ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr);
+			CanPtr->ErrorHandler(CanPtr->ErrorRef,ErrorStatus);
+		/*
+		 * Clear Error Status Register.
+		 */
+		XCanPs_ClearBusErrorStatus(CanPtr,ErrorStatus);
+	}
+
+	/*
+	 * Check if any following event interrupt is pending:
+	 *	  - RX FIFO Overflow
+	 *	  - RX FIFO Underflow
+	 *	  - TX High Priority Buffer full
+	 *	  - TX FIFO Full
+	 *	  - Wake up from sleep mode
+	 *	  - Enter sleep mode
+	 *	  - Enter Bus off status
+	 *	  - Arbitration is lost
+	 *
+	 * If so, call event callback provided by upper level.
+	 */
+	EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK |
+				(u32)XCANPS_IXR_RXUFLW_MASK |
+				(u32)XCANPS_IXR_TXBFLL_MASK |
+				(u32)XCANPS_IXR_TXFLL_MASK |
+				(u32)XCANPS_IXR_WKUP_MASK |
+				(u32)XCANPS_IXR_SLP_MASK |
+				(u32)XCANPS_IXR_BSOFF_MASK |
+				(u32)XCANPS_IXR_ARBLST_MASK);
+	if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) {
+		CanPtr->EventHandler(CanPtr->EventRef, EventIntr);
+
+		if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) {
+			/*
+			 * Event callback should reset whole device if "Enter
+			 * Bus Off Status" interrupt occurred. All pending
+			 * interrupts are cleared and no further checking and
+			 * handling of other interrupts is needed any more.
+			 */
+			return;
+		} else {
+			/*This else was made for misra-c compliance*/
+			;
+		}
+	}
+
+
+	if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK |
+			XCANPS_IXR_RXNEMP_MASK)) != (u32)0) &&
+		(CanPtr->RecvHandler != NULL)) {
+
+		/*
+		 * This case happens when
+		 * A number of frames depending on the Rx FIFO Watermark
+		 * threshold are received.
+		 * And  also when frame was received and is sitting in RX FIFO.
+		 *
+		 * XCANPS_IXR_RXOK_MASK is not used because the bit is set
+		 * just once even if there are multiple frames sitting
+		 * in the RX FIFO.
+		 *
+		 * XCANPS_IXR_RXNEMP_MASK is used because the bit can be
+		 * set again and again automatically as long as there is
+		 * at least one frame in RX FIFO.
+		 */
+		CanPtr->RecvHandler(CanPtr->RecvRef);
+	}
+
+	/*
+	 * A frame was transmitted successfully.
+	 */
+	if (((PendingIntr & (XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK)) != (u32)0) &&
+		(CanPtr->SendHandler != NULL)) {
+		CanPtr->SendHandler(CanPtr->SendRef);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This routine installs an asynchronous callback function for the given
+* HandlerType:
+*
+* <pre>
+* HandlerType			Callback Function Type
+* -----------------------	------------------------
+* XCANPS_HANDLER_SEND		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_RECV		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_ERROR		XCanPs_ErrorHandler
+* XCANPS_HANDLER_EVENT		XCanPs_EventHandler
+*
+* HandlerType			Invoked by this driver when:
+* -------------------------------------------------------------------------
+* XCANPS_HANDLER_SEND		A frame transmitted by a call to
+*				XCanPs_Send() has been sent successfully.
+*
+* XCANPS_HANDLER_RECV		A frame(s) has been received and is sitting in
+*				the RX FIFO.
+*
+* XCANPS_HANDLER_ERROR		An error interrupt is occurring.
+*
+* XCANPS_HANDLER_EVENT		Any other kind of interrupt is occurring.
+* </pre>
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+* @param	HandlerType specifies which handler is to be attached.
+* @param	CallBackFunc is the address of the callback function.
+* @param	CallBackRef is a user data item that will be passed to the
+*		callback function when it is invoked.
+*
+* @return
+*		- XST_SUCCESS when handler is installed.
+*		- XST_INVALID_PARAM when HandlerType is invalid.
+*
+* @note
+* Invoking this function for a handler that already has been installed replaces
+* it with the new handler.
+*
+******************************************************************************/
+s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
+			void *CallBackFunc, void *CallBackRef)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+		case XCANPS_HANDLER_SEND:
+			InstancePtr->SendHandler =
+				(XCanPs_SendRecvHandler) CallBackFunc;
+			InstancePtr->SendRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
+
+		case XCANPS_HANDLER_RECV:
+			InstancePtr->RecvHandler =
+				(XCanPs_SendRecvHandler) CallBackFunc;
+			InstancePtr->RecvRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
+
+		case XCANPS_HANDLER_ERROR:
+			InstancePtr->ErrorHandler =
+				(XCanPs_ErrorHandler) CallBackFunc;
+			InstancePtr->ErrorRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
+
+		case XCANPS_HANDLER_EVENT:
+			InstancePtr->EventHandler =
+				(XCanPs_EventHandler) CallBackFunc;
+			InstancePtr->EventRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
+
+		default:
+			Status = XST_INVALID_PARAM;
+			break;
+	}
+	return Status;
+}
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c
new file mode 100644
index 000000000..48a6f4031
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c
@@ -0,0 +1,234 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_selftest.c
+* @addtogroup canps_v3_0
+* @{
+*
+* This file contains a diagnostic self-test function for the XCanPs driver.
+*
+* Read xcanps.h file for more information.
+*
+* @note
+* The  Baud Rate Prescaler Register (BRPR) and Bit Timing Register(BTR)
+* are setup such that CAN baud rate equals 40Kbps, given the CAN clock
+* equal to 24MHz. These need to be changed based on the desired baudrate
+* and CAN clock frequency.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*						 SDK claims a 40kbps baud rate but it's not.
+* 3.00  kvn    02/13/15 Modified code for MISRA_C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xcanps.h"
+
+/************************** Constant Definitions ****************************/
+
+#define XCANPS_MAX_FRAME_SIZE_IN_WORDS ((XCANPS_MAX_FRAME_SIZE) / (sizeof(u32)))
+
+#define FRAME_DATA_LENGTH	8U /* Frame Data field length */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/*
+ * Buffers to hold frames to send and receive. These are declared as global so
+ * that they are not on the stack.
+ */
+static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS];
+static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS];
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the CAN driver/device. The test resets
+* the device, sets up the Loop Back mode, sends a standard frame, receives the
+* frame, verifies the contents, and resets the device again.
+*
+* Note that this is a destructive test in that resets of the device are
+* performed. Refer the device specification for the device status after
+* the reset operation.
+*
+*
+* @param	InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed. i.e., the frame
+*		  received via the internal loop back has the same contents as
+*		  the frame sent.
+* 		- XST_FAILURE   Otherwise.
+*
+* @note
+*
+* If the CAN device does not work properly, this function may enter an
+* infinite loop and will never return to the caller.
+* <br><br>
+* If XST_FAILURE is returned, the device is not reset so that the caller could
+* have a chance to check reason(s) causing the failure.
+*
+******************************************************************************/
+s32 XCanPs_SelfTest(XCanPs *InstancePtr)
+{
+	u8 *FramePtr;
+	s32 Status;
+	u32 Index;
+	u8 GetModeResult;
+	u32 RxEmptyResult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XCanPs_Reset(InstancePtr);
+
+	/*
+	 * The device should enter Configuration Mode immediately after
+	 * reset above is finished. Now check the mode and return error code if
+	 * it is not Configuration Mode.
+	 */
+	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/*
+	 * Setup Baud Rate Prescaler Register (BRPR) and Bit Timing Register
+	 * (BTR) such that CAN baud rate equals 40Kbps, given the CAN clock
+	 * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B,
+	 * ISO 11898-1 specifications.
+	 */
+	(void)XCanPs_SetBaudRatePrescaler(InstancePtr, (u8)29U);
+	(void)XCanPs_SetBitTiming(InstancePtr, (u8)3U, (u8)2U, (u8)15U);
+
+	/*
+	 * Enter the loop back mode.
+	 */
+	XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK);
+	GetModeResult = XCanPs_GetMode(InstancePtr);
+	while (GetModeResult != ((u8)XCANPS_MODE_LOOPBACK)) {
+		GetModeResult = XCanPs_GetMode(InstancePtr);
+	}
+
+	/*
+	 * Create a frame to send with known values so we can verify them
+	 * on receive.
+	 */
+	TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U);
+	TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8U);
+
+	FramePtr = (u8 *)((void *)(&TxFrame[2]));
+	for (Index = 0U; Index < 8U; Index++) {
+		if(*FramePtr != 0U) {
+			*FramePtr = (u8)Index;
+			FramePtr++;
+		}
+	}
+
+	/*
+	 * Send the frame.
+	 */
+	Status = XCanPs_Send(InstancePtr, TxFrame);
+	if (Status != (s32)XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/*
+	 * Wait until the frame arrives RX FIFO via internal loop back.
+	 */
+	RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
+			XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
+
+	while (RxEmptyResult == (u32)0U) {
+		RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
+				XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
+	}
+
+	/*
+	 * Receive the frame.
+	 */
+	Status = XCanPs_Recv(InstancePtr, RxFrame);
+	if (Status != (s32)XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/*
+	 * Verify Identifier and Data Length Code.
+	 */
+	if (RxFrame[0] !=
+		(u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U)) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+
+	for (Index = 2U; Index < (XCANPS_MAX_FRAME_SIZE_IN_WORDS); Index++) {
+		if (RxFrame[Index] != TxFrame[Index]) {
+			Status = XST_FAILURE;
+			return Status;
+		}
+	}
+
+	/*
+	 * Reset device again before returning to the caller.
+	 */
+	XCanPs_Reset(InstancePtr);
+
+	Status = XST_SUCCESS;
+	return Status;
+}
+
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c
new file mode 100644
index 000000000..230c429b3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_sinit.c
+* @addtogroup canps_v3_0
+* @{
+*
+* This file contains the implementation of the XCanPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XCanPs_ConfigTable[] contains the configuration information for
+* each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId)
+{
+	XCanPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XCANPS_NUM_INSTANCES; Index++) {
+		if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XCanPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XCanPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile
deleted file mode 100644
index 007162d8c..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner coresightps_dcc_comp_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling coresightps_dcc"
-
-coresightps_dcc_comp_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: coresightps_dcc_includes
-
-coresightps_dcc_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c
deleted file mode 100644
index e999f6f5d..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.c
-* @addtogroup coresightps_dcc_v1_1
-* @{
-*
-* Functions in this file are the minimum required functions for the
-* XCoreSightPs driver.
-*
-* @note 	None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date		Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    02/14/15 First release
-* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
-*       kvn    08/18/15 Modified Makefile according to compiler changes.
-* 1.2   kvn    10/09/15 Add support for IAR Compiler.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include <xil_types.h>
-#include <xpseudo_asm.h>
-
-#ifdef __ICCARM__
-#define INLINE
-#else
-#define INLINE __inline
-#endif
-
-/* DCC Status Bits */
-#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
-#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
-
-static INLINE u32 XCoresightPs_DccGetStatus(void);
-
-/****************************************************************************/
-/**
-*
-* This functions sends a single byte using the DCC. It is blocking in that it
-* waits for the transmitter to become non-full before it writes the byte to
-* the transmit register.
-*
-* @param	BaseAddress is a dummy parameter to match the function proto
-*		of functions for other stdio devices.
-* @param	Data is the byte of data to send
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
-{
-	(void) BaseAddress;
-	while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
-	dsb();
-#ifdef __aarch64__
-	asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
-	asm volatile("mcr p14, 0, %0, c0, c5, 0"
-			: : "r" (Data));
-#else
-	{
-		volatile register u32 Reg __asm("cp14:0:c0:c5:0");
-		Reg = Data;
-	}
-#endif
-	isb();
-
-}
-
-/****************************************************************************/
-/**
-*
-* This functions receives a single byte using the DCC. It is blocking in that
-* it waits for the receiver to become non-empty before it reads from the
-* receive register.
-*
-* @param	BaseAddress is a dummy parameter to match the function proto
-*		of functions for other stdio devices.
-*
-* @return	The byte of data received.
-*
-* @note		None.
-*
-******************************************************************************/
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
-{
-	u8 Data;
-	(void) BaseAddress;
-
-	while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
-		dsb();
-
-#ifdef __aarch64__
-	asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
-	asm volatile("mrc p14, 0, %0, c0, c5, 0"
-			: "=r" (Data));
-#else
-	{
-		volatile register u32 Reg __asm("cp14:0:c0:c5:0");
-		Data = Reg;
-	}
-#endif
-	isb();
-
-	return Data;
-}
-
-
-/****************************************************************************/
-/**INLINE
-*
-* This functions read the status register of the DCC.
-*
-* @param	BaseAddress is the base address of the device
-*
-* @return	The contents of the Status Register.
-*
-* @note		None.
-*
-******************************************************************************/
-static INLINE u32 XCoresightPs_DccGetStatus(void)
-{
-	u32 Status;
-
-#ifdef __aarch64__
-	asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
-#elif defined (__GNUC__) || defined (__ICCARM__)
-	asm volatile("mrc p14, 0, %0, c0, c1, 0"
-			: "=r" (Status) : : "cc");
-#else
-	{
-		volatile register u32 Reg __asm("cp14:0:c0:c1:0");
-		Status = Reg;
-	}
-#endif
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h
deleted file mode 100644
index 6bab7ae09..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_1
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note 	None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date		Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    02/14/15 First release
-* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
-*       kvn    08/18/15 Modified Makefile according to compiler changes.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include <xil_types.h>
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile
new file mode 100644
index 000000000..007162d8c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner coresightps_dcc_comp_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling coresightps_dcc"
+
+coresightps_dcc_comp_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: coresightps_dcc_includes
+
+coresightps_dcc_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c
new file mode 100644
index 000000000..4bad57094
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c
@@ -0,0 +1,188 @@
+/******************************************************************************
+*
+* Copyright (C) 2015-2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.c
+* @addtogroup coresightps_dcc_v1_1
+* @{
+*
+* Functions in this file are the minimum required functions for the
+* XCoreSightPs driver.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.2   kvn    10/09/15 Add support for IAR Compiler.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
+
+#include <xil_types.h>
+#include <xpseudo_asm.h>
+
+#ifdef __ICCARM__
+#define INLINE
+#else
+#define INLINE __inline
+#endif
+
+/* DCC Status Bits */
+#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
+#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
+
+static INLINE u32 XCoresightPs_DccGetStatus(void);
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the DCC. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param	BaseAddress is a dummy parameter to match the function proto
+*		of functions for other stdio devices.
+* @param	Data is the byte of data to send
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
+{
+	(void) BaseAddress;
+	while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
+	dsb();
+#ifdef __aarch64__
+	asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+	asm volatile("mcr p14, 0, %0, c0, c5, 0"
+			: : "r" (Data));
+#else
+	{
+		volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+		Reg = Data;
+	}
+#endif
+	isb();
+
+}
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the DCC. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param	BaseAddress is a dummy parameter to match the function proto
+*		of functions for other stdio devices.
+*
+* @return	The byte of data received.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
+{
+	u8 Data;
+	(void) BaseAddress;
+
+	while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
+		dsb();
+
+#ifdef __aarch64__
+	asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+	asm volatile("mrc p14, 0, %0, c0, c5, 0"
+			: "=r" (Data));
+#else
+	{
+		volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+		Data = Reg;
+	}
+#endif
+	isb();
+
+	return Data;
+}
+
+
+/****************************************************************************/
+/**INLINE
+*
+* This functions read the status register of the DCC.
+*
+* @param	BaseAddress is the base address of the device
+*
+* @return	The contents of the Status Register.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE u32 XCoresightPs_DccGetStatus(void)
+{
+	u32 Status;
+
+#ifdef __aarch64__
+	asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+	asm volatile("mrc p14, 0, %0, c0, c1, 0"
+			: "=r" (Status) : : "cc");
+#else
+	{
+		volatile register u32 Reg __asm("cp14:0:c0:c1:0");
+		Status = Reg;
+	}
+#endif
+	return Status;
+#endif
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h
new file mode 100644
index 000000000..a732b235d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_1
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include <xil_types.h>
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile
deleted file mode 100644
index 778797bcf..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner csudma_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling csudma"
-
-csudma_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: csudma_includes
-
-csudma_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c
deleted file mode 100644
index 2f6a62e50..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c
+++ /dev/null
@@ -1,767 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcsudma.c
-* @addtogroup csudma_v1_0
-* @{
-*
-* This file contains the implementation of the interface functions for CSU_DMA
-* driver. Refer to the header file xcsudma.h for more detailed information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- ---------------------------------------------------
-* 1.0   vnsld   22/10/14 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcsudma.h"
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Function Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function initializes an CSU_DMA core. This function must be called
-* prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting
-* up the instance data and ensuring the hardware is in a quiescent state.
-*
-* @param	InstancePtr is a pointer to the XCsuDma instance.
-* @param	CfgPtr is a reference to a structure containing information
-*		about a specific XCsuDma instance.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the
-*		address mapping from EffectiveAddr to the device physical
-*		base address unchanged once this function is invoked.
-*		Unexpected errors may occur if the address mapping changes
-*		after this function is called. If address translation is not
-*		used, pass in the physical address instead.
-*
-* @return
-*		- XST_SUCCESS if initialization was successful.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
-			u32 EffectiveAddr)
-{
-
-	/* Verify arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(CfgPtr != NULL);
-	Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0));
-
-	/* Setup the instance */
-	(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
-						sizeof(XCsuDma_Config));
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-
-	XCsuDma_Reset();
-
-	InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
-
-	return (XST_SUCCESS);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the starting address and amount(size) of the data to be
-* transfered from/to the memory through the AXI interface.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	Addr is a 64 bit variable which holds the starting address of
-* 		data which needs to write into the memory(DST) (or read	from
-* 		the memory(SRC)).
-* @param	Size is a 32 bit variable which represents the number of 4 byte
-* 		words needs to be transfered from starting address.
-* @param	EnDataLast is to trigger an end of message. It will enable or
-* 		disable data_inp_last signal to stream interface when current
-* 		command is completed. It is applicable only to source channel
-* 		and neglected for destination channel.
-* 		-	1 - Asserts data_inp_last signal.
-* 		-	0 - data_inp_last will not be asserted.
-*
-* @return	None.
-*
-* @note		Data_inp_last signal is asserted simultaneously with the
-* 		data_inp_valid signal associated with the final 32-bit word
-*		transfer.
-*
-******************************************************************************/
-void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-					UINTPTR Addr, u32 Size, u8 EnDataLast)
-{
-	/* Verify arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00);
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-					(Channel == (XCSUDMA_DST_CHANNEL)));
-	Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX));
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
-
-	/* Flushing cache memory */
-	if (Channel == (XCSUDMA_SRC_CHANNEL)) {
-		Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
-	}
-	/* Invalidating cache memory */
-	else {
-		Xil_DCacheInvalidateRange(Addr, Size <<
-					(u32)(XCSUDMA_SIZE_SHIFT));
-	}
-
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_ADDR_OFFSET) +
-		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-				((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK)));
-
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-		(((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) &
-					(u32)(XCSUDMA_MSB_ADDR_MASK)));
-
-	if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_SIZE_OFFSET) +
-				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-			((Size << (u32)(XCSUDMA_SIZE_SHIFT)) |
-					(u32)(XCSUDMA_LAST_WORD_MASK)));
-	}
-	else {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_SIZE_OFFSET) +
-				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-				(Size << (u32)(XCSUDMA_SIZE_SHIFT)));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current address location of the memory, from where
-* it has to read the data(SRC) or the location where it has to write the data
-* (DST) based on the channel selection.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	Address is a 64 bit variable which holds the current address.
-*		- From this location data has to be read(SRC)
-*		- At this location data has to be written(DST)
-*
-* @note		None.
-*
-******************************************************************************/
-u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
-{
-	u64 FullAddr;
-
-	/* Verify arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-					(Channel == (XCSUDMA_DST_CHANNEL)));
-
-	FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-				((u32)(XCSUDMA_ADDR_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
-
-	FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) <<
-				(u64)(XCSUDMA_MSB_ADDR_SHIFT));
-
-	return FullAddr;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the size of the data yet to be transfered from memory
-* to CSU_DMA or CSU_DMA to memory based on the channel selection.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	Size is amount of data yet to be transfered.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
-{
-	u32 Size;
-
-	/* Verify arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-					(Channel == (XCSUDMA_DST_CHANNEL)));
-
-	Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_SIZE_OFFSET) +
-		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >>
-					(u32)(XCSUDMA_SIZE_SHIFT);
-
-	return Size;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function pause the Channel data tranfer to/from memory or to/from stream
-* based on pause type.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	Type is type of the pause to be enabled.
-*		- XCSUDMA_PAUSE_MEMORY(0) - Pause memory
-*			- SRC Stops issuing of new read commands to memory.
-*			- DST Stops issuing of new write commands to memory.
-*		- XCSUDMA_PAUSE_STREAM(1) - Pause stream
-*			- SRC Stops transfer of data from FIFO to Stream.
-*			- DST Stops transfer of data from stream to FIFO.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-						XCsuDma_PauseType Type)
-{
-	/* Verify arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
-				(Type == (XCSUDMA_PAUSE_STREAM)));
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-					(Channel == (XCSUDMA_DST_CHANNEL)));
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
-
-	/* Pause Memory Read/Write/Stream operations */
-	if (Type == (XCSUDMA_PAUSE_MEMORY)) {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_CTRL_OFFSET) +
-				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-			(XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-				((u32)(XCSUDMA_CTRL_OFFSET) +
-				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) |
-					(u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)));
-	}
-	if (Type == (XCSUDMA_PAUSE_STREAM)) {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_CTRL_OFFSET) +
-				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-			(XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-				((u32)(XCSUDMA_CTRL_OFFSET) +
-				(Channel * (u32)XCSUDMA_OFFSET_DIFF))) |
-				(u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This functions checks whether Channel's memory or stream is paused or not
-* based on the given pause type.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	Type is type of the pause which needs to be checked.
-*		- XCSUDMA_PAUSE_MEMORY(0) - Pause memory
-*			- SRC Stops issuing of new read commands to memory.
-*			- DST Stops issuing of new write commands to memory.
-*		- XCSUDMA_PAUSE_STREAM(1) - Pause stream
-*			- SRC Stops transfer of data from FIFO to Stream.
-*			- DST Stops transfer of data from stream to FIFO.
-*
-* @return	Returns the pause status.
-*		- TRUE if it is in paused state.
-*		- FALSE if it is not in pause state.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-		XCsuDma_PauseType Type)
-{
-
-	u32 Data;
-	s32 PauseState;
-
-	/* Verify arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-					(Channel == (XCSUDMA_DST_CHANNEL)));
-	Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
-					(Type == (XCSUDMA_PAUSE_STREAM)));
-
-	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_CTRL_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
-
-	/* To know Pause condition of Memory Read/Write/Stream operations */
-	if (Type == (XCSUDMA_PAUSE_MEMORY)) {
-		if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) ==
-								(u32)0x00) {
-			PauseState = (s32)(FALSE);
-		}
-		else {
-			PauseState = (s32)(TRUE);
-		}
-	}
-	else {
-		if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) ==
-								(u32)0x00) {
-				PauseState = (s32)(FALSE);
-		}
-		else {
-			PauseState = (s32)(TRUE);
-		}
-	}
-
-	return (s32)PauseState;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function resumes the channel if it is in paused state and continues
-* where it has left or no effect if it is not in paused state, based on the
-* type of pause.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	Type is type of the pause to be Resume if it is in pause
-*		state.
-*		- XCSUDMA_PAUSE_MEMORY(0) - Pause memory
-*			- SRC Stops issuing of new read commands to memory.
-*			- DST Stops issuing of new write commands to memory.
-*		- XCSUDMA_PAUSE_STREAM(1) - Pause stream
-*			- SRC Stops transfer of data from FIFO to Stream.
-*			- DST Stops transfer of data from stream to FIFO.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-		XCsuDma_PauseType Type)
-{
-	u32 Data;
-	/* Verify arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
-			(Type == (XCSUDMA_PAUSE_STREAM)));
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-					(Channel == (XCSUDMA_DST_CHANNEL)));
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
-
-	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_CTRL_OFFSET) +
-		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
-
-	if (Type == (XCSUDMA_PAUSE_MEMORY)) {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_CTRL_OFFSET) +
-		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-		(Data &
-				(~(XCSUDMA_CTRL_PAUSE_MEM_MASK))));
-	}
-	if (Type == (XCSUDMA_PAUSE_STREAM)) {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_CTRL_OFFSET) +
-		(((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))),
-			( Data &
-			(~(XCSUDMA_CTRL_PAUSE_STRM_MASK))));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the sum of all the data read from AXI memory. It is
-* valid only one we use CSU_DMA source channel.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-*
-* @return	Returns the sum of all the data read from memory.
-*
-* @note		Before start of the transfer need to clear this register to get
-*		correct sum otherwise it adds to previous value which results
-*		to wrong output.
-*		Valid only for source channel
-*
-******************************************************************************/
-u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr)
-{
-	u32 ChkSum;
-
-	/* Verify arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady ==
-				(u32)(XIL_COMPONENT_IS_READY));
-
-	ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-						(u32)(XCSUDMA_CRC_OFFSET));
-
-	return ChkSum;
-
-}
-/*****************************************************************************/
-/**
-*
-* This function clears the check sum of the data read from AXI memory. It is
-* valid only for CSU_DMA source channel.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-*
-* @return	Returns the sum of all the data read from memory.
-*
-* @note		Before start of the transfer need to clear this register to get
-*		correct sum otherwise it adds to previous value which results
-*		to wrong output.
-*
-******************************************************************************/
-void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr)
-{
-
-	/* Verify arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		(u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK));
-}
-
-/*****************************************************************************/
-/**
-* This function cofigures all the values of CSU_DMA's Channels with the values
-* of updated XCsuDma_Configure structure.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	ConfigurValues is a pointer to the structure XCsuDma_Configure
-*		whose values are used to configure CSU_DMA core.
-*		- SssFifoThesh   When the DST FIFO level >= this value,
-*		  the SSS interface signal, "data_out_fifo_level_hit" will be
-*		  asserted. This mechanism can be used by the SSS to flow
-*		  control data that is being looped back from the SRC DMA.
-*			- Range is (0x10 to 0x7A) threshold is 17 to 123
-*			entries.
-*			- It is valid only for DST CSU_DMA IP.
-*		- ApbErr          When accessed to invalid APB the resulting
-*		  pslerr will be
-*			- 0 - 1'b0
-*			- 1 - 1'b1
-*		- EndianType      Type of endianness
-*			- 0 doesn't change order
-*			- 1 will flip the order.
-*		- AxiBurstType....Type of the burst
-*			- 0 will issue INCR type burst
-*			- 1 will issue FIXED type burst
-*		- TimeoutValue    Time out value for timers
-*			- 0x000 to 0xFFE are valid inputs
-*			- 0xFFF clears both timers
-*		- FifoThresh......Programmed watermark value
-*			- Range is 0x00 to 0x80 (0 to 128 entries).
-*		- Acache         Sets the AXI CACHE bits on the AXI Write/Read
-*		channel.
-*			- Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
-*			  for DST channel are always 1, we need to configure
-*			  remaining 3 signal support
-*			  (Bufferable, Read allocate and Write allocate).
-*			Valid inputs are:
-*			- 0x000 - Cacheable, but do not allocate
-*			- 0x001 - Cacheable and bufferable, but do not allocate
-*			- 0x010 - Cacheable write-through, allocate on reads
-*				  only
-*			- 0x011 - Cacheable write-back, allocate on reads only
-*			- 0x100 - Cacheable write-through, allocate on writes
-*				  only
-*			- 0x101 - Cacheable write-back, allocate on writes only
-*			- 0x110 - Cacheable write-through, allocate on both
-*				  reads and writes
-*			- 0x111 - Cacheable write-back, allocate on both reads
-*				  and writes
-*		- RouteBit        To select route
-*			- 0 : Command will be routed normally
-*			- 1 : Command will be routed to APU's cache controller
-*		- TimeoutEn       To enable or disable time out counters
-*			- 0 : The 2 Timeout counters are disabled
-*			- 1 : The 2 Timeout counters are enabled
-*		- TimeoutPre      Set the prescaler value for the timeout in
-*		clk (~2.5ns) cycles
-*			- Range is 0x000(Prescaler enables timer every cycles)
-*			  to 0xFFF(Prescaler enables timer every 4096 cycles)
-*		- MaxOutCmds      Controls the maximumum number of outstanding
-*		AXI read commands issued.
-*			- Range is 0x0(Up to 1 Outstanding Read command
-*			  allowed) to 0x8 (Up to 9 Outstanding Read
-*			  command allowed)
-*
-* @return	None.
-*
-* @note		To use timers timeout value Timeout enable field should be
-*		enabled.
-*
-******************************************************************************/
-void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-					XCsuDma_Configure *ConfigurValues)
-{
-	u32 Data;
-
-	/* Verify arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
-	Xil_AssertVoid(ConfigurValues != NULL);
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-				(Channel == (XCSUDMA_DST_CHANNEL)));
-	Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE));
-
-	Data = (((ConfigurValues->EndianType <<
-			(u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
-			(u32)(XCSUDMA_CTRL_ENDIAN_MASK)) |
-		((ConfigurValues->ApbErr <<
-			(u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) &
-			(u32)(XCSUDMA_CTRL_APB_ERR_MASK)) |
-		((ConfigurValues->AxiBurstType <<
-			(u32)(XCSUDMA_CTRL_BURST_SHIFT)) &
-			(u32)(XCSUDMA_CTRL_BURST_MASK)) |
-		((ConfigurValues->TimeoutValue <<
-			(u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) &
-			(u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) |
-		((ConfigurValues->FifoThresh <<
-			(u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) &
-			(u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)));
-	if(Channel == XCSUDMA_DST_CHANNEL) {
-		Data = Data | (u32)((ConfigurValues->SssFifoThesh <<
-				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) &
-				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK));
-	}
-
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_CTRL_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
-
-	Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_CTRL2_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) &
-				(u32)(XCSUDMA_CTRL2_RESERVED_MASK));
-	Data |= (((ConfigurValues->Acache <<
-			(u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) &
-			(u32)(XCSUDMA_CTRL2_ACACHE_MASK)) |
-		((ConfigurValues->RouteBit <<
-			(u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) &
-			(u32)(XCSUDMA_CTRL2_ROUTE_MASK)) |
-		((ConfigurValues->TimeoutEn <<
-			(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) &
-			(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) |
-		((ConfigurValues->TimeoutPre <<
-			(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) &
-			(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) |
-		((ConfigurValues->MaxOutCmds) &
-			(u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
-
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_CTRL2_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function updates XCsuDma_Configure structure members with the cofigured
-* values of CSU_DMA's Channel.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	ConfigurValues is a pointer to the structure XCsuDma_Configure
-*		whose members are updated with configurations of CSU_DMA core.
-*		- SssFifoThesh   When the DST FIFO level >= this value,
-*		  the SSS interface signal, "data_out_fifo_level_hit" will be
-*		  asserted. This mechanism can be used by the SSS to flow
-*		  control data that is being looped back from the SRC DMA.
-*			- Range is (0x10 to 0x7A) threshold is 17 to 123
-*			entries.
-*			- It is valid only for DST CSU_DMA IP.
-*		- ApbErr          When accessed to invalid APB the resulting
-*		  pslerr will be
-*			- 0 - 1'b0
-*			- 1 - 1'b1
-*		- EndianType      Type of endianness
-*			- 0 doesn't change order
-*			- 1 will flip the order.
-*		- AxiBurstType....Type of the burst
-*			- 0 will issue INCR type burst
-*			- 1 will issue FIXED type burst
-*		- TimeoutValue    Time out value for timers
-*			- 0x000 to 0xFFE are valid inputs
-*			- 0xFFF clears both timers
-*		- FifoThresh......Programmed watermark value
-*			- Range is 0x00 to 0x80 (0 to 128 entries).
-*		- Acache         Sets the AXI CACHE bits on the AXI Write/Read
-*		channel.
-*			- Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
-*			  for DST channel are always 1, we need to configure
-*			  remaining 3 signal support
-*			  (Bufferable, Read allocate and Write allocate).
-*			Valid inputs are:
-*			- 0x000 - Cacheable, but do not allocate
-*			- 0x001 - Cacheable and bufferable, but do not allocate
-*			- 0x010 - Cacheable write-through, allocate on reads
-*				  only
-*			- 0x011 - Cacheable write-back, allocate on reads only
-*			- 0x100 - Cacheable write-through, allocate on writes
-*				  only
-*			- 0x101 - Cacheable write-back, allocate on writes only
-*			- 0x110 - Cacheable write-through, allocate on both
-*				  reads and writes
-*			- 0x111 - Cacheable write-back, allocate on both reads
-*				  and writes
-*		- RouteBit        To select route
-*			- 0 : Command will be routed based normally
-*			- 1 : Command will be routed to APU's cache controller
-*		- TimeoutEn       To enable or disable time out counters
-*			- 0 : The 2 Timeout counters are disabled
-*			- 1 : The 2 Timeout counters are enabled
-*		- TimeoutPre      Set the prescaler value for the timeout in
-*		clk (~2.5ns) cycles
-*			- Range is 0x000(Prescaler enables timer every cycles)
-*			 to 0xFFF(Prescaler enables timer every 4096 cycles)
-*		- MaxOutCmds      Controls the maximumum number of outstanding
-*		AXI read commands issued.
-*			- Range is 0x0(Up to 1 Outstanding Read command
-*			allowed) to 0x8 (Up to 9 Outstanding Read command
-*			allowed)
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-				XCsuDma_Configure *ConfigurValues)
-{
-	u32 Data;
-
-	/* Verify arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(ConfigurValues != NULL);
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-				(Channel == (XCSUDMA_DST_CHANNEL)));
-
-	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_CTRL_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
-
-	if (Channel == (XCSUDMA_DST_CHANNEL)) {
-		ConfigurValues->SssFifoThesh =
-			(u8)((Data &
-				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >>
-				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT));
-	}
-	ConfigurValues->ApbErr =
-		(u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >>
-				(u32)(XCSUDMA_CTRL_APB_ERR_SHIFT));
-	ConfigurValues->EndianType =
-		(u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >>
-				(u32)(XCSUDMA_CTRL_ENDIAN_SHIFT));
-	ConfigurValues->AxiBurstType =
-		(u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >>
-				(u32)(XCSUDMA_CTRL_BURST_SHIFT));
-	ConfigurValues->TimeoutValue =
-		((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >>
-				(u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT));
-	ConfigurValues->FifoThresh =
-		(u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >>
-				(u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT));
-
-	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_CTRL2_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
-
-	ConfigurValues->Acache =
-			(u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >>
-					(u32)(XCSUDMA_CTRL2_ACACHE_SHIFT));
-	ConfigurValues->RouteBit =
-			(u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >>
-					(u32)(XCSUDMA_CTRL2_ROUTE_SHIFT));
-	ConfigurValues->TimeoutEn =
-			(u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >>
-				(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT));
-	ConfigurValues->TimeoutPre =
-			(u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >>
-				(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT));
-	ConfigurValues->MaxOutCmds =
-			(u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
-
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h
deleted file mode 100644
index fe63530a5..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* The CSU_DMA is present inside CSU (Configuration Security Unit) module which
-* is located within the Low-Power Subsystem (LPS) internal to the PS.
-* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit
-* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure
-* Stream Switch (SSS).
-*
-* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC
-* (read) channel and DST (write) channel. The DMA is effectively able to
-* transfer data:
-*	- From PS-side to the SSS-side (SRC DMA only)
-*	- From SSS-side to the PS-side (DST DMA only)
-*	- Simultaneous PS-side to SSS_side and SSS-side to the PS-side
-*
-* <b>Initialization & Configuration</b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the CSU_DMA core.
-*
-* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core.
-* The user needs to first call the XCsuDma_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to the
-* XCsuDma_CfgInitialize() API.
-*
-* <b> Interrupts </b>
-* This driver will not support handling of interrupts user should write handler
-* to handle the interrupts.
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XCsuDma driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* @file xcsudma.h
-* @addtogroup csudma_v1_0
-* @{
-* @details
-*
-* This header file contains identifiers and register-level driver functions (or
-* macros), range macros, structure typedefs that can be used to access the
-* Xilinx CSU_DMA core instance.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- -----------------------------------------------------
-* 1.0   vnsld   22/10/14 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XCSUDMA_H_
-#define XCSUDMA_H_	/**< Prevent circular inclusions
-			  *  by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xcsudma_hw.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xil_cache.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name CSU_DMA Channels
- * @{
- */
-typedef enum {
-	XCSUDMA_SRC_CHANNEL = 0U,	/**< Source Channel of CSU_DMA */
-	XCSUDMA_DST_CHANNEL		/**< Destination Channel of CSU_DMA */
-}XCsuDma_Channel;
-/*@}*/
-
-/** @name CSU_DMA pause types
- * @{
- */
-typedef enum {
-	XCSUDMA_PAUSE_MEMORY,		/**< Pauses memory data transfer
-					  *  to/from CSU_DMA */
-	XCSUDMA_PAUSE_STREAM,		/**< Pauses stream data transfer
-					  *  to/from CSU_DMA */
-}XCsuDma_PauseType;
-
-/*@}*/
-
-
-/** @name Ranges of Size
- * @{
- */
-#define XCSUDMA_SIZE_MAX 0x07FFFFFF	/**< Maximum allowed no of words */
-
-/*@}*/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-*
-* This function resets the CSU_DMA core.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*		C-style signature:
-*		void XCsuDma_Reset()
-*
-******************************************************************************/
-#define XCsuDma_Reset()  \
-	Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
-				(u32)(XCSUDMA_RESET_SET_MASK)); \
-	Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
-					(u32)(XCSUDMA_RESET_UNSET_MASK));
-
-/*****************************************************************************/
-/**
-* This function will be in busy while loop until the data transfer is
-* completed.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-*		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	None.
-*
-* @note		This function should be called after XCsuDma_Transfer in polled
-*		mode  to wait until the data gets transfered completely.
-*		C-style signature:
-*		void XCsuDma_WaitForDone(XCsuDma *InstancePtr,
-*						XCsuDma_Channel Channel)
-*
-******************************************************************************/
-#define XCsuDma_WaitForDone(InstancePtr,Channel) \
-		while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
-			((u32)(XCSUDMA_I_STS_OFFSET) + \
-			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
-		(u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function returns the number of completed SRC/DST DMA transfers that
-* have not been acknowledged by software based on the channel selection.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	Count is number of completed DMA transfers but not acknowledged
-*		(Range is 0 to 7).
-*		- 000 - All finished transfers have been acknowledged.
-*		- Count - Count number of finished transfers are still
-*		outstanding.
-*
-* @note		None.
-*		C-style signature:
-*		u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr,
-*						XCsuDma_Channel Channel)
-*
-******************************************************************************/
-#define XCsuDma_GetDoneCount(InstancePtr, Channel)  \
-		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
-			((u32)(XCSUDMA_STS_OFFSET) + \
-			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
-			(u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \
-				(u32)(XCSUDMA_STS_DONE_CNT_SHIFT))
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current SRC/DST FIFO level in 32 bit words of the
-* selected channel
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	FIFO level. (Range is 0 to 128)
-*		- 0 Indicates empty
-*		- Any number 1 to 128 indicates the number of entries in FIFO.
-*
-* @note		None.
-*		C-style signature:
-*		u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr,
-*					XCsuDma_Channel Channel)
-*
-******************************************************************************/
-#define XCsuDma_GetFIFOLevel(InstancePtr, Channel)  \
-		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
-			((u32)(XCSUDMA_STS_OFFSET) + \
-			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
-			(u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \
-					(u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT))
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current number of read(src)/write(dst) outstanding
-* commands based on the type of channel selected.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	Count of outstanding commands. (Range is 0 to 9).
-*
-* @note		None.
-*		C-style signature:
-*		u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr,
-*						XCsuDma_Channel Channel)
-*
-******************************************************************************/
-#define XCsuDma_GetWROutstandCount(InstancePtr, Channel)  \
-		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
-				((u32)(XCSUDMA_STS_OFFSET) + \
-			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
-			(u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \
-				(u32)(XCUSDMA_STS_OUTSTDG_SHIFT))
-
-/*****************************************************************************/
-/**
-*
-* This function returns the status of Channel either it is busy or not.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-* 		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	Returns the current status of the core.
-*		- TRUE represents core is currently busy.
-*		- FALSE represents core is not involved in any transfers.
-*
-* @note		None.
-*		C-style signature:
-*		s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
-*
-******************************************************************************/
-
-#define XCsuDma_IsBusy(InstancePtr, Channel) \
-		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
-					((u32)(XCSUDMA_STS_OFFSET) + \
-			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
-		(u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \
-				(TRUE) : (FALSE)
-
-
-/**************************** Type Definitions *******************************/
-
-/**
-* This typedef contains configuration information for a CSU_DMA core.
-* Each CSU_DMA core should have a configuration structure associated.
-*/
-typedef struct {
-	u16 DeviceId;		/**< DeviceId is the unique ID of the
-				  *  device */
-	u32 BaseAddress;	/**< BaseAddress is the physical base address
-				  *  of the device's registers */
-} XCsuDma_Config;
-
-
-/******************************************************************************/
-/**
-*
-* The XCsuDma driver instance data structure. A pointer to an instance data
-* structure is passed around by functions to refer to a specific driver
-* instance.
-*/
-typedef struct {
-	XCsuDma_Config Config;		/**< Hardware configuration */
-	u32 IsReady;			/**< Device and the driver instance
-					  *  are initialized */
-}XCsuDma;
-
-
-/******************************************************************************/
-/**
-* This typedef contains all the configuration feilds which needs to be set
-* before the start of the data transfer. All these feilds of CSU_DMA can be
-* configured by using XCsuDma_SetConfig API.
-*/
-typedef struct {
-	u8 SssFifoThesh;	/**< SSS FIFO threshold value */
-	u8 ApbErr;		/**< ABP invalid access error */
-	u8 EndianType;		/**< Type of endianess */
-	u8 AxiBurstType;	/**< Type of AXI bus */
-	u32 TimeoutValue;	/**< Time out value */
-	u8 FifoThresh;		/**< FIFO threshold value */
-	u8 Acache;		/**< AXI CACHE selection */
-	u8 RouteBit;		/**< Selection of Route */
-	u8 TimeoutEn;		/**< Enable of time out counters */
-	u16 TimeoutPre;		/**< Pre scaler value */
-	u8 MaxOutCmds;		/**< Maximum number of outstanding
-				  *  commands */
-}XCsuDma_Configure;
-
-/*****************************************************************************/
-
-
-/************************** Function Prototypes ******************************/
-
-XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId);
-
-s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
-			u32 EffectiveAddr);
-void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-					UINTPTR Addr, u32 Size, u8 EnDataLast);
-void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr,
-						u32 Size);
-u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
-u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
-
-void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-						XCsuDma_PauseType Type);
-s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-						XCsuDma_PauseType Type);
-void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-						XCsuDma_PauseType Type);
-
-u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr);
-void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr);
-
-void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-					XCsuDma_Configure *ConfigurValues);
-void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-					XCsuDma_Configure *ConfigurValues);
-void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
-
-void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value);
-u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr);
-
-/* Interrupt related APIs */
-u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
-void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-								u32 Mask);
-void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-								u32 Mask);
-void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-								u32 Mask);
-u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
-
-s32 XCsuDma_SelfTest(XCsuDma *InstancePtr);
-
-/******************************************************************************/
-
-#ifdef __cplusplus
-}
-
-#endif
-
-#endif /* End of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c
deleted file mode 100644
index b3fb65f5b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xcsudma.h"
-
-/*
-* The configuration table for devices
-*/
-
-XCsuDma_Config XCsuDma_ConfigTable[] =
-{
-	{
-		XPAR_PSU_CSUDMA_DEVICE_ID,
-		XPAR_PSU_CSUDMA_BASEADDR
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h
deleted file mode 100644
index 6b2c2cdb8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h
+++ /dev/null
@@ -1,311 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcsudma_hw.h
-* @addtogroup csudma_v1_0
-* @{
-*
-* This header file contains identifiers and register-level driver functions (or
-* macros) that can be used to access the Xilinx CSU_DMA core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- ------------------------------------------------------
-* 1.0   vnsld  22/10/14 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XCSUDMA_HW_H_
-#define XCSUDMA_HW_H_	/**< Prevent circular inclusions
-			  *  by using protection macros	*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers offsets
- * @{
- */
-#define XCSUDMA_ADDR_OFFSET	0x000	/**< Address Register Offset */
-#define XCSUDMA_SIZE_OFFSET	0x004	/**< Size Register Offset */
-#define XCSUDMA_STS_OFFSET	0x008	/**< Status Register Offset */
-#define XCSUDMA_CTRL_OFFSET	0x00C	/**< Control Register Offset */
-#define XCSUDMA_CRC_OFFSET	0x010	/**< CheckSum Register Offset */
-#define XCSUDMA_I_STS_OFFSET	0x014	/**< Interrupt Status Register
-					  *  Offset */
-#define XCSUDMA_I_EN_OFFSET	0x018	/**< Interrupt Enable Register
-					  *  Offset */
-#define XCSUDMA_I_DIS_OFFSET	0x01C	/**< Interrupt Disable Register
-					  *  Offset */
-#define XCSUDMA_I_MASK_OFFSET	0x020	/**< Interrupt Mask Register Offset */
-#define XCSUDMA_CTRL2_OFFSET	0x024	/**< Interrupt Control Register 2
-					  *  Offset */
-#define XCSUDMA_ADDR_MSB_OFFSET	0x028	/**< Address's MSB Register Offset */
-#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8	/**< Safety Check Field Offset */
-#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC	/**< Future potential ECO Offset */
-/*@}*/
-
-/** @name CSU Base address and CSU_DMA reset offset
- * @{
- */
-#define XCSU_BASEADDRESS	0xFFCA0000
-						/**< CSU Base Address */
-#define XCSU_DMA_RESET_OFFSET	0x0000000CU	/**< CSU_DMA Reset offset */
-/*@}*/
-
-/** @name CSU_DMA Reset register bit masks
- * @{
- */
-#define XCSUDMA_RESET_SET_MASK		0x00000001U	/**< Reset set mask */
-#define XCSUDMA_RESET_UNSET_MASK	0x00000000U	/**< Reset unset mask*/
-/*@}*/
-
-/** @name Offset difference for Source and destination
- * @{
- */
-#define XCSUDMA_OFFSET_DIFF	0x00000800U	/**< Offset difference for
-						  *  source and
-						  *  destination channels */
-/*@}*/
-
-/** @name Address register bit masks
- * @{
- */
-#define XCSUDMA_ADDR_MASK	0xFFFFFFFCU	/**< Address mask */
-#define XCSUDMA_ADDR_LSB_MASK	0x00000003U	/**< Address alignment check
-						  *  mask */
-/*@}*/
-
-/** @name Size register bit masks and shifts
- * @{
- */
-#define XCSUDMA_SIZE_MASK	0x1FFFFFFCU	/**< Mask for size */
-#define XCSUDMA_LAST_WORD_MASK	0x00000001U	/**< Last word check bit mask*/
-#define XCSUDMA_SIZE_SHIFT	2U		/**< Shift for size */
-/*@}*/
-
-/** @name Status register bit masks and shifts
- * @{
- */
-#define XCSUDMA_STS_DONE_CNT_MASK	0x0000E000U	/**< Count done mask */
-#define XCSUDMA_STS_FIFO_LEVEL_MASK	0x00001FE0U	/**< FIFO level mask */
-#define XCUSDMA_STS_OUTSTDG_MASK	0x0000001EU	/**< No.of outstanding
-							  *  read/write
-							  *  commands mask */
-#define XCSUDMA_STS_BUSY_MASK		0x00000001U	/**< Busy mask */
-#define XCSUDMA_STS_DONE_CNT_SHIFT	13U		/**< Shift for Count
-							  *  done */
-#define XCSUDMA_STS_FIFO_LEVEL_SHIFT	5U		/**< Shift for FIFO
-							  *  level */
-#define XCUSDMA_STS_OUTSTDG_SHIFT	1U		/**< Shift for No.of
-							  *  outstanding
-							  *  read/write
-							  *  commands */
-/*@}*/
-
-/** @name Control register bit masks and shifts
- * @{
- */
-#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U	/**< SSS FIFO threshold
-							  *  value mask */
-#define XCSUDMA_CTRL_APB_ERR_MASK	0x01000000U	/**< APB register
-							  *  access error
-							  *  mask */
-#define XCSUDMA_CTRL_ENDIAN_MASK	0x00800000U	/**< Endianess mask */
-#define XCSUDMA_CTRL_BURST_MASK		0x00400000U	/**< AXI burst type
-							  *  mask */
-#define XCSUDMA_CTRL_TIMEOUT_MASK	0x003FFC00U	/**< Time out value
-							  *  mask */
-#define XCSUDMA_CTRL_FIFO_THRESH_MASK	0x000003FCU	/**< FIFO threshold
-							  *  mask */
-#define XCSUDMA_CTRL_PAUSE_MEM_MASK	0x00000001U	/**< Memory pause
-							  *  mask */
-#define XCSUDMA_CTRL_PAUSE_STRM_MASK	0x00000002U	/**< Stream pause
-							  *  mask */
-#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U		/**< SSS FIFO threshold
-							  *  shift */
-#define XCSUDMA_CTRL_APB_ERR_SHIFT	24U		/**< APB error shift */
-#define XCSUDMA_CTRL_ENDIAN_SHIFT	23U		/**< Endianess shift */
-#define XCSUDMA_CTRL_BURST_SHIFT	22U		/**< AXI burst type
-							  *  shift */
-#define XCSUDMA_CTRL_TIMEOUT_SHIFT	10U		/**< Time out value
-							  *  shift */
-#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT	2U		/**< FIFO thresh
-							  *  shift */
-/*@}*/
-
-/** @name CheckSum register bit masks
- * @{
- */
-#define XCSUDMA_CRC_RESET_MASK		0x00000000U	/**< Mask to reset
-							  *  value of
-							  *  check sum */
-/*@}*/
-
-/** @name Interrupt Enable/Disable/Mask/Status registers bit masks
- * @{
- */
-#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK	0x00000001U	/**< FIFO overflow
-							  *  mask, it is valid
-							  *  only to Destination
-							  *  Channel */
-#define XCSUDMA_IXR_INVALID_APB_MASK	0x00000040U	/**< Invalid APB access
-							  *  mask */
-#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK	0x00000020U	/**< FIFO threshold hit
-							  *  indicator mask */
-#define XCSUDMA_IXR_TIMEOUT_MEM_MASK	0x00000010U	/**< Time out counter
-							  *  expired to access
-							  *  memory mask */
-#define XCSUDMA_IXR_TIMEOUT_STRM_MASK	0x00000008U	/**< Time out counter
-							  *  expired to access
-							  *  stream mask */
-#define XCSUDMA_IXR_AXI_WRERR_MASK	0x00000004U	/**< AXI Read/Write
-							  *  error mask */
-#define XCSUDMA_IXR_DONE_MASK		0x00000002U	/**< Done mask */
-#define XCSUDMA_IXR_MEM_DONE_MASK	0x00000001U	/**< Memory done
-							  *  mask, it is valid
-							  *  only for source
-							  *  channel*/
-#define XCSUDMA_IXR_SRC_MASK		0x0000007FU
-					/**< ((XCSUDMA_IXR_INVALID_APB_MASK)|
-					(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
-					(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
-					(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
-					(XCSUDMA_IXR_AXI_WRERR_MASK) |
-					(XCSUDMA_IXR_DONE_MASK) |
-					(XCSUDMA_IXR_MEM_DONE_MASK)) */
-					/**< All interrupt mask
-					  *  for source */
-#define XCSUDMA_IXR_DST_MASK		0x000000FEU
-					/**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
-					(XCSUDMA_IXR_INVALID_APB_MASK) |
-					(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
-					(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
-					(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
-					(XCSUDMA_IXR_AXI_WRERR_MASK) |
-					(XCSUDMA_IXR_DONE_MASK)) */
-					/**< All interrupt mask
-					  *  for destination */
-/*@}*/
-
-/** @name Control register 2 bit masks and shifts
- * @{
- */
-#define XCSUDMA_CTRL2_RESERVED_MASK	0x083F0000U	/**< Reserved bits
-							  *  mask */
-#define XCSUDMA_CTRL2_ACACHE_MASK	0X07000000U	/**< AXI CACHE mask */
-#define XCSUDMA_CTRL2_ROUTE_MASK	0x00800000U	/**< Route mask */
-#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK	0x00400000U	/**< Time out counters
-							  *  enable mask */
-#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK	0x0000FFF0U	/**< Time out pre
-							  *  mask */
-#define XCSUDMA_CTRL2_MAXCMDS_MASK	0x0000000FU	/**< Maximum commands
-							  *  mask */
-#define XCSUDMA_CTRL2_RESET_MASK	0x0000FFF8U	/**< Reset mask */
-#define XCSUDMA_CTRL2_ACACHE_SHIFT	24U		/**< Shift for
-							  *  AXI R/W CACHE */
-#define XCSUDMA_CTRL2_ROUTE_SHIFT	23U		/**< Shift for route */
-#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT	22U		/**< Shift for Timeout
-							  *  enable feild */
-#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT	4U		/**< Shift for Timeout
-							  *  pre feild */
-/*@}*/
-
-/** @name MSB Address register bit masks and shifts
- * @{
- */
-#define XCSUDMA_MSB_ADDR_MASK	0x0001FFFFU	/**< MSB bits of address
-						  *  mask */
-#define XCSUDMA_MSB_ADDR_SHIFT	32U		/**< Shift for MSB bits of
-						  *  address */
-/*@}*/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XCsuDma_In32		Xil_In32	/**< Input operation */
-#define XCsuDma_Out32		Xil_Out32	/**< Output operation */
-
-/*****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param	BaseAddress is the Xilinx base address of the CSU_DMA core.
-* @param	RegOffset is the register offset of the register.
-*
-* @return	The 32-bit value of the register.
-*
-* @note		C-style signature:
-*		u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-******************************************************************************/
-#define XCsuDma_ReadReg(BaseAddress, RegOffset) \
-		XCsuDma_In32((BaseAddress) + (u32)(RegOffset))
-
-/*****************************************************************************/
-/**
-*
-* This macro writes the value into the given register.
-*
-* @param	BaseAddress is the Xilinx base address of the CSU_DMA core.
-* @param	RegOffset is the register offset of the register.
-* @param	Data is the 32-bit value to write to the register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-******************************************************************************/
-#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \
-		XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-
-#ifdef __cplusplus
-}
-
-#endif
-
-
-#endif /* End of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c
deleted file mode 100644
index 9f37e4582..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcsudma_intr.c
-* @addtogroup csudma_v1_0
-* @{
-*
-* This file contains interrupt related functions of Xilinx CSU_DMA core.
-* Please see xcsudma.h for more details of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- ---------------------------------------------------
-* 1.0   vnsld  22/10/14  First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcsudma.h"
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Function Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This function returns interrupt status read from Interrupt Status Register.
-* Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to interpret the
-* returned value.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-*		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	The pending interrupts of the CSU_DMA. Use th following masks
-*		to interpret the returned value.
-*		XCSUDMA_IXR_SRC_MASK   - For Source channel
-*		XCSUDMA_IXR_DST_MASK   - For Destination channel
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
-{
-	u32 Data;
-
-	/* Verify arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-				(Channel == (XCSUDMA_DST_CHANNEL)));
-
-	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-				(u32)(XCSUDMA_I_STS_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)));
-
-	return Data;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function clears interrupt(s). Every bit set in Interrupt Status
-* Register indicates that a specific type of interrupt is occurring, and this
-* function clears one or more interrupts by writing a bit mask to Interrupt
-* Clear Register.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-*		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	Mask is the mask to clear. Bit positions of 1 will be cleared.
-*		Bit positions of 0 will not change the previous interrupt
-*		status. This mask is formed by OR'ing XCSUDMA_IXR_* bits
-*		defined in xcsudma_hw.h.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
-{
-
-
-	/* Verify arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-				(Channel == (XCSUDMA_DST_CHANNEL)));
-	if (Channel == (XCSUDMA_SRC_CHANNEL)) {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			(u32)(XCSUDMA_I_STS_OFFSET),
-				(Mask & (u32)(XCSUDMA_IXR_SRC_MASK)));
-	}
-	else {
-		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_I_STS_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
-				(Mask & (u32)(XCSUDMA_IXR_DST_MASK)));
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants
-* defined in xcsudma_hw.h to create the bit-mask to enable interrupts.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-*		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	Mask contains interrupts to be enabled.
-*		- Bit positions of 1 will be enabled.
-*		This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined
-*		in xcsudma_hw.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-							u32 Mask)
-{
-	u32 Data;
-
-	/* Verify arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-				(Channel == (XCSUDMA_DST_CHANNEL)));
-
-	if (Channel == (XCSUDMA_SRC_CHANNEL)) {
-		Data = Mask & (u32)(XCSUDMA_IXR_SRC_MASK);
-	}
-	else {
-		Data = Mask & (u32)(XCSUDMA_IXR_DST_MASK);
-	}
-	/*
-	 * Write the mask to the IER Register
-	 */
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_I_EN_OFFSET) +
-		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function disables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants
-* defined in xcsudma_hw.h to create the bit-mask to disable interrupts.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-*		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-* @param	Mask contains interrupts to be disabled.
-*		- Bit positions of 1 will be disabled.
-*		This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined
-*		in xcsudma_hw.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
-								u32 Mask)
-{
-	u32 Data;
-
-	/* Verify arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-			(Channel == (XCSUDMA_DST_CHANNEL)));
-
-	if (Channel == XCSUDMA_SRC_CHANNEL) {
-		Data = (Mask) & (u32)(XCSUDMA_IXR_SRC_MASK);
-	}
-	else {
-		Data = (Mask) & (u32)(XCSUDMA_IXR_DST_MASK);
-	}
-
-	/*
-	 * Write the mask to the IDR Register
-	 */
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-		((u32)(XCSUDMA_I_DIS_OFFSET) +
-		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the interrupt mask to know which interrupts are
-* enabled and which of them were disaled.
-*
-* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
-* @param	Channel represents the type of channel either it is Source or
-*		Destination.
-*		Source channel      - XCSUDMA_SRC_CHANNEL
-*		Destination Channel - XCSUDMA_DST_CHANNEL
-*
-* @return	The current interrupt mask. The mask indicates which interrupts
-*		are enabled/disabled.
-*		0 bit represents .....corresponding interrupt is enabled.
-*		1 bit represents .....Corresponding interrupt is disabled.
-*		To interpret returned mask use
-*		XCSUDMA_IXR_SRC_MASK........For source channel
-*		XCSUDMA_IXR_DST_MASK........For destination channel
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
-{
-
-	/* Verify arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
-					(Channel == (XCSUDMA_DST_CHANNEL)));
-
-	/*
-	 * Read the Interrupt Mask register
-	 */
-	return (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-			((u32)(XCSUDMA_I_MASK_OFFSET) +
-			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))));
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c
deleted file mode 100644
index f61910fd4..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcsudma_selftest.c
-* @addtogroup csudma_v1_0
-* @{
-*
-* This file contains a diagnostic self-test function for the CSU_DMA driver.
-* Refer to the header file xcsudma.h for more detailed information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- ---------------------------------------------------
-* 1.0   vnsld   22/10/14 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcsudma.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/************************** Function Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. Performs
-* reset of both source and destination channels and checks if reset is working
-* properly or not.
-*
-* @param	InstancePtr is a pointer to the XCsuDma instance.
-*
-* @return
-*		- XST_SUCCESS if the self-test passed.
-* 		- XST_FAILURE otherwise.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XCsuDma_SelfTest(XCsuDma *InstancePtr)
-{
-	u32 Data;
-	s32 Status;
-
-	/* Verify arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-
-	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-					(u32)(XCSUDMA_CTRL_OFFSET));
-
-	/* Changing Endianess of Source channel */
-
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-			(u32)(XCSUDMA_CTRL_OFFSET),
-			((Data) | (u32)(XCSUDMA_CTRL_ENDIAN_MASK)));
-
-	if ((XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
-		(u32)(XCSUDMA_CTRL_OFFSET)) &
-			(u32)(XCSUDMA_CTRL_ENDIAN_MASK)) ==
-				(XCSUDMA_CTRL_ENDIAN_MASK)) {
-		Status = (s32)(XST_SUCCESS);
-	}
-	else {
-		Status = (s32)(XST_FAILURE);
-	}
-
-	/* Changes made are being reverted back */
-	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
-				(u32)(XCSUDMA_CTRL_OFFSET), Data);
-
-	return Status;
-
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c
deleted file mode 100644
index 10e5c14f6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcsudma_sinit.c
-* @addtogroup csudma_v1_0
-* @{
-*
-* This file contains static initialization methods for Xilinx CSU_DMA core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- ---------------------------------------------------
-* 1.0   vnsld   22/10/14 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xcsudma.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure
-* based on the unique device id, <i>DeviceId</i>. The return value will refer
-* to an entry in the device configuration table defined in the xcsudma_g.c
-* file.
-*
-* @param	DeviceId is the unique device ID of the device for the lookup
-*		operation.
-*
-* @return	CfgPtr is a reference to a config record in the configuration
-*		table (in xcsudma_g.c) corresponding to <i>DeviceId</i>, or
-*		NULL if no match is found.
-*
-* @note		None.
-******************************************************************************/
-XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId)
-{
-	extern XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES];
-	XCsuDma_Config *CfgPtr = NULL;
-	u32 Index;
-
-	/* Checks all the instances */
-	for (Index = (u32)0x0; Index < (u32)(XPAR_XCSUDMA_NUM_INSTANCES);
-								Index++) {
-		if (XCsuDma_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XCsuDma_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XCsuDma_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile
new file mode 100644
index 000000000..778797bcf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner csudma_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling csudma"
+
+csudma_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: csudma_includes
+
+csudma_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c
new file mode 100644
index 000000000..4ed4dd60b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c
@@ -0,0 +1,773 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xcsudma.c
+* @addtogroup csudma_v1_0
+* @{
+*
+* This file contains the implementation of the interface functions for CSU_DMA
+* driver. Refer to the header file xcsudma.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+* 1.1   adk     10/05/16 Fixed CR#951040 race condition in the recv path when
+*                        source and destination points to the same buffer.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcsudma.h"
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes an CSU_DMA core. This function must be called
+* prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting
+* up the instance data and ensuring the hardware is in a quiescent state.
+*
+* @param	InstancePtr is a pointer to the XCsuDma instance.
+* @param	CfgPtr is a reference to a structure containing information
+*		about a specific XCsuDma instance.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the
+*		address mapping from EffectiveAddr to the device physical
+*		base address unchanged once this function is invoked.
+*		Unexpected errors may occur if the address mapping changes
+*		after this function is called. If address translation is not
+*		used, pass in the physical address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
+			u32 EffectiveAddr)
+{
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0));
+
+	/* Setup the instance */
+	(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
+						sizeof(XCsuDma_Config));
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	XCsuDma_Reset();
+
+	InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
+
+	return (XST_SUCCESS);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the starting address and amount(size) of the data to be
+* transfered from/to the memory through the AXI interface.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	Addr is a 64 bit variable which holds the starting address of
+* 		data which needs to write into the memory(DST) (or read	from
+* 		the memory(SRC)).
+* @param	Size is a 32 bit variable which represents the number of 4 byte
+* 		words needs to be transfered from starting address.
+* @param	EnDataLast is to trigger an end of message. It will enable or
+* 		disable data_inp_last signal to stream interface when current
+* 		command is completed. It is applicable only to source channel
+* 		and neglected for destination channel.
+* 		-	1 - Asserts data_inp_last signal.
+* 		-	0 - data_inp_last will not be asserted.
+*
+* @return	None.
+*
+* @note		Data_inp_last signal is asserted simultaneously with the
+* 		data_inp_valid signal associated with the final 32-bit word
+*		transfer.
+*
+******************************************************************************/
+void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+					UINTPTR Addr, u32 Size, u8 EnDataLast)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00);
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+					(Channel == (XCSUDMA_DST_CHANNEL)));
+	Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX));
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
+
+	/* Flushing cache memory */
+	if (Channel == (XCSUDMA_SRC_CHANNEL)) {
+		Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
+	}
+	/* Invalidating cache memory */
+	else {
+#if defined(__aarch64__)
+		Xil_DCacheInvalidateRange(Addr, Size <<
+					(u32)(XCSUDMA_SIZE_SHIFT));
+#else
+		Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
+#endif
+	}
+
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_ADDR_OFFSET) +
+		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+				((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK)));
+
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+		(((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) &
+					(u32)(XCSUDMA_MSB_ADDR_MASK)));
+
+	if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_SIZE_OFFSET) +
+				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+			((Size << (u32)(XCSUDMA_SIZE_SHIFT)) |
+					(u32)(XCSUDMA_LAST_WORD_MASK)));
+	}
+	else {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_SIZE_OFFSET) +
+				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+				(Size << (u32)(XCSUDMA_SIZE_SHIFT)));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current address location of the memory, from where
+* it has to read the data(SRC) or the location where it has to write the data
+* (DST) based on the channel selection.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	Address is a 64 bit variable which holds the current address.
+*		- From this location data has to be read(SRC)
+*		- At this location data has to be written(DST)
+*
+* @note		None.
+*
+******************************************************************************/
+u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
+{
+	u64 FullAddr;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+					(Channel == (XCSUDMA_DST_CHANNEL)));
+
+	FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+				((u32)(XCSUDMA_ADDR_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
+
+	FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) <<
+				(u64)(XCSUDMA_MSB_ADDR_SHIFT));
+
+	return FullAddr;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the size of the data yet to be transfered from memory
+* to CSU_DMA or CSU_DMA to memory based on the channel selection.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	Size is amount of data yet to be transfered.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
+{
+	u32 Size;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+					(Channel == (XCSUDMA_DST_CHANNEL)));
+
+	Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_SIZE_OFFSET) +
+		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >>
+					(u32)(XCSUDMA_SIZE_SHIFT);
+
+	return Size;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function pause the Channel data tranfer to/from memory or to/from stream
+* based on pause type.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	Type is type of the pause to be enabled.
+*		- XCSUDMA_PAUSE_MEMORY(0) - Pause memory
+*			- SRC Stops issuing of new read commands to memory.
+*			- DST Stops issuing of new write commands to memory.
+*		- XCSUDMA_PAUSE_STREAM(1) - Pause stream
+*			- SRC Stops transfer of data from FIFO to Stream.
+*			- DST Stops transfer of data from stream to FIFO.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+						XCsuDma_PauseType Type)
+{
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
+				(Type == (XCSUDMA_PAUSE_STREAM)));
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+					(Channel == (XCSUDMA_DST_CHANNEL)));
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
+
+	/* Pause Memory Read/Write/Stream operations */
+	if (Type == (XCSUDMA_PAUSE_MEMORY)) {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_CTRL_OFFSET) +
+				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+			(XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+				((u32)(XCSUDMA_CTRL_OFFSET) +
+				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) |
+					(u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)));
+	}
+	if (Type == (XCSUDMA_PAUSE_STREAM)) {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_CTRL_OFFSET) +
+				((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+			(XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+				((u32)(XCSUDMA_CTRL_OFFSET) +
+				(Channel * (u32)XCSUDMA_OFFSET_DIFF))) |
+				(u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This functions checks whether Channel's memory or stream is paused or not
+* based on the given pause type.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	Type is type of the pause which needs to be checked.
+*		- XCSUDMA_PAUSE_MEMORY(0) - Pause memory
+*			- SRC Stops issuing of new read commands to memory.
+*			- DST Stops issuing of new write commands to memory.
+*		- XCSUDMA_PAUSE_STREAM(1) - Pause stream
+*			- SRC Stops transfer of data from FIFO to Stream.
+*			- DST Stops transfer of data from stream to FIFO.
+*
+* @return	Returns the pause status.
+*		- TRUE if it is in paused state.
+*		- FALSE if it is not in pause state.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+		XCsuDma_PauseType Type)
+{
+
+	u32 Data;
+	s32 PauseState;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+					(Channel == (XCSUDMA_DST_CHANNEL)));
+	Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
+					(Type == (XCSUDMA_PAUSE_STREAM)));
+
+	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_CTRL_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
+
+	/* To know Pause condition of Memory Read/Write/Stream operations */
+	if (Type == (XCSUDMA_PAUSE_MEMORY)) {
+		if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) ==
+								(u32)0x00) {
+			PauseState = (s32)(FALSE);
+		}
+		else {
+			PauseState = (s32)(TRUE);
+		}
+	}
+	else {
+		if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) ==
+								(u32)0x00) {
+				PauseState = (s32)(FALSE);
+		}
+		else {
+			PauseState = (s32)(TRUE);
+		}
+	}
+
+	return (s32)PauseState;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resumes the channel if it is in paused state and continues
+* where it has left or no effect if it is not in paused state, based on the
+* type of pause.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	Type is type of the pause to be Resume if it is in pause
+*		state.
+*		- XCSUDMA_PAUSE_MEMORY(0) - Pause memory
+*			- SRC Stops issuing of new read commands to memory.
+*			- DST Stops issuing of new write commands to memory.
+*		- XCSUDMA_PAUSE_STREAM(1) - Pause stream
+*			- SRC Stops transfer of data from FIFO to Stream.
+*			- DST Stops transfer of data from stream to FIFO.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+		XCsuDma_PauseType Type)
+{
+	u32 Data;
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
+			(Type == (XCSUDMA_PAUSE_STREAM)));
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+					(Channel == (XCSUDMA_DST_CHANNEL)));
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
+
+	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_CTRL_OFFSET) +
+		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
+
+	if (Type == (XCSUDMA_PAUSE_MEMORY)) {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_CTRL_OFFSET) +
+		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+		(Data &
+				(~(XCSUDMA_CTRL_PAUSE_MEM_MASK))));
+	}
+	if (Type == (XCSUDMA_PAUSE_STREAM)) {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_CTRL_OFFSET) +
+		(((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))),
+			( Data &
+			(~(XCSUDMA_CTRL_PAUSE_STRM_MASK))));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the sum of all the data read from AXI memory. It is
+* valid only one we use CSU_DMA source channel.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+*
+* @return	Returns the sum of all the data read from memory.
+*
+* @note		Before start of the transfer need to clear this register to get
+*		correct sum otherwise it adds to previous value which results
+*		to wrong output.
+*		Valid only for source channel
+*
+******************************************************************************/
+u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr)
+{
+	u32 ChkSum;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady ==
+				(u32)(XIL_COMPONENT_IS_READY));
+
+	ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+						(u32)(XCSUDMA_CRC_OFFSET));
+
+	return ChkSum;
+
+}
+/*****************************************************************************/
+/**
+*
+* This function clears the check sum of the data read from AXI memory. It is
+* valid only for CSU_DMA source channel.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+*
+* @return	Returns the sum of all the data read from memory.
+*
+* @note		Before start of the transfer need to clear this register to get
+*		correct sum otherwise it adds to previous value which results
+*		to wrong output.
+*
+******************************************************************************/
+void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr)
+{
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		(u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK));
+}
+
+/*****************************************************************************/
+/**
+* This function cofigures all the values of CSU_DMA's Channels with the values
+* of updated XCsuDma_Configure structure.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	ConfigurValues is a pointer to the structure XCsuDma_Configure
+*		whose values are used to configure CSU_DMA core.
+*		- SssFifoThesh   When the DST FIFO level >= this value,
+*		  the SSS interface signal, "data_out_fifo_level_hit" will be
+*		  asserted. This mechanism can be used by the SSS to flow
+*		  control data that is being looped back from the SRC DMA.
+*			- Range is (0x10 to 0x7A) threshold is 17 to 123
+*			entries.
+*			- It is valid only for DST CSU_DMA IP.
+*		- ApbErr          When accessed to invalid APB the resulting
+*		  pslerr will be
+*			- 0 - 1'b0
+*			- 1 - 1'b1
+*		- EndianType      Type of endianness
+*			- 0 doesn't change order
+*			- 1 will flip the order.
+*		- AxiBurstType....Type of the burst
+*			- 0 will issue INCR type burst
+*			- 1 will issue FIXED type burst
+*		- TimeoutValue    Time out value for timers
+*			- 0x000 to 0xFFE are valid inputs
+*			- 0xFFF clears both timers
+*		- FifoThresh......Programmed watermark value
+*			- Range is 0x00 to 0x80 (0 to 128 entries).
+*		- Acache         Sets the AXI CACHE bits on the AXI Write/Read
+*		channel.
+*			- Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
+*			  for DST channel are always 1, we need to configure
+*			  remaining 3 signal support
+*			  (Bufferable, Read allocate and Write allocate).
+*			Valid inputs are:
+*			- 0x000 - Cacheable, but do not allocate
+*			- 0x001 - Cacheable and bufferable, but do not allocate
+*			- 0x010 - Cacheable write-through, allocate on reads
+*				  only
+*			- 0x011 - Cacheable write-back, allocate on reads only
+*			- 0x100 - Cacheable write-through, allocate on writes
+*				  only
+*			- 0x101 - Cacheable write-back, allocate on writes only
+*			- 0x110 - Cacheable write-through, allocate on both
+*				  reads and writes
+*			- 0x111 - Cacheable write-back, allocate on both reads
+*				  and writes
+*		- RouteBit        To select route
+*			- 0 : Command will be routed normally
+*			- 1 : Command will be routed to APU's cache controller
+*		- TimeoutEn       To enable or disable time out counters
+*			- 0 : The 2 Timeout counters are disabled
+*			- 1 : The 2 Timeout counters are enabled
+*		- TimeoutPre      Set the prescaler value for the timeout in
+*		clk (~2.5ns) cycles
+*			- Range is 0x000(Prescaler enables timer every cycles)
+*			  to 0xFFF(Prescaler enables timer every 4096 cycles)
+*		- MaxOutCmds      Controls the maximumum number of outstanding
+*		AXI read commands issued.
+*			- Range is 0x0(Up to 1 Outstanding Read command
+*			  allowed) to 0x8 (Up to 9 Outstanding Read
+*			  command allowed)
+*
+* @return	None.
+*
+* @note		To use timers timeout value Timeout enable field should be
+*		enabled.
+*
+******************************************************************************/
+void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+					XCsuDma_Configure *ConfigurValues)
+{
+	u32 Data;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
+	Xil_AssertVoid(ConfigurValues != NULL);
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+				(Channel == (XCSUDMA_DST_CHANNEL)));
+	Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE));
+
+	Data = (((ConfigurValues->EndianType <<
+			(u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
+			(u32)(XCSUDMA_CTRL_ENDIAN_MASK)) |
+		((ConfigurValues->ApbErr <<
+			(u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) &
+			(u32)(XCSUDMA_CTRL_APB_ERR_MASK)) |
+		((ConfigurValues->AxiBurstType <<
+			(u32)(XCSUDMA_CTRL_BURST_SHIFT)) &
+			(u32)(XCSUDMA_CTRL_BURST_MASK)) |
+		((ConfigurValues->TimeoutValue <<
+			(u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) &
+			(u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) |
+		((ConfigurValues->FifoThresh <<
+			(u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) &
+			(u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)));
+	if(Channel == XCSUDMA_DST_CHANNEL) {
+		Data = Data | (u32)((ConfigurValues->SssFifoThesh <<
+				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) &
+				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK));
+	}
+
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_CTRL_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
+
+	Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_CTRL2_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) &
+				(u32)(XCSUDMA_CTRL2_RESERVED_MASK));
+	Data |= (((ConfigurValues->Acache <<
+			(u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) &
+			(u32)(XCSUDMA_CTRL2_ACACHE_MASK)) |
+		((ConfigurValues->RouteBit <<
+			(u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) &
+			(u32)(XCSUDMA_CTRL2_ROUTE_MASK)) |
+		((ConfigurValues->TimeoutEn <<
+			(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) &
+			(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) |
+		((ConfigurValues->TimeoutPre <<
+			(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) &
+			(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) |
+		((ConfigurValues->MaxOutCmds) &
+			(u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
+
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_CTRL2_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function updates XCsuDma_Configure structure members with the cofigured
+* values of CSU_DMA's Channel.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	ConfigurValues is a pointer to the structure XCsuDma_Configure
+*		whose members are updated with configurations of CSU_DMA core.
+*		- SssFifoThesh   When the DST FIFO level >= this value,
+*		  the SSS interface signal, "data_out_fifo_level_hit" will be
+*		  asserted. This mechanism can be used by the SSS to flow
+*		  control data that is being looped back from the SRC DMA.
+*			- Range is (0x10 to 0x7A) threshold is 17 to 123
+*			entries.
+*			- It is valid only for DST CSU_DMA IP.
+*		- ApbErr          When accessed to invalid APB the resulting
+*		  pslerr will be
+*			- 0 - 1'b0
+*			- 1 - 1'b1
+*		- EndianType      Type of endianness
+*			- 0 doesn't change order
+*			- 1 will flip the order.
+*		- AxiBurstType....Type of the burst
+*			- 0 will issue INCR type burst
+*			- 1 will issue FIXED type burst
+*		- TimeoutValue    Time out value for timers
+*			- 0x000 to 0xFFE are valid inputs
+*			- 0xFFF clears both timers
+*		- FifoThresh......Programmed watermark value
+*			- Range is 0x00 to 0x80 (0 to 128 entries).
+*		- Acache         Sets the AXI CACHE bits on the AXI Write/Read
+*		channel.
+*			- Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
+*			  for DST channel are always 1, we need to configure
+*			  remaining 3 signal support
+*			  (Bufferable, Read allocate and Write allocate).
+*			Valid inputs are:
+*			- 0x000 - Cacheable, but do not allocate
+*			- 0x001 - Cacheable and bufferable, but do not allocate
+*			- 0x010 - Cacheable write-through, allocate on reads
+*				  only
+*			- 0x011 - Cacheable write-back, allocate on reads only
+*			- 0x100 - Cacheable write-through, allocate on writes
+*				  only
+*			- 0x101 - Cacheable write-back, allocate on writes only
+*			- 0x110 - Cacheable write-through, allocate on both
+*				  reads and writes
+*			- 0x111 - Cacheable write-back, allocate on both reads
+*				  and writes
+*		- RouteBit        To select route
+*			- 0 : Command will be routed based normally
+*			- 1 : Command will be routed to APU's cache controller
+*		- TimeoutEn       To enable or disable time out counters
+*			- 0 : The 2 Timeout counters are disabled
+*			- 1 : The 2 Timeout counters are enabled
+*		- TimeoutPre      Set the prescaler value for the timeout in
+*		clk (~2.5ns) cycles
+*			- Range is 0x000(Prescaler enables timer every cycles)
+*			 to 0xFFF(Prescaler enables timer every 4096 cycles)
+*		- MaxOutCmds      Controls the maximumum number of outstanding
+*		AXI read commands issued.
+*			- Range is 0x0(Up to 1 Outstanding Read command
+*			allowed) to 0x8 (Up to 9 Outstanding Read command
+*			allowed)
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+				XCsuDma_Configure *ConfigurValues)
+{
+	u32 Data;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(ConfigurValues != NULL);
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+				(Channel == (XCSUDMA_DST_CHANNEL)));
+
+	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_CTRL_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
+
+	if (Channel == (XCSUDMA_DST_CHANNEL)) {
+		ConfigurValues->SssFifoThesh =
+			(u8)((Data &
+				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >>
+				(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT));
+	}
+	ConfigurValues->ApbErr =
+		(u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >>
+				(u32)(XCSUDMA_CTRL_APB_ERR_SHIFT));
+	ConfigurValues->EndianType =
+		(u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >>
+				(u32)(XCSUDMA_CTRL_ENDIAN_SHIFT));
+	ConfigurValues->AxiBurstType =
+		(u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >>
+				(u32)(XCSUDMA_CTRL_BURST_SHIFT));
+	ConfigurValues->TimeoutValue =
+		((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >>
+				(u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT));
+	ConfigurValues->FifoThresh =
+		(u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >>
+				(u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT));
+
+	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_CTRL2_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
+
+	ConfigurValues->Acache =
+			(u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >>
+					(u32)(XCSUDMA_CTRL2_ACACHE_SHIFT));
+	ConfigurValues->RouteBit =
+			(u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >>
+					(u32)(XCSUDMA_CTRL2_ROUTE_SHIFT));
+	ConfigurValues->TimeoutEn =
+			(u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >>
+				(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT));
+	ConfigurValues->TimeoutPre =
+			(u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >>
+				(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT));
+	ConfigurValues->MaxOutCmds =
+			(u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h
new file mode 100644
index 000000000..03a32c1ce
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h
@@ -0,0 +1,420 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* The CSU_DMA is present inside CSU (Configuration Security Unit) module which
+* is located within the Low-Power Subsystem (LPS) internal to the PS.
+* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit
+* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure
+* Stream Switch (SSS).
+*
+* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC
+* (read) channel and DST (write) channel. The DMA is effectively able to
+* transfer data:
+*	- From PS-side to the SSS-side (SRC DMA only)
+*	- From SSS-side to the PS-side (DST DMA only)
+*	- Simultaneous PS-side to SSS_side and SSS-side to the PS-side
+*
+* <b>Initialization & Configuration</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the CSU_DMA core.
+*
+* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core.
+* The user needs to first call the XCsuDma_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to the
+* XCsuDma_CfgInitialize() API.
+*
+* <b> Interrupts </b>
+* This driver will not support handling of interrupts user should write handler
+* to handle the interrupts.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XCsuDma driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* @file xcsudma.h
+* @addtogroup csudma_v1_0
+* @{
+* @details
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros), range macros, structure typedefs that can be used to access the
+* Xilinx CSU_DMA core instance.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+* 1.1   adk     10/05/16 Fixed CR#951040 race condition in the recv path when
+*                        source and destination points to the same buffer.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XCSUDMA_H_
+#define XCSUDMA_H_	/**< Prevent circular inclusions
+			  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xcsudma_hw.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_cache.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name CSU_DMA Channels
+ * @{
+ */
+typedef enum {
+	XCSUDMA_SRC_CHANNEL = 0U,	/**< Source Channel of CSU_DMA */
+	XCSUDMA_DST_CHANNEL		/**< Destination Channel of CSU_DMA */
+}XCsuDma_Channel;
+/*@}*/
+
+/** @name CSU_DMA pause types
+ * @{
+ */
+typedef enum {
+	XCSUDMA_PAUSE_MEMORY,		/**< Pauses memory data transfer
+					  *  to/from CSU_DMA */
+	XCSUDMA_PAUSE_STREAM,		/**< Pauses stream data transfer
+					  *  to/from CSU_DMA */
+}XCsuDma_PauseType;
+
+/*@}*/
+
+
+/** @name Ranges of Size
+ * @{
+ */
+#define XCSUDMA_SIZE_MAX 0x07FFFFFF	/**< Maximum allowed no of words */
+
+/*@}*/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This function resets the CSU_DMA core.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*		C-style signature:
+*		void XCsuDma_Reset()
+*
+******************************************************************************/
+#define XCsuDma_Reset()  \
+	Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
+				(u32)(XCSUDMA_RESET_SET_MASK)); \
+	Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
+					(u32)(XCSUDMA_RESET_UNSET_MASK));
+
+/*****************************************************************************/
+/**
+* This function will be in busy while loop until the data transfer is
+* completed.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+*		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	None.
+*
+* @note		This function should be called after XCsuDma_Transfer in polled
+*		mode  to wait until the data gets transfered completely.
+*		C-style signature:
+*		void XCsuDma_WaitForDone(XCsuDma *InstancePtr,
+*						XCsuDma_Channel Channel)
+*
+******************************************************************************/
+#define XCsuDma_WaitForDone(InstancePtr,Channel) \
+		while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
+			((u32)(XCSUDMA_I_STS_OFFSET) + \
+			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
+		(u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function returns the number of completed SRC/DST DMA transfers that
+* have not been acknowledged by software based on the channel selection.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	Count is number of completed DMA transfers but not acknowledged
+*		(Range is 0 to 7).
+*		- 000 - All finished transfers have been acknowledged.
+*		- Count - Count number of finished transfers are still
+*		outstanding.
+*
+* @note		None.
+*		C-style signature:
+*		u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr,
+*						XCsuDma_Channel Channel)
+*
+******************************************************************************/
+#define XCsuDma_GetDoneCount(InstancePtr, Channel)  \
+		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
+			((u32)(XCSUDMA_STS_OFFSET) + \
+			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
+			(u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \
+				(u32)(XCSUDMA_STS_DONE_CNT_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current SRC/DST FIFO level in 32 bit words of the
+* selected channel
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	FIFO level. (Range is 0 to 128)
+*		- 0 Indicates empty
+*		- Any number 1 to 128 indicates the number of entries in FIFO.
+*
+* @note		None.
+*		C-style signature:
+*		u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr,
+*					XCsuDma_Channel Channel)
+*
+******************************************************************************/
+#define XCsuDma_GetFIFOLevel(InstancePtr, Channel)  \
+		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
+			((u32)(XCSUDMA_STS_OFFSET) + \
+			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
+			(u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \
+					(u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current number of read(src)/write(dst) outstanding
+* commands based on the type of channel selected.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	Count of outstanding commands. (Range is 0 to 9).
+*
+* @note		None.
+*		C-style signature:
+*		u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr,
+*						XCsuDma_Channel Channel)
+*
+******************************************************************************/
+#define XCsuDma_GetWROutstandCount(InstancePtr, Channel)  \
+		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
+				((u32)(XCSUDMA_STS_OFFSET) + \
+			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
+			(u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \
+				(u32)(XCUSDMA_STS_OUTSTDG_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns the status of Channel either it is busy or not.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+* 		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	Returns the current status of the core.
+*		- TRUE represents core is currently busy.
+*		- FALSE represents core is not involved in any transfers.
+*
+* @note		None.
+*		C-style signature:
+*		s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
+*
+******************************************************************************/
+
+#define XCsuDma_IsBusy(InstancePtr, Channel) \
+		((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
+					((u32)(XCSUDMA_STS_OFFSET) + \
+			((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
+		(u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \
+				(TRUE) : (FALSE)
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+* This typedef contains configuration information for a CSU_DMA core.
+* Each CSU_DMA core should have a configuration structure associated.
+*/
+typedef struct {
+	u16 DeviceId;		/**< DeviceId is the unique ID of the
+				  *  device */
+	u32 BaseAddress;	/**< BaseAddress is the physical base address
+				  *  of the device's registers */
+} XCsuDma_Config;
+
+
+/******************************************************************************/
+/**
+*
+* The XCsuDma driver instance data structure. A pointer to an instance data
+* structure is passed around by functions to refer to a specific driver
+* instance.
+*/
+typedef struct {
+	XCsuDma_Config Config;		/**< Hardware configuration */
+	u32 IsReady;			/**< Device and the driver instance
+					  *  are initialized */
+}XCsuDma;
+
+
+/******************************************************************************/
+/**
+* This typedef contains all the configuration feilds which needs to be set
+* before the start of the data transfer. All these feilds of CSU_DMA can be
+* configured by using XCsuDma_SetConfig API.
+*/
+typedef struct {
+	u8 SssFifoThesh;	/**< SSS FIFO threshold value */
+	u8 ApbErr;		/**< ABP invalid access error */
+	u8 EndianType;		/**< Type of endianess */
+	u8 AxiBurstType;	/**< Type of AXI bus */
+	u32 TimeoutValue;	/**< Time out value */
+	u8 FifoThresh;		/**< FIFO threshold value */
+	u8 Acache;		/**< AXI CACHE selection */
+	u8 RouteBit;		/**< Selection of Route */
+	u8 TimeoutEn;		/**< Enable of time out counters */
+	u16 TimeoutPre;		/**< Pre scaler value */
+	u8 MaxOutCmds;		/**< Maximum number of outstanding
+				  *  commands */
+}XCsuDma_Configure;
+
+/*****************************************************************************/
+
+
+/************************** Function Prototypes ******************************/
+
+XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId);
+
+s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
+			u32 EffectiveAddr);
+void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+					UINTPTR Addr, u32 Size, u8 EnDataLast);
+void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr,
+						u32 Size);
+u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
+u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
+
+void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+						XCsuDma_PauseType Type);
+s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+						XCsuDma_PauseType Type);
+void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+						XCsuDma_PauseType Type);
+
+u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr);
+void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr);
+
+void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+					XCsuDma_Configure *ConfigurValues);
+void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+					XCsuDma_Configure *ConfigurValues);
+void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
+
+void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value);
+u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr);
+
+/* Interrupt related APIs */
+u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
+void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+								u32 Mask);
+void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+								u32 Mask);
+void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+								u32 Mask);
+u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
+
+s32 XCsuDma_SelfTest(XCsuDma *InstancePtr);
+
+/******************************************************************************/
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* End of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c
new file mode 100644
index 000000000..09e7f739a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xcsudma.h"
+
+/*
+* The configuration table for devices
+*/
+
+XCsuDma_Config XCsuDma_ConfigTable[] =
+{
+	{
+		XPAR_PSU_CSUDMA_DEVICE_ID,
+		XPAR_PSU_CSUDMA_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h
new file mode 100644
index 000000000..6b2c2cdb8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h
@@ -0,0 +1,311 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcsudma_hw.h
+* @addtogroup csudma_v1_0
+* @{
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros) that can be used to access the Xilinx CSU_DMA core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vnsld  22/10/14 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XCSUDMA_HW_H_
+#define XCSUDMA_HW_H_	/**< Prevent circular inclusions
+			  *  by using protection macros	*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers offsets
+ * @{
+ */
+#define XCSUDMA_ADDR_OFFSET	0x000	/**< Address Register Offset */
+#define XCSUDMA_SIZE_OFFSET	0x004	/**< Size Register Offset */
+#define XCSUDMA_STS_OFFSET	0x008	/**< Status Register Offset */
+#define XCSUDMA_CTRL_OFFSET	0x00C	/**< Control Register Offset */
+#define XCSUDMA_CRC_OFFSET	0x010	/**< CheckSum Register Offset */
+#define XCSUDMA_I_STS_OFFSET	0x014	/**< Interrupt Status Register
+					  *  Offset */
+#define XCSUDMA_I_EN_OFFSET	0x018	/**< Interrupt Enable Register
+					  *  Offset */
+#define XCSUDMA_I_DIS_OFFSET	0x01C	/**< Interrupt Disable Register
+					  *  Offset */
+#define XCSUDMA_I_MASK_OFFSET	0x020	/**< Interrupt Mask Register Offset */
+#define XCSUDMA_CTRL2_OFFSET	0x024	/**< Interrupt Control Register 2
+					  *  Offset */
+#define XCSUDMA_ADDR_MSB_OFFSET	0x028	/**< Address's MSB Register Offset */
+#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8	/**< Safety Check Field Offset */
+#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC	/**< Future potential ECO Offset */
+/*@}*/
+
+/** @name CSU Base address and CSU_DMA reset offset
+ * @{
+ */
+#define XCSU_BASEADDRESS	0xFFCA0000
+						/**< CSU Base Address */
+#define XCSU_DMA_RESET_OFFSET	0x0000000CU	/**< CSU_DMA Reset offset */
+/*@}*/
+
+/** @name CSU_DMA Reset register bit masks
+ * @{
+ */
+#define XCSUDMA_RESET_SET_MASK		0x00000001U	/**< Reset set mask */
+#define XCSUDMA_RESET_UNSET_MASK	0x00000000U	/**< Reset unset mask*/
+/*@}*/
+
+/** @name Offset difference for Source and destination
+ * @{
+ */
+#define XCSUDMA_OFFSET_DIFF	0x00000800U	/**< Offset difference for
+						  *  source and
+						  *  destination channels */
+/*@}*/
+
+/** @name Address register bit masks
+ * @{
+ */
+#define XCSUDMA_ADDR_MASK	0xFFFFFFFCU	/**< Address mask */
+#define XCSUDMA_ADDR_LSB_MASK	0x00000003U	/**< Address alignment check
+						  *  mask */
+/*@}*/
+
+/** @name Size register bit masks and shifts
+ * @{
+ */
+#define XCSUDMA_SIZE_MASK	0x1FFFFFFCU	/**< Mask for size */
+#define XCSUDMA_LAST_WORD_MASK	0x00000001U	/**< Last word check bit mask*/
+#define XCSUDMA_SIZE_SHIFT	2U		/**< Shift for size */
+/*@}*/
+
+/** @name Status register bit masks and shifts
+ * @{
+ */
+#define XCSUDMA_STS_DONE_CNT_MASK	0x0000E000U	/**< Count done mask */
+#define XCSUDMA_STS_FIFO_LEVEL_MASK	0x00001FE0U	/**< FIFO level mask */
+#define XCUSDMA_STS_OUTSTDG_MASK	0x0000001EU	/**< No.of outstanding
+							  *  read/write
+							  *  commands mask */
+#define XCSUDMA_STS_BUSY_MASK		0x00000001U	/**< Busy mask */
+#define XCSUDMA_STS_DONE_CNT_SHIFT	13U		/**< Shift for Count
+							  *  done */
+#define XCSUDMA_STS_FIFO_LEVEL_SHIFT	5U		/**< Shift for FIFO
+							  *  level */
+#define XCUSDMA_STS_OUTSTDG_SHIFT	1U		/**< Shift for No.of
+							  *  outstanding
+							  *  read/write
+							  *  commands */
+/*@}*/
+
+/** @name Control register bit masks and shifts
+ * @{
+ */
+#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U	/**< SSS FIFO threshold
+							  *  value mask */
+#define XCSUDMA_CTRL_APB_ERR_MASK	0x01000000U	/**< APB register
+							  *  access error
+							  *  mask */
+#define XCSUDMA_CTRL_ENDIAN_MASK	0x00800000U	/**< Endianess mask */
+#define XCSUDMA_CTRL_BURST_MASK		0x00400000U	/**< AXI burst type
+							  *  mask */
+#define XCSUDMA_CTRL_TIMEOUT_MASK	0x003FFC00U	/**< Time out value
+							  *  mask */
+#define XCSUDMA_CTRL_FIFO_THRESH_MASK	0x000003FCU	/**< FIFO threshold
+							  *  mask */
+#define XCSUDMA_CTRL_PAUSE_MEM_MASK	0x00000001U	/**< Memory pause
+							  *  mask */
+#define XCSUDMA_CTRL_PAUSE_STRM_MASK	0x00000002U	/**< Stream pause
+							  *  mask */
+#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U		/**< SSS FIFO threshold
+							  *  shift */
+#define XCSUDMA_CTRL_APB_ERR_SHIFT	24U		/**< APB error shift */
+#define XCSUDMA_CTRL_ENDIAN_SHIFT	23U		/**< Endianess shift */
+#define XCSUDMA_CTRL_BURST_SHIFT	22U		/**< AXI burst type
+							  *  shift */
+#define XCSUDMA_CTRL_TIMEOUT_SHIFT	10U		/**< Time out value
+							  *  shift */
+#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT	2U		/**< FIFO thresh
+							  *  shift */
+/*@}*/
+
+/** @name CheckSum register bit masks
+ * @{
+ */
+#define XCSUDMA_CRC_RESET_MASK		0x00000000U	/**< Mask to reset
+							  *  value of
+							  *  check sum */
+/*@}*/
+
+/** @name Interrupt Enable/Disable/Mask/Status registers bit masks
+ * @{
+ */
+#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK	0x00000001U	/**< FIFO overflow
+							  *  mask, it is valid
+							  *  only to Destination
+							  *  Channel */
+#define XCSUDMA_IXR_INVALID_APB_MASK	0x00000040U	/**< Invalid APB access
+							  *  mask */
+#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK	0x00000020U	/**< FIFO threshold hit
+							  *  indicator mask */
+#define XCSUDMA_IXR_TIMEOUT_MEM_MASK	0x00000010U	/**< Time out counter
+							  *  expired to access
+							  *  memory mask */
+#define XCSUDMA_IXR_TIMEOUT_STRM_MASK	0x00000008U	/**< Time out counter
+							  *  expired to access
+							  *  stream mask */
+#define XCSUDMA_IXR_AXI_WRERR_MASK	0x00000004U	/**< AXI Read/Write
+							  *  error mask */
+#define XCSUDMA_IXR_DONE_MASK		0x00000002U	/**< Done mask */
+#define XCSUDMA_IXR_MEM_DONE_MASK	0x00000001U	/**< Memory done
+							  *  mask, it is valid
+							  *  only for source
+							  *  channel*/
+#define XCSUDMA_IXR_SRC_MASK		0x0000007FU
+					/**< ((XCSUDMA_IXR_INVALID_APB_MASK)|
+					(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
+					(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
+					(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
+					(XCSUDMA_IXR_AXI_WRERR_MASK) |
+					(XCSUDMA_IXR_DONE_MASK) |
+					(XCSUDMA_IXR_MEM_DONE_MASK)) */
+					/**< All interrupt mask
+					  *  for source */
+#define XCSUDMA_IXR_DST_MASK		0x000000FEU
+					/**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
+					(XCSUDMA_IXR_INVALID_APB_MASK) |
+					(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
+					(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
+					(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
+					(XCSUDMA_IXR_AXI_WRERR_MASK) |
+					(XCSUDMA_IXR_DONE_MASK)) */
+					/**< All interrupt mask
+					  *  for destination */
+/*@}*/
+
+/** @name Control register 2 bit masks and shifts
+ * @{
+ */
+#define XCSUDMA_CTRL2_RESERVED_MASK	0x083F0000U	/**< Reserved bits
+							  *  mask */
+#define XCSUDMA_CTRL2_ACACHE_MASK	0X07000000U	/**< AXI CACHE mask */
+#define XCSUDMA_CTRL2_ROUTE_MASK	0x00800000U	/**< Route mask */
+#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK	0x00400000U	/**< Time out counters
+							  *  enable mask */
+#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK	0x0000FFF0U	/**< Time out pre
+							  *  mask */
+#define XCSUDMA_CTRL2_MAXCMDS_MASK	0x0000000FU	/**< Maximum commands
+							  *  mask */
+#define XCSUDMA_CTRL2_RESET_MASK	0x0000FFF8U	/**< Reset mask */
+#define XCSUDMA_CTRL2_ACACHE_SHIFT	24U		/**< Shift for
+							  *  AXI R/W CACHE */
+#define XCSUDMA_CTRL2_ROUTE_SHIFT	23U		/**< Shift for route */
+#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT	22U		/**< Shift for Timeout
+							  *  enable feild */
+#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT	4U		/**< Shift for Timeout
+							  *  pre feild */
+/*@}*/
+
+/** @name MSB Address register bit masks and shifts
+ * @{
+ */
+#define XCSUDMA_MSB_ADDR_MASK	0x0001FFFFU	/**< MSB bits of address
+						  *  mask */
+#define XCSUDMA_MSB_ADDR_SHIFT	32U		/**< Shift for MSB bits of
+						  *  address */
+/*@}*/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XCsuDma_In32		Xil_In32	/**< Input operation */
+#define XCsuDma_Out32		Xil_Out32	/**< Output operation */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the Xilinx base address of the CSU_DMA core.
+* @param	RegOffset is the register offset of the register.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XCsuDma_ReadReg(BaseAddress, RegOffset) \
+		XCsuDma_In32((BaseAddress) + (u32)(RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes the value into the given register.
+*
+* @param	BaseAddress is the Xilinx base address of the CSU_DMA core.
+* @param	RegOffset is the register offset of the register.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \
+		XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+
+#ifdef __cplusplus
+}
+
+#endif
+
+
+#endif /* End of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c
new file mode 100644
index 000000000..9f37e4582
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c
@@ -0,0 +1,274 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xcsudma_intr.c
+* @addtogroup csudma_v1_0
+* @{
+*
+* This file contains interrupt related functions of Xilinx CSU_DMA core.
+* Please see xcsudma.h for more details of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld  22/10/14  First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcsudma.h"
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Function Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+* Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to interpret the
+* returned value.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+*		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	The pending interrupts of the CSU_DMA. Use th following masks
+*		to interpret the returned value.
+*		XCSUDMA_IXR_SRC_MASK   - For Source channel
+*		XCSUDMA_IXR_DST_MASK   - For Destination channel
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
+{
+	u32 Data;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+				(Channel == (XCSUDMA_DST_CHANNEL)));
+
+	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+				(u32)(XCSUDMA_I_STS_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)));
+
+	return Data;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears interrupt(s). Every bit set in Interrupt Status
+* Register indicates that a specific type of interrupt is occurring, and this
+* function clears one or more interrupts by writing a bit mask to Interrupt
+* Clear Register.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+*		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	Mask is the mask to clear. Bit positions of 1 will be cleared.
+*		Bit positions of 0 will not change the previous interrupt
+*		status. This mask is formed by OR'ing XCSUDMA_IXR_* bits
+*		defined in xcsudma_hw.h.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
+{
+
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+				(Channel == (XCSUDMA_DST_CHANNEL)));
+	if (Channel == (XCSUDMA_SRC_CHANNEL)) {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			(u32)(XCSUDMA_I_STS_OFFSET),
+				(Mask & (u32)(XCSUDMA_IXR_SRC_MASK)));
+	}
+	else {
+		XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_I_STS_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
+				(Mask & (u32)(XCSUDMA_IXR_DST_MASK)));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants
+* defined in xcsudma_hw.h to create the bit-mask to enable interrupts.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+*		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	Mask contains interrupts to be enabled.
+*		- Bit positions of 1 will be enabled.
+*		This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined
+*		in xcsudma_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+							u32 Mask)
+{
+	u32 Data;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+				(Channel == (XCSUDMA_DST_CHANNEL)));
+
+	if (Channel == (XCSUDMA_SRC_CHANNEL)) {
+		Data = Mask & (u32)(XCSUDMA_IXR_SRC_MASK);
+	}
+	else {
+		Data = Mask & (u32)(XCSUDMA_IXR_DST_MASK);
+	}
+	/*
+	 * Write the mask to the IER Register
+	 */
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_I_EN_OFFSET) +
+		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants
+* defined in xcsudma_hw.h to create the bit-mask to disable interrupts.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+*		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+* @param	Mask contains interrupts to be disabled.
+*		- Bit positions of 1 will be disabled.
+*		This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined
+*		in xcsudma_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
+								u32 Mask)
+{
+	u32 Data;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+			(Channel == (XCSUDMA_DST_CHANNEL)));
+
+	if (Channel == XCSUDMA_SRC_CHANNEL) {
+		Data = (Mask) & (u32)(XCSUDMA_IXR_SRC_MASK);
+	}
+	else {
+		Data = (Mask) & (u32)(XCSUDMA_IXR_DST_MASK);
+	}
+
+	/*
+	 * Write the mask to the IDR Register
+	 */
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+		((u32)(XCSUDMA_I_DIS_OFFSET) +
+		((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the interrupt mask to know which interrupts are
+* enabled and which of them were disaled.
+*
+* @param	InstancePtr is a pointer to XCsuDma instance to be worked on.
+* @param	Channel represents the type of channel either it is Source or
+*		Destination.
+*		Source channel      - XCSUDMA_SRC_CHANNEL
+*		Destination Channel - XCSUDMA_DST_CHANNEL
+*
+* @return	The current interrupt mask. The mask indicates which interrupts
+*		are enabled/disabled.
+*		0 bit represents .....corresponding interrupt is enabled.
+*		1 bit represents .....Corresponding interrupt is disabled.
+*		To interpret returned mask use
+*		XCSUDMA_IXR_SRC_MASK........For source channel
+*		XCSUDMA_IXR_DST_MASK........For destination channel
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
+{
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
+					(Channel == (XCSUDMA_DST_CHANNEL)));
+
+	/*
+	 * Read the Interrupt Mask register
+	 */
+	return (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+			((u32)(XCSUDMA_I_MASK_OFFSET) +
+			((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))));
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c
new file mode 100644
index 000000000..f61910fd4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xcsudma_selftest.c
+* @addtogroup csudma_v1_0
+* @{
+*
+* This file contains a diagnostic self-test function for the CSU_DMA driver.
+* Refer to the header file xcsudma.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcsudma.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. Performs
+* reset of both source and destination channels and checks if reset is working
+* properly or not.
+*
+* @param	InstancePtr is a pointer to the XCsuDma instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XCsuDma_SelfTest(XCsuDma *InstancePtr)
+{
+	u32 Data;
+	s32 Status;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+					(u32)(XCSUDMA_CTRL_OFFSET));
+
+	/* Changing Endianess of Source channel */
+
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+			(u32)(XCSUDMA_CTRL_OFFSET),
+			((Data) | (u32)(XCSUDMA_CTRL_ENDIAN_MASK)));
+
+	if ((XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
+		(u32)(XCSUDMA_CTRL_OFFSET)) &
+			(u32)(XCSUDMA_CTRL_ENDIAN_MASK)) ==
+				(XCSUDMA_CTRL_ENDIAN_MASK)) {
+		Status = (s32)(XST_SUCCESS);
+	}
+	else {
+		Status = (s32)(XST_FAILURE);
+	}
+
+	/* Changes made are being reverted back */
+	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
+				(u32)(XCSUDMA_CTRL_OFFSET), Data);
+
+	return Status;
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c
new file mode 100644
index 000000000..10e5c14f6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xcsudma_sinit.c
+* @addtogroup csudma_v1_0
+* @{
+*
+* This file contains static initialization methods for Xilinx CSU_DMA core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcsudma.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure
+* based on the unique device id, <i>DeviceId</i>. The return value will refer
+* to an entry in the device configuration table defined in the xcsudma_g.c
+* file.
+*
+* @param	DeviceId is the unique device ID of the device for the lookup
+*		operation.
+*
+* @return	CfgPtr is a reference to a config record in the configuration
+*		table (in xcsudma_g.c) corresponding to <i>DeviceId</i>, or
+*		NULL if no match is found.
+*
+* @note		None.
+******************************************************************************/
+XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId)
+{
+	extern XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES];
+	XCsuDma_Config *CfgPtr = NULL;
+	u32 Index;
+
+	/* Checks all the instances */
+	for (Index = (u32)0x0; Index < (u32)(XPAR_XCSUDMA_NUM_INSTANCES);
+								Index++) {
+		if (XCsuDma_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XCsuDma_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XCsuDma_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/Makefile
new file mode 100644
index 000000000..198637a46
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xddrcpsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ddrcpsu"
+
+xddrcpsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xddrcpsu_includes
+
+xddrcpsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h
new file mode 100644
index 000000000..2640a9462
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h
@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddcrpsu.h
+ * @addtogroup ddrcpsu_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrcPsu driver. This driver supports the Xilinx ddrcpsu
+ * IP core.
+ *
+ * @note	None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	ssc   04/28/16 First Release.
+ * 1.1  adk   04/08/16 Export DDR freq to xparameters.h file.
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRCPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRCPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRCPS_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile
deleted file mode 100644
index 7002e6223..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xemacps_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling emacps"
-
-xemacps_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xemacps_includes
-
-xemacps_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c
deleted file mode 100644
index 26df03c3d..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps.c
-* @addtogroup emacps_v3_1
-* @{
-*
-* The XEmacPs driver. Functions in this file are the minimum required functions
-* for this driver. See xemacps.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy  01/10/10 First release
-* 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
-*		      64-bit changes.
-* 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
-*                    Disable extended mode. Perform all 64 bit changes under
-*                    check for arch64.
-* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
-*
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-void XEmacPs_StubHandler(void);	/* Default handler routine */
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-* Initialize a specific XEmacPs instance/driver. The initialization entails:
-* - Initialize fields of the XEmacPs instance structure
-* - Reset hardware and apply default options
-* - Configure the DMA channels
-*
-* The PHY is setup independently from the device. Use the MII or whatever other
-* interface may be present for setup.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param CfgPtr is the device configuration structure containing required
-*        hardware build data.
-* @param EffectiveAddress is the base address of the device. If address
-*        translation is not utilized, this parameter can be passed in using
-*        CfgPtr->Config.BaseAddress to specify the physical base address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-*
-******************************************************************************/
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
-			   UINTPTR EffectiveAddress)
-{
-	/* Verify arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(CfgPtr != NULL);
-
-	/* Set device base address and ID */
-	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddress;
-
-	/* Set callbacks to an initial stub routine */
-	InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
-	InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
-	InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
-
-	/* Reset the hardware and set default options */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-	XEmacPs_Reset(InstancePtr);
-
-	return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
-* Start the Ethernet controller as follows:
-*   - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
-*   - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
-*   - Start the SG DMA send and receive channels and enable the device
-*     interrupt
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return N/A
-*
-* @note
-* Hardware is configured with scatter-gather DMA, the driver expects to start
-* the scatter-gather channels and expects that the user has previously set up
-* the buffer descriptor lists.
-*
-* This function makes use of internal resources that are shared between the
-* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
-* device options while another is trying to start the device, the user is
-* required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* This function must not be preempted by an interrupt that may service the
-* device.
-*
-******************************************************************************/
-void XEmacPs_Start(XEmacPs *InstancePtr)
-{
-	u32 Reg;
-
-	/* Assert bad arguments and conditions */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Start DMA */
-	/* When starting the DMA channels, both transmit and receive sides
-	 * need an initialized BD list.
-	 */
-	if (InstancePtr->Version == 2) {
-		Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
-		Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_RXQBASE_OFFSET,
-			   InstancePtr->RxBdRing.BaseBdAddr);
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_TXQBASE_OFFSET,
-			   InstancePtr->TxBdRing.BaseBdAddr);
-	}
-
-	/* clear any existed int status */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
-			   XEMACPS_IXR_ALL_MASK);
-
-	/* Enable transmitter if not already enabled */
-	if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-		if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					   XEMACPS_NWCTRL_OFFSET,
-				   Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
-		}
-	}
-
-	/* Enable receiver if not already enabled */
-	if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-		if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					   XEMACPS_NWCTRL_OFFSET,
-				   Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
-		}
-	}
-
-        /* Enable TX and RX interrupts */
-        XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
-	XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
-	(u32)XEMACPS_IXR_TXCOMPL_MASK));
-
-	/* Enable TX Q1 Interrupts */
-	if (InstancePtr->Version > 2)
-		XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
-
-	/* Mark as started */
-	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-
-	return;
-}
-
-
-/*****************************************************************************/
-/**
-* Gracefully stop the Ethernet MAC as follows:
-*   - Disable all interrupts from this device
-*   - Stop DMA channels
-*   - Disable the tansmitter and receiver
-*
-* Device options currently in effect are not changed.
-*
-* This function will disable all interrupts. Default interrupts settings that
-* had been enabled will be restored when XEmacPs_Start() is called.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @note
-* This function makes use of internal resources that are shared between the
-* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
-* setting device options while another is trying to start the device, the user
-* is required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* Stopping the DMA channels causes this function to block until the DMA
-* operation is complete.
-*
-******************************************************************************/
-void XEmacPs_Stop(XEmacPs *InstancePtr)
-{
-	u32 Reg;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Disable all interrupts */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
-			   XEMACPS_IXR_ALL_MASK);
-
-	/* Disable the receiver & transmitter */
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWCTRL_OFFSET);
-	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
-	Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_NWCTRL_OFFSET, Reg);
-
-	/* Mark as stopped */
-	InstancePtr->IsStarted = 0U;
-}
-
-
-/*****************************************************************************/
-/**
-* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
-* transmitter, and the receiver.
-*
-* Steps to reset
-* - Stops transmit and receive channels
-* - Stops DMA
-* - Configure transmit and receive buffer size to default
-* - Clear transmit and receive status register and counters
-* - Clear all interrupt sources
-* - Clear phy (if there is any previously detected) address
-* - Clear MAC addresses (1-4) as well as Type IDs and hash value
-*
-* All options are placed in their default state. Any frames in the
-* descriptor lists will remain in the lists. The side effect of doing
-* this is that after a reset and following a restart of the device, frames
-* were in the list before the reset may be transmitted or received.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the MAC after the reset. Note also that driver statistics
-* are not cleared on reset. It is up to the upper layer software to clear the
-* statistics if needed.
-*
-* When a reset is required, the driver notifies the upper layer software of
-* this need through the ErrorHandler callback and specific status codes.
-* The upper layer software is responsible for calling this Reset function
-* and then re-configuring the device.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-******************************************************************************/
-void XEmacPs_Reset(XEmacPs *InstancePtr)
-{
-	u32 Reg;
-	u8 i;
-	s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Stop the device and reset hardware */
-	XEmacPs_Stop(InstancePtr);
-	InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
-
-	InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
-
-	InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
-
-	InstancePtr->MaxMtuSize = XEMACPS_MTU;
-	InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
-					XEMACPS_TRL_SIZE;
-	InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
-					XEMACPS_HDR_VLAN_SIZE;
-	InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
-
-	/* Setup hardware with default values */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_NWCTRL_OFFSET,
-			(XEMACPS_NWCTRL_STATCLR_MASK |
-			XEMACPS_NWCTRL_MDEN_MASK) &
-			(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
-
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_NWCFG_OFFSET);
-	Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
-
-	Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
-			(u32)XEMACPS_NWCFG_FDEN_MASK |
-			(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCFG_OFFSET, Reg);
-	if (InstancePtr->Version > 2) {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
-			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
-				XEMACPS_NWCFG_DWIDTH_64_MASK));
-	}
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_DMACR_OFFSET,
-			(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
-				(((((u32)XEMACPS_RX_BUF_SIZE %
-				(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
-				(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
-				(u32)(XEMACPS_DMACR_RXBUF_MASK)) |
-				(u32)XEMACPS_DMACR_RXSIZE_MASK |
-				(u32)XEMACPS_DMACR_TXSIZE_MASK);
-
-
-	/* Single bursts */
-	/* FIXME: Why Single bursts? */
-	if (InstancePtr->Version > 2) {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
-			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
-#ifdef __aarch64__
-			(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
-#endif
-			(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
-	}
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_TXSR_OFFSET, 0x0U);
-
-	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
-	if (InstancePtr->Version > 2)
-		XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
-	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_RXSR_OFFSET, 0x0U);
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
-			   XEMACPS_IXR_ALL_MASK);
-
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_ISR_OFFSET);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
-			   Reg);
-
-	XEmacPs_ClearHash(InstancePtr);
-
-	for (i = 1U; i < 5U; i++) {
-		(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
-		(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
-	}
-
-	/* clear all counters */
-	for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
-	     i++) {
-		(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-                                   XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
-	}
-
-	/* Disable the receiver */
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWCTRL_OFFSET);
-	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_NWCTRL_OFFSET, Reg);
-
-	/* Sync default options with hardware but leave receiver and
-         * transmitter disabled. They get enabled with XEmacPs_Start() if
-	 * XEMACPS_TRANSMITTER_ENABLE_OPTION and
-         * XEMACPS_RECEIVER_ENABLE_OPTION are set.
-	 */
-	(void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
-			    ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
-			      (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
-
-	(void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
-}
-
-
-/******************************************************************************/
-/**
- * This is a stub for the asynchronous callbacks. The stub is here in case the
- * upper layer forgot to set the handler(s). On initialization, all handlers are
- * set to this callback. It is considered an error for this handler to be
- * invoked.
- *
- ******************************************************************************/
-void XEmacPs_StubHandler(void)
-{
-	Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-* This function sets the start address of the transmit/receive buffer queue.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @QPtr		Address of the Queue to be written
-* @QueueNum	Buffer Queue Index
-* @Direction	Transmit/Recive
-*
-* @note
-* The buffer queue addresses has to be set before starting the transfer, so
-* this function has to be called in prior to XEmacPs_Start()
-*
-******************************************************************************/
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
-			 u16 Direction)
-{
-	/* Assert bad arguments and conditions */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-        /* If already started, then there is nothing to do */
-        if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
-                return;
-        }
-
-	if (QueueNum == 0x00U) {
-		if (Direction == XEMACPS_SEND) {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_TXQBASE_OFFSET,
-				(QPtr & ULONG64_LO_MASK));
-		} else {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_RXQBASE_OFFSET,
-				(QPtr & ULONG64_LO_MASK));
-		}
-	}
-	 else {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_TXQ1BASE_OFFSET,
-			(QPtr & ULONG64_LO_MASK));
-	}
-#ifdef __aarch64__
-	if (Direction == XEMACPS_SEND) {
-		/* Set the MSB of TX Queue start address */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_MSBBUF_TXQBASE_OFFSET,
-				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
-	} else {
-		/* Set the MSB of RX Queue start address */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_MSBBUF_RXQBASE_OFFSET,
-				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
-	}
-#endif
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h
deleted file mode 100644
index f12092bec..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h
+++ /dev/null
@@ -1,792 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_1
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- *   - Memory mapped access to host interface registers
- *   - Statistics counter registers for RMON/MIB
- *   - API for interrupt driven frame transfers for hardware configured DMA
- *   - Virtual memory support
- *   - Unicast, broadcast, and multicast receive address filtering
- *   - Full and half duplex operation
- *   - Automatic PAD & FCS insertion and stripping
- *   - Flow control
- *   - Support up to four 48bit addresses
- *   - Address checking for four specific 48bit addresses
- *   - VLAN frame support
- *   - Pause frame support
- *   - Large frame support up to 1536 bytes
- *   - Checksum offload
- *
- * <b>Driver Description</b>
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * <b>Initialization & Configuration</b>
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- *   - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress):  Uses a
- *     configuration structure provided by the caller. If running in a system
- *     with address translation, the provided virtual memory base address
- *     replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * <b>Interrupts and Asynchronous Callbacks</b>
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * <b>Virtual Memory</b>
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * <b>DMA</b>
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not suppoted from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a  memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- *   1. Idle. The driver controls BDs in this state.
- *   2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- *      reserve BD(s). Once allocated, the user may setup the BD(s) with
- *      frame buffer address, length, and other attributes. The user controls
- *      BDs in this state.
- *   3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- *      in this state are either waiting to be processed by hardware, are in
- *      process, or have been processed. The DMA engine controls BDs in this
- *      state.
- *   4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- *      user. Once retrieved, the user can examine each BD for the outcome of
- *      the DMA transfer. The user controls BDs in this state. After examining
- *      the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- *      into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * <b>Alignment & Data Cache Restrictions</b>
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- *   - If frame buffers exist in cached memory, then they must be flushed
- *     prior to committing them to hardware.
- *
- * DMA Rx:
- *
- *   - If frame buffers exist in cached memory, then the cache must be
- *     invalidated for the memory region containing the frame prior to data
- *     access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * <b>Buffer Copying</b>
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * <b>Checksum Offloading</b>
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- *    must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- *    encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * <b>PHY Interfaces</b>
- *
- * RGMII 1.3 is the only interface supported.
- *
- * <b>Asserts</b>
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter.  The driver is independent of OS and processor
- * and is intended to be highly portable.  The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy  01/10/10 First release
- * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
- *		       xemacps_bdring.c is modified. Earlier it was checking for
- *		       "BdLimit"(passed argument) number of BDs for finding out
- *		       which BDs are successfully processed. Now one more check
- *		       is added. It looks for BDs till the current BD pointer
- *		       reaches HwTail. By doing this processing time is saved.
- * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
- *		       xemacps_bdring.c is modified. Now start of packet is
- *		       searched for returning the number of BDs processed.
- * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
- *		       registers. Added a new API to set the bust length.
- *		       Added some new hash-defines.
- * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
- *		       Rx errors. Under heavy Rx traffic, there will be a large
- *		       number of errors related to receive buffer not available.
- *		       Because of a HW bug (SI #692601), under such heavy errors,
- *		       the Rx data path can become unresponsive. To reduce the
- *		       probabilities for hitting this HW bug, the SW writes to
- *		       bit 18 to flush a packet from Rx DPRAM immediately. The
- *		       changes for it are done in the function
- *		       XEmacPs_IntrHandler.
- * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
- *		       removed. It is expected that all BDs are allocated in
- *		       from uncached area.
- * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- *				to 0x1fff. This fixes the CR#744902.
- *			  Made changes in example file xemacps_example.h to fix compilation
- *			  issues with iarcc compiler.
- * 2.0   adk  10/12/13 Updated as per the New Tcl API's
- * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
- *		       address in xparameters.h when GMII to RGMII converter
- *		       is present in hw.
- * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- *		       changes.
- * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- *                    1000BASE-X mode export proper values to the xparameters.h
- *                    file. Changes are made in the driver tcl file.
- * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
- *                    configured with PCS/PMA Core. Changes are made in the
- *		       test app tcl(CR:827686).
- * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
- *                     Disable extended mode. Perform all 64 bit changes under
- *                     check for arch64.
- *                     Remove "used bit set" from TX error interrupt masks.
- * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
- *                     there is no error. CR# 869403
- *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * </pre>
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H		/* prevent circular inclusions */
-#define XEMACPS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME     "xemacps"
-#define XEMACPS_DEVICE_DESC     "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION               0x00000001U
-/**< Accept all incoming packets.
- *   This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION             0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- *   This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION                  0x00000004U
-/**< VLAN Rx & Tx frame support.
- *   This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION          0x00000010U
-/**< Enable recognition of flow control frames on Rx
- *   This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION             0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- *   stripped.
- *   This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION            0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- *   This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION           0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- *   set, the MAC will filter frames that have a mismatched type/length field
- *   and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- *   types of frames are encountered. When this option is cleared, the MAC will
- *   allow these types of frames to be received.
- *
- *   This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION    0x00000100U
-/**< Enable the transmitter.
- *   This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION       0x00000200U
-/**< Enable the receiver
- *   This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION             0x00000400U
-/**< Allow reception of the broadcast address
- *   This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION             0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- *   This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION      0x00001000U
-/**< Enable the RX checksum offload
- *   This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION      0x00002000U
-/**< Enable the TX checksum offload
- *   This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION	0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION	0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS                     \
-    ((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
-     (u32)XEMACPS_FCS_INSERT_OPTION |                    \
-     (u32)XEMACPS_FCS_STRIP_OPTION |                     \
-     (u32)XEMACPS_BROADCAST_OPTION |                     \
-     (u32)XEMACPS_LENTYPE_ERR_OPTION |                   \
-     (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |            \
-     (u32)XEMACPS_RECEIVER_ENABLE_OPTION |               \
-     (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION |              \
-     (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR   3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT    MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE   6U	/* size of Ethernet header */
-
-#define XEMACPS_MTU             1500U	/* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO       10240U	/* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE        14U	/* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE   18U	/* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE        4U	/* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE       (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
-        XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE  (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
-        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO  (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
-        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST	0x00000001
-#define XEMACPS_4BYTE_BURST		0x00000004
-#define XEMACPS_8BYTE_BURST		0x00000008
-#define XEMACPS_16BYTE_BURST	0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * paramter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
-				     u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
-	u16 DeviceId;	/**< Unique ID  of device */
-	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
-	XEmacPs_Config Config;	/* Hardware configuration */
-	u32 IsStarted;		/* Device is currently started */
-	u32 IsReady;		/* Device is initialized and ready */
-	u32 Options;		/* Current options word */
-
-	XEmacPs_BdRing TxBdRing;	/* Transmit BD ring */
-	XEmacPs_BdRing RxBdRing;	/* Receive BD ring */
-
-	XEmacPs_Handler SendHandler;
-	XEmacPs_Handler RecvHandler;
-	void *SendRef;
-	void *RecvRef;
-
-	XEmacPs_ErrHandler ErrorHandler;
-	void *ErrorRef;
-	u32 Version;
-	u32 RxBufMask;
-	u32 MaxMtuSize;
-	u32 MaxFrameSize;
-	u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param  InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-*    XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param  InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-*    XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-*        be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-*     void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask)                            \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_IER_OFFSET,                                     \
-		((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-*        be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask)                           \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_IDR_OFFSET,                                     \
-		((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-*        be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-*     void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask)                            \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_INTQ1_IER_OFFSET,                                \
-		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-*        be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask)                           \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_INTQ1_IDR_OFFSET,                               \
-		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr)                              \
-        XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,          \
-        XEMACPS_NWCTRL_OFFSET,                                     \
-        (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,          \
-        XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr)                                     \
-        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,             \
-          XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U     \
-          ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr)                                     \
-        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,              \
-          XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U       \
-          ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
-			   UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
-			 u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
-			void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
-				XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
-		     u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
-		      u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h
deleted file mode 100644
index 52c5f7e7e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h
+++ /dev/null
@@ -1,804 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_1
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * <b>Buffer Descriptors</b>
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements.  See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * <b>Performance</b>
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy  01/10/10 First release
- * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
- *                     and 64-bit changes.
- * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0   hk   02/20/15 Added support for jumbo frames.
- *                     Disable extended mode. Perform all 64 bit changes under
- *                     check for arch64.
- * 3.2   hk   11/18/15 Change BD typedef and number of words.
- *
- * </pre>
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H		/* prevent circular inclusions */
-#define XEMACPS_BD_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include <string.h>
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr)                                  \
-    memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param    BaseAddress is the base address of the BD to read
-* @param    Offset is the word offset to be read
-*
-* @return   The 32-bit value of the field
-*
-* @note
-* C-style signature:
-*    u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset)             \
-	(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param    BaseAddress is the base address of the BD to write
-* @param    Offset is the word offset to be written
-* @param    Data is the 32-bit value to write to the field
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data)              \
-    (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param  BdPtr is the BD pointer to operate on
- * @param  Addr  is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- *    void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,		\
-			(u32)((Addr) & ULONG64_LO_MASK));		\
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET,		\
-	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param  BdPtr is the BD pointer to operate on
- * @param  Addr  is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within recevie BD's address field,
- *         read-modify-write is performed.
- *
- * C-style signature:
- *    void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
-	~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK))));  \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, 	\
-	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
-    ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param  BdPtr is the BD pointer to operate on
- * @param  Data  is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data)                           \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- *    u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr)                                 \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdGetBufAddr(BdPtr)                               \
-    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |		  \
-	(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr)                               \
-    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param  BdPtr is the BD pointer to operate on
- * @param  LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param  BdPtr is the BD pointer to operate on
- * @param  LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- *         XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- *    XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr)                                 \
-    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
-    XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- *         XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- *    RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr)                   \
-    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
-    (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr)                                    \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr)                                   \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
-    XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr)                                 \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
-    ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr)                                 \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |             \
-    XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr)                                  \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
-    XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr)                                 \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
-    XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr)                                  \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr)                                \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &             \
-    ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr)                                   \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
-    XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr)                                 \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
-    XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr)                               \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
-    ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr)                                  \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr)                                 \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr)                                  \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr)                                   \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- *    UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr)                                \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
-    XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- *    UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr)                              \
-    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
-    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
-    ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr)                                 \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr)                             \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr)                               \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr)                                  \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr)                                   \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr)                                   \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr)                                   \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr)                                   \
-    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
-    XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c
deleted file mode 100644
index d837e1df1..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c
+++ /dev/null
@@ -1,1075 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.c
-* @addtogroup emacps_v3_1
-* @{
-*
-* This file implements buffer descriptor ring related functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy  01/10/10 First release
-* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
-*		      Earlier it used to search in "BdLimit" number of BDs to
-*		      know which BDs are processed. Now one more check is
-*		      added. It looks for BDs till the current BD pointer
-*		      reaches HwTail. By doing this processing time is saved.
-* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
-*		      xemacps_bdring.c is modified. Now start of packet is
-*		      searched for returning the number of BDs processed.
-* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
-*		      removed. It is expected that all BDs are allocated in
-*		      from uncached area. Fix for CR #663885.
-* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_cache.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************
- * Compute the virtual address of a descriptor from its physical address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Virtual address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
-    ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Compute the physical address of a descriptor from its virtual address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Physical address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
-    ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
- * to the beginning of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is greater than
- * the high address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- *        final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd)                  \
-    {                                                                   \
-        UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                        \
-                                                                        \
-        Addr += ((RingPtr)->Separation * (NumBd));                        \
-        if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr))  \
-        {                                                               \
-            Addr -= (RingPtr)->Length;                                  \
-        }                                                               \
-                                                                        \
-        (BdPtr) = (XEmacPs_Bd*)(void *)Addr;                                     \
-    }
-
-/****************************************************************************
- * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
- * around to the end of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is less than
- * the base address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- *        final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd)                   \
-    {                                                                   \
-        UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                                  \
-                                                                        \
-        Addr -= ((RingPtr)->Separation * (NumBd));                        \
-        if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr))  \
-        {                                                               \
-            Addr += (RingPtr)->Length;                                  \
-        }                                                               \
-                                                                        \
-        (BdPtr) = (XEmacPs_Bd*)(void*)Addr;                                     \
-    }
-
-
-/************************** Function Prototypes ******************************/
-
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
- * Using a memory segment allocated by the caller, create and setup the BD list
- * for the given DMA channel.
- *
- * @param RingPtr is the instance to be worked on.
- * @param PhysAddr is the physical base address of user memory region.
- * @param VirtAddr is the virtual base address of the user memory region. If
- *        address translation is not being utilized, then VirtAddr should be
- *        equivalent to PhysAddr.
- * @param Alignment governs the byte alignment of individual BDs. This function
- *        will enforce a minimum alignment of 4 bytes with no maximum as long
- *        as it is specified as a power of 2.
- * @param BdCount is the number of BDs to setup in the user memory region. It
- *        is assumed the region is large enough to contain the BDs.
- *
- * @return
- *
- * - XST_SUCCESS if initialization was successful
- * - XST_NO_FEATURE if the provided instance is a non DMA type
- *   channel.
- * - XST_INVALID_PARAM under any of the following conditions:
- *   1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
- *      parameter.
- *   2) Alignment parameter does not meet minimum requirements or is not a
- *      power of 2 value.
- *   3) BdCount is 0.
- * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
- *   over address 0x00000000 in virtual address space.
- *
- * @note
- * Make sure to pass in the right alignment value.
- *****************************************************************************/
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
-			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
-{
-	u32 i;
-	UINTPTR BdVirtAddr;
-	UINTPTR BdPhyAddr;
-	UINTPTR VirtAddrLoc = VirtAddr;
-
-	/* In case there is a failure prior to creating list, make sure the
-	 * following attributes are 0 to prevent calls to other functions
-	 * from doing anything.
-	 */
-	RingPtr->AllCnt = 0U;
-	RingPtr->FreeCnt = 0U;
-	RingPtr->HwCnt = 0U;
-	RingPtr->PreCnt = 0U;
-	RingPtr->PostCnt = 0U;
-
-	/* Make sure Alignment parameter meets minimum requirements */
-	if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
-		return (LONG)(XST_INVALID_PARAM);
-	}
-
-	/* Make sure Alignment is a power of 2 */
-	if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
-		return (LONG)(XST_INVALID_PARAM);
-	}
-
-	/* Make sure PhysAddr and VirtAddr are on same Alignment */
-	if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
-		return (LONG)(XST_INVALID_PARAM);
-	}
-
-	/* Is BdCount reasonable? */
-	if (BdCount == 0x00000000U) {
-		return (LONG)(XST_INVALID_PARAM);
-	}
-
-	/* Figure out how many bytes will be between the start of adjacent BDs */
-	RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
-
-	/* Must make sure the ring doesn't span address 0x00000000. If it does,
-	 * then the next/prev BD traversal macros will fail.
-	 */
-	if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	/* Initial ring setup:
-	 *  - Clear the entire space
-	 *  - Setup each BD's BDA field with the physical address of the next BD
-	 */
-	(void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
-
-	BdVirtAddr = VirtAddrLoc;
-	BdPhyAddr = PhysAddr + RingPtr->Separation;
-	for (i = 1U; i < BdCount; i++) {
-		BdVirtAddr += RingPtr->Separation;
-		BdPhyAddr += RingPtr->Separation;
-	}
-
-	/* Setup and initialize pointers and counters */
-	RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
-	RingPtr->BaseBdAddr = VirtAddrLoc;
-	RingPtr->PhysBaseAddr = PhysAddr;
-	RingPtr->HighBdAddr = BdVirtAddr;
-	RingPtr->Length =
-		((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
-	RingPtr->AllCnt = (u32)BdCount;
-	RingPtr->FreeCnt = (u32)BdCount;
-	RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
-	RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
-
-	return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Clone the given BD into every BD in the list.
- * every field of the source BD is replicated in every BD of the list.
- *
- * This function can be called only when all BDs are in the free group such as
- * they are immediately after initialization with XEmacPs_BdRingCreate().
- * This prevents modification of BDs while they are in use by hardware or the
- * user.
- *
- * @param RingPtr is the pointer of BD ring instance to be worked on.
- * @param SrcBdPtr is the source BD template to be cloned into the list. This
- *        BD will be modified.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- *        which direction.
- *
- * @return
- *   - XST_SUCCESS if the list was modified.
- *   - XST_DMA_SG_NO_LIST if a list has not been created.
- *   - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
- *     hardware or user control.
- *   - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
-			 u8 Direction)
-{
-	u32 i;
-	UINTPTR CurBd;
-
-	/* Can't do this function if there isn't a ring */
-	if (RingPtr->AllCnt == 0x00000000U) {
-		return (LONG)(XST_DMA_SG_NO_LIST);
-	}
-
-	/* Can't do this function with the channel running */
-	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
-		return (LONG)(XST_DEVICE_IS_STARTED);
-	}
-
-	/* Can't do this function with some of the BDs in use */
-	if (RingPtr->FreeCnt != RingPtr->AllCnt) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
-		return (LONG)(XST_INVALID_PARAM);
-	}
-
-	/* Starting from the top of the ring, save BD.Next, overwrite the entire
-	 * BD with the template, then restore BD.Next
-	 */
-	CurBd = RingPtr->BaseBdAddr;
-	for (i = 0U; i < RingPtr->AllCnt; i++) {
-		memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
-	CurBd += RingPtr->Separation;
-	}
-
-	CurBd -= RingPtr->Separation;
-
-	if (Direction == XEMACPS_RECV) {
-		XEmacPs_BdSetRxWrap(CurBd);
-	}
-	else {
-		XEmacPs_BdSetTxWrap(CurBd);
-	}
-
-	return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Reserve locations in the BD list. The set of returned BDs may be modified
- * in preparation for future DMA transaction(s). Once the BDs are ready to be
- * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
- * order which they were allocated here. Example:
- *
- * <pre>
- *        NumBd = 2,
- *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
- *
- *        if (Status != XST_SUCCESS)
- *        {
- *            *Not enough BDs available for the request*
- *        }
- *
- *        CurBd = MyBdSet,
- *        for (i=0; i<NumBd; i++)
- *        {
- *            * Prepare CurBd *.....
- *
- *            * Onto next BD *
- *            CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
- *        }
- *
- *        * Give list to hardware *
- *        Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet),
- * </pre>
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be allocated and given to hardware in the correct sequence:
- * <pre>
- *        * Legal *
- *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
- *
- *        * Legal *
- *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
- *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
- *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
- *
- *        * Not legal *
- *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
- *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
- *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
- * </pre>
- *
- * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
- * of the BD set can be done using XEmacPs_BdRingNext() and
- * XEmacPs_BdRingPrev().
- *
- * @param RingPtr is a pointer to the BD ring instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- *        for modification.
- *
- * @return
- *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
- *     parameter.
- *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- *       call that modifies the BD space. It is the caller's responsibility to
- *       provide a mutual exclusion mechanism.
- *
- * @note Do not modify more BDs than the number requested with the NumBd
- *       parameter. Doing so will lead to data corruption and system
- *       instability.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			 XEmacPs_Bd ** BdSetPtr)
-{
-	LONG Status;
-	/* Enough free BDs available for the request? */
-	if (RingPtr->FreeCnt < NumBd) {
-		Status = (LONG)(XST_FAILURE);
-	} else {
-	/* Set the return argument and move FreeHead forward */
-	*BdSetPtr = RingPtr->FreeHead;
-	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
-	RingPtr->FreeCnt -= NumBd;
-	RingPtr->PreCnt += NumBd;
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
- * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
- * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
- * transferred to hardware with XEmacPs_BdRingToHw().
- *
- * This function helps out in situations when an unrelated error occurs after
- * BDs have been allocated but before they have been given to hardware.
- * An example of this type of error would be an OS running out of resources.
- *
- * This function is not the same as XEmacPs_BdRingFree(). The Free function
- * returns BDs to the free list after they have been processed by hardware,
- * while UnAlloc returns them before being processed by hardware.
- *
- * There are two scenarios where this function can be used. Full UnAlloc or
- * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
- *
- * <pre>
- *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
- *        ...
- *    if (Error)
- *    {
- *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
- *    }
- * </pre>
- *
- * A partial UnAlloc means some of the BDs Alloc'd will be returned:
- *
- * <pre>
- *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
- *    BdsLeft = 10,
- *    CurBdPtr = BdPtr,
- *
- *    while (BdsLeft)
- *    {
- *       if (Error)
- *       {
- *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
- *       }
- *
- *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
- *       BdsLeft--,
- *    }
- * </pre>
- *
- * A partial UnAlloc must include the last BD in the list that was Alloc'd.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- *        for modification.
- *
- * @return
- *   - XST_SUCCESS if the BDs were unallocated.
- *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
- *     the preprocessing state.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- *       call that modifies the BD space. It is the caller's responsibility to
- *       provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			   XEmacPs_Bd * BdSetPtr)
-{
-	LONG Status;
-	(void *)BdSetPtr;
-	Xil_AssertNonvoid(RingPtr != NULL);
-	Xil_AssertNonvoid(BdSetPtr != NULL);
-
-	/* Enough BDs in the free state for the request? */
-	if (RingPtr->PreCnt < NumBd) {
-		Status = (LONG)(XST_FAILURE);
-	} else {
-	/* Set the return argument and move FreeHead backward */
-		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
-	RingPtr->FreeCnt += NumBd;
-	RingPtr->PreCnt -= NumBd;
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Enqueue a set of BDs to hardware that were previously allocated by
- * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
- * under hardware control. Any changes made to these BDs after this point will
- * corrupt the BD list leading to data corruption and system instability.
- *
- * The set will be rejected if the last BD of the set does not mark the end of
- * a packet (see XEmacPs_BdSetLast()).
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs in the set.
- * @param BdSetPtr is the first BD of the set to commit to hardware.
- *
- * @return
- *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
- *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
- *     did not have its "last" bit set.
- *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- *     XEmacPs_BdRingAlloc().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- *       call that modifies the BD space. It is the caller's responsibility to
- *       provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr)
-{
-	XEmacPs_Bd *CurBdPtr;
-	u32 i;
-	LONG Status;
-	/* if no bds to process, simply return. */
-	if (0U == NumBd){
-		Status = (LONG)(XST_SUCCESS);
-	} else {
-	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
-	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
-			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
-		} else {
-	CurBdPtr = BdSetPtr;
-			for (i = 0U; i < NumBd; i++) {
-				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
-	}
-	/* Adjust ring pointers & counters */
-	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
-	RingPtr->PreCnt -= NumBd;
-	RingPtr->HwTail = CurBdPtr;
-	RingPtr->HwCnt += NumBd;
-
-			Status = (LONG)(XST_SUCCESS);
-		}
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- * <pre>
- *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
- *        if (NumBd == 0)
- *        {
- *           * hardware has nothing ready for us yet*
- *        }
- *
- *        CurBd = MyBdSet,
- *        for (i=0; i<NumBd; i++)
- *        {
- *           * Examine CurBd for post processing *.....
- *
- *           * Onto next BD *
- *           CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
- *           }
- *
- *           XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  *Return list*
- *        }
- * </pre>
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- * <pre>
- *        * Legal *
- *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- *
- *        * Legal *
- *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- *
- *        * Not legal *
- *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- * </pre>
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- *        for examination.
- *
- * @return
- *   The number of BDs processed by hardware. A value of 0 indicates that no
- *   data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- *       call that modifies the BD space. It is the caller's responsibility to
- *       provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr)
-{
-	XEmacPs_Bd *CurBdPtr;
-	u32 BdStr = 0U;
-	u32 BdCount;
-	u32 BdPartialCount;
-	u32 Sop = 0U;
-	u32 Status;
-	u32 BdLimitLoc = BdLimit;
-	CurBdPtr = RingPtr->HwHead;
-	BdCount = 0U;
-	BdPartialCount = 0U;
-
-	/* If no BDs in work group, then there's nothing to search */
-	if (RingPtr->HwCnt == 0x00000000U) {
-		*BdSetPtr = NULL;
-		Status = 0U;
-	} else {
-
-		if (BdLimitLoc > RingPtr->HwCnt){
-			BdLimitLoc = RingPtr->HwCnt;
-	}
-	/* Starting at HwHead, keep moving forward in the list until:
-	 *  - A BD is encountered with its new/used bit set which means
-	 *    hardware has not completed processing of that BD.
-	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
-	 *  - The number of requested BDs has been processed
-	 */
-		while (BdCount < BdLimitLoc) {
-		/* Read the status */
-			if(CurBdPtr != NULL){
-		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
-			}
-
-			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
-				Sop = 1U;
-			}
-			if (Sop == 0x00000001U) {
-			BdCount++;
-			BdPartialCount++;
-		}
-
-		/* hardware has processed this BD so check the "last" bit.
-		 * If it is clear, then there are more BDs for the current
-		 * packet. Keep a count of these partial packet BDs.
-		 */
-			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
-				Sop = 0U;
-				BdPartialCount = 0U;
-		}
-
-		/* Move on to next BD in work group */
-		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
-	}
-
-	/* Subtract off any partial packet BDs found */
-        BdCount -= BdPartialCount;
-
-	/* If BdCount is non-zero then BDs were found to return. Set return
-	 * parameters, update pointers and counters, return success
-	 */
-		if (BdCount > 0x00000000U) {
-		*BdSetPtr = RingPtr->HwHead;
-		RingPtr->HwCnt -= BdCount;
-		RingPtr->PostCnt += BdCount;
-		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
-			Status = (BdCount);
-		} else {
-			*BdSetPtr = NULL;
-			Status = 0U;
-	}
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- * <pre>
- *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
- *
- *        if (NumBd == 0)
- *        {
- *           *hardware has nothing ready for us yet*
- *        }
- *
- *        CurBd = MyBdSet,
- *        for (i=0; i<NumBd; i++)
- *        {
- *           * Examine CurBd for post processing *.....
- *
- *           * Onto next BD *
- *           CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
- *           }
- *
- *           XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  * Return list *
- *        }
- * </pre>
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- * <pre>
- *        * Legal *
- *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- *
- *        * Legal *
- *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- *
- *        * Not legal *
- *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
- *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- * </pre>
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- *        for examination.
- *
- * @return
- *   The number of BDs processed by hardware. A value of 0 indicates that no
- *   data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- *       call that modifies the BD space. It is the caller's responsibility to
- *       provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr)
-{
-	XEmacPs_Bd *CurBdPtr;
-	u32 BdStr = 0U;
-	u32 BdCount;
-	u32 BdPartialCount;
-	u32 Status;
-
-	CurBdPtr = RingPtr->HwHead;
-	BdCount = 0U;
-	BdPartialCount = 0U;
-
-	/* If no BDs in work group, then there's nothing to search */
-	if (RingPtr->HwCnt == 0x00000000U) {
-		*BdSetPtr = NULL;
-		Status = 0U;
-	} else {
-
-	/* Starting at HwHead, keep moving forward in the list until:
-	 *  - A BD is encountered with its new/used bit set which means
-	 *    hardware has completed processing of that BD.
-	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
-	 *  - The number of requested BDs has been processed
-	 */
-	while (BdCount < BdLimit) {
-
-		/* Read the status */
-			if(CurBdPtr!=NULL){
-		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
-			}
-			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
-			break;
-		}
-
-		BdCount++;
-
-		/* hardware has processed this BD so check the "last" bit. If
-                 * it is clear, then there are more BDs for the current packet.
-                 * Keep a count of these partial packet BDs.
-		 */
-			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
-				BdPartialCount = 0U;
-			} else {
-			BdPartialCount++;
-		}
-
-		/* Move on to next BD in work group */
-		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
-	}
-
-	/* Subtract off any partial packet BDs found */
-	BdCount -= BdPartialCount;
-
-	/* If BdCount is non-zero then BDs were found to return. Set return
-	 * parameters, update pointers and counters, return success
-	 */
-		if (BdCount > 0x00000000U) {
-		*BdSetPtr = RingPtr->HwHead;
-		RingPtr->HwCnt -= BdCount;
-		RingPtr->PostCnt += BdCount;
-		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
-			Status = (BdCount);
-	}
-	else {
-		*BdSetPtr = NULL;
-			Status = 0U;
-	}
-}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Frees a set of BDs that had been previously retrieved with
- * XEmacPs_BdRingFromHw().
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to free.
- * @param BdSetPtr is the head of a list of BDs returned by
- * XEmacPs_BdRingFromHw().
- *
- * @return
- *   - XST_SUCCESS if the set of BDs was freed.
- *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- *     XEmacPs_BdRingFromHw().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- *       call that modifies the BD space. It is the caller's responsibility to
- *       provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr)
-{
-	LONG Status;
-	/* if no bds to process, simply return. */
-	if (0x00000000U == NumBd){
-		Status = (LONG)(XST_SUCCESS);
-	} else {
-	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
-	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
-			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
-		} else {
-	/* Update pointers and counters */
-	RingPtr->FreeCnt += NumBd;
-	RingPtr->PostCnt -= NumBd;
-	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
-			Status = (LONG)(XST_SUCCESS);
-		}
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Check the internal data structures of the BD ring for the provided channel.
- * The following checks are made:
- *
- *   - Is the BD ring linked correctly in physical address space.
- *   - Do the internal pointers point to BDs in the ring.
- *   - Do the internal counters add up.
- *
- * The channel should be stopped prior to calling this function.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- *        which direction.
- *
- * @return
- *   - XST_SUCCESS if the set of BDs was freed.
- *   - XST_DMA_SG_NO_LIST if the list has not been created.
- *   - XST_IS_STARTED if the channel is not stopped.
- *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
- *     structures. If this value is returned, the channel should be reset to
- *     avoid data corruption or system instability.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- *       call that modifies the BD space. It is the caller's responsibility to
- *       provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
-{
-	UINTPTR AddrV, AddrP;
-	u32 i;
-
-	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
-		return (LONG)(XST_INVALID_PARAM);
-	}
-
-	/* Is the list created */
-	if (RingPtr->AllCnt == 0x00000000U) {
-		return (LONG)(XST_DMA_SG_NO_LIST);
-	}
-
-	/* Can't check if channel is running */
-	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
-		return (LONG)(XST_IS_STARTED);
-	}
-
-	/* RunState doesn't make sense */
-	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	/* Verify internal pointers point to correct memory space */
-	AddrV = (UINTPTR) RingPtr->FreeHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	AddrV = (UINTPTR) RingPtr->PreHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	AddrV = (UINTPTR) RingPtr->HwHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	AddrV = (UINTPTR) RingPtr->HwTail;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	AddrV = (UINTPTR) RingPtr->PostHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	/* Verify internal counters add up */
-	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
-	     RingPtr->PostCnt) != RingPtr->AllCnt) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
-
-	/* Verify BDs are linked correctly */
-	AddrV = RingPtr->BaseBdAddr;
-	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
-
-	for (i = 1U; i < RingPtr->AllCnt; i++) {
-		/* Check BDA for this BD. It should point to next physical addr */
-		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
-			return (LONG)(XST_DMA_SG_LIST_ERROR);
-		}
-
-		/* Move on to next BD */
-		AddrV += RingPtr->Separation;
-		AddrP += RingPtr->Separation;
-	}
-
-	/* Last BD should have wrap bit set */
-	if (XEMACPS_SEND == Direction) {
-		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
-			return (LONG)(XST_DMA_SG_LIST_ERROR);
-		}
-	}
-	else {			/* XEMACPS_RECV */
-		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
-			return (LONG)(XST_DMA_SG_LIST_ERROR);
-		}
-	}
-
-	/* No problems found */
-	return (LONG)(XST_SUCCESS);
-}
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
-{
-    u32 DataValueRx;
-	u32 *TempPtr;
-
-	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
-	TempPtr = (u32 *)BdPtr;
-	if(TempPtr != NULL) {
-		DataValueRx = *TempPtr;
-		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
-		*TempPtr = DataValueRx;
-	}
-}
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param  BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
-{
-    u32 DataValueTx;
-	u32 *TempPtr;
-
-	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
-	TempPtr = (u32 *)BdPtr;
-	if(TempPtr != NULL) {
-		DataValueTx = *TempPtr;
-		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
-		*TempPtr = DataValueTx;
-	}
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h
deleted file mode 100644
index de78cf28f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.h
-* @addtogroup emacps_v3_1
-* @{
-*
-* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
-* DMA functionalities.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy  01/10/10 First release
-* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
-#define XEMACPS_BDRING_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
-	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
-	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
-	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
-	u32 Length;	 /**< Total size of ring in bytes */
-	u32 RunState;	 /**< Flag to indicate DMA is started */
-	u32 Separation;	 /**< Number of bytes between the starting address
-                                  of adjacent BDs */
-	XEmacPs_Bd *FreeHead;
-			     /**< First BD in the free group */
-	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
-	XEmacPs_Bd *HwHead; /**< First BD in the work group */
-	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
-	XEmacPs_Bd *PostHead;
-			     /**< First BD in the post-work group */
-	XEmacPs_Bd *BdaRestart;
-			     /**< BDA to load when channel is started */
-
-	u32 HwCnt;	     /**< Number of BDs in work group */
-	u32 PreCnt;     /**< Number of BDs in pre-work group */
-	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
-	u32 PostCnt;    /**< Number of BDs in post-work group */
-	u32 AllCnt;     /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
-    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-*        parameter must be a power of 2 to get an accurate calculation (32, 64,
-*        128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-*         given memory constraints.
-*
-* @note
-* C-style signature:
-*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
-    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param  RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param  RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param  RingPtr is the DMA channel to operate on.
-* @param  BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-*                                      XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
-    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
-    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
-    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param  RingPtr is the DMA channel to operate on.
-* @param  BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-*                                      XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
-    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
-    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
-    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
-			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
-			 u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			 XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			   XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c
deleted file mode 100644
index f52451a8c..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c
+++ /dev/null
@@ -1,1174 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xemacps_control.c
-* @addtogroup emacps_v3_1
-* @{
- *
- * Functions in this file implement general purpose command and control related
- * functionality. See xemacps.h for a detailed description of the driver.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy  01/10/10 First release
- * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
- *					   register. Added a new API for setting the BURST length
- *					   in DMACR register.
- * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
- * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0   hk   02/20/15 Added support for jumbo frames.
- * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * </pre>
- *****************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Set the MAC address for this driver/device.  The address is a 48-bit value.
- * The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- * @param Index is a index to which MAC (1-4) address.
- *
- * @return
- * - XST_SUCCESS if the MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- *****************************************************************************/
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
-	u32 MacAddr;
-	u8 *Aptr = (u8 *)(void *)AddressPtr;
-	u8 IndexLoc = Index;
-	LONG Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(Aptr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
-	/* Be sure device has been stopped */
-	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
-		Status = (LONG)(XST_DEVICE_IS_STARTED);
-	}
-	else{
-	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
-		IndexLoc--;
-
-	/* Set the MAC bits [31:0] in BOT */
-		MacAddr = *(Aptr);
-		MacAddr |= ((u32)(*(Aptr+1)) << 8U);
-		MacAddr |= ((u32)(*(Aptr+2)) << 16U);
-		MacAddr |= ((u32)(*(Aptr+3)) << 24U);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
-	/* There are reserved bits in TOP so don't affect them */
-	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
-
-		MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
-
-	/* Set MAC bits [47:32] in TOP */
-		MacAddr |= (u32)(*(Aptr+4));
-		MacAddr |= (u32)(*(Aptr+5)) << 8U;
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Get the MAC address for this driver/device.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is an output parameter, and is a pointer to a buffer into
- *        which the current MAC address will be copied.
- * @param Index is a index to which MAC (1-4) address.
- *
- *****************************************************************************/
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
-	u32 MacAddr;
-	u8 *Aptr = (u8 *)(void *)AddressPtr;
-	u8 IndexLoc = Index;
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(Aptr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
-	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
-	IndexLoc--;
-
-	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
-	*Aptr = (u8) MacAddr;
-	*(Aptr+1) = (u8) (MacAddr >> 8U);
-	*(Aptr+2) = (u8) (MacAddr >> 16U);
-	*(Aptr+3) = (u8) (MacAddr >> 24U);
-
-	/* Read MAC bits [47:32] in TOP */
-	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
-	*(Aptr+4) = (u8) MacAddr;
-	*(Aptr+5) = (u8) (MacAddr >> 8U);
-}
-
-
-/*****************************************************************************/
-/**
- * Set 48-bit MAC addresses in hash table.
- * The device must be stopped before calling this function.
- *
- * The hash address register is 64 bits long and takes up two locations in
- * the memory map. The least significant bits are stored in hash register
- * bottom and the most significant bits in hash register top.
- *
- * The unicast hash enable and the multicast hash enable bits in the network
- * configuration register enable the reception of hash matched frames. The
- * destination address is reduced to a 6 bit index into the 64 bit hash
- * register using the following hash function. The hash function is an XOR
- * of every sixth bit of the destination address.
- *
- * <pre>
- * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
- * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
- * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
- * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
- * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
- * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
- * </pre>
- *
- * da[0] represents the least significant bit of the first byte received,
- * that is, the multicast/unicast indicator, and da[47] represents the most
- * significant bit of the last byte received.
- *
- * If the hash index points to a bit that is set in the hash register then
- * the frame will be matched according to whether the frame is multicast
- * or unicast.
- *
- * A multicast match will be signaled if the multicast hash enable bit is
- * set, da[0] is logic 1 and the hash index points to a bit set in the hash
- * register.
- *
- * A unicast match will be signaled if the unicast hash enable bit is set,
- * da[0] is logic 0 and the hash index points to a bit set in the hash
- * register.
- *
- * To receive all multicast frames, the hash register should be set with
- * all ones and the multicast hash enable bit should be set in the network
- * configuration register.
- *
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- *
- * @return
- * - XST_SUCCESS if the HASH MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
- *   requirement after calculation
- *
- * @note
- * Having Aptr be unsigned type prevents the following operations from sign
- * extending.
- *****************************************************************************/
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
-{
-	u32 HashAddr;
-	u8 *Aptr = (u8 *)(void *)AddressPtr;
-	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
-	u32 Result;
-	LONG Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(AddressPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Be sure device has been stopped */
-	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
-		Status = (LONG)(XST_DEVICE_IS_STARTED);
-	} else {
-		Temp1 = (*(Aptr+0)) & 0x3FU;
-		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
-
-		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
-		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
-		Temp5 =   (*(Aptr+3)) & 0x3FU;
-		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
-		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
-		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
-
-		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
-				(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
-
-		if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
-			Status = (LONG)(XST_INVALID_PARAM);
-		} else {
-
-			if (Result < (u32)32) {
-		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_HASHL_OFFSET);
-				HashAddr |= (u32)(0x00000001U << Result);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_HASHL_OFFSET, HashAddr);
-	} else {
-		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_HASHH_OFFSET);
-				HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_HASHH_OFFSET, HashAddr);
-	}
-			Status = (LONG)(XST_SUCCESS);
-		}
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
- * Delete 48-bit MAC addresses in hash table.
- * The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- *
- * @return
- * - XST_SUCCESS if the HASH MAC address was deleted successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
- *   requirement after calculation
- *
- * @note
- * Having Aptr be unsigned type prevents the following operations from sign
- * extending.
- *****************************************************************************/
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
-{
-	u32 HashAddr;
-	u8 *Aptr = (u8 *)(void *)AddressPtr;
-	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
-	u32 Result;
-	LONG Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(Aptr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Be sure device has been stopped */
-	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
-		Status = (LONG)(XST_DEVICE_IS_STARTED);
-	} else {
-		Temp1 = (*(Aptr+0)) & 0x3FU;
-		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
-		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
-		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
-		Temp5 =   (*(Aptr+3)) & 0x3FU;
-		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
-		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
-		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
-
-		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
-					(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
-
-		if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
-			Status =  (LONG)(XST_INVALID_PARAM);
-		} else {
-			if (Result < (u32)32) {
-		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_HASHL_OFFSET);
-				HashAddr &= (u32)(~(0x00000001U << Result));
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_HASHL_OFFSET, HashAddr);
-	} else {
-		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_HASHH_OFFSET);
-				HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_HASHH_OFFSET, HashAddr);
-	}
-			Status = (LONG)(XST_SUCCESS);
-		}
-	}
-	return Status;
-}
-/*****************************************************************************/
-/**
- * Clear the Hash registers for the mac address pointed by AddressPtr.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- *
- *****************************************************************************/
-void XEmacPs_ClearHash(XEmacPs *InstancePtr)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_HASHL_OFFSET, 0x0U);
-
-	/* write bits [63:32] in TOP */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_HASHH_OFFSET, 0x0U);
-}
-
-
-/*****************************************************************************/
-/**
- * Get the Hash address for this driver/device.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is an output parameter, and is a pointer to a buffer into
- *        which the current HASH MAC address will be copied.
- *
- *****************************************************************************/
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
-{
-	u32 *Aptr = (u32 *)(void *)AddressPtr;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(AddressPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_HASHL_OFFSET);
-
-	/* Read Hash bits [63:32] in TOP */
-	*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_HASHH_OFFSET);
-}
-
-
-/*****************************************************************************/
-/**
- * Set the Type ID match for this driver/device.  The register is a 32-bit
- * value. The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Id_Check is type ID to be configured.
- * @param Index is a index to which Type ID (1-4).
- *
- * @return
- * - XST_SUCCESS if the MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- *****************************************************************************/
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
-{
-	u8 IndexLoc = Index;
-	LONG Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
-
-	/* Be sure device has been stopped */
-	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
-		Status = (LONG)(XST_DEVICE_IS_STARTED);
-	} else {
-
-	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
-		IndexLoc--;
-
-	/* Set the ID bits in MATCHx register */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
-
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
- * Set options for the driver/device. The driver should be stopped with
- * XEmacPs_Stop() before changing options.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Options are the options to set. Multiple options can be set by OR'ing
- *        XTE_*_OPTIONS constants together. Options not specified are not
- *        affected.
- *
- * @return
- * - XST_SUCCESS if the options were set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- * @note
- * See xemacps.h for a description of the available options.
- *
- *****************************************************************************/
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
-{
-	u32 Reg;		/* Generic register contents */
-	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
-	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
-	LONG Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Be sure device has been stopped */
-	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
-		Status = (LONG)(XST_DEVICE_IS_STARTED);
-	} else {
-
-	/* Many of these options will change the NET_CONFIG registers.
-	 * To reduce the amount of IO to the device, group these options here
-	 * and change them all at once.
-	 */
-
-	/* Grab current register contents */
-	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				      XEMACPS_NWCFG_OFFSET);
-	RegNewNetCfg = RegNetCfg;
-
-	/*
-	 * It is configured to max 1536.
-	 */
-		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
-	}
-
-	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
-		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
-	}
-
-	/* Turn on FCS stripping on receive packets */
-		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
-	}
-
-	/* Turn on length/type field checking on receive packets */
-		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
-			RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
-	}
-
-	/* Turn on flow control */
-		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
-	}
-
-	/* Turn on promiscuous frame filtering (all frames are received) */
-		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
-	}
-
-	/* Allow broadcast address reception */
-		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
-	}
-
-	/* Allow multicast address filtering */
-		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
-	}
-
-	/* enable RX checksum offload */
-		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
-	}
-
-	/* Enable jumbo frames */
-	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
-		(InstancePtr->Version > 2)) {
-		RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				      XEMACPS_DMACR_OFFSET);
-		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
-		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
-			(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
-			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
-			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
-			(u32)(XEMACPS_DMACR_RXBUF_MASK));
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_DMACR_OFFSET, Reg);
-		InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
-		InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
-					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
-		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
-					XEMACPS_HDR_VLAN_SIZE;
-		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
-	}
-
-	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
-		(InstancePtr->Version > 2)) {
-		RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
-						XEMACPS_NWCFG_PCSSEL_MASK);
-	}
-
-	/* Officially change the NET_CONFIG registers if it needs to be
-	 * modified.
-	 */
-	if (RegNetCfg != RegNewNetCfg) {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
-	}
-
-	/* Enable TX checksum offload */
-		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_DMACR_OFFSET);
-		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					 XEMACPS_DMACR_OFFSET, Reg);
-	}
-
-	/* Enable transmitter */
-		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_NWCTRL_OFFSET, Reg);
-	}
-
-	/* Enable receiver */
-		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_NWCTRL_OFFSET, Reg);
-	}
-
-	/* The remaining options not handled here are managed elsewhere in the
-	 * driver. No register modifications are needed at this time. Reflecting
-	 * the option in InstancePtr->Options is good enough for now.
-	 */
-
-	/* Set options word to its new value */
-	InstancePtr->Options |= Options;
-
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Clear options for the driver/device
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Options are the options to clear. Multiple options can be cleared by
- *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
- *        are not affected.
- *
- * @return
- * - XST_SUCCESS if the options were set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- * @note
- * See xemacps.h for a description of the available options.
- *
- *****************************************************************************/
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
-{
-	u32 Reg;		/* Generic */
-	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
-	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
-	LONG Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Be sure device has been stopped */
-	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
-		Status = (LONG)(XST_DEVICE_IS_STARTED);
-	} else {
-
-	/* Many of these options will change the NET_CONFIG registers.
-	 * To reduce the amount of IO to the device, group these options here
-	 * and change them all at once.
-	 */
-
-	/* Grab current register contents */
-	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				      XEMACPS_NWCFG_OFFSET);
-	RegNewNetCfg = RegNetCfg;
-
-	/* There is only RX configuration!?
-	 * It is configured in two different length, upto 1536 and 10240 bytes
-	 */
-		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
-	}
-
-	/* Turn off VLAN packet only */
-		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
-	}
-
-	/* Turn off FCS stripping on receive packets */
-		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
-	}
-
-	/* Turn off length/type field checking on receive packets */
-		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
-	}
-
-	/* Turn off flow control */
-		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
-	}
-
-	/* Turn off promiscuous frame filtering (all frames are received) */
-		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
-	}
-
-	/* Disallow broadcast address filtering => broadcast reception */
-		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
-		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
-	}
-
-	/* Disallow multicast address filtering */
-		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
-	}
-
-	/* Disable RX checksum offload */
-		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
-			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
-	}
-
-	/* Disable jumbo frames */
-	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
-		(InstancePtr->Version > 2)) {
-		RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				      XEMACPS_DMACR_OFFSET);
-		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
-		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
-			(((((u32)XEMACPS_RX_BUF_SIZE %
-			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
-			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
-			(u32)(XEMACPS_DMACR_RXBUF_MASK));
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_DMACR_OFFSET, Reg);
-		InstancePtr->MaxMtuSize = XEMACPS_MTU;
-		InstancePtr->MaxFrameSize = XEMACPS_MTU +
-					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
-		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
-					XEMACPS_HDR_VLAN_SIZE;
-		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
-	}
-
-	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
-		(InstancePtr->Version > 2)) {
-		RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
-						XEMACPS_NWCFG_PCSSEL_MASK));
-	}
-
-	/* Officially change the NET_CONFIG registers if it needs to be
-	 * modified.
-	 */
-	if (RegNetCfg != RegNewNetCfg) {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
-	}
-
-	/* Disable TX checksum offload */
-		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_DMACR_OFFSET);
-			Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					 XEMACPS_DMACR_OFFSET, Reg);
-	}
-
-	/* Disable transmitter */
-		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-			Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_NWCTRL_OFFSET, Reg);
-	}
-
-	/* Disable receiver */
-		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-			Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_NWCTRL_OFFSET, Reg);
-	}
-
-	/* The remaining options not handled here are managed elsewhere in the
-	 * driver. No register modifications are needed at this time. Reflecting
-	 * option in InstancePtr->Options is good enough for now.
-	 */
-
-	/* Set options word to its new value */
-	InstancePtr->Options &= ~Options;
-
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Get current option settings
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- *
- * @return
- * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
- * as a set opion.
- *
- * @note
- * See xemacps.h for a description of the available options.
- *
- *****************************************************************************/
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
-{
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	return (InstancePtr->Options);
-}
-
-
-/*****************************************************************************/
-/**
- * Send a pause packet
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- *
- * @return
- * - XST_SUCCESS if pause frame transmission was initiated
- * - XST_DEVICE_IS_STOPPED if the device has not been started.
- *
- *****************************************************************************/
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
-{
-	u32 Reg;
-	LONG Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* Make sure device is ready for this operation */
-	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
-		Status = (LONG)(XST_DEVICE_IS_STOPPED);
-	} else {
-	/* Send flow control frame */
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWCTRL_OFFSET);
-	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_NWCTRL_OFFSET, Reg);
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
- * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
- * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
- *
- * @param InstancePtr references the TEMAC channel on which to operate.
- *
- * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
- *         megabits per second.
- *
- * @note
- *
- *****************************************************************************/
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
-{
-	u32 Reg;
-	u16 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_NWCFG_OFFSET);
-
-	if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
-		Status = (u16)(1000);
-	} else {
-		if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
-			Status = (u16)(100);
-		} else {
-			Status = (u16)(10);
-		}
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
- * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
- * link speed.
- *
- * @param InstancePtr references the TEMAC channel on which to operate.
- * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
- *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
- *
- * @note
- *
- *****************************************************************************/
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
-{
-        u32 Reg;
-	u16 Status;
-        Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-    Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
-
-        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_NWCFG_OFFSET);
-	Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
-
-	switch (Speed) {
-		case (u16)10:
-				Status = 0U;
-                break;
-
-        case (u16)100:
-			Status = 0U;
-                Reg |= XEMACPS_NWCFG_100_MASK;
-                break;
-
-        case (u16)1000:
-			Status = 0U;
-                Reg |= XEMACPS_NWCFG_1000_MASK;
-                break;
-
-        default:
-			Status = 1U;
-                break;
-    }
-	if(Status == (u16)1){
-                return;
-        }
-
-        /* Set register and return */
-        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-                XEMACPS_NWCFG_OFFSET, Reg);
-}
-
-
-/*****************************************************************************/
-/**
- * Set the MDIO clock divisor.
- *
- * Calculating the divisor:
- *
- * <pre>
- *              f[HOSTCLK]
- *   f[MDC] = -----------------
- *            (1 + Divisor) * 2
- * </pre>
- *
- * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
- * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
- * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
- * access. Here is the table to show values to generate MDC,
- *
- * <pre>
- * 000 : divide pclk by   8 (pclk up to  20 MHz)
- * 001 : divide pclk by  16 (pclk up to  40 MHz)
- * 010 : divide pclk by  32 (pclk up to  80 MHz)
- * 011 : divide pclk by  48 (pclk up to 120 MHz)
- * 100 : divide pclk by  64 (pclk up to 160 MHz)
- * 101 : divide pclk by  96 (pclk up to 240 MHz)
- * 110 : divide pclk by 128 (pclk up to 320 MHz)
- * 111 : divide pclk by 224 (pclk up to 540 MHz)
- * </pre>
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
- *
- *****************************************************************************/
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
-{
-	u32 Reg;
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
-
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWCFG_OFFSET);
-	/* clear these three bits, could be done with mask */
-	Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
-
-	Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
-
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_NWCFG_OFFSET, Reg);
-}
-
-
-/*****************************************************************************/
-/**
-* Read the current value of the PHY register indicated by the PhyAddress and
-* the RegisterNum parameters. The MAC provides the driver with the ability to
-* talk to a PHY that adheres to the Media Independent Interface (MII) as
-* defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be read (supports multiple
-*        PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-*        to read
-* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
-*        which the current value of the register will be copied.
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was read from successfully
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the read is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
-		     u32 RegisterNum, u16 *PhyDataPtr)
-{
-	u32 Mgtcr;
-	volatile u32 Ipisr;
-	u32 IpReadTemp;
-	LONG Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-
-	/* Make sure no other PHY operation is currently in progress */
-	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWSR_OFFSET) &
-	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
-		Status = (LONG)(XST_EMAC_MII_BUSY);
-	} else {
-
-	/* Construct Mgtcr mask for the operation */
-	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
-			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
-			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
-
-	/* Write Mgtcr and wait for completion */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
-	do {
-		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XEMACPS_NWSR_OFFSET);
-			IpReadTemp = Ipisr;
-		} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
-	/* Read data */
-		*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_PHYMNTNC_OFFSET);
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
-* Write data to the specified PHY register. The Ethernet driver does not
-* require the device to be stopped before writing to the PHY.  Although it is
-* probably a good idea to stop the device, it is the responsibility of the
-* application to deem this necessary. The MAC provides the driver with the
-* ability to talk to a PHY that adheres to the Media Independent Interface
-* (MII) as defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be written (supports multiple
-*        PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-*        to write
-* @param PhyData is the 16-bit value that will be written to the register
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
-*   status from the MAC on a write, the user should read the PHY to verify the
-*   write was successful.
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the write is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
-		      u32 RegisterNum, u16 PhyData)
-{
-	u32 Mgtcr;
-	volatile u32 Ipisr;
-	u32 IpWriteTemp;
-	LONG Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-
-	/* Make sure no other PHY operation is currently in progress */
-	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWSR_OFFSET) &
-	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
-		Status = (LONG)(XST_EMAC_MII_BUSY);
-	} else {
-	/* Construct Mgtcr mask for the operation */
-	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
-			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
-			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
-
-	/* Write Mgtcr and wait for completion */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
-	do {
-		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XEMACPS_NWSR_OFFSET);
-				IpWriteTemp = Ipisr;
-		} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
-		Status = (LONG)(XST_SUCCESS);
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-* API to update the Burst length in the DMACR register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param BLength is the length in bytes for the dma burst.
-*
-* @return None
-*
-******************************************************************************/
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
-{
-	u32 Reg;
-	u32 RegUpdateVal;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
-					(BLength == XEMACPS_4BYTE_BURST) ||
-					(BLength == XEMACPS_8BYTE_BURST) ||
-					(BLength == XEMACPS_16BYTE_BURST));
-
-	switch (BLength) {
-		case XEMACPS_SINGLE_BURST:
-			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
-			break;
-
-		case XEMACPS_4BYTE_BURST:
-			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
-			break;
-
-		case XEMACPS_8BYTE_BURST:
-			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
-			break;
-
-		case XEMACPS_16BYTE_BURST:
-			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
-			break;
-
-		default:
-			RegUpdateVal = 0x00000000U;
-			break;
-	}
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-						XEMACPS_DMACR_OFFSET);
-
-	Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
-	Reg |= RegUpdateVal;
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
-																	Reg);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c
deleted file mode 100644
index 6a7cc7866..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xemacps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XEmacPs_Config XEmacPs_ConfigTable[] =
-{
-	{
-		XPAR_PSU_ETHERNET_3_DEVICE_ID,
-		XPAR_PSU_ETHERNET_3_BASEADDR
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c
deleted file mode 100644
index daba38397..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.c
-* @addtogroup emacps_v3_1
-* @{
-*
-* This file contains the implementation of the ethernet interface reset sequence
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.05a kpc  28/06/13 First release
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps_hw.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given emacps interface by
-* configuring the appropriate control bits in the emacps specifc registers.
-* the emacps reset squence involves the following steps
-*	Disable all the interuupts
-*	Clear the status registers
-*	Disable Rx and Tx engines
-*	Update the Tx and Rx descriptor queue registers with reset values
-*	Update the other relevant control registers with reset value
-*
-* @param   BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* emacps controller
-******************************************************************************/
-void XEmacPs_ResetHw(u32 BaseAddr)
-{
-	u32 RegVal;
-
-	/* Disable the interrupts  */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
-
-	/* Stop transmission,disable loopback and Stop tx and Rx engines */
-	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
-	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
-				(u32)XEMACPS_NWCTRL_RXEN_MASK|
-				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
-				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
-	/* Clear the statistic registers, flush the packets in DPRAM*/
-	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
-				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
-	/* Clear the interrupt status */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
-	/* Clear the tx status */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
-									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
-									(u32)XEMACPS_TXSR_TXGO_MASK));
-	/* Clear the rx status */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
-								XEMACPS_RXSR_FRAMERX_MASK);
-	/* Clear the tx base address */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
-	/* Clear the rx base address */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
-	/* Update the network config register with reset value */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
-	/* Update the hash address registers with reset value */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h
deleted file mode 100644
index 953cc6265..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.h
-* @addtogroup emacps_v3_1
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
-* High-level driver functions are defined in xemacps.h.
-*
-* @note
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy  01/10/10 First release.
-* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-*					  to 0x1fff. This fixes the CR#744902.
-* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
-* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0  hk   03/18/15 Added support for jumbo frames.
-*                    Remove "used bit set" from TX error interrupt masks.
-* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
-#define XEMACPS_HW_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
-                                           supported */
-#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
-                                           on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
-                                           on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
-                                           options that impose alignment
-                                           restrictions on the buffer data on
-                                           the local bus */
-
-/** @name Direction identifiers
- *
- *  These are used by several functions and callbacks that need
- *  to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND        1U	      /**< send direction */
-#define XEMACPS_RECV        2U	      /**< receive direction */
-/*@}*/
-
-/**  @name MDC clock division
- *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
-	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
-                                       bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
-                                       unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
-                                                      reg */
-#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
-                                                      reg */
-
-#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
-                                                      transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
-                                                      Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
-                                                      Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
-                                                      Counter */
-#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
-                                                      Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
-                                                      Frames Transmitted
-                                                      counter */
-#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
-                                                      Frames Transmitted
-                                                      counter*/
-#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
-                                                      Frames transmitted
-                                                      counter */
-#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
-                                                      Frames transmitted
-                                                      counter */
-#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
-                                                      Frames transmitted
-                                                      counter */
-#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
-                                                      1519 byte Frames
-                                                      transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
-                                                      counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
-                                                      Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
-                                                      Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
-                                                      Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
-                                                      Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
-                                                      Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
-                                                      Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
-                                                      Low */
-#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
-                                                      High */
-
-#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
-                                                      Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
-                                                      Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
-                                                      Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
-                                                      Received Counter */
-#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
-                                                      Received Counter */
-#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
-                                                      Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
-                                                      Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
-                                                      Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
-                                                      Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
-                                                      Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
-                                                      Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
-                                                      Counter */
-#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
-                                                      Counter */
-#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
-                                                      Counter */
-#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
-                                                      Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
-                                                      Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
-                                                      Counter */
-#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
-                                                      Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
-                                                      Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
-                                                      Counter */
-#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
-						      offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
-						      adjustment counter */
-#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
-						      increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
-						      counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
-						      nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
-						      counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
-						      nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
-						      second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
-						      nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
-						      second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
-						      nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
-							reg */
-#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
-							reg */
-#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
-							reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
-							reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
-							reg */
-#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
-							reg */
-#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
-							reg */
-#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
-							reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
-							Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
-                                                         pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
-                                                         after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
-                                                         stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
-                                                         registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
-                                                         registers */
-#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
-                                                        non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK     0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
-                                                        FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
-                                                        offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
-                                                        Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
-                                                        received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK      0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
-                                                        frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
-                                                        frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
-                                                        frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
-                                                        broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
-                                                        frames */
-#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
-                                                      bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
-													size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
-												size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
-													    checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
-                                                       mid frame */
-#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
-                                       (u32)XEMACPS_TXSR_URUN_MASK | \
-                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
-                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
-                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
-                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
-                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
-                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
-					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
-#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
-						     transmitted */
-#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
-#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
-						*/
-#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
-#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
-#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
-#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
-#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
-                                                     zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
-                                                     no buffers*/
-#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
-                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
-                                     (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
-                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
-                                     (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process.  After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
-                                                      matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32  Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param    BaseAddress is the base address of the device
-* @param    RegOffset is the register offset to be read
-*
-* @return   The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
-    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param    BaseAddress is the base address of the device
-* @param    RegOffset is the register offset to be written
-* @param    Data is the 32-bit value to write to the register
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-*         u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
-    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
-  }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c
deleted file mode 100644
index 59636c4ef..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_intr.c
-* @addtogroup emacps_v3_1
-* @{
-*
-* Functions in this file implement general purpose interrupt processing related
-* functionality. See xemacps.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy  01/10/10 First release
-* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
-*		      Rx errors. Under heavy Rx traffic, there will be a large
-*		      number of errors related to receive buffer not available.
-*		      Because of a HW bug (SI #692601), under such heavy errors,
-*		      the Rx data path can become unresponsive. To reduce the
-*		      probabilities for hitting this HW bug, the SW writes to
-*		      bit 18 to flush a packet from Rx DPRAM immediately. The
-*		      changes for it are done in the function
-*		      XEmacPs_IntrHandler.
-* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
-*		       and 64-bit changes.
-* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1   hk   07/27/15 Do not call error handler with '0' error code when
-*                     there is no error. CR# 869403
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Install an asynchronious handler function for the given HandlerType:
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param HandlerType indicates what interrupt handler type is.
- *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
- *        XEMACPS_HANDLER_ERROR.
- * @param FuncPointer is the pointer to the callback function
- * @param CallBackRef is the upper layer callback reference passed back when
- *        when the callback function is invoked.
- *
- * @return
- *
- * None.
- *
- * @note
- * There is no assert on the CallBackRef since the driver doesn't know what
- * it is.
- *
- *****************************************************************************/
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
-			void *FuncPointer, void *CallBackRef)
-{
-	LONG Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(FuncPointer != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	switch (HandlerType) {
-	case XEMACPS_HANDLER_DMASEND:
-		Status = (LONG)(XST_SUCCESS);
-		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
-		InstancePtr->SendRef = CallBackRef;
-		break;
-	case XEMACPS_HANDLER_DMARECV:
-		Status = (LONG)(XST_SUCCESS);
-		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
-		InstancePtr->RecvRef = CallBackRef;
-		break;
-	case XEMACPS_HANDLER_ERROR:
-		Status = (LONG)(XST_SUCCESS);
-		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
-		InstancePtr->ErrorRef = CallBackRef;
-		break;
-	default:
-		Status = (LONG)(XST_INVALID_PARAM);
-		break;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-* Master interrupt handler for EMAC driver. This routine will query the
-* status of the device, bump statistics, and invoke user callbacks.
-*
-* This routine must be connected to an interrupt controller using OS/BSP
-* specific methods.
-*
-* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
-*        interrupt.
-*
-******************************************************************************/
-void XEmacPs_IntrHandler(void *XEmacPsPtr)
-{
-	u32 RegISR;
-	u32 RegSR;
-	u32 RegCtrl;
-	u32 RegQ1ISR = 0U;
-	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/* This ISR will try to handle as many interrupts as it can in a single
-	 * call. However, in most of the places where the user's error handler
-         * is called, this ISR exits because it is expected that the user will
-         * reset the device in nearly all instances.
-	 */
-	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_ISR_OFFSET);
-
-	/* Read Transmit Q1 ISR */
-
-	if (InstancePtr->Version > 2)
-		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_INTQ1_STS_OFFSET);
-
-	/* Clear the interrupt status register */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
-			   RegISR);
-
-	/* Receive complete interrupt */
-	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
-		/* Clear RX status register RX complete indication but preserve
-		 * error bits if there is any */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_RXSR_OFFSET,
-				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
-				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
-		InstancePtr->RecvHandler(InstancePtr->RecvRef);
-	}
-
-	/* Transmit Q1 complete interrupt */
-	if ((InstancePtr->Version > 2) &&
-			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
-		/* Clear TX status register TX complete indication but preserve
-		 * error bits if there is any */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_INTQ1_STS_OFFSET,
-				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_TXSR_OFFSET,
-				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
-				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
-		InstancePtr->SendHandler(InstancePtr->SendRef);
-	}
-
-	/* Transmit complete interrupt */
-	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
-		/* Clear TX status register TX complete indication but preserve
-		 * error bits if there is any */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_TXSR_OFFSET,
-				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
-				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
-		InstancePtr->SendHandler(InstancePtr->SendRef);
-	}
-
-	/* Receive error conditions interrupt */
-	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
-		/* Clear RX status register */
-		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XEMACPS_RXSR_OFFSET);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_RXSR_OFFSET, RegSR);
-
-		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
-		 * register to flush a packet out of Rx SRAM upon
-		 * an error for receive buffer not available. */
-		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
-			RegCtrl =
-			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-						XEMACPS_NWCTRL_OFFSET);
-			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET, RegCtrl);
-		}
-
-		if(RegSR != 0) {
-			InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
-						XEMACPS_RECV, RegSR);
-		}
-	}
-
-        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
-         * will be asserted the same time.
-         * Have to distinguish this bit to handle the real error condition.
-         */
-	/* Transmit Q1 error conditions interrupt */
-        if ((InstancePtr->Version > 2) &&
-			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
-            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
-			/* Clear Interrupt Q1 status register */
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
-			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
-					  RegQ1ISR);
-	   }
-
-	/* Transmit error conditions interrupt */
-        if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
-            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
-		/* Clear TX status register */
-		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XEMACPS_TXSR_OFFSET);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_TXSR_OFFSET, RegSR);
-		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
-					  RegSR);
-	}
-
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c
deleted file mode 100644
index 1bc5b3b19..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_sinit.c
-* @addtogroup emacps_v3_1
-* @{
-*
-* This file contains lookup method by device ID when success, it returns
-* pointer to config table to be used to initialize the device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy  01/10/10 New
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/*************************** Variable Definitions *****************************/
-extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID.  The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return
-* A pointer to the configuration table entry corresponding to the given
-* device ID, or NULL if no match is found.
-*
-******************************************************************************/
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
-{
-	XEmacPs_Config *CfgPtr = NULL;
-	u32 i;
-
-	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
-		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
-			CfgPtr = &XEmacPs_ConfigTable[i];
-			break;
-		}
-	}
-
-	return (XEmacPs_Config *)(CfgPtr);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile
new file mode 100644
index 000000000..7002e6223
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xemacps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling emacps"
+
+xemacps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xemacps_includes
+
+xemacps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c
new file mode 100644
index 000000000..26df03c3d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c
@@ -0,0 +1,489 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* The XEmacPs driver. Functions in this file are the minimum required functions
+* for this driver. See xemacps.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+*		      64-bit changes.
+* 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
+*                    Disable extended mode. Perform all 64 bit changes under
+*                    check for arch64.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XEmacPs_StubHandler(void);	/* Default handler routine */
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* Initialize a specific XEmacPs instance/driver. The initialization entails:
+* - Initialize fields of the XEmacPs instance structure
+* - Reset hardware and apply default options
+* - Configure the DMA channels
+*
+* The PHY is setup independently from the device. Use the MII or whatever other
+* interface may be present for setup.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param CfgPtr is the device configuration structure containing required
+*        hardware build data.
+* @param EffectiveAddress is the base address of the device. If address
+*        translation is not utilized, this parameter can be passed in using
+*        CfgPtr->Config.BaseAddress to specify the physical base address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+******************************************************************************/
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
+			   UINTPTR EffectiveAddress)
+{
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+
+	/* Set device base address and ID */
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddress;
+
+	/* Set callbacks to an initial stub routine */
+	InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
+	InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
+	InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
+
+	/* Reset the hardware and set default options */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	XEmacPs_Reset(InstancePtr);
+
+	return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+* Start the Ethernet controller as follows:
+*   - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
+*   - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
+*   - Start the SG DMA send and receive channels and enable the device
+*     interrupt
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return N/A
+*
+* @note
+* Hardware is configured with scatter-gather DMA, the driver expects to start
+* the scatter-gather channels and expects that the user has previously set up
+* the buffer descriptor lists.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
+* device options while another is trying to start the device, the user is
+* required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* This function must not be preempted by an interrupt that may service the
+* device.
+*
+******************************************************************************/
+void XEmacPs_Start(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+
+	/* Assert bad arguments and conditions */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Start DMA */
+	/* When starting the DMA channels, both transmit and receive sides
+	 * need an initialized BD list.
+	 */
+	if (InstancePtr->Version == 2) {
+		Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+		Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_RXQBASE_OFFSET,
+			   InstancePtr->RxBdRing.BaseBdAddr);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_TXQBASE_OFFSET,
+			   InstancePtr->TxBdRing.BaseBdAddr);
+	}
+
+	/* clear any existed int status */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   XEMACPS_IXR_ALL_MASK);
+
+	/* Enable transmitter if not already enabled */
+	if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XEMACPS_NWCTRL_OFFSET,
+				   Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
+		}
+	}
+
+	/* Enable receiver if not already enabled */
+	if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XEMACPS_NWCTRL_OFFSET,
+				   Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
+		}
+	}
+
+        /* Enable TX and RX interrupts */
+        XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
+	XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
+	(u32)XEMACPS_IXR_TXCOMPL_MASK));
+
+	/* Enable TX Q1 Interrupts */
+	if (InstancePtr->Version > 2)
+		XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+
+	/* Mark as started */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+	return;
+}
+
+
+/*****************************************************************************/
+/**
+* Gracefully stop the Ethernet MAC as follows:
+*   - Disable all interrupts from this device
+*   - Stop DMA channels
+*   - Disable the tansmitter and receiver
+*
+* Device options currently in effect are not changed.
+*
+* This function will disable all interrupts. Default interrupts settings that
+* had been enabled will be restored when XEmacPs_Start() is called.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @note
+* This function makes use of internal resources that are shared between the
+* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
+* setting device options while another is trying to start the device, the user
+* is required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* Stopping the DMA channels causes this function to block until the DMA
+* operation is complete.
+*
+******************************************************************************/
+void XEmacPs_Stop(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Disable all interrupts */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+			   XEMACPS_IXR_ALL_MASK);
+
+	/* Disable the receiver & transmitter */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+	Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+
+	/* Mark as stopped */
+	InstancePtr->IsStarted = 0U;
+}
+
+
+/*****************************************************************************/
+/**
+* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
+* transmitter, and the receiver.
+*
+* Steps to reset
+* - Stops transmit and receive channels
+* - Stops DMA
+* - Configure transmit and receive buffer size to default
+* - Clear transmit and receive status register and counters
+* - Clear all interrupt sources
+* - Clear phy (if there is any previously detected) address
+* - Clear MAC addresses (1-4) as well as Type IDs and hash value
+*
+* All options are placed in their default state. Any frames in the
+* descriptor lists will remain in the lists. The side effect of doing
+* this is that after a reset and following a restart of the device, frames
+* were in the list before the reset may be transmitted or received.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required, the driver notifies the upper layer software of
+* this need through the ErrorHandler callback and specific status codes.
+* The upper layer software is responsible for calling this Reset function
+* and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+******************************************************************************/
+void XEmacPs_Reset(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u8 i;
+	s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Stop the device and reset hardware */
+	XEmacPs_Stop(InstancePtr);
+	InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
+
+	InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
+
+	InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
+
+	InstancePtr->MaxMtuSize = XEMACPS_MTU;
+	InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
+					XEMACPS_TRL_SIZE;
+	InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+	InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+
+	/* Setup hardware with default values */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCTRL_OFFSET,
+			(XEMACPS_NWCTRL_STATCLR_MASK |
+			XEMACPS_NWCTRL_MDEN_MASK) &
+			(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
+
+	Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
+			(u32)XEMACPS_NWCFG_FDEN_MASK |
+			(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCFG_OFFSET, Reg);
+	if (InstancePtr->Version > 2) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
+				XEMACPS_NWCFG_DWIDTH_64_MASK));
+	}
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET,
+			(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+				(((((u32)XEMACPS_RX_BUF_SIZE %
+				(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+				(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+				(u32)(XEMACPS_DMACR_RXBUF_MASK)) |
+				(u32)XEMACPS_DMACR_RXSIZE_MASK |
+				(u32)XEMACPS_DMACR_TXSIZE_MASK);
+
+
+	/* Single bursts */
+	/* FIXME: Why Single bursts? */
+	if (InstancePtr->Version > 2) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
+#ifdef __aarch64__
+			(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
+#endif
+			(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
+	}
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_TXSR_OFFSET, 0x0U);
+
+	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
+	if (InstancePtr->Version > 2)
+		XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_RXSR_OFFSET, 0x0U);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+			   XEMACPS_IXR_ALL_MASK);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_ISR_OFFSET);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   Reg);
+
+	XEmacPs_ClearHash(InstancePtr);
+
+	for (i = 1U; i < 5U; i++) {
+		(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
+		(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
+	}
+
+	/* clear all counters */
+	for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
+	     i++) {
+		(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                                   XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
+	}
+
+	/* Disable the receiver */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+
+	/* Sync default options with hardware but leave receiver and
+         * transmitter disabled. They get enabled with XEmacPs_Start() if
+	 * XEMACPS_TRANSMITTER_ENABLE_OPTION and
+         * XEMACPS_RECEIVER_ENABLE_OPTION are set.
+	 */
+	(void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
+			    ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
+			      (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
+
+	(void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
+}
+
+
+/******************************************************************************/
+/**
+ * This is a stub for the asynchronous callbacks. The stub is here in case the
+ * upper layer forgot to set the handler(s). On initialization, all handlers are
+ * set to this callback. It is considered an error for this handler to be
+ * invoked.
+ *
+ ******************************************************************************/
+void XEmacPs_StubHandler(void)
+{
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+* This function sets the start address of the transmit/receive buffer queue.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @QPtr		Address of the Queue to be written
+* @QueueNum	Buffer Queue Index
+* @Direction	Transmit/Recive
+*
+* @note
+* The buffer queue addresses has to be set before starting the transfer, so
+* this function has to be called in prior to XEmacPs_Start()
+*
+******************************************************************************/
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+			 u16 Direction)
+{
+	/* Assert bad arguments and conditions */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+        /* If already started, then there is nothing to do */
+        if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+                return;
+        }
+
+	if (QueueNum == 0x00U) {
+		if (Direction == XEMACPS_SEND) {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_TXQBASE_OFFSET,
+				(QPtr & ULONG64_LO_MASK));
+		} else {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_RXQBASE_OFFSET,
+				(QPtr & ULONG64_LO_MASK));
+		}
+	}
+	 else {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_TXQ1BASE_OFFSET,
+			(QPtr & ULONG64_LO_MASK));
+	}
+#ifdef __aarch64__
+	if (Direction == XEMACPS_SEND) {
+		/* Set the MSB of TX Queue start address */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_MSBBUF_TXQBASE_OFFSET,
+				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+	} else {
+		/* Set the MSB of RX Queue start address */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_MSBBUF_RXQBASE_OFFSET,
+				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+	}
+#endif
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h
new file mode 100644
index 000000000..f12092bec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h
@@ -0,0 +1,792 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_1
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ *   - Memory mapped access to host interface registers
+ *   - Statistics counter registers for RMON/MIB
+ *   - API for interrupt driven frame transfers for hardware configured DMA
+ *   - Virtual memory support
+ *   - Unicast, broadcast, and multicast receive address filtering
+ *   - Full and half duplex operation
+ *   - Automatic PAD & FCS insertion and stripping
+ *   - Flow control
+ *   - Support up to four 48bit addresses
+ *   - Address checking for four specific 48bit addresses
+ *   - VLAN frame support
+ *   - Pause frame support
+ *   - Large frame support up to 1536 bytes
+ *   - Checksum offload
+ *
+ * <b>Driver Description</b>
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * <b>Initialization & Configuration</b>
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ *   - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress):  Uses a
+ *     configuration structure provided by the caller. If running in a system
+ *     with address translation, the provided virtual memory base address
+ *     replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * <b>Interrupts and Asynchronous Callbacks</b>
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * <b>Virtual Memory</b>
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * <b>DMA</b>
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a  memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ *   1. Idle. The driver controls BDs in this state.
+ *   2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ *      reserve BD(s). Once allocated, the user may setup the BD(s) with
+ *      frame buffer address, length, and other attributes. The user controls
+ *      BDs in this state.
+ *   3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ *      in this state are either waiting to be processed by hardware, are in
+ *      process, or have been processed. The DMA engine controls BDs in this
+ *      state.
+ *   4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ *      user. Once retrieved, the user can examine each BD for the outcome of
+ *      the DMA transfer. The user controls BDs in this state. After examining
+ *      the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ *      into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * <b>Alignment & Data Cache Restrictions</b>
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ *   - If frame buffers exist in cached memory, then they must be flushed
+ *     prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ *   - If frame buffers exist in cached memory, then the cache must be
+ *     invalidated for the memory region containing the frame prior to data
+ *     access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * <b>Buffer Copying</b>
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * <b>Checksum Offloading</b>
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ *    must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ *    encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * <b>PHY Interfaces</b>
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * <b>Asserts</b>
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter.  The driver is independent of OS and processor
+ * and is intended to be highly portable.  The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * </pre>
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H		/* prevent circular inclusions */
+#define XEMACPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME     "xemacps"
+#define XEMACPS_DEVICE_DESC     "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION               0x00000001U
+/**< Accept all incoming packets.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION             0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION                  0x00000004U
+/**< VLAN Rx & Tx frame support.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION          0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION             0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ *   stripped.
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION            0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION           0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ *   set, the MAC will filter frames that have a mismatched type/length field
+ *   and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ *   types of frames are encountered. When this option is cleared, the MAC will
+ *   allow these types of frames to be received.
+ *
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION    0x00000100U
+/**< Enable the transmitter.
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION       0x00000200U
+/**< Enable the receiver
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION             0x00000400U
+/**< Allow reception of the broadcast address
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION             0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ *   This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION      0x00001000U
+/**< Enable the RX checksum offload
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION      0x00002000U
+/**< Enable the TX checksum offload
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION	0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION	0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS                     \
+    ((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
+     (u32)XEMACPS_FCS_INSERT_OPTION |                    \
+     (u32)XEMACPS_FCS_STRIP_OPTION |                     \
+     (u32)XEMACPS_BROADCAST_OPTION |                     \
+     (u32)XEMACPS_LENTYPE_ERR_OPTION |                   \
+     (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |            \
+     (u32)XEMACPS_RECEIVER_ENABLE_OPTION |               \
+     (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION |              \
+     (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR   3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT    MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE   6U	/* size of Ethernet header */
+
+#define XEMACPS_MTU             1500U	/* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO       10240U	/* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE        14U	/* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE   18U	/* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE        4U	/* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE       (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+        XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE  (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO  (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST	0x00000001
+#define XEMACPS_4BYTE_BURST		0x00000004
+#define XEMACPS_8BYTE_BURST		0x00000008
+#define XEMACPS_16BYTE_BURST	0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+				     u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID  of device */
+	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+	XEmacPs_Config Config;	/* Hardware configuration */
+	u32 IsStarted;		/* Device is currently started */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Current options word */
+
+	XEmacPs_BdRing TxBdRing;	/* Transmit BD ring */
+	XEmacPs_BdRing RxBdRing;	/* Receive BD ring */
+
+	XEmacPs_Handler SendHandler;
+	XEmacPs_Handler RecvHandler;
+	void *SendRef;
+	void *RecvRef;
+
+	XEmacPs_ErrHandler ErrorHandler;
+	void *ErrorRef;
+	u32 Version;
+	u32 RxBufMask;
+	u32 MaxMtuSize;
+	u32 MaxFrameSize;
+	u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param  InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+*    XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param  InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+*    XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask)                            \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_IER_OFFSET,                                     \
+		((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask)                           \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_IDR_OFFSET,                                     \
+		((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask)                            \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_INTQ1_IER_OFFSET,                                \
+		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask)                           \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_INTQ1_IDR_OFFSET,                               \
+		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr)                              \
+        XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,          \
+        XEMACPS_NWCTRL_OFFSET,                                     \
+        (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,          \
+        XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr)                                     \
+        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,             \
+          XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U     \
+          ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr)                                     \
+        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,              \
+          XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U       \
+          ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+			   UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+			 u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+				XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h
new file mode 100644
index 000000000..52c5f7e7e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h
@@ -0,0 +1,804 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_1
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * <b>Buffer Descriptors</b>
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements.  See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * <b>Performance</b>
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H		/* prevent circular inclusions */
+#define XEMACPS_BD_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include <string.h>
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr)                                  \
+    memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param    BaseAddress is the base address of the BD to read
+* @param    Offset is the word offset to be read
+*
+* @return   The 32-bit value of the field
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset)             \
+	(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param    BaseAddress is the base address of the BD to write
+* @param    Offset is the word offset to be written
+* @param    Data is the 32-bit value to write to the field
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data)              \
+    (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Addr  is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ *    void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,		\
+			(u32)((Addr) & ULONG64_LO_MASK));		\
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET,		\
+	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Addr  is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ *         read-modify-write is performed.
+ *
+ * C-style signature:
+ *    void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+	~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK))));  \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, 	\
+	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Data  is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data)                           \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ *    u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr)                                 \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdGetBufAddr(BdPtr)                               \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |		  \
+	(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr)                               \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ *         XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ *    XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr)                                 \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
+    XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ *         XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ *    RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr)                   \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
+    (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr)                                    \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr)                                   \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |             \
+    XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr)                                \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &             \
+    ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr)                               \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr)                                 \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr)                                \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr)                              \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr)                                 \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr)                             \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr)                               \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c
new file mode 100644
index 000000000..d837e1df1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c
@@ -0,0 +1,1075 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file implements buffer descriptor ring related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+*		      Earlier it used to search in "BdLimit" number of BDs to
+*		      know which BDs are processed. Now one more check is
+*		      added. It looks for BDs till the current BD pointer
+*		      reaches HwTail. By doing this processing time is saved.
+* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+*		      xemacps_bdring.c is modified. Now start of packet is
+*		      searched for returning the number of BDs processed.
+* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+*		      removed. It is expected that all BDs are allocated in
+*		      from uncached area. Fix for CR #663885.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_cache.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************
+ * Compute the virtual address of a descriptor from its physical address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Virtual address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
+    ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Compute the physical address of a descriptor from its virtual address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Physical address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
+    ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
+ * to the beginning of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is greater than
+ * the high address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ *        final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd)                  \
+    {                                                                   \
+        UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                        \
+                                                                        \
+        Addr += ((RingPtr)->Separation * (NumBd));                        \
+        if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr))  \
+        {                                                               \
+            Addr -= (RingPtr)->Length;                                  \
+        }                                                               \
+                                                                        \
+        (BdPtr) = (XEmacPs_Bd*)(void *)Addr;                                     \
+    }
+
+/****************************************************************************
+ * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
+ * around to the end of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is less than
+ * the base address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ *        final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd)                   \
+    {                                                                   \
+        UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                                  \
+                                                                        \
+        Addr -= ((RingPtr)->Separation * (NumBd));                        \
+        if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr))  \
+        {                                                               \
+            Addr += (RingPtr)->Length;                                  \
+        }                                                               \
+                                                                        \
+        (BdPtr) = (XEmacPs_Bd*)(void*)Addr;                                     \
+    }
+
+
+/************************** Function Prototypes ******************************/
+
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * Using a memory segment allocated by the caller, create and setup the BD list
+ * for the given DMA channel.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param PhysAddr is the physical base address of user memory region.
+ * @param VirtAddr is the virtual base address of the user memory region. If
+ *        address translation is not being utilized, then VirtAddr should be
+ *        equivalent to PhysAddr.
+ * @param Alignment governs the byte alignment of individual BDs. This function
+ *        will enforce a minimum alignment of 4 bytes with no maximum as long
+ *        as it is specified as a power of 2.
+ * @param BdCount is the number of BDs to setup in the user memory region. It
+ *        is assumed the region is large enough to contain the BDs.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if initialization was successful
+ * - XST_NO_FEATURE if the provided instance is a non DMA type
+ *   channel.
+ * - XST_INVALID_PARAM under any of the following conditions:
+ *   1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
+ *      parameter.
+ *   2) Alignment parameter does not meet minimum requirements or is not a
+ *      power of 2 value.
+ *   3) BdCount is 0.
+ * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
+ *   over address 0x00000000 in virtual address space.
+ *
+ * @note
+ * Make sure to pass in the right alignment value.
+ *****************************************************************************/
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
+{
+	u32 i;
+	UINTPTR BdVirtAddr;
+	UINTPTR BdPhyAddr;
+	UINTPTR VirtAddrLoc = VirtAddr;
+
+	/* In case there is a failure prior to creating list, make sure the
+	 * following attributes are 0 to prevent calls to other functions
+	 * from doing anything.
+	 */
+	RingPtr->AllCnt = 0U;
+	RingPtr->FreeCnt = 0U;
+	RingPtr->HwCnt = 0U;
+	RingPtr->PreCnt = 0U;
+	RingPtr->PostCnt = 0U;
+
+	/* Make sure Alignment parameter meets minimum requirements */
+	if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Make sure Alignment is a power of 2 */
+	if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Make sure PhysAddr and VirtAddr are on same Alignment */
+	if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is BdCount reasonable? */
+	if (BdCount == 0x00000000U) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Figure out how many bytes will be between the start of adjacent BDs */
+	RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
+
+	/* Must make sure the ring doesn't span address 0x00000000. If it does,
+	 * then the next/prev BD traversal macros will fail.
+	 */
+	if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Initial ring setup:
+	 *  - Clear the entire space
+	 *  - Setup each BD's BDA field with the physical address of the next BD
+	 */
+	(void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
+
+	BdVirtAddr = VirtAddrLoc;
+	BdPhyAddr = PhysAddr + RingPtr->Separation;
+	for (i = 1U; i < BdCount; i++) {
+		BdVirtAddr += RingPtr->Separation;
+		BdPhyAddr += RingPtr->Separation;
+	}
+
+	/* Setup and initialize pointers and counters */
+	RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
+	RingPtr->BaseBdAddr = VirtAddrLoc;
+	RingPtr->PhysBaseAddr = PhysAddr;
+	RingPtr->HighBdAddr = BdVirtAddr;
+	RingPtr->Length =
+		((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
+	RingPtr->AllCnt = (u32)BdCount;
+	RingPtr->FreeCnt = (u32)BdCount;
+	RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
+	RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
+
+	return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clone the given BD into every BD in the list.
+ * every field of the source BD is replicated in every BD of the list.
+ *
+ * This function can be called only when all BDs are in the free group such as
+ * they are immediately after initialization with XEmacPs_BdRingCreate().
+ * This prevents modification of BDs while they are in use by hardware or the
+ * user.
+ *
+ * @param RingPtr is the pointer of BD ring instance to be worked on.
+ * @param SrcBdPtr is the source BD template to be cloned into the list. This
+ *        BD will be modified.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the list was modified.
+ *   - XST_DMA_SG_NO_LIST if a list has not been created.
+ *   - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
+ *     hardware or user control.
+ *   - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction)
+{
+	u32 i;
+	UINTPTR CurBd;
+
+	/* Can't do this function if there isn't a ring */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't do this function with the channel running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_DEVICE_IS_STARTED);
+	}
+
+	/* Can't do this function with some of the BDs in use */
+	if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Starting from the top of the ring, save BD.Next, overwrite the entire
+	 * BD with the template, then restore BD.Next
+	 */
+	CurBd = RingPtr->BaseBdAddr;
+	for (i = 0U; i < RingPtr->AllCnt; i++) {
+		memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+	CurBd += RingPtr->Separation;
+	}
+
+	CurBd -= RingPtr->Separation;
+
+	if (Direction == XEMACPS_RECV) {
+		XEmacPs_BdSetRxWrap(CurBd);
+	}
+	else {
+		XEmacPs_BdSetTxWrap(CurBd);
+	}
+
+	return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Reserve locations in the BD list. The set of returned BDs may be modified
+ * in preparation for future DMA transaction(s). Once the BDs are ready to be
+ * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
+ * order which they were allocated here. Example:
+ *
+ * <pre>
+ *        NumBd = 2,
+ *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            *Not enough BDs available for the request*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *            * Prepare CurBd *.....
+ *
+ *            * Onto next BD *
+ *            CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ *        }
+ *
+ *        * Give list to hardware *
+ *        Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet),
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * <pre>
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ *     parameter.
+ *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ *       parameter. Doing so will lead to data corruption and system
+ *       instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr)
+{
+	LONG Status;
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ *    }
+ * </pre>
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *    BdsLeft = 10,
+ *    CurBdPtr = BdPtr,
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
+ *       }
+ *
+ *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
+ *       BdsLeft--,
+ *    }
+ * </pre>
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the BDs were unallocated.
+ *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ *     the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	(void *)BdSetPtr;
+	Xil_AssertNonvoid(RingPtr != NULL);
+	Xil_AssertNonvoid(BdSetPtr != NULL);
+
+	/* Enough BDs in the free state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead backward */
+		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ *     did not have its "last" bit set.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 i;
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	CurBdPtr = BdSetPtr;
+			for (i = 0U; i < NumBd; i++) {
+				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+	}
+	/* Adjust ring pointers & counters */
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * <pre>
+ *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ *        if (NumBd == 0)
+ *        {
+ *           * hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *           * Examine CurBd for post processing *.....
+ *
+ *           * Onto next BD *
+ *           CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ *           }
+ *
+ *           XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  *Return list*
+ *        }
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * <pre>
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Sop = 0U;
+	u32 Status;
+	u32 BdLimitLoc = BdLimit;
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+		if (BdLimitLoc > RingPtr->HwCnt){
+			BdLimitLoc = RingPtr->HwCnt;
+	}
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has not completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+		while (BdCount < BdLimitLoc) {
+		/* Read the status */
+			if(CurBdPtr != NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+
+			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+				Sop = 1U;
+			}
+			if (Sop == 0x00000001U) {
+			BdCount++;
+			BdPartialCount++;
+		}
+
+		/* hardware has processed this BD so check the "last" bit.
+		 * If it is clear, then there are more BDs for the current
+		 * packet. Keep a count of these partial packet BDs.
+		 */
+			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+				Sop = 0U;
+				BdPartialCount = 0U;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+        BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+		} else {
+			*BdSetPtr = NULL;
+			Status = 0U;
+	}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * <pre>
+ *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           *hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *           * Examine CurBd for post processing *.....
+ *
+ *           * Onto next BD *
+ *           CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ *           }
+ *
+ *           XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  * Return list *
+ *        }
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * <pre>
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Status;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+
+		/* Read the status */
+			if(CurBdPtr!=NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+			break;
+		}
+
+		BdCount++;
+
+		/* hardware has processed this BD so check the "last" bit. If
+                 * it is clear, then there are more BDs for the current packet.
+                 * Keep a count of these partial packet BDs.
+		 */
+			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+				BdPartialCount = 0U;
+			} else {
+			BdPartialCount++;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+			Status = 0U;
+	}
+}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0x00000000U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *   - Is the BD ring linked correctly in physical address space.
+ *   - Do the internal pointers point to BDs in the ring.
+ *   - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_NO_LIST if the list has not been created.
+ *   - XST_IS_STARTED if the channel is not stopped.
+ *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ *     structures. If this value is returned, the channel should be reset to
+ *     avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+	UINTPTR AddrV, AddrP;
+	u32 i;
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_IS_STARTED);
+	}
+
+	/* RunState doesn't make sense */
+	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (UINTPTR) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PreHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwTail;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PostHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->BaseBdAddr;
+	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+	for (i = 1U; i < RingPtr->AllCnt; i++) {
+		/* Check BDA for this BD. It should point to next physical addr */
+		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	/* Last BD should have wrap bit set */
+	if (XEMACPS_SEND == Direction) {
+		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+	else {			/* XEMACPS_RECV */
+		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+
+	/* No problems found */
+	return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueRx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueRx = *TempPtr;
+		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+		*TempPtr = DataValueRx;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueTx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueTx = *TempPtr;
+		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+		*TempPtr = DataValueTx;
+	}
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h
new file mode 100644
index 000000000..de78cf28f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h
@@ -0,0 +1,238 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+
+	u32 HwCnt;	     /**< Number of BDs in work group */
+	u32 PreCnt;     /**< Number of BDs in pre-work group */
+	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+	u32 PostCnt;    /**< Number of BDs in post-work group */
+	u32 AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
+    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c
new file mode 100644
index 000000000..f52451a8c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c
@@ -0,0 +1,1174 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_1
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *					   register. Added a new API for setting the BURST length
+ *					   in DMACR register.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * </pre>
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device.  The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	}
+	else{
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the MAC bits [31:0] in BOT */
+		MacAddr = *(Aptr);
+		MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+		MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+		MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+	/* There are reserved bits in TOP so don't affect them */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+		MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+	/* Set MAC bits [47:32] in TOP */
+		MacAddr |= (u32)(*(Aptr+4));
+		MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Aptr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	IndexLoc--;
+
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*Aptr = (u8) MacAddr;
+	*(Aptr+1) = (u8) (MacAddr >> 8U);
+	*(Aptr+2) = (u8) (MacAddr >> 16U);
+	*(Aptr+3) = (u8) (MacAddr >> 24U);
+
+	/* Read MAC bits [47:32] in TOP */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*(Aptr+4) = (u8) MacAddr;
+	*(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * <pre>
+ * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * </pre>
+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+				(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
+			Status = (LONG)(XST_INVALID_PARAM);
+		} else {
+
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr |= (u32)(0x00000001U << Result);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+					(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
+			Status =  (LONG)(XST_INVALID_PARAM);
+		} else {
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << Result));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET, 0x0U);
+
+	/* write bits [63:32] in TOP */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET, 0x0U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 *Aptr = (u32 *)(void *)AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET);
+
+	/* Read Hash bits [63:32] in TOP */
+	*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device.  The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the ID bits in MATCHx register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ *        XTE_*_OPTIONS constants together. Options not specified are not
+ *        affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic register contents */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/*
+	 * It is configured to max 1536.
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn on FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn on length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
+	}
+
+	/* Turn on flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn on promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Allow broadcast address reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
+	}
+
+	/* Allow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* enable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Enable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK);
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Enable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Enable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Enable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * the option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options |= Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ *        are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/* There is only RX configuration!?
+	 * It is configured in two different length, upto 1536 and 10240 bytes
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn off VLAN packet only */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
+	}
+
+	/* Turn off FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
+	}
+
+	/* Turn off length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
+	}
+
+	/* Turn off flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
+	}
+
+	/* Turn off promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
+	}
+
+	/* Disallow broadcast address filtering => broadcast reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Disallow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
+	}
+
+	/* Disable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
+	}
+
+	/* Disable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK));
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Disable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+			Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Disable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Disable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options &= ~Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set opion.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Make sure device is ready for this operation */
+	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STOPPED);
+	} else {
+	/* Send flow control frame */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ *         megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u16 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+
+	if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
+		Status = (u16)(1000);
+	} else {
+		if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
+			Status = (u16)(100);
+		} else {
+			Status = (u16)(10);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+        u32 Reg;
+	u16 Status;
+        Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
+
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
+
+	switch (Speed) {
+		case (u16)10:
+				Status = 0U;
+                break;
+
+        case (u16)100:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_100_MASK;
+                break;
+
+        case (u16)1000:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_1000_MASK;
+                break;
+
+        default:
+			Status = 1U;
+                break;
+    }
+	if(Status == (u16)1){
+                return;
+        }
+
+        /* Set register and return */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * <pre>
+ *              f[HOSTCLK]
+ *   f[MDC] = -----------------
+ *            (1 + Divisor) * 2
+ * </pre>
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * <pre>
+ * 000 : divide pclk by   8 (pclk up to  20 MHz)
+ * 001 : divide pclk by  16 (pclk up to  40 MHz)
+ * 010 : divide pclk by  32 (pclk up to  80 MHz)
+ * 011 : divide pclk by  48 (pclk up to 120 MHz)
+ * 100 : divide pclk by  64 (pclk up to 160 MHz)
+ * 101 : divide pclk by  96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * </pre>
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+	u32 Reg;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCFG_OFFSET);
+	/* clear these three bits, could be done with mask */
+	Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+	Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+*        which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpReadTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+			IpReadTemp = Ipisr;
+		} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+	/* Read data */
+		*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_PHYMNTNC_OFFSET);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY.  Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+*   status from the MAC on a write, the user should read the PHY to verify the
+*   write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpWriteTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+				IpWriteTemp = Ipisr;
+		} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+	u32 Reg;
+	u32 RegUpdateVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+					(BLength == XEMACPS_4BYTE_BURST) ||
+					(BLength == XEMACPS_8BYTE_BURST) ||
+					(BLength == XEMACPS_16BYTE_BURST));
+
+	switch (BLength) {
+		case XEMACPS_SINGLE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+			break;
+
+		case XEMACPS_4BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+			break;
+
+		case XEMACPS_8BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+			break;
+
+		case XEMACPS_16BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+			break;
+
+		default:
+			RegUpdateVal = 0x00000000U;
+			break;
+	}
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_DMACR_OFFSET);
+
+	Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+	Reg |= RegUpdateVal;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+																	Reg);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c
new file mode 100644
index 000000000..db734b924
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_ETHERNET_3_DEVICE_ID,
+		XPAR_PSU_ETHERNET_3_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c
new file mode 100644
index 000000000..daba38397
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc  28/06/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status registers
+*	Disable Rx and Tx engines
+*	Update the Tx and Rx descriptor queue registers with reset values
+*	Update the other relevant control registers with reset value
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+	u32 RegVal;
+
+	/* Disable the interrupts  */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+				(u32)XEMACPS_NWCTRL_RXEN_MASK|
+				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
+				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+	/* Clear the statistic registers, flush the packets in DPRAM*/
+	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+	/* Clear the interrupt status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+	/* Clear the tx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
+									(u32)XEMACPS_TXSR_TXGO_MASK));
+	/* Clear the rx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+								XEMACPS_RXSR_FRAMERX_MASK);
+	/* Clear the tx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+	/* Clear the rx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+	/* Update the network config register with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+	/* Update the hash address registers with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h
new file mode 100644
index 000000000..953cc6265
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1U	      /**< send direction */
+#define XEMACPS_RECV        2U	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
+							reg */
+#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
+							reg */
+#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
+							reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
+							reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
+							reg */
+#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
+							reg */
+#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
+							reg */
+#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
+							reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK     0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK      0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_TXSR_URUN_MASK | \
+                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
+                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
+                                     (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
+                                     (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c
new file mode 100644
index 000000000..59636c4ef
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c
@@ -0,0 +1,268 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
+*		      Rx errors. Under heavy Rx traffic, there will be a large
+*		      number of errors related to receive buffer not available.
+*		      Because of a HW bug (SI #692601), under such heavy errors,
+*		      the Rx data path can become unresponsive. To reduce the
+*		      probabilities for hitting this HW bug, the SW writes to
+*		      bit 18 to flush a packet from Rx DPRAM immediately. The
+*		      changes for it are done in the function
+*		      XEmacPs_IntrHandler.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+*		       and 64-bit changes.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+*                     there is no error. CR# 869403
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ *        XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ *        when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef)
+{
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FuncPointer != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+	case XEMACPS_HANDLER_DMASEND:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->SendRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_DMARECV:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->RecvRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_ERROR:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+		InstancePtr->ErrorRef = CallBackRef;
+		break;
+	default:
+		Status = (LONG)(XST_INVALID_PARAM);
+		break;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+*        interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+	u32 RegISR;
+	u32 RegSR;
+	u32 RegCtrl;
+	u32 RegQ1ISR = 0U;
+	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* This ISR will try to handle as many interrupts as it can in a single
+	 * call. However, in most of the places where the user's error handler
+         * is called, this ISR exits because it is expected that the user will
+         * reset the device in nearly all instances.
+	 */
+	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_ISR_OFFSET);
+
+	/* Read Transmit Q1 ISR */
+
+	if (InstancePtr->Version > 2)
+		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET);
+
+	/* Clear the interrupt status register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   RegISR);
+
+	/* Receive complete interrupt */
+	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+		/* Clear RX status register RX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET,
+				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
+		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	}
+
+	/* Transmit Q1 complete interrupt */
+	if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET,
+				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Transmit complete interrupt */
+	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Receive error conditions interrupt */
+	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+		/* Clear RX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_RXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET, RegSR);
+
+		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
+		 * register to flush a packet out of Rx SRAM upon
+		 * an error for receive buffer not available. */
+		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+			RegCtrl =
+			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_NWCTRL_OFFSET);
+			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+		}
+
+		if(RegSR != 0) {
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+						XEMACPS_RECV, RegSR);
+		}
+	}
+
+        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+         * will be asserted the same time.
+         * Have to distinguish this bit to handle the real error condition.
+         */
+	/* Transmit Q1 error conditions interrupt */
+        if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+			/* Clear Interrupt Q1 status register */
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegQ1ISR);
+	   }
+
+	/* Transmit error conditions interrupt */
+        if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_TXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET, RegSR);
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegSR);
+	}
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c
new file mode 100644
index 000000000..1bc5b3b19
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 New
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+	XEmacPs_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmacPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
index 597b38a12..38a5b9355 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile
deleted file mode 100644
index 8c16c35ae..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xiicps_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling iicps"
-
-xiicps_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xiicps_includes
-
-xiicps_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c
deleted file mode 100644
index 812c2ecdc..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* Contains implementation of required functions for the XIicPs driver.
-* See xiicps.h for detailed description of the device and driver.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- --------------------------------------------
-* 1.00a drg/jz  01/30/10 First release
-* 1.00a sdm     09/21/11 Updated the InstancePtr->Options in the
-*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
-* 2.1   hk      04/25/14 Explicitly reset CR and clear FIFO in Abort function
-*                        and state the same in the comments. CR# 784254.
-*                        Fix for CR# 761060 - provision for repeated start.
-* 2.3	sk		10/07/14 Repeated start feature removed.
-* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
-* 						 in XIicPs_Reset.
-*				12/06/14 Implemented Repeated start feature.
-*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void *CallBackRef, u32 StatusEvent);
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XIicPs instance such that the driver is ready to use.
-*
-* The state of the device after initialization is:
-*   - Device is disabled
-*   - Slave mode
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	ConfigPtr is a reference to a structure containing information
-*		about a specific IIC device. This function initializes an
-*		InstancePtr object for a specific device specified by the
-*		contents of Config.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the address
-*		mapping from EffectiveAddr to the device physical base address
-*		unchanged once this function is invoked. Unexpected errors may
-*		occur if the address mapping changes after this function is
-*		called. If address translation is not used, use
-*		ConfigPtr->BaseAddress for this parameter, passing the physical
-*		address instead.
-*
-* @return	The return value is XST_SUCCESS if successful.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
-				  u32 EffectiveAddr)
-{
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	/*
-	 * Set some default values.
-	 */
-	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
-	InstancePtr->StatusHandler = StubHandler;
-	InstancePtr->CallBackRef = NULL;
-
-	InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
-
-	/*
-	 * Reset the IIC device to get it into its initial state. It is expected
-	 * that device configuration will take place after this initialization
-	 * is done, but before the device is started.
-	 */
-	XIicPs_Reset(InstancePtr);
-
-	/*
-	 * Keep a copy of what options this instance has.
-	 */
-	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
-
-	/* Initialize repeated start flag to 0 */
-	InstancePtr->IsRepeatedStart = 0;
-
-	return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* Check whether the I2C bus is busy
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return
-* 		- TRUE if the bus is busy.
-*		- FALSE if the bus is not busy.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
-{
-	u32 StatusReg;
-	s32	Status;
-
-	StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-					   XIICPS_SR_OFFSET);
-	if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
-		Status = (s32)TRUE;
-	}else {
-		Status = (s32)FALSE;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param	CallBackRef is a pointer to the upper layer callback reference.
-* @param	StatusEvent is the event that just occurred.
-* @param	ByteCount is the number of bytes transferred up until the event
-*		occurred.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-static void StubHandler(void *CallBackRef, u32 StatusEvent)
-{
-	(void) ((void *)CallBackRef);
-	(void) StatusEvent;
-	Xil_AssertVoidAlways();
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
-* cleared.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XIicPs_Abort(XIicPs *InstancePtr)
-{
-	u32 IntrMaskReg;
-	u32 IntrStatusReg;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Enter a critical section, so disable the interrupts while we clear
-	 * the FIFO and the status register.
-	 */
-	IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-					   XIICPS_IMR_OFFSET);
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
-
-	/*
-	 * Reset the settings in config register and clear the FIFOs.
-	 */
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
-			  XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK);
-
-	/*
-	 * Read, then write the interrupt status to make sure there are no
-	 * pending interrupts.
-	 */
-	IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-					 XIICPS_ISR_OFFSET);
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XIICPS_ISR_OFFSET, IntrStatusReg);
-
-	/*
-	 * Restore the interrupt state.
-	 */
-	IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XIICPS_IER_OFFSET, IntrMaskReg);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the IIC device. Reset must only be called after the driver has been
-* initialized. The configuration of the device after reset is the same as its
-* configuration after initialization.  Any data transfer that is in progress is
-* aborted.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and reenabling interrupts for the IIC device after the reset.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XIicPs_Reset(XIicPs *InstancePtr)
-{
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Abort any transfer that is in progress.
-	 */
-	XIicPs_Abort(InstancePtr);
-
-	/*
-	 * Reset any values so the software state matches the hardware device.
-	 */
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
-			  XIICPS_CR_RESET_VALUE);
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
-			  XIICPS_IXR_ALL_INTR_MASK);
-
-}
-/*****************************************************************************/
-/**
-* Put more data into the transmit FIFO, number of bytes is ether expected
-* number of bytes for this transfer or available space in FIFO, which ever
-* is less.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	Number of bytes left for this instance.
-*
-* @note		This is function is shared by master and slave.
-*
-******************************************************************************/
-s32 TransmitFifoFill(XIicPs *InstancePtr)
-{
-	u8 AvailBytes;
-	s32 LoopCnt;
-	s32 NumBytesToSend;
-
-	/*
-	 * Determine number of bytes to write to FIFO.
-	 */
-	AvailBytes = (u8)XIICPS_FIFO_DEPTH -
-		(u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-					   XIICPS_TRANS_SIZE_OFFSET);
-
-	if (InstancePtr->SendByteCount > (s32)AvailBytes) {
-		NumBytesToSend = (s32)AvailBytes;
-	} else {
-		NumBytesToSend = InstancePtr->SendByteCount;
-	}
-
-	/*
-	 * Fill FIFO with amount determined above.
-	 */
-	for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
-		XIicPs_SendByte(InstancePtr);
-	}
-
-	return InstancePtr->SendByteCount;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h
deleted file mode 100644
index 73ad5dc64..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps.h
-* @addtogroup iicps_v3_0
-* @{
-* @details
-*
-* This is an implementation of IIC driver in the PS block. The device can
-* be either a master or a slave on the IIC bus. This implementation supports
-* both interrupt mode transfer and polled mode transfer. Only 7-bit address
-* is used in the driver, although the hardware also supports 10-bit address.
-*
-* IIC is a 2-wire serial interface.  The master controls the clock, so it can
-* regulate when it wants to send or receive data. The slave is under control of
-* the master, it must respond quickly since it has no control of the clock and
-* must send/receive data as fast or as slow as the master does.
-*
-* The higher level software must implement a higher layer protocol to inform
-* the slave what to send to the master.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XIicPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-*
-*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
-*      the static configuration structure defined in xiicps_g.c. This is
-*      setup by the tools. For some operating systems the config structure
-*      will be initialized by the software and this call is not needed.
-*
-*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-*     configuration structure provided by the caller. If running in a
-*     system with address translation, the provided virtual memory base
-*     address replaces the physical address in the configuration
-*     structure.
-*
-* <b>Multiple Masters</b>
-*
-* More than one master can exist, bus arbitration is defined in the IIC
-* standard. Lost of arbitration causes arbitration loss interrupt on the device.
-*
-* <b>Multiple Slaves</b>
-*
-* Multiple slaves are supported by selecting them with unique addresses. It is
-* up to the system designer to be sure all devices on the IIC bus have
-* unique addresses.
-*
-* <b>Addressing</b>
-*
-* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
-* ability to control which address size is sent in messages as a master to a
-* slave device.
-*
-* <b>FIFO Size </b>
-* The hardware FIFO is 32 bytes deep. The user must know the limitations of
-* other IIC devices on the bus. Some are only able to receive a limited number
-* of bytes in a single transfer.
-*
-* <b>Data Rates</b>
-*
-* The data rate is set by values in the control register. The formula for
-* determining the correct register values is:
-* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
-*
-* When the device is configured as a slave, the slck setting controls the
-* sample rate and so must be set to be at least as fast as the fastest scl
-* expected to be seen in the system.
-*
-* <b>Polled Mode Operation</b>
-*
-* This driver supports polled mode transfers.
-*
-* <b>Interrupts</b>
-*
-* The user must connect the interrupt handler of the driver,
-* XIicPs_InterruptHandler to an interrupt system such that it will be called
-* when an interrupt occurs. This function does not save and restore the
-* processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Transfer complete
-* - More Data
-* - Transfer not Acknowledged
-* - Transfer Time out
-* - Monitored slave ready - master mode only
-* - Receive Overflow
-* - Transmit FIFO overflow
-* - Receive FIFO underflow
-* - Arbitration lost
-*
-* <b>Bus Busy</b>
-*
-* Bus busy is checked before the setup of a master mode device, to avoid
-* unnecessary arbitration loss interrupt.
-*
-* <b>RTOS Independence</b>
-*
-* This driver is intended to be RTOS and processor independent.  It works with
-* physical addresses only.  Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied by
-* the layer above this driver.
-*
-*<b>Repeated Start</b>
-*
-* The I2C controller does not indicate completion of a receive transfer if HOLD
-* bit is set. Due to this errata, repeated start cannot be used if a receive
-* transfer is followed by any other transfer.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- -----------------------------------------------
-* 1.00a drg/jz  01/30/08 First release
-* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
-*			 XIicPs_ClearOptions where the InstancePtr->Options
-*			 was not updated correctly.
-* 			 Updated the InstancePtr->Options in the
-*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
-*			 Updated the XIicPs_SetupMaster to not check for
-*			 Bus Busy condition when the Hold Bit is set.
-*			 Removed some unused variables.
-* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
-*			 check for transfer completion is added, which indicates
-*			 the completion of current transfer.
-* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
-*			 to achieve I2C clock with minimum error for
-*			 CR #674195
-* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
-*			 This is fix for CR#704398 to remove warning.
-* 2.0   hk  03/07/14 Added check for error status in the while loop that
-*                    checks for completion.
-*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
-*                    Limited frequency set when 100KHz or 400KHz is
-*                    selected. This is a hardware limitation. CR#779290.
-* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
-*                    Explicitly reset CR and clear FIFO in Abort function
-*                    and state the same in the comments. CR# 784254.
-*                    Fix for CR# 761060 - provision for repeated start.
-* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
-*                    read mode and clear transfer size register.
-*                    Disable NACK to avoid interrupts on each retry.
-* 2.3	sk	10/07/14 Repeated start feature deleted.
-* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
-* 					 in XIicPs_Reset.
-* 			12/06/14 Implemented Repeated start feature.
-*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*			02/18/15 Implemented larger data transfer using repeated start
-*					  in Zynq UltraScale MP.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIICPS_H       /* prevent circular inclusions */
-#define XIICPS_H       /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xiicps_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options may be specified or retrieved for the device and
- * enable/disable additional features of the IIC.  Each of the options
- * are bit fields, so more than one may be specified.
- *
- * @{
- */
-#define XIICPS_7_BIT_ADDR_OPTION	0x01U  /**< 7-bit address mode */
-#define XIICPS_10_BIT_ADDR_OPTION	0x02U  /**< 10-bit address mode */
-#define XIICPS_SLAVE_MON_OPTION		0x04U  /**< Slave monitor mode */
-#define XIICPS_REP_START_OPTION		0x08U  /**< Repeated Start */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to an application
- * event handler from the driver.  These constants are bit masks such that
- * more than one event can be passed to the handler.
- *
- * @{
- */
-#define XIICPS_EVENT_COMPLETE_SEND	0x0001U  /**< Transmit Complete Event*/
-#define XIICPS_EVENT_COMPLETE_RECV	0x0002U  /**< Receive Complete Event*/
-#define XIICPS_EVENT_TIME_OUT		0x0004U  /**< Transfer timed out */
-#define XIICPS_EVENT_ERROR			0x0008U  /**< Receive error */
-#define XIICPS_EVENT_ARB_LOST		0x0010U  /**< Arbitration lost */
-#define XIICPS_EVENT_NACK			0x0020U  /**< NACK Received */
-#define XIICPS_EVENT_SLAVE_RDY		0x0040U  /**< Slave ready */
-#define XIICPS_EVENT_RX_OVR			0x0080U  /**< RX overflow */
-#define XIICPS_EVENT_TX_OVR			0x0100U  /**< TX overflow */
-#define XIICPS_EVENT_RX_UNF			0x0200U  /**< RX underflow */
-/*@}*/
-
-/** @name Role constants
- *
- * These constants are used to pass into the device setup routines to
- * set up the device according to transfer direction.
- */
-#define SENDING_ROLE		1  /**< Transfer direction is sending */
-#define RECVING_ROLE		0  /**< Transfer direction is receiving */
-
-/* Maximum transfer size */
-#define XIICPS_MAX_TRANSFER_SIZE	(u32)(255U - 3U)
-
-/**************************** Type Definitions *******************************/
-
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param	CallBackRef is the callback reference passed in by the upper
-*		layer when setting the callback functions, and passed back to
-*		the upper layer when the callback is invoked. Its type is
-*		not important to the driver, so it is a void pointer.
-* @param	StatusEvent indicates one or more status events that occurred.
-*/
-typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;     /**< Unique ID  of device */
-	u32 BaseAddress;  /**< Base address of the device */
-	u32 InputClockHz; /**< Input clock frequency */
-} XIicPs_Config;
-
-/**
- * The XIicPs driver instance data. The user is required to allocate a
- * variable of this type for each IIC device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XIicPs_Config Config;	/* Configuration structure */
-	u32 IsReady;		/* Device is initialized and ready */
-	u32 Options;		/* Options set in the device */
-
-	u8 *SendBufferPtr;	/* Pointer to send buffer */
-	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
-	s32 SendByteCount;	/* Number of bytes still expected to send */
-	s32 RecvByteCount;	/* Number of bytes still expected to receive */
-	s32 CurrByteCount;	/* No. of bytes expected in current transfer */
-
-	s32 UpdateTxSize;	/* If tx size register has to be updated */
-	s32 IsSend;		/* Whether master is sending or receiving */
-	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
-
-	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
-	void *CallBackRef;	/* Callback reference for event handler */
-} XIicPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/*
-*
-* Place one byte into the transmit FIFO.
-*
-* @param	InstancePtr is the instance of IIC
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XIicPs_SendByte(XIicPs *InstancePtr)
-*
-*****************************************************************************/
-#define XIicPs_SendByte(InstancePtr)					\
-{									\
-	u8 Data;							\
-	Data = *((InstancePtr)->SendBufferPtr);				\
-	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
-			 + (u32)(XIICPS_DATA_OFFSET), 			\
-					(u32)(Data));			\
-	(InstancePtr)->SendBufferPtr += 1;				\
-	(InstancePtr)->SendByteCount -= 1;\
-}
-
-/****************************************************************************/
-/*
-*
-* Receive one byte from FIFO.
-*
-* @param	InstancePtr is the instance of IIC
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
-*
-*****************************************************************************/
-#define XIicPs_RecvByte(InstancePtr)					\
-{									\
-	u8 *Data, Value;						\
-	Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress	\
-		  + (u32)XIICPS_DATA_OFFSET));  			\
-	Data = &Value;							\
-	*(InstancePtr)->RecvBufferPtr = *Data;				\
-	(InstancePtr)->RecvBufferPtr += 1;				\
-	 (InstancePtr)->RecvByteCount --; 				\
-}
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Function for configuration lookup, in xiicps_sinit.c
- */
-XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions for general setup, in xiicps.c
- */
-s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
-				  u32 EffectiveAddr);
-
-void XIicPs_Abort(XIicPs *InstancePtr);
-void XIicPs_Reset(XIicPs *InstancePtr);
-
-s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
-s32 TransmitFifoFill(XIicPs *InstancePtr);
-
-/*
- * Functions for interrupts, in xiicps_intr.c
- */
-void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
-				  XIicPs_IntrHandler FunctionPtr);
-
-/*
- * Functions for device as master, in xiicps_master.c
- */
-void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
-		u16 SlaveAddr);
-void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
-		u16 SlaveAddr);
-s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
-		u16 SlaveAddr);
-s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
-		u16 SlaveAddr);
-void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
-void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
-void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
-
-/*
- * Functions for device as slave, in xiicps_slave.c
- */
-void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
-void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
-
-/*
- * Functions for selftest, in xiicps_selftest.c
- */
-s32 XIicPs_SelfTest(XIicPs *InstancePtr);
-
-/*
- * Functions for setting and getting data rate, in xiicps_options.c
- */
-s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
-s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
-u32 XIicPs_GetOptions(XIicPs *InstancePtr);
-
-s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
-u32 XIicPs_GetSClk(XIicPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c
deleted file mode 100644
index 50f1c1413..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c
+++ /dev/null
@@ -1,61 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xiicps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XIicPs_Config XIicPs_ConfigTable[] =
-{
-	{
-		XPAR_PSU_I2C_0_DEVICE_ID,
-		XPAR_PSU_I2C_0_BASEADDR,
-		XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_I2C_1_DEVICE_ID,
-		XPAR_PSU_I2C_1_BASEADDR,
-		XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c
deleted file mode 100644
index 8b7a58fc6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_hw.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* Contains implementation of required functions for providing the reset sequence
-* to the i2c interface
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- --------------------------------------------
-* 1.04a kpc     11/07/13 First release
-* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
-*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps_hw.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given I2c interface by
-* configuring the appropriate control bits in the I2c specifc registers
-* the i2cps reset squence involves the following steps
-*	Disable all the interuupts
-*	Clear the status
-*	Clear FIFO's and disable hold bit
-*	Clear the line status
-*	Update relevant config registers with reset values
-*
-* @param   BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* I2c controller
-******************************************************************************/
-void XIicPs_ResetHw(u32 BaseAddress)
-{
-	u32 RegVal;
-
-	/* Disable all the interrupts */
-	XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
-	/* Clear the interrupt status */
-	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
-	XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
-	/* Clear the hold bit,master enable bit and ack bit */
-	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
-	RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
-	/* Clear the fifos */
-	RegVal |= XIICPS_CR_CLR_FIFO_MASK;
-	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
-	/* Clear the timeout register */
-	XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
-	/* Clear the transfer size register */
-	XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
-	/* Clear the status register */
-	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
-	XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
-	/* Update the configuraqtion register with reset value */
-	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h
deleted file mode 100644
index cec349928..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_hw.h
-* @addtogroup iicps_v3_0
-* @{
-*
-* This header file contains the hardware definition for an IIC device.
-* It includes register definitions and interface functions to read/write
-* the registers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who 	Date     Changes
-* ----- ------  -------- -----------------------------------------------
-* 1.00a drg/jz  01/30/10 First release
-* 1.04a kpc		11/07/13 Added function prototype.
-* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
-*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIICPS_HW_H		/* prevent circular inclusions */
-#define XIICPS_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the IIC.
- * @{
- */
-#define XIICPS_CR_OFFSET			0x00U  /**< 32-bit Control */
-#define XIICPS_SR_OFFSET			0x04U  /**< Status */
-#define XIICPS_ADDR_OFFSET			0x08U  /**< IIC Address */
-#define XIICPS_DATA_OFFSET			0x0CU  /**< IIC FIFO Data */
-#define XIICPS_ISR_OFFSET			0x10U  /**< Interrupt Status */
-#define XIICPS_TRANS_SIZE_OFFSET	0x14U  /**< Transfer Size */
-#define XIICPS_SLV_PAUSE_OFFSET		0x18U  /**< Slave monitor pause */
-#define XIICPS_TIME_OUT_OFFSET		0x1CU  /**< Time Out */
-#define XIICPS_IMR_OFFSET			0x20U  /**< Interrupt Enabled Mask */
-#define XIICPS_IER_OFFSET			0x24U  /**< Interrupt Enable */
-#define XIICPS_IDR_OFFSET			0x28U  /**< Interrupt Disable */
-/* @} */
-
-/** @name Control Register
- *
- * This register contains various control bits that
- * affects the operation of the IIC controller. Read/Write.
- * @{
- */
-
-#define XIICPS_CR_DIV_A_MASK	0x0000C000U /**< Clock Divisor A */
-#define XIICPS_CR_DIV_A_SHIFT			14U /**< Clock Divisor A shift */
-#define XIICPS_DIV_A_MAX				 4U /**< Maximum value of Divisor A */
-#define XIICPS_CR_DIV_B_MASK	0x00003F00U /**< Clock Divisor B */
-#define XIICPS_CR_DIV_B_SHIFT			 8U /**< Clock Divisor B shift */
-#define XIICPS_CR_CLR_FIFO_MASK	0x00000040U /**< Clear FIFO, auto clears*/
-#define XIICPS_CR_SLVMON_MASK	0x00000020U /**< Slave monitor mode */
-#define XIICPS_CR_HOLD_MASK		0x00000010U /**<  Hold bus 1=Hold scl,
-												0=terminate transfer */
-#define XIICPS_CR_ACKEN_MASK	0x00000008U /**< Enable TX of ACK when
-												Master receiver*/
-#define XIICPS_CR_NEA_MASK		0x00000004U /**< Addressing Mode 1=7 bit,
-												0=10 bit */
-#define XIICPS_CR_MS_MASK		0x00000002U /**< Master mode bit 1=Master,
-												0=Slave */
-#define XIICPS_CR_RD_WR_MASK	0x00000001U /**< Read or Write Master
-												transfer  0=Transmitter,
-												1=Receiver*/
-#define XIICPS_CR_RESET_VALUE			 0U /**< Reset value of the Control
-												register */
-/* @} */
-
-/** @name IIC Status Register
- *
- * This register is used to indicate status of the IIC controller. Read only
- * @{
- */
-#define XIICPS_SR_BA_MASK		0x00000100U  /**< Bus Active Mask */
-#define XIICPS_SR_RXOVF_MASK	0x00000080U  /**< Receiver Overflow Mask */
-#define XIICPS_SR_TXDV_MASK		0x00000040U  /**< Transmit Data Valid Mask */
-#define XIICPS_SR_RXDV_MASK		0x00000020U  /**< Receiver Data Valid Mask */
-#define XIICPS_SR_RXRW_MASK		0x00000008U  /**< Receive read/write Mask */
-/* @} */
-
-/** @name IIC Address Register
- *
- * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
- * A write access to this register always initiates a transfer if the IIC is in
- * master mode. Read/Write
- * @{
- */
-#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
-/* @} */
-
-/** @name IIC Data Register
- *
- * When written to, the data register sets data to transmit. When read from, the
- * data register reads the last received byte of data. Read/Write
- * @{
- */
-#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
-/* @} */
-
-/** @name IIC Interrupt Registers
- *
- * <b>IIC Interrupt Status Register</b>
- *
- * This register holds the interrupt status flags for the IIC controller. Some
- * of the flags are level triggered
- * - i.e. are set as long as the interrupt condition exists.  Other flags are
- *   edge triggered, which means they are set one the interrupt condition occurs
- *   then remain set until they are cleared by software.
- *   The interrupts are cleared by writing a one to the interrupt bit position
- *   in the Interrupt Status Register. Read/Write.
- *
- * <b>IIC Interrupt Enable Register</b>
- *
- * This register is used to enable interrupt sources for the IIC controller.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * IIC Interrupt Mask register.  Write only.
- *
- * <b>IIC Interrupt Disable Register </b>
- *
- * This register is used to disable interrupt sources for the IIC controller.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * IIC Interrupt Mask register. Write only.
- *
- * <b>IIC Interrupt Mask Register</b>
- *
- * This register shows the enabled/disabled status of each IIC controller
- * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
- * the status register. A bit set to 0 means the interrupt is enabled.
- * All mask bits are set and all interrupts are disabled after reset. Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Interrupt Status Register
- * @{
- */
-
-#define XIICPS_IXR_ARB_LOST_MASK  0x00000200U	 /**< Arbitration Lost Interrupt
-													mask */
-#define XIICPS_IXR_RX_UNF_MASK    0x00000080U	 /**< FIFO Recieve Underflow
-													Interrupt mask */
-#define XIICPS_IXR_TX_OVR_MASK    0x00000040U	 /**< Transmit Overflow
-													Interrupt mask */
-#define XIICPS_IXR_RX_OVR_MASK    0x00000020U	 /**< Receive Overflow Interrupt
-													mask */
-#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U	 /**< Monitored Slave Ready
-													Interrupt mask */
-#define XIICPS_IXR_TO_MASK        0x00000008U	 /**< Transfer Time Out
-													Interrupt mask */
-#define XIICPS_IXR_NACK_MASK      0x00000004U	 /**< NACK Interrupt mask */
-#define XIICPS_IXR_DATA_MASK      0x00000002U	 /**< Data Interrupt mask */
-#define XIICPS_IXR_COMP_MASK      0x00000001U	 /**< Transfer Complete
-													Interrupt mask */
-#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU	 /**< Default ISR Mask */
-#define XIICPS_IXR_ALL_INTR_MASK  0x000002FFU	 /**< All ISR Mask */
-/* @} */
-
-
-/** @name IIC Transfer Size Register
-*
-* The register's meaning varies according to the operating mode as follows:
-*   - Master transmitter mode: number of data bytes still not transmitted minus
-*     one
-*   - Master receiver mode: number of data bytes that are still expected to be
-*     received
-*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
-*     master terminates the transfer
-*   - Slave receiver mode: number of valid data bytes in the FIFO
-*
-* This register is cleared if CLR_FIFO bit in the control register is set.
-* Read/Write
-* @{
-*/
-#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
-#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
-#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
-/* @} */
-
-
-/** @name IIC Slave Monitor Pause Register
-*
-* This register is associated with the slave monitor mode of the I2C interface.
-* It is meaningful only when the module is in master mode and bit SLVMON in the
-* control register is set.
-*
-* This register defines the pause interval between consecutive attempts to
-* address the slave once a write to an I2C address register is done by the
-* host. It represents the number of sclk cycles minus one between two attempts.
-*
-* The reset value of the register is 0, which results in the master repeatedly
-* trying to access the slave immediately after unsuccessful attempt.
-* Read/Write
-* @{
-*/
-#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
-/* @} */
-
-
-/** @name IIC Time Out Register
-*
-* The value of time out register represents the time out interval in number of
-* sclk cycles minus one.
-*
-* When the accessed slave holds the sclk line low for longer than the time out
-* period, thus prohibiting the I2C interface in master mode to complete the
-* current transfer, an interrupt is generated and TO interrupt flag is set.
-*
-* The reset value of the register is 0x1f.
-* Read/Write
-* @{
- */
-#define XIICPS_TIME_OUT_MASK    0x000000FFU    /**< IIC Time Out mask */
-#define XIICPS_TO_RESET_VALUE   0x000000FFU    /**< IIC Time Out reset value */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XIicPs_In32 Xil_In32
-#define XIicPs_Out32 Xil_Out32
-
-/****************************************************************************/
-/**
-* Read an IIC register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to select the specific register.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XIicPs_ReadReg(BaseAddress, RegOffset) \
-	XIicPs_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write an IIC register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to select the specific register.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note	C-Style signature:
-*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
-*
-******************************************************************************/
-#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
-	XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/***************************************************************************/
-/**
-* Read the interrupt enable register.
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @return	Current bit mask that represents currently enabled interrupts.
-*
-* @note		C-Style signature:
-*		u32 XIicPs_ReadIER(u32 BaseAddress)
-*
-******************************************************************************/
-#define XIicPs_ReadIER(BaseAddress) \
-	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
-
-/***************************************************************************/
-/**
-* Write to the interrupt enable register.
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @param	IntrMask is the interrupts to be enabled.
-*
-* @return	None.
-*
-* @note	C-Style signature:
-*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
-*
-******************************************************************************/
-#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
-	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
-
-/***************************************************************************/
-/**
-* Disable all interrupts.
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
-*
-******************************************************************************/
-#define XIicPs_DisableAllInterrupts(BaseAddress) \
-	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
-		XIICPS_IXR_ALL_INTR_MASK)
-
-/***************************************************************************/
-/**
-* Disable selected interrupts.
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @param	IntrMask is the interrupts to be disabled.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
-*
-******************************************************************************/
-#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
-	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
-		(IntrMask))
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the I2c interface
- */
-void XIicPs_ResetHw(u32 BaseAddress);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c
deleted file mode 100644
index de05b93b6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_intr.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* Contains functions of the XIicPs driver for interrupt-driven transfers.
-* See xiicps.h for a detailed description of the device and driver.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- -----------------------------------------------
-* 1.00a drg/jz  01/30/10 First release
-* 3.00	sk		01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************* Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function sets the status callback function, the status handler, which the
-* driver calls when it encounters conditions that should be reported to the
-* higher layer software. The handler executes in an interrupt context, so
-* the amount of processing should be minimized
-*
-* Refer to the xiicps.h file for a list of the Callback events. The events are
-* defined to start with XIICPS_EVENT_*.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	CallBackRef is the upper layer callback reference passed back
-*		when the callback function is invoked.
-* @param	FunctionPtr is the pointer to the callback function.
-*
-* @return	None.
-*
-* @note
-*
-* The handler is called within interrupt context, so it should finish its
-* work quickly.
-*
-******************************************************************************/
-void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
-				  XIicPs_IntrHandler FunctionPtr)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(FunctionPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	InstancePtr->StatusHandler = FunctionPtr;
-	InstancePtr->CallBackRef = CallBackRef;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c
deleted file mode 100644
index d49feecdf..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c
+++ /dev/null
@@ -1,987 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_master.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* Handles master mode transfers.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---  -------- ---------------------------------------------
-* 1.00a jz   01/30/10 First release
-* 1.00a sdm  09/21/11 Updated the XIicPs_SetupMaster to not check for
-*		      Bus Busy condition when the Hold Bit is set.
-* 1.01a sg   03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
-*		      check for transfer completion is added, which indicates
-*			 the completion of current transfer.
-* 2.0   hk   03/07/14 Added check for error status in the while loop that
-*                     checks for completion. CR# 762244, 764875.
-* 2.1   hk   04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
-*                     Fix for CR# 761060 - provision for repeated start.
-* 2.2   hk   08/23/14 Slave monitor mode changes - clear FIFO, enable
-*                     read mode and clear transfer size register.
-*                     Disable NACK to avoid interrupts on each retry.
-* 2.3	sk	 10/06/14 Fill transmit fifo before address register when sending.
-* 					  Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
-* 					  Repeated start feature removed.
-* 3.0	sk	 12/06/14 Implemented Repeated start feature.
-*			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*			 02/18/15 Implemented larger data transfer using repeated start
-*					  in Zynq UltraScale MP.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-s32 TransmitFifoFill(XIicPs *InstancePtr);
-
-static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
-static void MasterSendData(XIicPs *InstancePtr);
-
-/************************* Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function initiates an interrupt-driven send in master mode.
-*
-* It tries to send the first FIFO-full of data, then lets the interrupt
-* handler to handle the rest of the data if there is any.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the send buffer.
-* @param	ByteCount is the number of bytes to be sent.
-* @param	SlaveAddr is the address of the slave we are sending to.
-*
-* @return	None.
-*
-* @note		This send routine is for interrupt-driven transfer only.
-*
- ****************************************************************************/
-void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
-		 u16 SlaveAddr)
-{
-	u32 BaseAddr;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(MsgPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	InstancePtr->SendBufferPtr = MsgPtr;
-	InstancePtr->SendByteCount = ByteCount;
-	InstancePtr->RecvBufferPtr = NULL;
-	InstancePtr->IsSend = 1;
-
-	/*
-	 * Set repeated start if sending more than FIFO of data.
-	 */
-	if (((InstancePtr->IsRepeatedStart) != 0)||
-		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
-		XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
-			XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
-				(u32)XIICPS_CR_HOLD_MASK);
-	}
-
-	/*
-	 * Setup as a master sending role.
-	 */
-	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
-
-	(void)TransmitFifoFill(InstancePtr);
-
-	XIicPs_EnableInterrupts(BaseAddr,
-		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
-		(u32)XIICPS_IXR_ARB_LOST_MASK);
-	/*
-	 * Do the address transfer to notify the slave.
-	 */
-	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
-}
-
-/*****************************************************************************/
-/**
-* This function initiates an interrupt-driven receive in master mode.
-*
-* It sets the transfer size register so the slave can send data to us.
-* The rest of the work is managed by interrupt handler.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the receive buffer.
-* @param	ByteCount is the number of bytes to be received.
-* @param	SlaveAddr is the address of the slave we are receiving from.
-*
-* @return	None.
-*
-* @note		This receive routine is for interrupt-driven transfer only.
-*
-****************************************************************************/
-void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
-		 u16 SlaveAddr)
-{
-	u32 BaseAddr;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(MsgPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	InstancePtr->RecvBufferPtr = MsgPtr;
-	InstancePtr->RecvByteCount = ByteCount;
-	InstancePtr->CurrByteCount = ByteCount;
-	InstancePtr->SendBufferPtr = NULL;
-	InstancePtr->IsSend = 0;
-	InstancePtr->UpdateTxSize = 0;
-
-	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
-		((InstancePtr->IsRepeatedStart) !=0))
-	{
-		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
-						(u32)XIICPS_CR_HOLD_MASK);
-	}
-
-	/*
-	 * Initialize for a master receiving role.
-	 */
-	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
-	/*
-	 * Setup the transfer size register so the slave knows how much
-	 * to send to us.
-	 */
-	if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
-		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
-				XIICPS_MAX_TRANSFER_SIZE);
-		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
-		InstancePtr->UpdateTxSize = 1;
-	}else {
-		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
-			 (u32)ByteCount);
-	}
-
-	XIicPs_EnableInterrupts(BaseAddr,
-		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
-		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
-		(u32)XIICPS_IXR_ARB_LOST_MASK);
-	/*
-	 * Do the address transfer to signal the slave.
-	 */
-	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
-}
-
-/*****************************************************************************/
-/**
-* This function initiates a polled mode send in master mode.
-*
-* It sends data to the FIFO and waits for the slave to pick them up.
-* If slave fails to remove data from FIFO, the send fails with
-* time out.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the send buffer.
-* @param	ByteCount is the number of bytes to be sent.
-* @param	SlaveAddr is the address of the slave we are sending to.
-*
-* @return
-*		- XST_SUCCESS if everything went well.
-*		- XST_FAILURE if timed out.
-*
-* @note		This send routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
-		 s32 ByteCount, u16 SlaveAddr)
-{
-	u32 IntrStatusReg;
-	u32 StatusReg;
-	u32 BaseAddr;
-	u32 Intrs;
-	u32 Value;
-	s32 Status;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(MsgPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	InstancePtr->SendBufferPtr = MsgPtr;
-	InstancePtr->SendByteCount = ByteCount;
-
-	if (((InstancePtr->IsRepeatedStart) != 0) ||
-		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
-		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
-						(u32)XIICPS_CR_HOLD_MASK);
-	}
-
-	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
-
-	/*
-	 * Intrs keeps all the error-related interrupts.
-	 */
-	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
-		(u32)XIICPS_IXR_NACK_MASK;
-
-	/*
-	 * Clear the interrupt status register before use it to monitor.
-	 */
-	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-	/*
-	 * Transmit first FIFO full of data.
-	 */
-	(void)TransmitFifoFill(InstancePtr);
-
-	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
-	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-
-	/*
-	 * Continue sending as long as there is more data and
-	 * there are no errors.
-	 */
-	Value = ((InstancePtr->SendByteCount > (s32)0) &&
-		((IntrStatusReg & Intrs) == (u32)0U));
-	while (Value != (u32)0x00U) {
-		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
-		/*
-		 * Wait until transmit FIFO is empty.
-		 */
-		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
-			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
-					XIICPS_ISR_OFFSET);
-			Value = ((InstancePtr->SendByteCount > (s32)0) &&
-				((IntrStatusReg & Intrs) == (u32)0U));
-			continue;
-		}
-
-		/*
-		 * Send more data out through transmit FIFO.
-		 */
-		(void)TransmitFifoFill(InstancePtr);
-		Value = ((InstancePtr->SendByteCount > (s32)0) &&
-			((IntrStatusReg & Intrs) == (u32)0U));
-	}
-
-	/*
-	 * Check for completion of transfer.
-	 */
-	while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
-
-		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-		/*
-		 * If there is an error, tell the caller.
-		 */
-		if ((IntrStatusReg & Intrs) != 0U) {
-			return (s32)XST_FAILURE;
-		}
-	}
-
-	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
-		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
-						(~XIICPS_CR_HOLD_MASK));
-	}
-
-	return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function initiates a polled mode receive in master mode.
-*
-* It repeatedly sets the transfer size register so the slave can
-* send data to us. It polls the data register for data to come in.
-* If slave fails to send us data, it fails with time out.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the receive buffer.
-* @param	ByteCount is the number of bytes to be received.
-* @param	SlaveAddr is the address of the slave we are receiving from.
-*
-* @return
-*		- XST_SUCCESS if everything went well.
-*		- XST_FAILURE if timed out.
-*
-* @note		This receive routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
-				s32 ByteCount, u16 SlaveAddr)
-{
-	u32 IntrStatusReg;
-	u32 Intrs;
-	u32 StatusReg;
-	u32 BaseAddr;
-	s32 BytesToRecv;
-	s32 BytesToRead;
-	s32 TransSize;
-	s32 Tmp = 0;
-	u32 Status_Rcv;
-	u32 Status;
-	s32 Result;
-	s32 IsHold = 0;
-	s32 UpdateTxSize = 0;
-	s32 ByteCountVar = ByteCount;
-	u32 Platform;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(MsgPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	InstancePtr->RecvBufferPtr = MsgPtr;
-	InstancePtr->RecvByteCount = ByteCountVar;
-
-	Platform = XGetPlatform_Info();
-
-	if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
-		((InstancePtr->IsRepeatedStart) !=0))
-	{
-		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
-						(u32)XIICPS_CR_HOLD_MASK);
-		IsHold = 1;
-	}
-
-	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
-
-	/*
-	 * Clear the interrupt status register before use it to monitor.
-	 */
-	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
-	/*
-	 * Set up the transfer size register so the slave knows how much
-	 * to send to us.
-	 */
-	if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) {
-		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
-				XIICPS_MAX_TRANSFER_SIZE);
-		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
-		UpdateTxSize = 1;
-	}else {
-		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
-			 ByteCountVar);
-	}
-
-	/*
-	 * Intrs keeps all the error-related interrupts.
-	 */
-	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
-			(u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
-	/*
-	 * Poll the interrupt status register to find the errors.
-	 */
-	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-	while ((InstancePtr->RecvByteCount > 0) &&
-			((IntrStatusReg & Intrs) == 0U)) {
-		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
-	    while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
-		    if (((InstancePtr->RecvByteCount <
-			    XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
-			    ((!InstancePtr->IsRepeatedStart) != 0) &&
-			    (UpdateTxSize == 0)) {
-				IsHold = 0;
-				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-						XIicPs_ReadReg(BaseAddr,
-						XIICPS_CR_OFFSET) &
-						(~XIICPS_CR_HOLD_MASK));
-			}
-			XIicPs_RecvByte(InstancePtr);
-		    ByteCountVar --;
-
-			if (Platform == XPLAT_ZYNQ) {
-			    if ((UpdateTxSize != 0) &&
-				    ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
-				    break;
-				}
-			}
-
-			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-		}
-		if (Platform == XPLAT_ZYNQ) {
-			if ((UpdateTxSize != 0) &&
-				((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
-			    /*  wait while fifo is full */
-			    while (XIicPs_ReadReg(BaseAddr,
-				    XIICPS_TRANS_SIZE_OFFSET) !=
-				    (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
-				}
-
-				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
-					XIICPS_MAX_TRANSFER_SIZE) {
-
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						XIICPS_MAX_TRANSFER_SIZE);
-				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
-							XIICPS_FIFO_DEPTH;
-				} else {
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						InstancePtr->RecvByteCount -
-						XIICPS_FIFO_DEPTH);
-					UpdateTxSize = 0;
-				    ByteCountVar = InstancePtr->RecvByteCount;
-				}
-			}
-		} else {
-		    if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
-				/*
-				 * Clear the interrupt status register before use it to
-				 * monitor.
-				 */
-				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
-				if ((InstancePtr->RecvByteCount) >
-					XIICPS_MAX_TRANSFER_SIZE) {
-
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						XIICPS_MAX_TRANSFER_SIZE);
-				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
-				} else {
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						InstancePtr->RecvByteCount);
-					UpdateTxSize = 0;
-				    ByteCountVar = InstancePtr->RecvByteCount;
-				}
-			}
-		}
-
-		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-	}
-
-	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
-		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
-						(~XIICPS_CR_HOLD_MASK));
-	}
-	if ((IntrStatusReg & Intrs) != 0x0U) {
-		Result = (s32)XST_FAILURE;
-	}
-	else {
-		Result =  (s32)XST_SUCCESS;
-	}
-
-	return Result;
-}
-
-/*****************************************************************************/
-/**
-* This function enables the slave monitor mode.
-*
-* It enables slave monitor in the control register and enables
-* slave ready interrupt. It then does an address transfer to slave.
-* Interrupt handler will signal the caller if slave responds to
-* the address transfer.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	SlaveAddr is the address of the slave we want to contact.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
-{
-	u32 BaseAddr;
-	u32 ConfigReg;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-
-	/* Clear transfer size register */
-	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
-
-	/*
-	 * Enable slave monitor mode in control register.
-	 */
-	ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
-	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
-			(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
-	ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
-
-	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
-
-	/*
-	 * Set up interrupt flag for slave monitor interrupt.
-	 * Dont enable NACK.
-	 */
-	XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
-
-	/*
-	 * Initialize the slave monitor register.
-	 */
-	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
-
-	/*
-	 * Set the slave address to start the slave address transmission.
-	 */
-	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
-	return;
-}
-
-/*****************************************************************************/
-/**
-* This function disables slave monitor mode.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
-{
-	u32 BaseAddr;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-
-	/*
-	 * Clear slave monitor control bit.
-	 */
-	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-		XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
-			& (~XIICPS_CR_SLVMON_MASK));
-
-	/*
-	 * Clear interrupt flag for slave monitor interrupt.
-	 */
-	XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
-
-	return;
-}
-
-/*****************************************************************************/
-/**
-* The interrupt handler for the master mode. It does the protocol handling for
-* the interrupt-driven transfers.
-*
-* Completion events and errors are signaled to upper layer for proper handling.
-*
-* <pre>
-* The interrupts that are handled are:
-* - DATA
-*	This case is handled only for master receive data.
-*	The master has to request for more data (if there is more data to
-*	receive) and read the data from the FIFO .
-*
-* - COMP
-*	If the Master is transmitting data and there is more data to be
-*	sent then the data is written to the FIFO. If there is no more data to
-*	be transmitted then a completion event is signalled to the upper layer
-*	by calling the callback handler.
-*
-*	If the Master is receiving data then the data is read from the FIFO and
-*	the Master has to request for more data (if there is more data to
-*	receive). If all the data has been received then a completion event
-*	is signalled to the upper layer by calling the callback handler.
-*	It is an error if the amount of received data is more than expected.
-*
-* - NAK and SLAVE_RDY
-*	This is signalled to the upper layer by calling the callback handler.
-*
-* - All Other interrupts
-*	These interrupts are marked as error. This is signalled to the upper
-*	layer by calling the callback handler.
-*
-* </pre>
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	None.
-*
-* @note 	None.
-*
-****************************************************************************/
-void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
-{
-	u32 IntrStatusReg;
-	u32 StatusEvent = 0U;
-	u32 BaseAddr;
-	u16 SlaveAddr;
-	s32 ByteCnt;
-	s32 IsHold;
-	u32 Platform;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-
-	Platform = XGetPlatform_Info();
-
-	/*
-	 * Read the Interrupt status register.
-	 */
-	IntrStatusReg = XIicPs_ReadReg(BaseAddr,
-					 (u32)XIICPS_ISR_OFFSET);
-
-	/*
-	 * Write the status back to clear the interrupts so no events are
-	 * missed while processing this interrupt.
-	 */
-	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
-
-	/*
-	 * Use the Mask register AND with the Interrupt Status register so
-	 * disabled interrupts are not processed.
-	 */
-	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
-
-	ByteCnt = InstancePtr->CurrByteCount;
-
-	IsHold = 0;
-	if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
-		IsHold = 1;
-	}
-
-	/*
-	 * Send
-	 */
-	if (((InstancePtr->IsSend) != 0) &&
-		((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
-		if (InstancePtr->SendByteCount > 0) {
-			MasterSendData(InstancePtr);
-		} else {
-			StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
-		}
-	}
-
-
-	/*
-	 * Receive
-	 */
-	if (((!(InstancePtr->IsSend))!= 0) &&
-		((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
-		(0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
-
-		while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
-				XIICPS_SR_RXDV_MASK) != 0U) {
-			if (((InstancePtr->RecvByteCount <
-				XIICPS_DATA_INTR_DEPTH)!= 0U)  && (IsHold != 0)  &&
-				((!InstancePtr->IsRepeatedStart)!= 0) &&
-				(InstancePtr->UpdateTxSize == 0)) {
-				IsHold = 0;
-				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-						XIicPs_ReadReg(BaseAddr,
-						XIICPS_CR_OFFSET) &
-						(~XIICPS_CR_HOLD_MASK));
-			}
-			XIicPs_RecvByte(InstancePtr);
-			ByteCnt--;
-
-			if (Platform == XPLAT_ZYNQ) {
-			    if ((InstancePtr->UpdateTxSize != 0) &&
-				    ((ByteCnt == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
-				    break;
-				}
-			}
-		}
-
-		if (Platform == XPLAT_ZYNQ) {
-			if ((InstancePtr->UpdateTxSize != 0) &&
-				((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
-				/* wait while fifo is full */
-				while (XIicPs_ReadReg(BaseAddr,
-					XIICPS_TRANS_SIZE_OFFSET) !=
-					(u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
-				}
-
-				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
-					XIICPS_MAX_TRANSFER_SIZE) {
-
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						XIICPS_MAX_TRANSFER_SIZE);
-					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
-							XIICPS_FIFO_DEPTH;
-				} else {
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						InstancePtr->RecvByteCount -
-						XIICPS_FIFO_DEPTH);
-					InstancePtr->UpdateTxSize = 0;
-					ByteCnt = InstancePtr->RecvByteCount;
-				}
-			}
-		} else {
-			if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
-				/*
-				 * Clear the interrupt status register before use it to
-				 * monitor.
-				 */
-				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-				SlaveAddr = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
-				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
-				if ((InstancePtr->RecvByteCount) >
-					XIICPS_MAX_TRANSFER_SIZE) {
-
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						XIICPS_MAX_TRANSFER_SIZE);
-					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
-				} else {
-					XIicPs_WriteReg(BaseAddr,
-						XIICPS_TRANS_SIZE_OFFSET,
-						InstancePtr->RecvByteCount);
-					InstancePtr->UpdateTxSize = 0;
-					ByteCnt = InstancePtr->RecvByteCount;
-				}
-				XIicPs_EnableInterrupts(BaseAddr,
-					(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
-					(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
-					(u32)XIICPS_IXR_ARB_LOST_MASK);
-			}
-		}
-		InstancePtr->CurrByteCount = ByteCnt;
-	}
-
-	if (((!(InstancePtr->IsSend)) != 0) &&
-		(0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
-		/*
-		 * If all done, tell the application.
-		 */
-		if (InstancePtr->RecvByteCount == 0){
-			if ((!(InstancePtr->IsRepeatedStart)) != 0) {
-				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-						XIicPs_ReadReg(BaseAddr,
-						XIICPS_CR_OFFSET) &
-						(~XIICPS_CR_HOLD_MASK));
-			}
-			StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
-		}
-	}
-
-
-	/*
-	 * Slave ready interrupt, it is only meaningful for master mode.
-	 */
-	if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
-		StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
-	}
-
-	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
-		if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
-			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-					XIicPs_ReadReg(BaseAddr,
-					XIICPS_CR_OFFSET) &
-					(~XIICPS_CR_HOLD_MASK));
-		}
-		StatusEvent |= XIICPS_EVENT_NACK;
-	}
-
-	/*
-	 * Arbitration lost interrupt
-	 */
-	if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
-		StatusEvent |= XIICPS_EVENT_ARB_LOST;
-	}
-
-	/*
-	 * All other interrupts are treated as error.
-	 */
-	if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
-			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
-			XIICPS_IXR_RX_OVR_MASK))) {
-		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
-			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-					XIicPs_ReadReg(BaseAddr,
-					XIICPS_CR_OFFSET) &
-					(~XIICPS_CR_HOLD_MASK));
-		}
-		StatusEvent |= XIICPS_EVENT_ERROR;
-	}
-
-	/*
-	 * Signal application if there are any events.
-	 */
-	if (StatusEvent != 0U) {
-		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
-					   StatusEvent);
-	}
-
-}
-
-/*****************************************************************************/
-/*
-* This function prepares a device to transfers as a master.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @param	Role specifies whether the device is sending or receiving.
-*
-* @return
-*		- XST_SUCCESS if everything went well.
-*		- XST_FAILURE if bus is busy.
-*
-* @note		Interrupts are always disabled, device which needs to use
-*		interrupts needs to setup interrupts after this call.
-*
-****************************************************************************/
-static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
-{
-	u32 ControlReg;
-	u32 BaseAddr;
-	u32 EnabledIntr = 0x0U;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
-
-
-	/*
-	 * Only check if bus is busy when repeated start option is not set.
-	 */
-	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
-		if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
-			return (s32)XST_FAILURE;
-		}
-	}
-
-	/*
-	 * Set up master, AckEn, nea and also clear fifo.
-	 */
-	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
-			(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
-
-	if (Role == RECVING_ROLE) {
-		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
-		EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK;
-	}else {
-		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
-	}
-	EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK;
-
-	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
-
-	XIicPs_DisableAllInterrupts(BaseAddr);
-
-	return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-* This function handles continuation of sending data. It is invoked
-* from interrupt handler.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-static void MasterSendData(XIicPs *InstancePtr)
-{
-	(void)TransmitFifoFill(InstancePtr);
-
-	/*
-	 * Clear hold bit if done, so stop can be sent out.
-	 */
-	if (InstancePtr->SendByteCount == 0) {
-
-		/*
-		 * If user has enabled repeated start as an option,
-		 * do not disable it.
-		 */
-		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
-
-			XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			(u32)XIICPS_CR_OFFSET,
-			XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-			(u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
-		}
-	}
-
-	return;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c
deleted file mode 100644
index 5d7427a48..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_options.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* Contains functions for the configuration of the XIccPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------  -------- -----------------------------------------------
-* 1.00a drg/jz  01/30/10 First release
-* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
-*			 to achieve I2C clock with minimum error.
-*			 This is a fix for CR #674195
-* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
-*			 This is fix for CR#704398 to remove warning.
-* 2.0   hk  03/07/14 Limited frequency set when 100KHz or 400KHz is
-*                    selected. This is a hardware limitation. CR#779290.
-* 2.1   hk  04/24/14 Fix for CR# 761060 - provision for repeated start.
-* 2.3	sk	10/07/14 Repeated start feature removed.
-* 3.0	sk	12/06/14 Implemented Repeated start feature.
-*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
-		u32 Option;
-		u32 Mask;
-} OptionsMap;
-
-static OptionsMap OptionsTable[] = {
-		{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
-		{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
-		{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
-		{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
-};
-
-#define XIICPS_NUM_OPTIONS      (sizeof(OptionsTable) / sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the IIC device driver. The options control
-* how the device behaves relative to the IIC bus. The device must be idle
-* rather than busy transferring data before setting these device options.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	Options contains the specified options to be set. This is a bit
-*		mask where a 1 means to turn the option on. One or more bit
-*		values may be contained in the mask. See the bit definitions
-*		named XIICPS_*_OPTION in xiicps.h.
-*
-* @return
-*		- XST_SUCCESS if options are successfully set.
-*		- XST_DEVICE_IS_STARTED if the device is currently transferring
-*		data. The transfer must complete or be aborted before setting
-*		options.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
-{
-	u32 ControlReg;
-	u32 Index;
-	u32 OptionsVar = Options;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-				      XIICPS_CR_OFFSET);
-
-	/*
-	 * If repeated start option is requested, set the flag.
-	 * The hold bit in CR will be written by driver when the next transfer
-	 * is initiated.
-	 */
-	if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) {
-		InstancePtr->IsRepeatedStart = 1;
-		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
-	}
-
-	/*
-	 * Loop through the options table, turning the option on.
-	 */
-	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
-		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
-			/*
-			 * 10-bit option is specially treated, because it is
-			 * using the 7-bit option, so turning it on means
-			 * turning 7-bit option off.
-			 */
-			if ((OptionsTable[Index].Option &
-				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
-				/* Turn 7-bit off */
-				ControlReg &= ~OptionsTable[Index].Mask;
-			} else {
-				/* Turn 7-bit on */
-				ControlReg |= OptionsTable[Index].Mask;
-			}
-		}
-	}
-
-	/*
-	 * Now write to the control register. Leave it to the upper layers
-	 * to restart the device.
-	 */
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
-			  ControlReg);
-
-	/*
-	 * Keep a copy of what options this instance has.
-	 */
-	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
-
-	return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function clears the options for the IIC device driver. The options
-* control how the device behaves relative to the IIC bus. The device must be
-* idle rather than busy transferring data before setting these device options.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	Options contains the specified options to be cleared. This is a
-*		bit mask where a 1 means to turn the option off. One or more bit
-*		values may be contained in the mask. See the bit definitions
-*		named XIICPS_*_OPTION in xiicps.h.
-*
-* @return
-*		- XST_SUCCESS if options are successfully set.
-*		- XST_DEVICE_IS_STARTED if the device is currently transferring
-*		data. The transfer must complete or be aborted before setting
-*		options.
-*
-* @note		None
-*
-******************************************************************************/
-s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
-{
-	u32 ControlReg;
-	u32 Index;
-	u32 OptionsVar = Options;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XIICPS_CR_OFFSET);
-
-	/*
-	 * If repeated start option is cleared, set the flag.
-	 * The hold bit in CR will be cleared by driver when the
-	 * following transfer ends.
-	 */
-	if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
-		InstancePtr->IsRepeatedStart = 0;
-		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
-	}
-
-	/*
-	 * Loop through the options table and clear the specified options.
-	 */
-	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
-		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
-
-			/*
-			 * 10-bit option is specially treated, because it is
-			 * using the 7-bit option, so clearing it means turning
-			 * 7-bit option on.
-			 */
-			if ((OptionsTable[Index].Option &
-				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
-
-				/* Turn 7-bit on */
-				ControlReg |= OptionsTable[Index].Mask;
-			} else {
-
-				/* Turn 7-bit off */
-				ControlReg &= ~OptionsTable[Index].Mask;
-			}
-		}
-	}
-
-
-	/*
-	 * Now write the control register. Leave it to the upper layers
-	 * to restart the device.
-	 */
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
-			  ControlReg);
-
-	/*
-	 * Keep a copy of what options this instance has.
-	 */
-	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the options for the IIC device. The options control how
-* the device behaves relative to the IIC bus.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	32 bit mask of the options, where a 1 means the option is on,
-*		and a 0 means to the option is off. One or more bit values may
-*		be contained in the mask. See the bit definitions named
-* 		XIICPS_*_OPTION in the file xiicps.h.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XIicPs_GetOptions(XIicPs *InstancePtr)
-{
-	u32 OptionsFlag = 0U;
-	u32 ControlReg;
-	u32 Index;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read control register to find which options are currently set.
-	 */
-	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-				      XIICPS_CR_OFFSET);
-
-	/*
-	 * Loop through the options table to determine which options are set.
-	 */
-	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
-		if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
-			OptionsFlag |= OptionsTable[Index].Option;
-		}
-		if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
-			OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
-		}
-	}
-
-	if (InstancePtr->IsRepeatedStart != 0 ) {
-		OptionsFlag |= XIICPS_REP_START_OPTION;
-	}
-	return OptionsFlag;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the serial clock rate for the IIC device. The device
-* must be idle rather than busy transferring data before setting these device
-* options.
-*
-* The data rate is set by values in the control register. The formula for
-* determining the correct register values is:
-* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
-* See the hardware data sheet for a full explanation of setting the serial
-* clock rate.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	FsclHz is the clock frequency in Hz. The two most common clock
-*		rates are 100KHz and 400KHz.
-*
-* @return
-*		- XST_SUCCESS if options are successfully set.
-*		- XST_DEVICE_IS_STARTED if the device is currently transferring
-*		data. The transfer must complete or be aborted before setting
-*		options.
-*		- XST_FAILURE if the Fscl frequency can not be set.
-*
-* @note		The clock can not be faster than the input clock divide by 22.
-*
-******************************************************************************/
-s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
-{
-	u32 Div_a;
-	u32 Div_b;
-	u32 ActualFscl;
-	u32 Temp;
-	u32 TempLimit;
-	u32 LastError;
-	u32 BestError;
-	u32 CurrentError;
-	u32 ControlReg;
-	u32 CalcDivA;
-	u32 CalcDivB;
-	u32 BestDivA = 0;
-	u32 BestDivB = 0;
-	u32 FsclHzVar = FsclHz;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(FsclHzVar > 0U);
-
-	if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
-					XIICPS_TRANS_SIZE_OFFSET)) {
-		return (s32)XST_DEVICE_IS_STARTED;
-	}
-
-	/*
-	 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
-	 */
-	Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
-
-	/*
-	 * If the answer is negative or 0, the Fscl input is out of range.
-	 */
-	if ((u32)(0U) == Temp) {
-		return (s32)XST_FAILURE;
-	}
-
-	/*
-	 * If frequency 400KHz is selected, 384.6KHz should be set.
-	 * If frequency 100KHz is selected, 90KHz should be set.
-	 * This is due to a hardware limitation.
-	 */
-	if(FsclHzVar > 384600U) {
-		FsclHzVar = 384600U;
-	}
-
-	if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) {
-		FsclHzVar = 90000U;
-	}
-
-	/*
-	 * TempLimit helps in iterating over the consecutive value of Temp to
-	 * find the closest clock rate achievable with divisors.
-	 * Iterate over the next value only if fractional part is involved.
-	 */
-	TempLimit = (((InstancePtr->Config.InputClockHz) %
-			((u32)22 * FsclHzVar)) != 	(u32)0x0U) ?
-						Temp + (u32)1U : Temp;
-	BestError = FsclHzVar;
-
-	BestDivA = 0U;
-	BestDivB = 0U;
-	for ( ; Temp <= TempLimit ; Temp++)
-	{
-		LastError = FsclHzVar;
-		CalcDivA = 0U;
-		CalcDivB = 0U;
-
-		for (Div_b = 0U; Div_b < 64U; Div_b++) {
-
-			Div_a = Temp / (Div_b + 1U);
-
-			if (Div_a != 0U){
-				Div_a = Div_a - (u32)1U;
-			}
-			if (Div_a > 3U){
-				continue;
-			}
-			ActualFscl = (InstancePtr->Config.InputClockHz) /
-						(22U * (Div_a + 1U) * (Div_b + 1U));
-
-			if (ActualFscl > FsclHzVar){
-				CurrentError = (ActualFscl - FsclHzVar);}
-			else{
-				CurrentError = (FsclHzVar - ActualFscl);}
-
-			if (LastError > CurrentError) {
-				CalcDivA = Div_a;
-				CalcDivB = Div_b;
-				LastError = CurrentError;
-			}
-		}
-
-		/*
-		 * Used to capture the best divisors.
-		 */
-		if (LastError < BestError) {
-			BestError = LastError;
-			BestDivA = CalcDivA;
-			BestDivB = CalcDivB;
-		}
-	}
-
-
-	/*
-	 * Read the control register and mask the Divisors.
-	 */
-	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  (u32)XIICPS_CR_OFFSET);
-	ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
-	ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
-		(BestDivB << XIICPS_CR_DIV_B_SHIFT);
-
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
-			  ControlReg);
-
-	return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the serial clock rate for the IIC device. The device
-* must be idle rather than busy transferring data before setting these device
-* options.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	The value of the IIC clock to the nearest Hz based on the
-*		control register settings. The actual value may not be exact to
-*		to integer math rounding errors.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XIicPs_GetSClk(XIicPs *InstancePtr)
-{
-	u32 ControlReg;
-	u32 ActualFscl;
-	u32 Div_a;
-	u32 Div_b;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XIICPS_CR_OFFSET);
-
-	Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
-	Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
-
-	ActualFscl = (InstancePtr->Config.InputClockHz) /
-		(22U * (Div_a + 1U) * (Div_b + 1U));
-
-	return ActualFscl;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c
deleted file mode 100644
index 2d9e0e35e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_selftest.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* This component contains the implementation of selftest functions for the
-* XIicPs driver component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 1.00a sdm    09/22/11 Removed unused code
-* 3.0	sk	   11/03/14 Removed TimeOut Register value check
-*			   01/31/15	Modified the code according to MISRAC 2012 Compliant.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-#define REG_TEST_VALUE    0x00000005U
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device. The self-test is destructive in that
-* a reset of the device is performed in order to check the reset values of
-* the registers and to get the device into a known state.
-*
-* Upon successful return from the self-test, the device is reset.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_REGISTER_ERROR indicates a register did not read or write
-*		correctly
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XIicPs_SelfTest(XIicPs *InstancePtr)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	/*
-	 * All the IIC registers should be in their default state right now.
-	 */
-	if ((XIICPS_CR_RESET_VALUE !=
-		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XIICPS_CR_OFFSET)) ||
-		(XIICPS_IXR_ALL_INTR_MASK !=
-		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XIICPS_IMR_OFFSET))) {
-		return (s32)XST_FAILURE;
-	}
-
-	XIicPs_Reset(InstancePtr);
-
-	/*
-	 * Write, Read then write a register
-	 */
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
-
-	if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
-						   XIICPS_SLV_PAUSE_OFFSET)) {
-		return (s32)XST_FAILURE;
-	}
-
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XIICPS_SLV_PAUSE_OFFSET, 0U);
-
-	XIicPs_Reset(InstancePtr);
-
-	return (s32)XST_SUCCESS;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c
deleted file mode 100644
index 40ee7733e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_sinit.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* The implementation of the XIicPs component's static initialization
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- --------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 3.00	sk	   01/31/15	Modified the code according to MISRAC 2012 Compliant.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param	DeviceId contains the ID of the device to look up the
-*		configuration for.
-*
-* @return	A pointer to the configuration found or NULL if the specified
-*		device ID was not found. See xiicps.h for the definition of
-*		XIicPs_Config.
-*
-* @note		None.
-*
-******************************************************************************/
-XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
-{
-	XIicPs_Config *CfgPtr = NULL;
-	s32 Index;
-
-	for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
-		if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XIicPs_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XIicPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c
deleted file mode 100644
index 074b5ea2e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xiicps_slave.c
-* @addtogroup iicps_v3_0
-* @{
-*
-* Handles slave transfers
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --  -------- ---------------------------------------------
-* 1.00a jz  01/30/10 First release
-* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
-* 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-extern s32 TransmitFifoFill(XIicPs *InstancePtr);
-
-static s32 SlaveRecvData(XIicPs *InstancePtr);
-
-/************************* Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function sets up the device to be a slave.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	SlaveAddr is the address of the slave we are receiving from.
-*
-* @return	None.
-*
-* @note
-*	Interrupt is always enabled no matter the tranfer is interrupt-
-*	driven or polled mode. Whether device will be interrupted or not
-*	depends on whether the device is connected to an interrupt
-*	controller and interrupt for the device is enabled.
-*
-****************************************************************************/
-void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
-{
-	u32 ControlReg;
-	u32 BaseAddr;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-
-	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
-
-	/*
-	 * Set up master, AckEn, nea and also clear fifo.
-	 */
-	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
-	ControlReg |= (u32)XIICPS_CR_NEA_MASK;
-	ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
-
-	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
-			  ControlReg);
-
-	XIicPs_DisableAllInterrupts(BaseAddr);
-
-	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
-	return;
-}
-
-/*****************************************************************************/
-/**
-* This function setup a slave interrupt-driven send. It set the repeated
-* start for the device is the tranfer size is larger than FIFO depth.
-* Data processing for the send is initiated by the interrupt handler.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the send buffer.
-* @param	ByteCount is the number of bytes to be sent.
-*
-* @return	None.
-*
-* @note		This send routine is for interrupt-driven transfer only.
-*
-****************************************************************************/
-void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
-	u32 BaseAddr;
-
-	/*
-	 * Assert validates the input arguments
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(MsgPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	InstancePtr->SendBufferPtr = MsgPtr;
-	InstancePtr->SendByteCount = ByteCount;
-	InstancePtr->RecvBufferPtr = NULL;
-
-	XIicPs_EnableInterrupts(BaseAddr,
-			(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
-			(u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
-			(u32)XIICPS_IXR_TX_OVR_MASK);
-}
-
-/*****************************************************************************/
-/**
-* This function setup a slave interrupt-driven receive.
-* Data processing for the receive is handled by the interrupt handler.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the receive buffer.
-* @param	ByteCount is the number of bytes to be received.
-*
-* @return	None.
-*
-* @note		This routine is for interrupt-driven transfer only.
-*
-****************************************************************************/
-void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(MsgPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-
-	InstancePtr->RecvBufferPtr = MsgPtr;
-	InstancePtr->RecvByteCount = ByteCount;
-	InstancePtr->SendBufferPtr = NULL;
-
-	XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
-		(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
-		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
-		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
-
-}
-
-/*****************************************************************************/
-/**
-* This function sends  a buffer in polled mode as a slave.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the send buffer.
-* @param	ByteCount is the number of bytes to be sent.
-*
-* @return
-*		- XST_SUCCESS if everything went well.
-*		- XST_FAILURE if master sends us data or master terminates the
-*		transfer before all data has sent out.
-*
-* @note		This send routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
-	u32 IntrStatusReg;
-	u32 StatusReg;
-	u32 BaseAddr;
-	s32 Tmp;
-	s32 BytesToSend;
-	s32 Error = 0;
-	s32 Status = (s32)XST_SUCCESS;
-	u32 Value;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(MsgPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	InstancePtr->SendBufferPtr = MsgPtr;
-	InstancePtr->SendByteCount = ByteCount;
-
-	/*
-	 * Use RXRW bit in status register to wait master to start a read.
-	 */
-	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-	while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
-				((!Error) != 0)) {
-
-		/*
-		 * If master tries to send us data, it is an error.
-		 */
-		if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
-			Error = 1;
-		}
-
-		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-	}
-
-	if (Error != 0) {
-		Status = (s32)XST_FAILURE;
-	} else {
-
-		/*
-		 * Clear the interrupt status register.
-		 */
-		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-		XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-		/*
-		 * Send data as long as there is more data to send and
-		 * there are no errors.
-		 */
-		Value = (InstancePtr->SendByteCount > (s32)0) &&
-						((!Error) != 0);
-		while (Value != (u32)0x00U) {
-
-			/*
-			 * Find out how many can be sent.
-			 */
-			BytesToSend = InstancePtr->SendByteCount;
-			if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
-				BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
-			}
-
-			for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
-				XIicPs_SendByte(InstancePtr);
-			}
-
-			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
-			/*
-			 * Wait for master to read the data out of fifo.
-			 */
-			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
-							((!Error) != 0)) {
-
-				/*
-				 * If master terminates the transfer before all data is
-				 * sent, it is an error.
-				 */
-				IntrStatusReg = XIicPs_ReadReg(BaseAddr,
-				XIICPS_ISR_OFFSET);
-				if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
-					Error = 1;
-				}
-
-				/* Clear ISR.
-				 */
-				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
-							IntrStatusReg);
-
-				StatusReg = XIicPs_ReadReg(BaseAddr,
-						XIICPS_SR_OFFSET);
-			}
-			Value = (InstancePtr->SendByteCount > (s32)0U) &&
-							((!Error) != 0);
-		}
-	}
-	if (Error != 0) {
-	Status = (s32)XST_FAILURE;
-	}
-
-	return Status;
-}
-/*****************************************************************************/
-/**
-* This function receives a buffer in polled mode as a slave.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-* @param	MsgPtr is the pointer to the receive buffer.
-* @param	ByteCount is the number of bytes to be received.
-*
-* @return
-*		- XST_SUCCESS if everything went well.
-*		- XST_FAILURE if timed out.
-*
-* @note		This receive routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
-	u32 IntrStatusReg;
-	u32 StatusReg;
-	u32 BaseAddr;
-	s32 Count;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(MsgPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-	InstancePtr->RecvBufferPtr = MsgPtr;
-	InstancePtr->RecvByteCount = ByteCount;
-
-	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
-	/*
-	 * Clear the interrupt status register.
-	 */
-	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-	/*
-	 * Clear the status register.
-	 */
-	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-	XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
-
-	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-	Count = InstancePtr->RecvByteCount;
-	while (Count > (s32)0) {
-
-		/* Wait for master to put data */
-		while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
-		    StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
-			/*
-			 * If master terminates the transfer before we get all
-			 * the data or the master tries to read from us,
-			 * it is an error.
-			 */
-			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
-						XIICPS_ISR_OFFSET);
-			if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
-					XIICPS_IXR_COMP_MASK))!=0x0U) &&
-				((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
-				((InstancePtr->RecvByteCount > 0) != 0x0U)) {
-
-				return (s32)XST_FAILURE;
-			}
-
-			/*
-			 * Clear the interrupt status register.
-			 */
-			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
-			IntrStatusReg);
-		}
-
-		/*
-		 * Read all data from FIFO.
-		 */
-		while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
-			 ((InstancePtr->RecvByteCount > 0) != 0x0U)){
-
-			XIicPs_RecvByte(InstancePtr);
-
-			StatusReg = XIicPs_ReadReg(BaseAddr,
-				XIICPS_SR_OFFSET);
-		}
-		Count = InstancePtr->RecvByteCount;
-	}
-
-	return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* The interrupt handler for slave mode. It does the protocol handling for
-* the interrupt-driven transfers.
-*
-* Completion events and errors are signaled to upper layer for proper
-* handling.
-*
-* <pre>
-*
-* The interrupts that are handled are:
-* - DATA
-*	If the instance is sending, it means that the master wants to read more
-*	data from us. Send more data, and check whether we are done with this
-*	send.
-*
-*	If the instance is receiving, it means that the master has writen
-* 	more data to us. Receive more data, and check whether we are done with
-*	with this receive.
-*
-* - COMP
-*	This marks that stop sequence has been sent from the master, transfer
-*	is about to terminate. However, for receiving, the master may have
-*	written us some data, so receive that first.
-*
-*	It is an error if the amount of transfered data is less than expected.
-*
-* - NAK
-*	This marks that master does not want our data. It is for send only.
-*
-* - Other interrupts
-*	These interrupts are marked as error.
-*
-* </pre>
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	None.
-*
-* @note 	None.
-*
-****************************************************************************/
-void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
-{
-	u32 IntrStatusReg;
-	u32 IsSend = 0U;
-	u32 StatusEvent = 0U;
-	s32 LeftOver;
-	u32 BaseAddr;
-
-	/*
-	 * Assert validates the input arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-
-	/*
-	 * Read the Interrupt status register.
-	 */
-	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-
-	/*
-	 * Write the status back to clear the interrupts so no events are missed
-	 * while processing this interrupt.
-	 */
-	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-	/*
-	 * Use the Mask register AND with the Interrupt Status register so
-	 * disabled interrupts are not processed.
-	 */
-	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
-
-	/*
-	 * Determine whether the device is sending.
-	 */
-	if (InstancePtr->RecvBufferPtr == NULL) {
-		IsSend = 1U;
-	}
-
-	/* Data interrupt
-	 *
-	 * This means master wants to do more data transfers.
-	 * Also check for completion of transfer, signal upper layer if done.
-	 */
-	if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
-		if (IsSend != 0x0U) {
-			LeftOver = TransmitFifoFill(InstancePtr);
-				/*
-				 * We may finish send here
-				 */
-				if (LeftOver == 0) {
-					StatusEvent |=
-						XIICPS_EVENT_COMPLETE_SEND;
-				}
-		} else {
-			LeftOver = SlaveRecvData(InstancePtr);
-
-			/* We may finish the receive here */
-			if (LeftOver == 0) {
-				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
-			}
-		}
-	}
-
-	/*
-	 * Complete interrupt.
-	 *
-	 * In slave mode, it means the master has done with this transfer, so
-	 * we signal the application using completion event.
-	 */
-	if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
-		if (IsSend != 0x0U) {
-			if (InstancePtr->SendByteCount > 0) {
-				StatusEvent |= XIICPS_EVENT_ERROR;
-			}else {
-				StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
-			}
-		} else {
-			LeftOver = SlaveRecvData(InstancePtr);
-			if (LeftOver > 0) {
-				StatusEvent |= XIICPS_EVENT_ERROR;
-			} else {
-				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
-			}
-		}
-	}
-
-	/*
-	 * Nack interrupt, pass this information to application.
-	 */
-	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
-		StatusEvent |= XIICPS_EVENT_NACK;
-	}
-
-	/*
-	 * All other interrupts are treated as error.
-	 */
-	if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
-				XIICPS_IXR_RX_UNF_MASK |
-				XIICPS_IXR_TX_OVR_MASK |
-				XIICPS_IXR_RX_OVR_MASK))){
-
-		StatusEvent |= XIICPS_EVENT_ERROR;
-	}
-
-	/*
-	 * Signal application if there are any events.
-	 */
-	if (0U != StatusEvent) {
-		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
-					   StatusEvent);
-	}
-}
-
-/*****************************************************************************/
-/*
-*
-* This function handles continuation of receiving data. It is invoked
-* from interrupt handler.
-*
-* @param	InstancePtr is a pointer to the XIicPs instance.
-*
-* @return	Number of bytes still expected by the instance.
-*
-* @note		None.
-*
-****************************************************************************/
-static s32 SlaveRecvData(XIicPs *InstancePtr)
-{
-	u32 StatusReg;
-	u32 BaseAddr;
-
-	BaseAddr = InstancePtr->Config.BaseAddress;
-
-	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
-	while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
-			((InstancePtr->RecvByteCount > 0) != 0x0U)) {
-		XIicPs_RecvByte(InstancePtr);
-		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-	}
-
-	return InstancePtr->RecvByteCount;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile
new file mode 100644
index 000000000..8c16c35ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xiicps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling iicps"
+
+xiicps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xiicps_includes
+
+xiicps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c
new file mode 100644
index 000000000..1c6819152
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains implementation of required functions for the XIicPs driver.
+* See xiicps.h for detailed description of the device and driver.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.00a sdm     09/21/11 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* 2.1   hk      04/25/14 Explicitly reset CR and clear FIFO in Abort function
+*                        and state the same in the comments. CR# 784254.
+*                        Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk		10/07/14 Repeated start feature removed.
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+* 						 in XIicPs_Reset.
+*				12/06/14 Implemented Repeated start feature.
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn		05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef, u32 StatusEvent);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XIicPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Device is disabled
+*   - Slave mode
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific IIC device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return	The return value is XST_SUCCESS if successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
+				  u32 EffectiveAddr)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->StatusHandler = StubHandler;
+	InstancePtr->CallBackRef = NULL;
+
+	InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the IIC device to get it into its initial state. It is expected
+	 * that device configuration will take place after this initialization
+	 * is done, but before the device is started.
+	 */
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	/* Initialize repeated start flag to 0 */
+	InstancePtr->IsRepeatedStart = 0;
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Check whether the I2C bus is busy
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* 		- TRUE if the bus is busy.
+*		- FALSE if the bus is not busy.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	s32	Status;
+
+	StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_SR_OFFSET);
+	if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
+		Status = (s32)TRUE;
+	}else {
+		Status = (s32)FALSE;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference.
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef, u32 StatusEvent)
+{
+	(void) ((void *)CallBackRef);
+	(void) StatusEvent;
+	Xil_AssertVoidAlways();
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
+* cleared.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Abort(XIicPs *InstancePtr)
+{
+	u32 IntrMaskReg;
+	u32 IntrStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enter a critical section, so disable the interrupts while we clear
+	 * the FIFO and the status register.
+	 */
+	IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_IMR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+
+	/*
+	 * Reset the settings in config register and clear the FIFOs.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
+
+	/*
+	 * Read, then write the interrupt status to make sure there are no
+	 * pending interrupts.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Restore the interrupt state.
+	 */
+	IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IER_OFFSET, IntrMaskReg);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the IIC device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization.  Any data transfer that is in progress is
+* aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and reenabling interrupts for the IIC device after the reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Reset(XIicPs *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress.
+	 */
+	XIicPs_Abort(InstancePtr);
+
+	/*
+	 * Reset any values so the software state matches the hardware device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
+			  XIICPS_IXR_ALL_INTR_MASK);
+
+}
+/*****************************************************************************/
+/**
+* Put more data into the transmit FIFO, number of bytes is ether expected
+* number of bytes for this transfer or available space in FIFO, which ever
+* is less.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes left for this instance.
+*
+* @note		This is function is shared by master and slave.
+*
+******************************************************************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr)
+{
+	u8 AvailBytes;
+	s32 LoopCnt;
+	s32 NumBytesToSend;
+
+	/*
+	 * Determine number of bytes to write to FIFO.
+	 */
+	AvailBytes = (u8)XIICPS_FIFO_DEPTH -
+		(u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_TRANS_SIZE_OFFSET);
+
+	if (InstancePtr->SendByteCount > (s32)AvailBytes) {
+		NumBytesToSend = (s32)AvailBytes;
+	} else {
+		NumBytesToSend = InstancePtr->SendByteCount;
+	}
+
+	/*
+	 * Fill FIFO with amount determined above.
+	 */
+	for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
+		XIicPs_SendByte(InstancePtr);
+	}
+
+	return InstancePtr->SendByteCount;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h
new file mode 100644
index 000000000..b26193486
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h
@@ -0,0 +1,421 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+* @addtogroup iicps_v3_0
+* @{
+* @details
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface.  The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+*      the static configuration structure defined in xiicps_g.c. This is
+*      setup by the tools. For some operating systems the config structure
+*      will be initialized by the software and this call is not needed.
+*
+*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base
+*     address replaces the physical address in the configuration
+*     structure.
+*
+* <b>Multiple Masters</b>
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* <b>Multiple Slaves</b>
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* <b>Addressing</b>
+*
+* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* <b>FIFO Size </b>
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* <b>Data Rates</b>
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* <b>Polled Mode Operation</b>
+*
+* This driver supports polled mode transfers.
+*
+* <b>Interrupts</b>
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* <b>Bus Busy</b>
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*<b>Repeated Start</b>
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIICPS_H       /* prevent circular inclusions */
+#define XIICPS_H       /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC.  Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION	0x01U  /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION	0x02U  /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION		0x04U  /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION		0x08U  /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver.  These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND	0x0001U  /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV	0x0002U  /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT		0x0004U  /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR			0x0008U  /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST		0x0010U  /**< Arbitration lost */
+#define XIICPS_EVENT_NACK			0x0020U  /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY		0x0040U  /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR			0x0080U  /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR			0x0100U  /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF			0x0200U  /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE		1  /**< Transfer direction is sending */
+#define RECVING_ROLE		0  /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE	(u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;     /**< Unique ID  of device */
+	u32 BaseAddress;  /**< Base address of the device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIicPs_Config Config;	/* Configuration structure */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Options set in the device */
+
+	u8 *SendBufferPtr;	/* Pointer to send buffer */
+	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
+	s32 SendByteCount;	/* Number of bytes still expected to send */
+	s32 RecvByteCount;	/* Number of bytes still expected to receive */
+	s32 CurrByteCount;	/* No. of bytes expected in current transfer */
+
+	s32 UpdateTxSize;	/* If tx size register has to be updated */
+	s32 IsSend;		/* Whether master is sending or receiving */
+	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
+
+	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr)					\
+{									\
+	u8 Data;							\
+	Data = *((InstancePtr)->SendBufferPtr);				\
+	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
+			 + (u32)(XIICPS_DATA_OFFSET), 			\
+					(u32)(Data));			\
+	(InstancePtr)->SendBufferPtr += 1;				\
+	(InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr)					\
+{									\
+	u8 *Data, Value;						\
+	Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress	\
+		  + (u32)XIICPS_DATA_OFFSET));  			\
+	Data = &Value;							\
+	*(InstancePtr)->RecvBufferPtr = *Data;				\
+	(InstancePtr)->RecvBufferPtr += 1;				\
+	 (InstancePtr)->RecvByteCount --; 				\
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+				  u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c
new file mode 100644
index 000000000..f449e0ed6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c
@@ -0,0 +1,61 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xiicps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIicPs_Config XIicPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_I2C_0_DEVICE_ID,
+		XPAR_PSU_I2C_0_BASEADDR,
+		XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_I2C_1_DEVICE_ID,
+		XPAR_PSU_I2C_1_BASEADDR,
+		XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c
new file mode 100644
index 000000000..a1dba8e62
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains implementation of required functions for providing the reset sequence
+* to the i2c interface
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.04a kpc     11/07/13 First release
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given I2c interface by
+* configuring the appropriate control bits in the I2c specifc registers
+* the i2cps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status
+*	Clear FIFO's and disable hold bit
+*	Clear the line status
+*	Update relevant config registers with reset values
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* I2c controller
+******************************************************************************/
+void XIicPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Disable all the interrupts */
+	XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+	/* Clear the interrupt status */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
+	/* Clear the hold bit,master enable bit and ack bit */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
+	RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
+	/* Clear the fifos */
+	RegVal |= XIICPS_CR_CLR_FIFO_MASK;
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
+	/* Clear the timeout register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	/* Clear the transfer size register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+	/* Clear the status register */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
+	/* Update the configuraqtion register with reset value */
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h
new file mode 100644
index 000000000..3b00cf8b1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+* @addtogroup iicps_v3_0
+* @{
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIICPS_HW_H		/* prevent circular inclusions */
+#define XIICPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET			0x00U  /**< 32-bit Control */
+#define XIICPS_SR_OFFSET			0x04U  /**< Status */
+#define XIICPS_ADDR_OFFSET			0x08U  /**< IIC Address */
+#define XIICPS_DATA_OFFSET			0x0CU  /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET			0x10U  /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET	0x14U  /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET		0x18U  /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET		0x1CU  /**< Time Out */
+#define XIICPS_IMR_OFFSET			0x20U  /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET			0x24U  /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET			0x28U  /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK	0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT			14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX				 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK	0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT			 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK	0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK	0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK		0x00000010U /**<  Hold bus 1=Hold scl,
+												0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK	0x00000008U /**< Enable TX of ACK when
+												Master receiver*/
+#define XIICPS_CR_NEA_MASK		0x00000004U /**< Addressing Mode 1=7 bit,
+												0=10 bit */
+#define XIICPS_CR_MS_MASK		0x00000002U /**< Master mode bit 1=Master,
+												0=Slave */
+#define XIICPS_CR_RD_WR_MASK	0x00000001U /**< Read or Write Master
+												transfer  0=Transmitter,
+												1=Receiver*/
+#define XIICPS_CR_RESET_VALUE			 0U /**< Reset value of the Control
+												register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK		0x00000100U  /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK	0x00000080U  /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK		0x00000040U  /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK		0x00000020U  /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK		0x00000008U  /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * <b>IIC Interrupt Status Register</b>
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists.  Other flags are
+ *   edge triggered, which means they are set one the interrupt condition occurs
+ *   then remain set until they are cleared by software.
+ *   The interrupts are cleared by writing a one to the interrupt bit position
+ *   in the Interrupt Status Register. Read/Write.
+ *
+ * <b>IIC Interrupt Enable Register</b>
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register.  Write only.
+ *
+ * <b>IIC Interrupt Disable Register </b>
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * <b>IIC Interrupt Mask Register</b>
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK  0x00000200U	 /**< Arbitration Lost Interrupt
+													mask */
+#define XIICPS_IXR_RX_UNF_MASK    0x00000080U	 /**< FIFO Recieve Underflow
+													Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK    0x00000040U	 /**< Transmit Overflow
+													Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK    0x00000020U	 /**< Receive Overflow Interrupt
+													mask */
+#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U	 /**< Monitored Slave Ready
+													Interrupt mask */
+#define XIICPS_IXR_TO_MASK        0x00000008U	 /**< Transfer Time Out
+													Interrupt mask */
+#define XIICPS_IXR_NACK_MASK      0x00000004U	 /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK      0x00000002U	 /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK      0x00000001U	 /**< Transfer Complete
+													Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU	 /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK  0x000002FFU	 /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+*   - Master transmitter mode: number of data bytes still not transmitted minus
+*     one
+*   - Master receiver mode: number of data bytes that are still expected to be
+*     received
+*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
+*     master terminates the transfer
+*   - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK    0x000000FFU    /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE   0x000000FFU    /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+	XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	Current bit mask that represents currently enabled interrupts.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be enabled.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be disabled.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		(IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c
new file mode 100644
index 000000000..5231049c7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_intr.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains functions of the XIicPs driver for interrupt-driven transfers.
+* See xiicps.h for a detailed description of the device and driver.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 3.00	sk		01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function, the status handler, which the
+* driver calls when it encounters conditions that should be reported to the
+* higher layer software. The handler executes in an interrupt context, so
+* the amount of processing should be minimized
+*
+* Refer to the xiicps.h file for a list of the Callback events. The events are
+* defined to start with XIICPS_EVENT_*.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FunctionPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should finish its
+* work quickly.
+*
+******************************************************************************/
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FunctionPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FunctionPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c
new file mode 100644
index 000000000..7824d86b6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c
@@ -0,0 +1,991 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_master.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Handles master mode transfers.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---  -------- ---------------------------------------------
+* 1.00a jz   01/30/10 First release
+* 1.00a sdm  09/21/11 Updated the XIicPs_SetupMaster to not check for
+*		      Bus Busy condition when the Hold Bit is set.
+* 1.01a sg   03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*		      check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 2.0   hk   03/07/14 Added check for error status in the while loop that
+*                     checks for completion. CR# 762244, 764875.
+* 2.1   hk   04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                     Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk   08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                     read mode and clear transfer size register.
+*                     Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	 10/06/14 Fill transmit fifo before address register when sending.
+* 					  Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
+* 					  Repeated start feature removed.
+* 3.0	sk	 12/06/14 Implemented Repeated start feature.
+*			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			 02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
+static void MasterSendData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven send in master mode.
+*
+* It tries to send the first FIFO-full of data, then lets the interrupt
+* handler to handle the rest of the data if there is any.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+ ****************************************************************************/
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 Platform = XGetPlatform_Info();
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->IsSend = 1;
+
+	/*
+	 * Set repeated start if sending more than FIFO of data.
+	 */
+	if (((InstancePtr->IsRepeatedStart) != 0)||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+				(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Setup as a master sending role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to notify the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	/* Clear the Hold bit in ZYNQ if receive byte count is less than
+	 * the FIFO depth to get the completion interrupt properly.
+	 */
+	if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
+				(u32)(~XIICPS_CR_HOLD_MASK));
+	}
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven receive in master mode.
+*
+* It sets the transfer size register so the slave can send data to us.
+* The rest of the work is managed by interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note		This receive routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->IsSend = 0;
+
+	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Initialize for a master receiving role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+	/*
+	 * Setup the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		InstancePtr->UpdateTxSize = 1;
+	}else {
+		InstancePtr->CurrByteCount = ByteCount;
+		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
+			 (u32)ByteCount);
+		InstancePtr->UpdateTxSize = 0;
+	}
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to signal the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode send in master mode.
+*
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+		 s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	u32 Intrs;
+	_Bool Value;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	if (((InstancePtr->IsRepeatedStart) != 0) ||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
+		(u32)XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Transmit first FIFO full of data.
+	 */
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Continue sending as long as there is more data and
+	 * there are no errors.
+	 */
+	Value = ((InstancePtr->SendByteCount > (s32)0) &&
+		((IntrStatusReg & Intrs) == (u32)0U));
+	while (Value != FALSE) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait until transmit FIFO is empty.
+		 */
+		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+				((IntrStatusReg & Intrs) == (u32)0U));
+			continue;
+		}
+
+		/*
+		 * Send more data out through transmit FIFO.
+		 */
+		(void)TransmitFifoFill(InstancePtr);
+		Value = ((InstancePtr->SendByteCount > (s32)0) &&
+			((IntrStatusReg & Intrs) == (u32)0U));
+	}
+
+	/*
+	 * Check for completion of transfer.
+	 */
+	while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		/*
+		 * If there is an error, tell the caller.
+		 */
+		if ((IntrStatusReg & Intrs) != 0U) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+				s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 Intrs;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Result;
+	s32 IsHold;
+	s32 UpdateTxSize = 0;
+	s32 ByteCountVar = ByteCount;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCountVar;
+
+	Platform = XGetPlatform_Info();
+
+	if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+		IsHold = 1;
+	} else {
+		IsHold = 0;
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Set up the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCountVar);
+	}
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
+			(u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
+	/*
+	 * Poll the interrupt status register to find the errors.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	while ((InstancePtr->RecvByteCount > 0) &&
+			((IntrStatusReg & Intrs) == 0U)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	    while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
+		    if (((InstancePtr->RecvByteCount <
+			    XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
+			    ((!InstancePtr->IsRepeatedStart) != 0) &&
+			    (UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+		    ByteCountVar --;
+
+			if (Platform == (u32)XPLAT_ZYNQ) {
+			    if ((UpdateTxSize != 0) &&
+				    (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+				    break;
+				}
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		}
+		if (Platform == (u32)XPLAT_ZYNQ) {
+			if ((UpdateTxSize != 0) &&
+				(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+			    /*  wait while fifo is full */
+			    while (XIicPs_ReadReg(BaseAddr,
+				    XIICPS_TRANS_SIZE_OFFSET) !=
+				    (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+		    if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		}
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+	if ((IntrStatusReg & Intrs) != 0x0U) {
+		Result = (s32)XST_FAILURE;
+	}
+	else {
+		Result =  (s32)XST_SUCCESS;
+	}
+
+	return Result;
+}
+
+/*****************************************************************************/
+/**
+* This function enables the slave monitor mode.
+*
+* It enables slave monitor in the control register and enables
+* slave ready interrupt. It then does an address transfer to slave.
+* Interrupt handler will signal the caller if slave responds to
+* the address transfer.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we want to contact.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/* Clear transfer size register */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+
+	/*
+	 * Enable slave monitor mode in control register.
+	 */
+	ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
+	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
+			(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
+	ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Set up interrupt flag for slave monitor interrupt.
+	 * Dont enable NACK.
+	 */
+	XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
+
+	/*
+	 * Initialize the slave monitor register.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
+
+	/*
+	 * Set the slave address to start the slave address transmission.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function disables slave monitor mode.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
+{
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Clear slave monitor control bit.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+		XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+			& (~XIICPS_CR_SLVMON_MASK));
+
+	/*
+	 * Clear interrupt flag for slave monitor interrupt.
+	 */
+	XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the master mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper handling.
+*
+* <pre>
+* The interrupts that are handled are:
+* - DATA
+*	This case is handled only for master receive data.
+*	The master has to request for more data (if there is more data to
+*	receive) and read the data from the FIFO .
+*
+* - COMP
+*	If the Master is transmitting data and there is more data to be
+*	sent then the data is written to the FIFO. If there is no more data to
+*	be transmitted then a completion event is signalled to the upper layer
+*	by calling the callback handler.
+*
+*	If the Master is receiving data then the data is read from the FIFO and
+*	the Master has to request for more data (if there is more data to
+*	receive). If all the data has been received then a completion event
+*	is signalled to the upper layer by calling the callback handler.
+*	It is an error if the amount of received data is more than expected.
+*
+* - NAK and SLAVE_RDY
+*	This is signalled to the upper layer by calling the callback handler.
+*
+* - All Other interrupts
+*	These interrupts are marked as error. This is signalled to the upper
+*	layer by calling the callback handler.
+*
+* </pre>
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 StatusEvent = 0U;
+	u32 BaseAddr;
+	u16 SlaveAddr;
+	s32 ByteCnt;
+	s32 IsHold;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	Platform = XGetPlatform_Info();
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					 (u32)XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are
+	 * missed while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
+
+	ByteCnt = InstancePtr->CurrByteCount;
+
+	IsHold = 0;
+	if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
+		IsHold = 1;
+	}
+
+	/*
+	 * Send
+	 */
+	if (((InstancePtr->IsSend) != 0) &&
+		((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
+		if (InstancePtr->SendByteCount > 0) {
+			MasterSendData(InstancePtr);
+		} else {
+			StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+		}
+	}
+
+
+	/*
+	 * Receive
+	 */
+	if (((!(InstancePtr->IsSend))!= 0) &&
+		((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
+		(0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
+
+		while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
+				XIICPS_SR_RXDV_MASK) != 0U) {
+			if (((InstancePtr->RecvByteCount <
+				XIICPS_DATA_INTR_DEPTH)!= 0U)  && (IsHold != 0)  &&
+				((!InstancePtr->IsRepeatedStart)!= 0) &&
+				(InstancePtr->UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+			ByteCnt--;
+
+			if (Platform == (u32)XPLAT_ZYNQ) {
+			    if ((InstancePtr->UpdateTxSize != 0) &&
+				    (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+				    break;
+				}
+			}
+		}
+
+		if (Platform == (u32)XPLAT_ZYNQ) {
+			if ((InstancePtr->UpdateTxSize != 0) &&
+				(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+				/* wait while fifo is full */
+				while (XIicPs_ReadReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET) !=
+					(u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+			if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+				XIicPs_EnableInterrupts(BaseAddr,
+					(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+					(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+					(u32)XIICPS_IXR_ARB_LOST_MASK);
+			}
+		}
+		InstancePtr->CurrByteCount = ByteCnt;
+	}
+
+	if (((!(InstancePtr->IsSend)) != 0) &&
+		(0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+		/*
+		 * If all done, tell the application.
+		 */
+		if (InstancePtr->RecvByteCount == 0){
+			if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+		}
+	}
+
+
+	/*
+	 * Slave ready interrupt, it is only meaningful for master mode.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
+		StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
+	}
+
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * Arbitration lost interrupt
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
+		StatusEvent |= XIICPS_EVENT_ARB_LOST;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
+			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
+			XIICPS_IXR_RX_OVR_MASK))) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (StatusEvent != 0U) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+
+}
+
+/*****************************************************************************/
+/*
+* This function prepares a device to transfers as a master.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @param	Role specifies whether the device is sending or receiving.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if bus is busy.
+*
+* @note		Interrupts are always disabled, device which needs to use
+*		interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+	/*
+	 * Only check if bus is busy when repeated start option is not set.
+	 */
+	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
+		if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
+			(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
+
+	if (Role == RECVING_ROLE) {
+		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
+	}else {
+		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+	}
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* This function handles continuation of sending data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+static void MasterSendData(XIicPs *InstancePtr)
+{
+	(void)TransmitFifoFill(InstancePtr);
+
+	/*
+	 * Clear hold bit if done, so stop can be sent out.
+	 */
+	if (InstancePtr->SendByteCount == 0) {
+
+		/*
+		 * If user has enabled repeated start as an option,
+		 * do not disable it.
+		 */
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+
+			XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
+		}
+	}
+
+	return;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c
new file mode 100644
index 000000000..1ebd78673
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c
@@ -0,0 +1,497 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_options.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains functions for the configuration of the XIccPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error.
+*			 This is a fix for CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk	10/07/14 Repeated start feature removed.
+* 3.0	sk	12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+		u32 Option;
+		u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+		{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
+		{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
+};
+
+#define XIICPS_NUM_OPTIONS      (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the IIC device driver. The options control
+* how the device behaves relative to the IIC bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is requested, set the flag.
+	 * The hold bit in CR will be written by driver when the next transfer
+	 * is initiated.
+	 */
+	if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
+		InstancePtr->IsRepeatedStart = 1;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table, turning the option on.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so turning it on means
+			 * turning 7-bit option off.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			} else {
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+	/*
+	 * Now write to the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears the options for the IIC device driver. The options
+* control how the device behaves relative to the IIC bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be cleared. This is a
+*		bit mask where a 1 means to turn the option off. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is cleared, set the flag.
+	 * The hold bit in CR will be cleared by driver when the
+	 * following transfer ends.
+	 */
+	if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
+		InstancePtr->IsRepeatedStart = 0;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table and clear the specified options.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so clearing it means turning
+			 * 7-bit option on.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			} else {
+
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the IIC device. The options control how
+* the device behaves relative to the IIC bus.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	32 bit mask of the options, where a 1 means the option is on,
+*		and a 0 means to the option is off. One or more bit values may
+*		be contained in the mask. See the bit definitions named
+* 		XIICPS_*_OPTION in the file xiicps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetOptions(XIicPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 ControlReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read control register to find which options are currently set.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+		if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
+			OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
+		}
+	}
+
+	if (InstancePtr->IsRepeatedStart != 0 ) {
+		OptionsFlag |= XIICPS_REP_START_OPTION;
+	}
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+* See the hardware data sheet for a full explanation of setting the serial
+* clock rate.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	FsclHz is the clock frequency in Hz. The two most common clock
+*		rates are 100KHz and 400KHz.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*		- XST_FAILURE if the Fscl frequency can not be set.
+*
+* @note		The clock can not be faster than the input clock divide by 22.
+*
+******************************************************************************/
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
+{
+	u32 Div_a;
+	u32 Div_b;
+	u32 ActualFscl;
+	u32 Temp;
+	u32 TempLimit;
+	u32 LastError;
+	u32 BestError;
+	u32 CurrentError;
+	u32 ControlReg;
+	u32 CalcDivA;
+	u32 CalcDivB;
+	u32 BestDivA;
+	u32 BestDivB;
+	u32 FsclHzVar = FsclHz;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FsclHzVar > 0U);
+
+	if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
+					XIICPS_TRANS_SIZE_OFFSET)) {
+		return (s32)XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
+	 */
+	Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
+
+	/*
+	 * If the answer is negative or 0, the Fscl input is out of range.
+	 */
+	if ((u32)(0U) == Temp) {
+		return (s32)XST_FAILURE;
+	}
+
+	/*
+	 * If frequency 400KHz is selected, 384.6KHz should be set.
+	 * If frequency 100KHz is selected, 90KHz should be set.
+	 * This is due to a hardware limitation.
+	 */
+	if(FsclHzVar > (u32)384600U) {
+		FsclHzVar = (u32)384600U;
+	}
+
+	if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
+		FsclHzVar = (u32)90000U;
+	}
+
+	/*
+	 * TempLimit helps in iterating over the consecutive value of Temp to
+	 * find the closest clock rate achievable with divisors.
+	 * Iterate over the next value only if fractional part is involved.
+	 */
+	TempLimit = (((InstancePtr->Config.InputClockHz) %
+			((u32)22 * FsclHzVar)) != 	(u32)0x0U) ?
+						Temp + (u32)1U : Temp;
+	BestError = FsclHzVar;
+
+	BestDivA = 0U;
+	BestDivB = 0U;
+	for ( ; Temp <= TempLimit ; Temp++)
+	{
+		LastError = FsclHzVar;
+		CalcDivA = 0U;
+		CalcDivB = 0U;
+
+		for (Div_b = 0U; Div_b < 64U; Div_b++) {
+
+			Div_a = Temp / (Div_b + 1U);
+
+			if (Div_a != 0U){
+				Div_a = Div_a - (u32)1U;
+			}
+			if (Div_a > 3U){
+				continue;
+			}
+			ActualFscl = (InstancePtr->Config.InputClockHz) /
+						(22U * (Div_a + 1U) * (Div_b + 1U));
+
+			if (ActualFscl > FsclHzVar){
+				CurrentError = (ActualFscl - FsclHzVar);}
+			else{
+				CurrentError = (FsclHzVar - ActualFscl);}
+
+			if (LastError > CurrentError) {
+				CalcDivA = Div_a;
+				CalcDivB = Div_b;
+				LastError = CurrentError;
+			}
+		}
+
+		/*
+		 * Used to capture the best divisors.
+		 */
+		if (LastError < BestError) {
+			BestError = LastError;
+			BestDivA = CalcDivA;
+			BestDivB = CalcDivB;
+		}
+	}
+
+
+	/*
+	 * Read the control register and mask the Divisors.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  (u32)XIICPS_CR_OFFSET);
+	ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
+	ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
+		(BestDivB << XIICPS_CR_DIV_B_SHIFT);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	The value of the IIC clock to the nearest Hz based on the
+*		control register settings. The actual value may not be exact to
+*		to integer math rounding errors.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetSClk(XIicPs *InstancePtr)
+{
+	u32 ControlReg;
+	u32 ActualFscl;
+	u32 Div_a;
+	u32 Div_b;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XIICPS_CR_OFFSET);
+
+	Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
+	Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
+
+	ActualFscl = (InstancePtr->Config.InputClockHz) /
+		(22U * (Div_a + 1U) * (Div_b + 1U));
+
+	return ActualFscl;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c
new file mode 100644
index 000000000..dd57a1a51
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_selftest.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* This component contains the implementation of selftest functions for the
+* XIicPs driver component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm    09/22/11 Removed unused code
+* 3.0	sk	   11/03/14 Removed TimeOut Register value check
+*			   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+#define REG_TEST_VALUE    0x00000005U
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SelfTest(XIicPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the IIC registers should be in their default state right now.
+	 */
+	if ((XIICPS_CR_RESET_VALUE !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_CR_OFFSET)) ||
+		(XIICPS_IXR_ALL_INTR_MASK !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_IMR_OFFSET))) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Write, Read then write a register
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
+
+	if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XIICPS_SLV_PAUSE_OFFSET)) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, 0U);
+
+	XIicPs_Reset(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c
new file mode 100644
index 000000000..7d7dadaa8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_sinit.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* The implementation of the XIicPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 3.00	sk	   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*		device ID was not found. See xiicps.h for the definition of
+*		XIicPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
+{
+	XIicPs_Config *CfgPtr = NULL;
+	s32 Index;
+
+	for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
+		if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIicPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XIicPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c
new file mode 100644
index 000000000..fef640b77
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c
@@ -0,0 +1,595 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xiicps_slave.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Handles slave transfers
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --  -------- ---------------------------------------------
+* 1.00a jz  01/30/10 First release
+* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
+* 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 SlaveRecvData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function sets up the device to be a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note
+*	Interrupt is always enabled no matter the tranfer is interrupt-
+*	driven or polled mode. Whether device will be interrupted or not
+*	depends on whether the device is connected to an interrupt
+*	controller and interrupt for the device is enabled.
+*
+****************************************************************************/
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
+	ControlReg |= (u32)XIICPS_CR_NEA_MASK;
+	ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven send. It set the repeated
+* start for the device is the tranfer size is larger than FIFO depth.
+* Data processing for the send is initiated by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(BaseAddr,
+			(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+			(u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
+			(u32)XIICPS_IXR_TX_OVR_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven receive.
+* Data processing for the receive is handled by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return	None.
+*
+* @note		This routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
+		(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+* This function sends  a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if master sends us data or master terminates the
+*		transfer before all data has sent out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Tmp;
+	s32 BytesToSend;
+	s32 Error = 0;
+	s32 Status = (s32)XST_SUCCESS;
+	_Bool Value;
+	_Bool Result;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	/*
+	 * Use RXRW bit in status register to wait master to start a read.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+			(Error == 0));
+	while (Result != FALSE) {
+
+		/*
+		 * If master tries to send us data, it is an error.
+		 */
+		if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
+			Error = 1;
+		}
+
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+				(Error == 0));
+	}
+
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	} else {
+
+		/*
+		 * Clear the interrupt status register.
+		 */
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+		/*
+		 * Send data as long as there is more data to send and
+		 * there are no errors.
+		 */
+		Value = (InstancePtr->SendByteCount > (s32)0) &&
+						((Error == 0));
+		while (Value != FALSE) {
+
+			/*
+			 * Find out how many can be sent.
+			 */
+			BytesToSend = InstancePtr->SendByteCount;
+			if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
+				BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
+			}
+
+			for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
+				XIicPs_SendByte(InstancePtr);
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * Wait for master to read the data out of fifo.
+			 */
+			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
+							(Error == 0)) {
+
+				/*
+				 * If master terminates the transfer before all data is
+				 * sent, it is an error.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_ISR_OFFSET);
+				if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
+					Error = 1;
+				}
+
+				/* Clear ISR.
+				 */
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+							IntrStatusReg);
+
+				StatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_SR_OFFSET);
+			}
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+							(Error == 0));
+		}
+	}
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	}
+
+	return Status;
+}
+/*****************************************************************************/
+/**
+* This function receives a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Count;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	/*
+	 * Clear the interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Clear the status register.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Count = InstancePtr->RecvByteCount;
+	while (Count > (s32)0) {
+
+		/* Wait for master to put data */
+		while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
+		    StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * If master terminates the transfer before we get all
+			 * the data or the master tries to read from us,
+			 * it is an error.
+			 */
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_ISR_OFFSET);
+			if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
+					XIICPS_IXR_COMP_MASK))!=0x0U) &&
+				((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
+				((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+
+				return (s32)XST_FAILURE;
+			}
+
+			/*
+			 * Clear the interrupt status register.
+			 */
+			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+			IntrStatusReg);
+		}
+
+		/*
+		 * Read all data from FIFO.
+		 */
+		while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			 ((InstancePtr->RecvByteCount > 0) != 0x0U)){
+
+			XIicPs_RecvByte(InstancePtr);
+
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_SR_OFFSET);
+		}
+		Count = InstancePtr->RecvByteCount;
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for slave mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper
+* handling.
+*
+* <pre>
+*
+* The interrupts that are handled are:
+* - DATA
+*	If the instance is sending, it means that the master wants to read more
+*	data from us. Send more data, and check whether we are done with this
+*	send.
+*
+*	If the instance is receiving, it means that the master has writen
+* 	more data to us. Receive more data, and check whether we are done with
+*	with this receive.
+*
+* - COMP
+*	This marks that stop sequence has been sent from the master, transfer
+*	is about to terminate. However, for receiving, the master may have
+*	written us some data, so receive that first.
+*
+*	It is an error if the amount of transfered data is less than expected.
+*
+* - NAK
+*	This marks that master does not want our data. It is for send only.
+*
+* - Other interrupts
+*	These interrupts are marked as error.
+*
+* </pre>
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 IsSend = 0U;
+	u32 StatusEvent = 0U;
+	s32 LeftOver;
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are missed
+	 * while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+	/*
+	 * Determine whether the device is sending.
+	 */
+	if (InstancePtr->RecvBufferPtr == NULL) {
+		IsSend = 1U;
+	}
+
+	/* Data interrupt
+	 *
+	 * This means master wants to do more data transfers.
+	 * Also check for completion of transfer, signal upper layer if done.
+	 */
+	if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
+		if (IsSend != 0x0U) {
+			LeftOver = TransmitFifoFill(InstancePtr);
+				/*
+				 * We may finish send here
+				 */
+				if (LeftOver == 0) {
+					StatusEvent |=
+						XIICPS_EVENT_COMPLETE_SEND;
+				}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+
+			/* We may finish the receive here */
+			if (LeftOver == 0) {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Complete interrupt.
+	 *
+	 * In slave mode, it means the master has done with this transfer, so
+	 * we signal the application using completion event.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+		if (IsSend != 0x0U) {
+			if (InstancePtr->SendByteCount > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			}else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+			}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+			if (LeftOver > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			} else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Nack interrupt, pass this information to application.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
+				XIICPS_IXR_RX_UNF_MASK |
+				XIICPS_IXR_TX_OVR_MASK |
+				XIICPS_IXR_RX_OVR_MASK))){
+
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if ((u32)0U != StatusEvent) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function handles continuation of receiving data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes still expected by the instance.
+*
+* @note		None.
+*
+****************************************************************************/
+static s32 SlaveRecvData(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	u32 BaseAddr;
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+		XIicPs_RecvByte(InstancePtr);
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	return InstancePtr->RecvByteCount;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile
deleted file mode 100644
index 3e1fc71f7..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xipipsu_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling ipipsu"
-
-xipipsu_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xipipsu_includes
-
-xipipsu_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c
deleted file mode 100644
index f8f902330..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xipipsu.c
-* @addtogroup ipipsu_v1_0
-* @{
-*
-* This file contains the implementation of the interface functions for XIpiPsu
-* driver. Refer to the header file xipipsu.h for more detailed information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver	Who	Date	Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00	mjr	03/15/15	First Release
-* 2.0	mjr	01/22/16	Fixed response buffer address
-*                               calculation. CR# 932582.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xipipsu.h"
-#include "xipipsu_hw.h"
-
-/****************************************************************************/
-/**
- * Initialize the Instance pointer based on a given Config Pointer
- *
- * @param	InstancePtr is a pointer to the instance to be worked on
- * @param	CfgPtr is the device configuration structure containing required
- *		  	hardware build data
- * @param	EffectiveAddress is the base address of the device. If address
- *        	translation is not utilized, this parameter can be passed in using
- *        	CfgPtr->Config.BaseAddress to specify the physical base address.
- * @return	XST_SUCCESS if initialization was successful
- * 			XST_FAILURE in case of failure
- *
- */
-
-XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
-		UINTPTR EffectiveAddress)
-{
-	u32 Index;
-	/* Verify arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(CfgPtr != NULL);
-	/* Set device base address and ID */
-	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddress;
-	InstancePtr->Config.BitMask = CfgPtr->BitMask;
-	InstancePtr->Config.IntId = CfgPtr->IntId;
-
-	InstancePtr->Config.TargetCount = CfgPtr->TargetCount;
-
-	for (Index = 0; Index < CfgPtr->TargetCount; Index++) {
-		InstancePtr->Config.TargetList[Index].Mask =
-				CfgPtr->TargetList[Index].Mask;
-		InstancePtr->Config.TargetList[Index].BufferIndex =
-				CfgPtr->TargetList[Index].BufferIndex;
-	}
-
-	/* Mark the component as Ready */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-	return (XST_SUCCESS);
-}
-
-/**
- * @brief	Reset the given IPI register set.
- *        	This function can be called to disable the IPIs from all
- *        	the sources and clear any pending IPIs in status register
- *
- * @param 	InstancePtr is the pointer to current IPI instance
- *
- */
-
-void XIpiPsu_Reset(XIpiPsu *InstancePtr)
-{
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/**************Disable***************/
-
-	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_IDR_OFFSET,
-			XIPIPSU_ALL_MASK);
-
-	/**************Clear***************/
-	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_ISR_OFFSET,
-			XIPIPSU_ALL_MASK);
-
-}
-
-/**
- * @brief	Trigger an IPI to a Destination CPU
- *
- * @param	InstancePtr is the pointer to current IPI instance
- * @param	DestCpuMask is the Mask of the CPU to which IPI is to be triggered
- *
- *
- * @return	XST_SUCCESS if successful
- * 			XST_FAILURE if an error occurred
- */
-
-XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask)
-{
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Trigger an IPI to the Target */
-	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_TRIG_OFFSET,
-			DestCpuMask);
-	return XST_SUCCESS;
-
-}
-
-/**
- * @brief Poll for an acknowledgement using Observation Register
- *
- * @param	InstancePtr is the pointer to current IPI instance
- * @param	DestCpuMask is the Mask of the destination CPU from which ACK is expected
- * @param	TimeOutCount is the Count after which the routines returns failure
- *
- * @return	XST_SUCCESS if successful
- * 			XST_FAILURE if a timeout occurred
- */
-
-XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
-		u32 TimeOutCount)
-{
-	u32 Flag, PollCount;
-	XStatus Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	PollCount = 0;
-	/* Poll the OBS register until the corresponding DestCpu bit is cleared */
-	do {
-		Flag = (XIpiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-				XIPIPSU_OBS_OFFSET)) & (DestCpuMask);
-		PollCount++;
-		/* Check if the IPI was Acknowledged by the Target or we Timed Out*/
-	} while ((0x00000000U != Flag) && (PollCount < TimeOutCount));
-
-	if (PollCount >= TimeOutCount) {
-		Status = XST_FAILURE;
-	} else {
-		Status = XST_SUCCESS;
-	}
-
-	return Status;
-}
-
-/**
- * @brief	Get the Buffer Index for a CPU specified by Mask
- *
- * @param	InstancePtr is the pointer to current IPI instance
- * @param	CpuMask is the Mask of the CPU form which Index is required
- *
- * @return	Buffer Index value if CPU Mask is valid
- * 			XIPIPSU_MAX_BUFF_INDEX+1 if not valid
- *
- * @note	Static function used only by XIpiPsu_GetBufferAddress
- *
- */
-static u32 XIpiPsu_GetBufferIndex(XIpiPsu *InstancePtr, u32 CpuMask)
-{
-	u32 BufferIndex;
-	u32 Index;
-	/* Init Index with an invalid value */
-	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1;
-
-	/*Search for CPU in the List */
-	for (Index = 0; Index < InstancePtr->Config.TargetCount; Index++) {
-		/*If we find the CPU , then set the Index and break the loop*/
-		if (InstancePtr->Config.TargetList[Index].Mask == CpuMask) {
-			BufferIndex = InstancePtr->Config.TargetList[Index].BufferIndex;
-			break;
-		}
-	}
-
-	/* Return the Index */
-	return BufferIndex;
-}
-
-/**
- * @brief	Get the Buffer Address for a given pair of CPUs
- *
- * @param	InstancePtr is the pointer to current IPI instance
- * @param	SrcCpuMask is the Mask for Source CPU
- * @param	DestCpuMask is the Mask for Destination CPU
- * @param	BufferType is either XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP
- *
- * @return	Valid Buffer Address if no error
- * 			NULL if an error occurred in calculating Address
- *
- */
-
-static u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
-		u32 DestCpuMask, u32 BufferType)
-{
-#ifdef __aarch64__
-	u64 BufferAddr;
-#else
-	u32 BufferAddr;
-#endif
-
-	u32 SrcIndex;
-	u32 DestIndex;
-	/* Get the buffer indices */
-	SrcIndex = XIpiPsu_GetBufferIndex(InstancePtr, SrcCpuMask);
-	DestIndex = XIpiPsu_GetBufferIndex(InstancePtr, DestCpuMask);
-
-	/* If we got an invalid buffer index, then return NULL pointer, else valid address */
-	if ((SrcIndex > XIPIPSU_MAX_BUFF_INDEX)
-			|| (DestIndex > XIPIPSU_MAX_BUFF_INDEX)) {
-		BufferAddr = 0U;
-	} else {
-
-		if (XIPIPSU_BUF_TYPE_MSG == BufferType) {
-			BufferAddr = XIPIPSU_MSG_RAM_BASE
-					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
-					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_TARGET);
-		} else if (XIPIPSU_BUF_TYPE_RESP == BufferType) {
-			BufferAddr = XIPIPSU_MSG_RAM_BASE
-					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
-					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_TARGET)
-					+ (XIPIPSU_BUFFER_OFFSET_RESPONSE);
-		} else {
-			BufferAddr = 0U;
-		}
-
-	}
-
-	return (u32 *) BufferAddr;
-}
-
-/**
- * @brief	Read an Incoming Message from a Source
- *
- * @param 	InstancePtr is the pointer to current IPI instance
- * @param 	SrcCpuMask is the Device Mask for the CPU which has sent the message
- * @param 	MsgPtr is the pointer to Buffer to which the read message needs to be stored
- * @param 	MsgLength is the length of the buffer/message
- * @param 	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
- *
- * @return	XST_SUCCESS if successful
- * 			XST_FAILURE if an error occurred
- */
-
-XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufferType)
-{
-	u32 *BufferPtr;
-	u32 Index;
-	u32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(MsgPtr != NULL);
-	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
-
-	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, TargetMask,
-			InstancePtr->Config.BitMask, BufferType);
-	if (BufferPtr != NULL) {
-		/* Copy the IPI Buffer contents into Users's Buffer*/
-		for (Index = 0; Index < MsgLength; Index++) {
-			MsgPtr[Index] = BufferPtr[Index];
-		}
-		Status = XST_SUCCESS;
-	} else {
-		Status = XST_FAILURE;
-	}
-
-	return Status;
-}
-
-
-/**
- * @brief	Send a Message to Destination
- *
- * @param	InstancePtr is the pointer to current IPI instance
- * @param	DestCpuMask is the Device Mask for the destination CPU
- * @param	MsgPtr is the pointer to Buffer which contains the message to be sent
- * @param	MsgLength is the length of the buffer/message
- * @param	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
- *
- * @return	XST_SUCCESS if successful
- * 			XST_FAILURE if an error occurred
- */
-
-XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufferType)
-{
-	u32 *BufferPtr;
-	u32 Index;
-	u32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(MsgPtr != NULL);
-	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
-
-	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr,
-			InstancePtr->Config.BitMask, TargetMask, BufferType);
-	if (BufferPtr != NULL) {
-		/* Copy the Message to IPI Buffer */
-		for (Index = 0; Index < MsgLength; Index++) {
-			BufferPtr[Index] = MsgPtr[Index];
-		}
-		Status = XST_SUCCESS;
-	} else {
-		Status = XST_FAILURE;
-	}
-
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h
deleted file mode 100644
index 7eb8e5469..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- * @file xipipsu.h
-* @addtogroup ipipsu_v1_0
-* @{
-* @details
- *
- * This is the header file for implementation of IPIPSU driver.
- * Inter Processor Interrupt (IPI) is used for communication between
- * different processors on ZynqMP SoC. Each IPI register set has Trigger, Status
- * and Observation registers for communication between processors. Each IPI path
- * has a 32 byte buffer associated with it and these buffers are located in the
- * XPPU RAM. This driver supports the following operations:
- *
- * - Trigger IPIs to CPUs on the SoC
- * - Write and Read Message buffers
- * - Read the status of Observation Register to get status of Triggered IPI
- * - Enable/Disable IPIs from selected Masters
- * - Read the Status register to get the source of an incoming IPI
- *
- * <b>Initialization</b>
- * The config data for the driver is loaded and is based on the HW build. The
- * XIpiPsu_Config data structure contains all the data related to the
- * IPI driver instance and also teh available Target CPUs.
- *
- * <b>Sending an IPI</b>
- * The following steps can be followed to send an IPI:
- * - Write the Message into Message Buffer using XIpiPsu_WriteMessage()
- * - Trigger IPI using XIpiPsu_TriggerIpi()
- * - Wait for Ack using XIpiPsu_PollForAck()
- * - Read response using XIpiPsu_ReadMessage()
- *
- * @note	XIpiPsu_GetObsStatus() before sending an IPI to ensure that the
- * previous IPI was serviced by the target
- *
- * <b>Receiving an IPI</b>
- * To receive an IPI, the following sequence can be followed:
- * - Register an interrupt handler for the IPIs interrupt ID
- * - Enable the required sources using XIpiPsu_InterruptEnable()
- * - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus
- * - Read the message form source using XIpiPsu_ReadMessage()
- * - Write the response using XIpiPsu_WriteMessage()
- * - Ack the IPI using XIpiPsu_ClearInterruptStatus()
- *
- * @note	XIpiPsu_Reset can be used at startup to clear the status and
- * disable all sources
- *
- */
-/*****************************************************************************/
-#ifndef XIPIPSU_H_
-#define XIPIPSU_H_
-
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "xstatus.h"
-#include "xipipsu_hw.h"
-
-/************************** Constant Definitions *****************************/
-#define XIPIPSU_BUF_TYPE_MSG	(0x00000001U)
-#define XIPIPSU_BUF_TYPE_RESP	(0x00000002U)
-#define XIPIPSU_MAX_MSG_LEN		XIPIPSU_MSG_BUF_SIZE
-/**************************** Type Definitions *******************************/
-/**
- * Data structure used to refer IPI Targets
- */
-typedef struct {
-	u32 Mask; /**< Bit Mask for the target */
-	u32 BufferIndex; /**< Buffer Index used for calculating buffer address */
-} XIpiPsu_Target;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u32 DeviceId; /**< Unique ID  of device */
-	u32 BaseAddress; /**< Base address of the device */
-	u32 BitMask; /**< BitMask to be used to identify this CPU */
-	u32 BufferIndex; /**< Index of the IPI Message Buffer */
-	u32 IntId; /**< Interrupt ID on GIC **/
-	u32 TargetCount; /**< Number of available IPI Targets */
-	XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */
-} XIpiPsu_Config;
-
-/**
- * The XIpiPsu driver instance data. The user is required to allocate a
- * variable of this type for each IPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XIpiPsu_Config Config; /**< Configuration structure */
-	u32 IsReady; /**< Device is initialized and ready */
-	u32 Options; /**< Options set in the device */
-} XIpiPsu;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/**
-*
-* Read the register specified by the base address and offset
-*
-* @param	BaseAddress is the base address of the IPI instance
-* @param	RegOffset is the offset of the register relative to base
-*
-* @return	Value of the specified register
-* @note
-* C-style signature
-*	u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-
-#define XIpiPsu_ReadReg(BaseAddress, RegOffset) \
-		Xil_In32((BaseAddress) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write a value into a register specified by base address and offset
-*
-* @param BaseAddress is the base address of the IPI instance
-* @param RegOffset is the offset of the register relative to base
-* @param Data is a 32-bit value that is to be written into the specified register
-*
-* @note
-* C-style signature
-*	void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-
-#define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \
-		Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Mask contains a bit mask of interrupts to enable. The mask can
-*			be formed using a set of bitwise or'd values of individual CPU masks
-*
-* @note
-* C-style signature
-*	void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XIpiPsu_InterruptEnable(InstancePtr, Mask) \
-	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
-		XIPIPSU_IER_OFFSET, \
-		((Mask) & XIPIPSU_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be disabled.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Mask contains a bit mask of interrupts to disable. The mask can
-*			be formed using a set of bitwise or'd values of individual CPU masks
-*
-* @note
-* C-style signature
-*	void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XIpiPsu_InterruptDisable(InstancePtr, Mask)  \
-	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
-		XIPIPSU_IDR_OFFSET, \
-		((Mask) & XIPIPSU_ALL_MASK));
-/****************************************************************************/
-/**
-*
-* Get the <i>STATUS REGISTER</i> of the current IPI instance.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @return Returns the Interrupt Status register(ISR) contents
-* @note User needs to parse this 32-bit value to check the source CPU
-* C-style signature
-*	u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr)
-*
-*****************************************************************************/
-#define XIpiPsu_GetInterruptStatus(InstancePtr)  \
-	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
-		XIPIPSU_ISR_OFFSET)
-/****************************************************************************/
-/**
-*
-* Clear the <i>STATUS REGISTER</i> of the current IPI instance.
-* The corresponding interrupt status for
-* each bit set to 1 in <i>Mask</i>, will be cleared
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask corresponding to the source CPU*
-*
-* @note This function should be used after handling the IPI.
-* Clearing the status will automatically clear the corresponding bit in
-* OBSERVATION register of Source CPU
-* C-style signature
-*	void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-
-#define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask)  \
-	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
-		XIPIPSU_ISR_OFFSET, \
-		((Mask) & XIPIPSU_ALL_MASK));
-/****************************************************************************/
-/**
-*
-* Get the <i>OBSERVATION REGISTER</i> of the current IPI instance.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @return	Returns the Observation register(OBS) contents
-* @note		User needs to parse this 32-bit value to check the status of
-*			individual CPUs
-* C-style signature
-*	u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr)
-*
-*****************************************************************************/
-#define XIpiPsu_GetObsStatus(InstancePtr)  \
-	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
-		XIPIPSU_OBS_OFFSET)
-/****************************************************************************/
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xipipsu_sinit.c */
-
-XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId);
-
-/* Interface Functions implemented in xipipsu.c */
-
-XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
-		UINTPTR EffectiveAddress);
-
-void XIpiPsu_Reset(XIpiPsu *InstancePtr);
-
-XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask);
-
-XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
-		u32 TimeOutCount);
-
-XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufType);
-
-XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufType);
-
-#endif /* XIPIPSU_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
deleted file mode 100644
index f5728c502..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
+++ /dev/null
@@ -1,161 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xipipsu.h"
-
-/*
-* The configuration table for devices
-*/
-
-XIpiPsu_Config XIpiPsu_ConfigTable[] =
-{
-
-	{
-		XPAR_PSU_IPI_1_DEVICE_ID,
-		XPAR_PSU_IPI_1_BASE_ADDRESS,
-		XPAR_PSU_IPI_1_BIT_MASK,
-		XPAR_PSU_IPI_1_BUFFER_INDEX,
-		XPAR_PSU_IPI_1_INT_ID,
-		XPAR_XIPIPSU_NUM_TARGETS,
-		{
-
-			{
-				XPAR_PSU_IPI_0_BIT_MASK,
-				XPAR_PSU_IPI_0_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_1_BIT_MASK,
-				XPAR_PSU_IPI_1_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_2_BIT_MASK,
-				XPAR_PSU_IPI_2_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_3_BIT_MASK,
-				XPAR_PSU_IPI_3_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_4_BIT_MASK,
-				XPAR_PSU_IPI_4_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_5_BIT_MASK,
-				XPAR_PSU_IPI_5_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_6_BIT_MASK,
-				XPAR_PSU_IPI_6_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_7_BIT_MASK,
-				XPAR_PSU_IPI_7_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_8_BIT_MASK,
-				XPAR_PSU_IPI_8_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_9_BIT_MASK,
-				XPAR_PSU_IPI_9_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_10_BIT_MASK,
-				XPAR_PSU_IPI_10_BUFFER_INDEX
-			}
-		}
-	},
-
-	{
-		XPAR_PSU_IPI_2_DEVICE_ID,
-		XPAR_PSU_IPI_2_BASE_ADDRESS,
-		XPAR_PSU_IPI_2_BIT_MASK,
-		XPAR_PSU_IPI_2_BUFFER_INDEX,
-		XPAR_PSU_IPI_2_INT_ID,
-		XPAR_XIPIPSU_NUM_TARGETS,
-		{
-
-			{
-				XPAR_PSU_IPI_0_BIT_MASK,
-				XPAR_PSU_IPI_0_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_1_BIT_MASK,
-				XPAR_PSU_IPI_1_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_2_BIT_MASK,
-				XPAR_PSU_IPI_2_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_3_BIT_MASK,
-				XPAR_PSU_IPI_3_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_4_BIT_MASK,
-				XPAR_PSU_IPI_4_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_5_BIT_MASK,
-				XPAR_PSU_IPI_5_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_6_BIT_MASK,
-				XPAR_PSU_IPI_6_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_7_BIT_MASK,
-				XPAR_PSU_IPI_7_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_8_BIT_MASK,
-				XPAR_PSU_IPI_8_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_9_BIT_MASK,
-				XPAR_PSU_IPI_9_BUFFER_INDEX
-			},
-			{
-				XPAR_PSU_IPI_10_BIT_MASK,
-				XPAR_PSU_IPI_10_BUFFER_INDEX
-			}
-		}
-	}
-};
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h
deleted file mode 100644
index d24a8ea0a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/**
-*
-* @file xipipsu_hw.h
-* @addtogroup ipipsu_v1_0
-* @{
-*
-* This file contains macro definitions for low level HW related params
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------.
-* 1.0   mjr  03/15/15 First release
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XIPIPSU_HW_H_	/* prevent circular inclusions */
-#define XIPIPSU_HW_H_	/* by using protection macros */
-
-/************************** Constant Definitions *****************************/
-/* Message RAM related params */
-#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
-#define XIPIPSU_MSG_BUF_SIZE 8U	/* Size in Words */
-#define XIPIPSU_MAX_BUFF_INDEX	7
-
-/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
-#define XIPIPSU_BUFFER_OFFSET_GROUP	(8U * 2U * 32U)
-#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
-#define XIPIPSU_BUFFER_OFFSET_RESPONSE		(32U)
-
-/* Max Number of IPI slots on the device */
-#define XIPIPSU_MAX_TARGETS	11
-
-/* Register Offsets for each member  of IPI Register Set */
-#define XIPIPSU_TRIG_OFFSET 0x00U
-#define XIPIPSU_OBS_OFFSET 0x04U
-#define XIPIPSU_ISR_OFFSET 0x10U
-#define XIPIPSU_IMR_OFFSET 0x14U
-#define XIPIPSU_IER_OFFSET 0x18U
-#define XIPIPSU_IDR_OFFSET 0x1CU
-
-/* MASK of all valid IPI bits in above registers */
-#define XIPIPSU_ALL_MASK	0x0F0F0301U
-
-#endif /* XIPIPSU_HW_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c
deleted file mode 100644
index 26495c8dd..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/**
-*
-* @file xipipsu_sinit.c
-* @addtogroup ipipsu_v1_0
-* @{
-*
-* The implementation of the XIpiPsu component's static initialization
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------
-* 1.0   mjr  03/15/15 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xparameters.h"
-#include "xipipsu.h"
-
-/************************** Variable Definitions *****************************/
-extern XIpiPsu_Config XIpiPsu_ConfigTable[];
-
-/*****************************************************************************/
-
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param	DeviceId contains the ID of the device to look up the
-*			configuration for.
-*
-* @return	A pointer to the configuration found or NULL if the specified
-*			device ID was not found. See xipipsu.h for the definition of
-*			XIpiPsu_Config.
-*
-* @note		None.
-*
-******************************************************************************/
-XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId)
-{
-	XIpiPsu_Config *CfgPtr = NULL;
-	int Index;
-
-	for (Index = 0; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
-		if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XIpiPsu_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile
new file mode 100644
index 000000000..3e1fc71f7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xipipsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ipipsu"
+
+xipipsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xipipsu_includes
+
+xipipsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c
new file mode 100644
index 000000000..7c9d98ab0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c
@@ -0,0 +1,353 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xipipsu.c
+* @addtogroup ipipsu_v1_0
+* @{
+*
+* This file contains the implementation of the interface functions for XIpiPsu
+* driver. Refer to the header file xipipsu.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who	Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	mjr	03/15/15	First Release
+* 2.0	mjr	01/22/16	Fixed response buffer address
+*                               calculation. CR# 932582.
+* 2.1	kvn	05/05/16	Modified code for MISRA-C:2012 Compliance
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xipipsu.h"
+#include "xipipsu_hw.h"
+
+/****************************************************************************/
+/**
+ * Initialize the Instance pointer based on a given Config Pointer
+ *
+ * @param	InstancePtr is a pointer to the instance to be worked on
+ * @param	CfgPtr is the device configuration structure containing required
+ *		  	hardware build data
+ * @param	EffectiveAddress is the base address of the device. If address
+ *        	translation is not utilized, this parameter can be passed in using
+ *        	CfgPtr->Config.BaseAddress to specify the physical base address.
+ * @return	XST_SUCCESS if initialization was successful
+ * 			XST_FAILURE in case of failure
+ *
+ */
+
+XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
+		UINTPTR EffectiveAddress)
+{
+	u32 Index;
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+	/* Set device base address and ID */
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddress;
+	InstancePtr->Config.BitMask = CfgPtr->BitMask;
+	InstancePtr->Config.IntId = CfgPtr->IntId;
+
+	InstancePtr->Config.TargetCount = CfgPtr->TargetCount;
+
+	for (Index = 0U; Index < CfgPtr->TargetCount; Index++) {
+		InstancePtr->Config.TargetList[Index].Mask =
+				CfgPtr->TargetList[Index].Mask;
+		InstancePtr->Config.TargetList[Index].BufferIndex =
+				CfgPtr->TargetList[Index].BufferIndex;
+	}
+
+	/* Mark the component as Ready */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	return (XST_SUCCESS);
+}
+
+/**
+ * @brief	Reset the given IPI register set.
+ *        	This function can be called to disable the IPIs from all
+ *        	the sources and clear any pending IPIs in status register
+ *
+ * @param 	InstancePtr is the pointer to current IPI instance
+ *
+ */
+
+void XIpiPsu_Reset(XIpiPsu *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/**************Disable***************/
+
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_IDR_OFFSET,
+			XIPIPSU_ALL_MASK);
+
+	/**************Clear***************/
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_ISR_OFFSET,
+			XIPIPSU_ALL_MASK);
+
+}
+
+/**
+ * @brief	Trigger an IPI to a Destination CPU
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Mask of the CPU to which IPI is to be triggered
+ *
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Trigger an IPI to the Target */
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_TRIG_OFFSET,
+			DestCpuMask);
+	return XST_SUCCESS;
+
+}
+
+/**
+ * @brief Poll for an acknowledgement using Observation Register
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Mask of the destination CPU from which ACK is expected
+ * @param	TimeOutCount is the Count after which the routines returns failure
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if a timeout occurred
+ */
+
+XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
+		u32 TimeOutCount)
+{
+	u32 Flag, PollCount;
+	XStatus Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PollCount = 0U;
+	/* Poll the OBS register until the corresponding DestCpu bit is cleared */
+	do {
+		Flag = (XIpiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XIPIPSU_OBS_OFFSET)) & (DestCpuMask);
+		PollCount++;
+		/* Check if the IPI was Acknowledged by the Target or we Timed Out*/
+	} while ((0x00000000U != Flag) && (PollCount < TimeOutCount));
+
+	if (PollCount >= TimeOutCount) {
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/**
+ * @brief	Get the Buffer Index for a CPU specified by Mask
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	CpuMask is the Mask of the CPU form which Index is required
+ *
+ * @return	Buffer Index value if CPU Mask is valid
+ * 			XIPIPSU_MAX_BUFF_INDEX+1 if not valid
+ *
+ * @note	Static function used only by XIpiPsu_GetBufferAddress
+ *
+ */
+static u32 XIpiPsu_GetBufferIndex(XIpiPsu *InstancePtr, u32 CpuMask)
+{
+	u32 BufferIndex;
+	u32 Index;
+	/* Init Index with an invalid value */
+	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1U;
+
+	/*Search for CPU in the List */
+	for (Index = 0U; Index < InstancePtr->Config.TargetCount; Index++) {
+		/*If we find the CPU , then set the Index and break the loop*/
+		if (InstancePtr->Config.TargetList[Index].Mask == CpuMask) {
+			BufferIndex = InstancePtr->Config.TargetList[Index].BufferIndex;
+			break;
+		}
+	}
+
+	/* Return the Index */
+	return BufferIndex;
+}
+
+/**
+ * @brief	Get the Buffer Address for a given pair of CPUs
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	SrcCpuMask is the Mask for Source CPU
+ * @param	DestCpuMask is the Mask for Destination CPU
+ * @param	BufferType is either XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP
+ *
+ * @return	Valid Buffer Address if no error
+ * 			NULL if an error occurred in calculating Address
+ *
+ */
+
+static u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
+		u32 DestCpuMask, u32 BufferType)
+{
+#ifdef __aarch64__
+	u64 BufferAddr;
+#else
+	u32 BufferAddr;
+#endif
+
+	u32 SrcIndex;
+	u32 DestIndex;
+	/* Get the buffer indices */
+	SrcIndex = XIpiPsu_GetBufferIndex(InstancePtr, SrcCpuMask);
+	DestIndex = XIpiPsu_GetBufferIndex(InstancePtr, DestCpuMask);
+
+	/* If we got an invalid buffer index, then return NULL pointer, else valid address */
+	if ((SrcIndex > XIPIPSU_MAX_BUFF_INDEX)
+			|| (DestIndex > XIPIPSU_MAX_BUFF_INDEX)) {
+		BufferAddr = 0U;
+	} else {
+
+		if (XIPIPSU_BUF_TYPE_MSG == BufferType) {
+			BufferAddr = XIPIPSU_MSG_RAM_BASE
+					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_TARGET);
+		} else if (XIPIPSU_BUF_TYPE_RESP == BufferType) {
+			BufferAddr = XIPIPSU_MSG_RAM_BASE
+					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_TARGET)
+					+ (XIPIPSU_BUFFER_OFFSET_RESPONSE);
+		} else {
+			BufferAddr = 0U;
+		}
+
+	}
+
+	return (u32 *) BufferAddr;
+}
+
+/**
+ * @brief	Read an Incoming Message from a Source
+ *
+ * @param 	InstancePtr is the pointer to current IPI instance
+ * @param 	SrcCpuMask is the Device Mask for the CPU which has sent the message
+ * @param 	MsgPtr is the pointer to Buffer to which the read message needs to be stored
+ * @param 	MsgLength is the length of the buffer/message
+ * @param 	BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType)
+{
+	u32 *BufferPtr;
+	u32 Index;
+	XStatus Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
+
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, SrcCpuMask,
+			InstancePtr->Config.BitMask, BufferType);
+	if (BufferPtr != NULL) {
+		/* Copy the IPI Buffer contents into Users's Buffer*/
+		for (Index = 0U; Index < MsgLength; Index++) {
+			MsgPtr[Index] = BufferPtr[Index];
+		}
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+
+
+/**
+ * @brief	Send a Message to Destination
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Device Mask for the destination CPU
+ * @param	MsgPtr is the pointer to Buffer which contains the message to be sent
+ * @param	MsgLength is the length of the buffer/message
+ * @param	BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType)
+{
+	u32 *BufferPtr;
+	u32 Index;
+	XStatus Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
+
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr,
+			InstancePtr->Config.BitMask, DestCpuMask, BufferType);
+	if (BufferPtr != NULL) {
+		/* Copy the Message to IPI Buffer */
+		for (Index = 0U; Index < MsgLength; Index++) {
+			BufferPtr[Index] = MsgPtr[Index];
+		}
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h
new file mode 100644
index 000000000..0253b9a68
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h
@@ -0,0 +1,281 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ * @file xipipsu.h
+* @addtogroup ipipsu_v1_0
+* @{
+* @details
+ *
+ * This is the header file for implementation of IPIPSU driver.
+ * Inter Processor Interrupt (IPI) is used for communication between
+ * different processors on ZynqMP SoC. Each IPI register set has Trigger, Status
+ * and Observation registers for communication between processors. Each IPI path
+ * has a 32 byte buffer associated with it and these buffers are located in the
+ * XPPU RAM. This driver supports the following operations:
+ *
+ * - Trigger IPIs to CPUs on the SoC
+ * - Write and Read Message buffers
+ * - Read the status of Observation Register to get status of Triggered IPI
+ * - Enable/Disable IPIs from selected Masters
+ * - Read the Status register to get the source of an incoming IPI
+ *
+ * <b>Initialization</b>
+ * The config data for the driver is loaded and is based on the HW build. The
+ * XIpiPsu_Config data structure contains all the data related to the
+ * IPI driver instance and also teh available Target CPUs.
+ *
+ * <b>Sending an IPI</b>
+ * The following steps can be followed to send an IPI:
+ * - Write the Message into Message Buffer using XIpiPsu_WriteMessage()
+ * - Trigger IPI using XIpiPsu_TriggerIpi()
+ * - Wait for Ack using XIpiPsu_PollForAck()
+ * - Read response using XIpiPsu_ReadMessage()
+ *
+ * @note	XIpiPsu_GetObsStatus() before sending an IPI to ensure that the
+ * previous IPI was serviced by the target
+ *
+ * <b>Receiving an IPI</b>
+ * To receive an IPI, the following sequence can be followed:
+ * - Register an interrupt handler for the IPIs interrupt ID
+ * - Enable the required sources using XIpiPsu_InterruptEnable()
+ * - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus
+ * - Read the message form source using XIpiPsu_ReadMessage()
+ * - Write the response using XIpiPsu_WriteMessage()
+ * - Ack the IPI using XIpiPsu_ClearInterruptStatus()
+ *
+ * @note	XIpiPsu_Reset can be used at startup to clear the status and
+ * disable all sources
+ *
+ */
+/*****************************************************************************/
+#ifndef XIPIPSU_H_
+#define XIPIPSU_H_
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xstatus.h"
+#include "xipipsu_hw.h"
+
+/************************** Constant Definitions *****************************/
+#define XIPIPSU_BUF_TYPE_MSG	(0x00000001U)
+#define XIPIPSU_BUF_TYPE_RESP	(0x00000002U)
+#define XIPIPSU_MAX_MSG_LEN		XIPIPSU_MSG_BUF_SIZE
+/**************************** Type Definitions *******************************/
+/**
+ * Data structure used to refer IPI Targets
+ */
+typedef struct {
+	u32 Mask; /**< Bit Mask for the target */
+	u32 BufferIndex; /**< Buffer Index used for calculating buffer address */
+} XIpiPsu_Target;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u32 DeviceId; /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of the device */
+	u32 BitMask; /**< BitMask to be used to identify this CPU */
+	u32 BufferIndex; /**< Index of the IPI Message Buffer */
+	u32 IntId; /**< Interrupt ID on GIC **/
+	u32 TargetCount; /**< Number of available IPI Targets */
+	XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */
+} XIpiPsu_Config;
+
+/**
+ * The XIpiPsu driver instance data. The user is required to allocate a
+ * variable of this type for each IPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIpiPsu_Config Config; /**< Configuration structure */
+	u32 IsReady; /**< Device is initialized and ready */
+	u32 Options; /**< Options set in the device */
+} XIpiPsu;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/**
+*
+* Read the register specified by the base address and offset
+*
+* @param	BaseAddress is the base address of the IPI instance
+* @param	RegOffset is the offset of the register relative to base
+*
+* @return	Value of the specified register
+* @note
+* C-style signature
+*	u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+
+#define XIpiPsu_ReadReg(BaseAddress, RegOffset) \
+		Xil_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write a value into a register specified by base address and offset
+*
+* @param BaseAddress is the base address of the IPI instance
+* @param RegOffset is the offset of the register relative to base
+* @param Data is a 32-bit value that is to be written into the specified register
+*
+* @note
+* C-style signature
+*	void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+
+#define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \
+		Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Mask contains a bit mask of interrupts to enable. The mask can
+*			be formed using a set of bitwise or'd values of individual CPU masks
+*
+* @note
+* C-style signature
+*	void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XIpiPsu_InterruptEnable(InstancePtr, Mask) \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_IER_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be disabled.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Mask contains a bit mask of interrupts to disable. The mask can
+*			be formed using a set of bitwise or'd values of individual CPU masks
+*
+* @note
+* C-style signature
+*	void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XIpiPsu_InterruptDisable(InstancePtr, Mask)  \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_IDR_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+/****************************************************************************/
+/**
+*
+* Get the <i>STATUS REGISTER</i> of the current IPI instance.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @return Returns the Interrupt Status register(ISR) contents
+* @note User needs to parse this 32-bit value to check the source CPU
+* C-style signature
+*	u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XIpiPsu_GetInterruptStatus(InstancePtr)  \
+	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_ISR_OFFSET)
+/****************************************************************************/
+/**
+*
+* Clear the <i>STATUS REGISTER</i> of the current IPI instance.
+* The corresponding interrupt status for
+* each bit set to 1 in <i>Mask</i>, will be cleared
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask corresponding to the source CPU*
+*
+* @note This function should be used after handling the IPI.
+* Clearing the status will automatically clear the corresponding bit in
+* OBSERVATION register of Source CPU
+* C-style signature
+*	void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+
+#define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask)  \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_ISR_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+/****************************************************************************/
+/**
+*
+* Get the <i>OBSERVATION REGISTER</i> of the current IPI instance.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @return	Returns the Observation register(OBS) contents
+* @note		User needs to parse this 32-bit value to check the status of
+*			individual CPUs
+* C-style signature
+*	u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XIpiPsu_GetObsStatus(InstancePtr)  \
+	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_OBS_OFFSET)
+/****************************************************************************/
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xipipsu_sinit.c */
+
+XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId);
+
+/* Interface Functions implemented in xipipsu.c */
+
+XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
+		UINTPTR EffectiveAddress);
+
+void XIpiPsu_Reset(XIpiPsu *InstancePtr);
+
+XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask);
+
+XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
+		u32 TimeOutCount);
+
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType);
+
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType);
+
+#endif /* XIPIPSU_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c
new file mode 100644
index 000000000..afbbc5809
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c
@@ -0,0 +1,161 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xipipsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIpiPsu_Config XIpiPsu_ConfigTable[] =
+{
+
+	{
+		XPAR_PSU_IPI_1_DEVICE_ID,
+		XPAR_PSU_IPI_1_BASE_ADDRESS,
+		XPAR_PSU_IPI_1_BIT_MASK,
+		XPAR_PSU_IPI_1_BUFFER_INDEX,
+		XPAR_PSU_IPI_1_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	},
+
+	{
+		XPAR_PSU_IPI_2_DEVICE_ID,
+		XPAR_PSU_IPI_2_BASE_ADDRESS,
+		XPAR_PSU_IPI_2_BIT_MASK,
+		XPAR_PSU_IPI_2_BUFFER_INDEX,
+		XPAR_PSU_IPI_2_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	}
+};
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h
new file mode 100644
index 000000000..b4c02b6e1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/**
+*
+* @file xipipsu_hw.h
+* @addtogroup ipipsu_v1_0
+* @{
+*
+* This file contains macro definitions for low level HW related params
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   mjr  03/15/15 First release
+* 2.1   kvn  05/05/16 Modified code for MISRA-C:2012 Compliance
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XIPIPSU_HW_H_	/* prevent circular inclusions */
+#define XIPIPSU_HW_H_	/* by using protection macros */
+
+/************************** Constant Definitions *****************************/
+/* Message RAM related params */
+#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
+#define XIPIPSU_MSG_BUF_SIZE 8U	/* Size in Words */
+#define XIPIPSU_MAX_BUFF_INDEX	7U
+
+/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
+#define XIPIPSU_BUFFER_OFFSET_GROUP	(8U * 2U * 32U)
+#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
+#define XIPIPSU_BUFFER_OFFSET_RESPONSE		(32U)
+
+/* Max Number of IPI slots on the device */
+#define XIPIPSU_MAX_TARGETS	11
+
+/* Register Offsets for each member  of IPI Register Set */
+#define XIPIPSU_TRIG_OFFSET 0x00U
+#define XIPIPSU_OBS_OFFSET 0x04U
+#define XIPIPSU_ISR_OFFSET 0x10U
+#define XIPIPSU_IMR_OFFSET 0x14U
+#define XIPIPSU_IER_OFFSET 0x18U
+#define XIPIPSU_IDR_OFFSET 0x1CU
+
+/* MASK of all valid IPI bits in above registers */
+#define XIPIPSU_ALL_MASK	0x0F0F0301U
+
+#endif /* XIPIPSU_HW_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c
new file mode 100644
index 000000000..ae0900498
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/**
+*
+* @file xipipsu_sinit.c
+* @addtogroup ipipsu_v1_0
+* @{
+*
+* The implementation of the XIpiPsu component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   mjr  03/15/15 First release
+* 2.1   kvn  05/05/16 Modified code for MISRA-C:2012 Compliance
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xparameters.h"
+#include "xipipsu.h"
+
+/************************** Variable Definitions *****************************/
+extern XIpiPsu_Config XIpiPsu_ConfigTable[];
+
+/*****************************************************************************/
+
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*			configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*			device ID was not found. See xipipsu.h for the definition of
+*			XIpiPsu_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId)
+{
+	XIpiPsu_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
+		if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIpiPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile
deleted file mode 100644
index 88a66dd93..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xqspipsu_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling qspipsu"
-
-xqspipsu_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xqspipsu_includes
-
-xqspipsu_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c
deleted file mode 100644
index cd415ae07..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c
+++ /dev/null
@@ -1,1290 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspipsu.c
-* @addtogroup qspipsu_v1_0
-* @{
-*
-* This file implements the functions required to use the QSPIPSU hardware to
-* perform a transfer. These are accessible to the user via xqspipsu.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------
-* 1.0   hk  08/21/14 First release
-*       sk  03/13/15 Added IO mode support.
-*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
-*                    Clear and disbale DMA interrupts/status in abort.
-*                    Use DMA DONE bit instead of BUSY as recommended.
-*       sk  04/24/15 Modified the code according to MISRAC-2012.
-*       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
-*                    writing/reading from 0x0 location is permitted.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspipsu.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
-			u32 ByteCount);
-static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
-static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
-			u32 *GenFifoEntry);
-static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
-			XQspiPsu_Msg *Msg, s32 Size);
-static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
-			XQspiPsu_Msg *Msg);
-static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr);
-static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
-			XQspiPsu_Msg *Msg, s32 Index);
-static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr);
-static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
-			XQspiPsu_Msg *Msg, s32 Size);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XQspiPsu instance such that the driver is ready to use.
-*
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	ConfigPtr is a reference to a structure containing information
-*		about a specific QSPIPSU device. This function initializes an
-*		InstancePtr object for a specific device specified by the
-*		contents of Config.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the address
-*		mapping from EffectiveAddr to the device physical base address
-*		unchanged once this function is invoked. Unexpected errors may
-*		occur if the address mapping changes after this function is
-*		called. If address translation is not used, use
-*		ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_DEVICE_IS_STARTED if the device is already started.
-*		It must be stopped to re-initialize.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
-				u32 EffectiveAddr)
-{
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-	s32 Status;
-
-	/*
-	 * If the device is busy, disallow the initialize and return a status
-	 * indicating it is already started. This allows the user to stop the
-	 * device and re-initialize, but prevents a user from inadvertently
-	 * initializing. This assumes the busy flag is cleared at startup.
-	 */
-	if (InstancePtr->IsBusy == TRUE) {
-		Status = (s32)XST_DEVICE_IS_STARTED;
-	} else {
-
-		/* Set some default values. */
-		InstancePtr->IsBusy = FALSE;
-
-		InstancePtr->Config.BaseAddress = EffectiveAddr + XQSPIPSU_OFFSET;
-		InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
-		InstancePtr->StatusHandler = StubStatusHandler;
-		InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
-
-		/* Other instance variable initializations */
-		InstancePtr->SendBufferPtr = NULL;
-		InstancePtr->RecvBufferPtr = NULL;
-		InstancePtr->GenFifoBufferPtr = NULL;
-		InstancePtr->TxBytes = 0;
-		InstancePtr->RxBytes = 0;
-		InstancePtr->GenFifoEntries = 0;
-		InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
-		InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
-		InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
-		InstancePtr->IsUnaligned = 0;
-		InstancePtr->IsManualstart = TRUE;
-
-		/* Select QSPIPSU */
-		XQspiPsu_Select(InstancePtr);
-
-		/*
-		 * Reset the QSPIPSU device to get it into its initial state. It is
-		 * expected that device configuration will take place after this
-		 * initialization is done, but before the device is started.
-		 */
-		XQspiPsu_Reset(InstancePtr);
-
-		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-		Status = XST_SUCCESS;
-	}
-
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the QSPIPSU device. Reset must only be called after the driver has
-* been initialized. Any data transfer that is in progress is aborted.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the QSPIPSU device after the reset.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XQspiPsu_Reset(XQspiPsu *InstancePtr)
-{
-	u32 ConfigReg;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	/* Abort any transfer that is in progress */
-	XQspiPsu_Abort(InstancePtr);
-
-	/* Default value to config register */
-	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_CFG_OFFSET);
-
-	/* DMA mode */
-	ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
-	ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
-	/* Manual start */
-	ConfigReg |= XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK;
-	/* Little endain by default */
-	ConfigReg &= ~XQSPIPSU_CFG_ENDIAN_MASK;
-	/* Disable poll timeout */
-	ConfigReg &= ~XQSPIPSU_CFG_EN_POLL_TO_MASK;
-	/* Set hold bit */
-	ConfigReg |= XQSPIPSU_CFG_WP_HOLD_MASK;
-	/* Clear prescalar by default */
-	ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
-	/* CPOL CPHA 00 */
-	ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_PHA_MASK);
-	ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_POL_MASK);
-
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_CFG_OFFSET, ConfigReg);
-
-	/* Set by default to allow for high frequencies */
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_LPBK_DLY_ADJ_OFFSET,
-		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_LPBK_DLY_ADJ_OFFSET) |
-			XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK);
-
-	/* Reset thresholds */
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_TX_THRESHOLD_OFFSET,
-		XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL);
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_RX_THRESHOLD_OFFSET,
-		XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL);
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_GF_THRESHOLD_OFFSET,
-		XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL);
-
-	/* DMA init */
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET,
-			XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Aborts a transfer in progress by
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-*
-* @return	None.
-*
-* @note
-*
-******************************************************************************/
-void XQspiPsu_Abort(XQspiPsu *InstancePtr)
-{
-
-	u32 IntrStatus, ConfigReg;
-
-	IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-					XQSPIPSU_ISR_OFFSET);
-
-	/* Clear and disable interrupts */
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
-		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-				XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
-			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-				XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
-				XQSPIPSU_QSPIDMA_DST_STS_WTC);
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
-			XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
-
-	/* Clear FIFO */
-	if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK) != FALSE) {
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_FIFO_CTRL_OFFSET,
-			XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
-			XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK);
-	}
-
-	/*
-	 * Switch to IO mode to Clear RX FIFO. This is becuase of DMA behaviour
-	 * where it waits on RX empty and goes busy assuming there is data
-	 * to be transfered even if there is no request.
-	 */
-	if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0U) {
-		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-					XQSPIPSU_CFG_OFFSET);
-		ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-				XQSPIPSU_CFG_OFFSET, ConfigReg);
-
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-				XQSPIPSU_FIFO_CTRL_OFFSET,
-				XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK);
-
-		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
-			ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
-			XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-					XQSPIPSU_CFG_OFFSET, ConfigReg);
-		}
-	}
-
-	/* Disable QSPIPSU */
-	XQspiPsu_Disable(InstancePtr);
-
-	InstancePtr->TxBytes = 0;
-	InstancePtr->RxBytes = 0;
-	InstancePtr->GenFifoEntries = 0;
-	InstancePtr->IsBusy = FALSE;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function performs a transfer on the bus in polled mode. The messages
-* passed are all transferred on the bus between one CS assert and de-assert.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Msg is a pointer to the structure containing transfer data.
-* @param	NumMsg is the number of messages to be transferred.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if transfer fails.
-*		- XST_DEVICE_BUSY if a transfer is already in progress.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
-				u32 NumMsg)
-{
-	u32 StatusReg;
-	u32 ConfigReg;
-	s32 Index;
-	u32 QspiPsuStatusReg, DmaStatusReg;
-	u32 BaseAddress;
-	s32 Status;
-	s32 RxThr;
-	u32 IOPending = (u32)FALSE;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	for (Index = 0; Index < (s32)NumMsg; Index++) {
-		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
-	}
-
-	/* Check whether there is another transfer in progress. Not thread-safe */
-	if (InstancePtr->IsBusy == TRUE) {
-		return (s32)XST_DEVICE_BUSY;
-	}
-
-	/* Check for ByteCount upper limit - 2^28 for DMA */
-	for (Index = 0; Index < (s32)NumMsg; Index++) {
-		if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
-				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
-			return (s32)XST_FAILURE;
-		}
-	}
-
-	/*
-	 * Set the busy flag, which will be cleared when the transfer is
-	 * entirely done.
-	 */
-	InstancePtr->IsBusy = TRUE;
-
-	BaseAddress = InstancePtr->Config.BaseAddress;
-
-	/* Enable */
-	XQspiPsu_Enable(InstancePtr);
-
-	/* Select slave */
-	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
-
-	/* list */
-	Index = 0;
-	while (Index < (s32)NumMsg) {
-		XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
-
-		if (InstancePtr->IsManualstart == TRUE) {
-			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
-				XQspiPsu_ReadReg(BaseAddress,
-					XQSPIPSU_CFG_OFFSET) |
-					XQSPIPSU_CFG_START_GEN_FIFO_MASK);
-		}
-
-		/* Use thresholds here */
-		/* If there is more data to be transmitted */
-		do {
-			QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
-						XQSPIPSU_ISR_OFFSET);
-
-			/* Transmit more data if left */
-			if (((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
-				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
-				(InstancePtr->TxBytes > 0)) {
-				XQspiPsu_FillTxFifo(InstancePtr, &Msg[Index],
-						XQSPIPSU_TXD_DEPTH);
-			}
-
-			/* Check if DMA RX is complete and update RxBytes */
-			if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
-				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
-				u32 DmaIntrSts;
-				DmaIntrSts = XQspiPsu_ReadReg(BaseAddress,
-								XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
-				if ((DmaIntrSts & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
-					XQspiPsu_WriteReg(BaseAddress,
-						XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
-						DmaIntrSts);
-					/* Read remaining bytes using IO mode */
-					if((InstancePtr->RxBytes % 4) != 0 ) {
-						XQspiPsu_WriteReg(BaseAddress,
-							XQSPIPSU_CFG_OFFSET,
-							(XQspiPsu_ReadReg(BaseAddress,
-							XQSPIPSU_CFG_OFFSET) &
-							~XQSPIPSU_CFG_MODE_EN_MASK));
-						InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
-						Msg[Index].ByteCount =
-							(InstancePtr->RxBytes % 4);
-						Msg[Index].RxBfrPtr += (InstancePtr->RxBytes -
-								(InstancePtr->RxBytes % 4));
-						InstancePtr->IsUnaligned = 1;
-						IOPending = (u32)TRUE;
-						break;
-					}
-					InstancePtr->RxBytes = 0;
-				}
-			} else {
-				if ((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE) {
-					/* Check if PIO RX is complete and update RxBytes */
-					RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
-							XQSPIPSU_RX_THRESHOLD_OFFSET);
-					if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
-									!= 0U) {
-						XQspiPsu_ReadRxFifo(InstancePtr,
-								&Msg[Index], RxThr*4);
-
-					} else {
-						if ((QspiPsuStatusReg &
-							XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U) {
-								XQspiPsu_ReadRxFifo(InstancePtr,
-									&Msg[Index], InstancePtr->RxBytes);
-						}
-					}
-				}
-			}
-		} while (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) ||
-			(InstancePtr->TxBytes != 0) ||
-			((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) == FALSE) ||
-			(InstancePtr->RxBytes != 0));
-
-		if((InstancePtr->IsUnaligned != 0) && (IOPending == (u32)FALSE)) {
-			InstancePtr->IsUnaligned = 0;
-			XQspiPsu_WriteReg(BaseAddress,
-				XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
-				BaseAddress,
-				XQSPIPSU_CFG_OFFSET) |
-				XQSPIPSU_CFG_MODE_EN_DMA_MASK));
-			InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
-		}
-
-		if (IOPending == (u32)TRUE) {
-			IOPending = (u32)FALSE;
-		} else {
-			Index++;
-		}
-	}
-
-	/* De-select slave */
-	XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
-
-	if (InstancePtr->IsManualstart == TRUE) {
-		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
-			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
-				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
-	}
-
-	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
-	while ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) {
-		QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
-						XQSPIPSU_ISR_OFFSET);
-	}
-
-	/* Clear the busy flag. */
-	InstancePtr->IsBusy = FALSE;
-
-	/* Disable the device. */
-	XQspiPsu_Disable(InstancePtr);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function initiates a transfer on the bus and enables interrupts.
-* The transfer is completed by the interrupt handler. The messages passed are
-* all transferred on the bus between one CS assert and de-assert.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Msg is a pointer to the structure containing transfer data.
-* @param	NumMsg is the number of messages to be transferred.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if transfer fails.
-*		- XST_DEVICE_BUSY if a transfer is already in progress.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
-				u32 NumMsg)
-{
-	u32 StatusReg;
-	u32 ConfigReg;
-	s32 Index;
-	u32 BaseAddress;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	for (Index = 0; Index < (s32)NumMsg; Index++) {
-		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
-	}
-
-	/* Check whether there is another transfer in progress. Not thread-safe */
-	if (InstancePtr->IsBusy == TRUE) {
-		return (s32)XST_DEVICE_BUSY;
-	}
-
-	/* Check for ByteCount upper limit - 2^28 for DMA */
-	for (Index = 0; Index < (s32)NumMsg; Index++) {
-		if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
-				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
-			return (s32)XST_FAILURE;
-		}
-	}
-
-	/*
-	 * Set the busy flag, which will be cleared when the transfer is
-	 * entirely done.
-	 */
-	InstancePtr->IsBusy = TRUE;
-
-	BaseAddress = InstancePtr->Config.BaseAddress;
-
-	InstancePtr->Msg = Msg;
-	InstancePtr->NumMsg = (s32)NumMsg;
-	InstancePtr->MsgCnt = 0;
-
-	/* Enable */
-	XQspiPsu_Enable(InstancePtr);
-
-	/* Select slave */
-	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
-
-	/* This might not work if not manual start */
-	/* Put first message in FIFO along with the above slave select */
-	XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
-
-	if (InstancePtr->IsManualstart == TRUE) {
-		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
-			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
-				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
-	}
-
-	/* Enable interrupts */
-	XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IER_OFFSET,
-		(u32)XQSPIPSU_IER_TXNOT_FULL_MASK | (u32)XQSPIPSU_IER_TXEMPTY_MASK |
-		(u32)XQSPIPSU_IER_RXNEMPTY_MASK | (u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
-		(u32)XQSPIPSU_IER_RXEMPTY_MASK);
-
-	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
-		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
-				XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
-	}
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if transfer fails.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
-{
-	u32 QspiPsuStatusReg, DmaIntrStatusReg = 0;
-	u32 BaseAddress;
-	XQspiPsu_Msg *Msg;
-	s32 NumMsg;
-	s32 MsgCnt;
-	u8 DeltaMsgCnt = 0;
-	s32 RxThr;
-	u32 TxRxFlag;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-
-	BaseAddress = InstancePtr->Config.BaseAddress;
-	Msg = InstancePtr->Msg;
-	NumMsg = InstancePtr->NumMsg;
-	MsgCnt = InstancePtr->MsgCnt;
-	TxRxFlag = Msg[MsgCnt].Flags;
-
-	/* QSPIPSU Intr cleared on read */
-	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
-	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
-		/* DMA Intr write to clear */
-		DmaIntrStatusReg = XQspiPsu_ReadReg(BaseAddress,
-					XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
-
-		XQspiPsu_WriteReg(BaseAddress,
-			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrStatusReg);
-	}
-	if (((QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) != FALSE) ||
-		((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
-		/* Call status handler to indicate error */
-		InstancePtr->StatusHandler(InstancePtr->StatusRef,
-					XST_SPI_COMMAND_ERROR, 0);
-	}
-
-	/* Fill more data to be txed if required */
-	if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
-		((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
-		(InstancePtr->TxBytes > 0)) {
-		XQspiPsu_FillTxFifo(InstancePtr, &Msg[MsgCnt],
-				XQSPIPSU_TXD_DEPTH);
-	}
-
-	/*
-	 * Check if the entry is ONLY TX and increase MsgCnt.
-	 * This is to allow TX and RX together in one entry - corner case.
-	 */
-	if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
-		((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) != FALSE) &&
-		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
-		(InstancePtr->TxBytes == 0) &&
-		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
-		MsgCnt += 1;
-		DeltaMsgCnt = 1U;
-	}
-
-	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
-		(MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
-		if ((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
-				/* Read remaining bytes using IO mode */
-			if((InstancePtr->RxBytes % 4) != 0 ) {
-				XQspiPsu_WriteReg(BaseAddress,
-					XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
-					BaseAddress, XQSPIPSU_CFG_OFFSET) &
-					~XQSPIPSU_CFG_MODE_EN_MASK));
-				InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
-				Msg[MsgCnt].ByteCount = (InstancePtr->RxBytes % 4);
-				Msg[MsgCnt].RxBfrPtr += (InstancePtr->RxBytes -
-						(InstancePtr->RxBytes % 4));
-				InstancePtr->IsUnaligned = 1;
-				XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
-						MsgCnt);
-				if(InstancePtr->IsManualstart == TRUE) {
-					XQspiPsu_WriteReg(BaseAddress,
-						XQSPIPSU_CFG_OFFSET,
-						XQspiPsu_ReadReg(BaseAddress,
-						XQSPIPSU_CFG_OFFSET) |
-						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
-				}
-			}
-			else {
-				InstancePtr->RxBytes = 0;
-				MsgCnt += 1;
-				DeltaMsgCnt = 1U;
-			}
-		}
-	} else {
-		if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
-			if (InstancePtr->RxBytes != 0) {
-				if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
-								!= FALSE) {
-					RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
-								XQSPIPSU_RX_THRESHOLD_OFFSET);
-					XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
-						RxThr*4);
-				} else {
-					if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
-						((QspiPsuStatusReg & XQSPIPSU_ISR_RXEMPTY_MASK) == FALSE)) {
-						XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
-							InstancePtr->RxBytes);
-					}
-				}
-				if (InstancePtr->RxBytes == 0) {
-					MsgCnt += 1;
-					DeltaMsgCnt = 1U;
-				}
-			}
-		}
-	}
-
-	/*
-	 * Dummy byte transfer
-	 * MsgCnt < NumMsg check is to ensure is it a valid dummy cycle message
-	 * If one of the above conditions increased MsgCnt, then
-	 * the new message is yet to be placed in the FIFO; hence !DeltaMsgCnt.
-	 */
-	if ((MsgCnt < NumMsg) && (DeltaMsgCnt == FALSE) &&
-		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE) &&
-		((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
-		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE)) {
-		MsgCnt += 1;
-		DeltaMsgCnt = 1U;
-	}
-	InstancePtr->MsgCnt = MsgCnt;
-
-	/*
-	 * DeltaMsgCnt is to handle conditions where genfifo empty can be set
-	 * while tx is still not empty or rx dma is not yet done.
-	 * MsgCnt > NumMsg indicates CS de-assert entry was also executed.
-	 */
-	if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
-		((DeltaMsgCnt != FALSE) || (MsgCnt > NumMsg))) {
-		if (MsgCnt < NumMsg) {
-			if(InstancePtr->IsUnaligned != 0) {
-				InstancePtr->IsUnaligned = 0;
-				XQspiPsu_WriteReg(InstancePtr->Config.
-					BaseAddress, XQSPIPSU_CFG_OFFSET,
-					(XQspiPsu_ReadReg(InstancePtr->Config.
-					BaseAddress, XQSPIPSU_CFG_OFFSET) |
-					XQSPIPSU_CFG_MODE_EN_DMA_MASK));
-				InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
-			}
-			/* This might not work if not manual start */
-			XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
-
-			if (InstancePtr->IsManualstart == TRUE) {
-				XQspiPsu_WriteReg(BaseAddress,
-					XQSPIPSU_CFG_OFFSET,
-					XQspiPsu_ReadReg(BaseAddress,
-						XQSPIPSU_CFG_OFFSET) |
-						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
-			}
-		} else if (MsgCnt == NumMsg) {
-			/* This is just to keep track of the de-assert entry */
-			MsgCnt += 1;
-			InstancePtr->MsgCnt = MsgCnt;
-
-			/* De-select slave */
-			XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
-
-			if (InstancePtr->IsManualstart == TRUE) {
-				XQspiPsu_WriteReg(BaseAddress,
-					XQSPIPSU_CFG_OFFSET,
-					XQspiPsu_ReadReg(BaseAddress,
-						XQSPIPSU_CFG_OFFSET) |
-						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
-			}
-		} else {
-			/* Disable interrupts */
-			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
-					(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
-					(u32)XQSPIPSU_IER_TXEMPTY_MASK |
-					(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
-					(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
-					(u32)XQSPIPSU_IER_RXEMPTY_MASK);
-			if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
-				XQspiPsu_WriteReg(BaseAddress,
-					XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
-					XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
-			}
-
-			/* Clear the busy flag. */
-			InstancePtr->IsBusy = FALSE;
-
-			/* Disable the device. */
-			XQspiPsu_Disable(InstancePtr);
-
-			/* Call status handler to indicate completion */
-			InstancePtr->StatusHandler(InstancePtr->StatusRef,
-						XST_SPI_TRANSFER_DONE, 0);
-		}
-	}
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the status callback function, the status handler, which the driver
-* calls when it encounters conditions that should be reported to upper
-* layer software. The handler executes in an interrupt context, so it must
-* minimize the amount of processing performed. One of the following status
-* events is passed to the status handler.
-*
-* <pre>
-*
-* XST_SPI_TRANSFER_DONE		The requested data transfer is done
-*
-* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
-*				but there were none available in the transmit
-*				register/FIFO. This typically means the slave
-*				application did not issue a transfer request
-*				fast enough, or the processor/driver could not
-*				fill the transmit register/FIFO fast enough.
-*
-* XST_SPI_RECEIVE_OVERRUN	The QSPIPSU device lost data. Data was received
-*				but the receive data register/FIFO was full.
-*
-* </pre>
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	CallBackRef is the upper layer callback reference passed back
-*		when the callback function is invoked.
-* @param	FuncPointer is the pointer to the callback function.
-*
-* @return	None.
-*
-* @note
-*
-* The handler is called within interrupt context, so it should do its work
-* quickly and queue potentially time-consuming work to a task-level thread.
-*
-******************************************************************************/
-void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
-				XQspiPsu_StatusHandler FuncPointer)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(FuncPointer != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	InstancePtr->StatusHandler = FuncPointer;
-	InstancePtr->StatusRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param	CallBackRef is a pointer to the upper layer callback reference
-* @param	StatusEvent is the event that just occurred.
-* @param	ByteCount is the number of bytes transferred up until the event
-*		occurred.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
-				u32 ByteCount)
-{
-	(void *) CallBackRef;
-	(void) StatusEvent;
-	(void) ByteCount;
-
-	Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-*
-* Selects SPI mode - x1 or x2 or x4.
-*
-* @param	SpiMode - spi or dual or quad.
-* @return	Mask to set desired SPI mode in GENFIFO entry.
-*
-* @note		None.
-*
-******************************************************************************/
-static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
-{
-	u32 Mask;
-	switch (SpiMode) {
-		case XQSPIPSU_SELECT_MODE_DUALSPI:
-			Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
-			break;
-		case XQSPIPSU_SELECT_MODE_QUADSPI:
-			Mask = XQSPIPSU_GENFIFO_MODE_QUADSPI;
-			break;
-		case XQSPIPSU_SELECT_MODE_SPI:
-			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
-			break;
-		default:
-			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
-			break;
-	}
-
-	return Mask;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function checks the TX/RX buffers in the message and setups up the
-* GENFIFO entries, TX FIFO or RX DMA as required.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Msg is a pointer to the structure containing transfer data.
-* @param	GenFifoEntry is pointer to the variable in which GENFIFO mask
-*		is returned to calling function
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
-					u32 *GenFifoEntry)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	/* Transmit */
-	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
-			((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
-		/* Setup data to be TXed */
-		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
-		*GenFifoEntry |= XQSPIPSU_GENFIFO_TX;
-		InstancePtr->TxBytes = (s32)Msg->ByteCount;
-		InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
-		InstancePtr->RecvBufferPtr = NULL;
-		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
-		/* Discard RX data */
-		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_RX;
-		InstancePtr->RxBytes = 0;
-	}
-
-	/* Receive */
-	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE) &&
-			((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE)) {
-		/* TX auto fill */
-		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_TX;
-		InstancePtr->TxBytes = 0;
-		/* Setup RX */
-		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
-		*GenFifoEntry |= XQSPIPSU_GENFIFO_RX;
-		InstancePtr->RxBytes = (s32)Msg->ByteCount;
-		InstancePtr->SendBufferPtr = NULL;
-		InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
-		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
-			XQspiPsu_SetupRxDma(InstancePtr, Msg);
-		}
-	}
-
-	/* If only dummy is requested as a separate entry */
-	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
-			(Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE) {
-		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
-		*GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
-		InstancePtr->TxBytes = 0;
-		InstancePtr->RxBytes = 0;
-		InstancePtr->SendBufferPtr = NULL;
-		InstancePtr->RecvBufferPtr = NULL;
-	}
-
-	/* Dummy and cmd sent by upper layer to received data */
-	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
-			((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
-		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
-		*GenFifoEntry |= (XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
-		InstancePtr->TxBytes = (s32)Msg->ByteCount;
-		InstancePtr->RxBytes = (s32)Msg->ByteCount;
-		InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
-		InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
-		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
-		/* Add check for DMA or PIO here */
-		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
-			XQspiPsu_SetupRxDma(InstancePtr, Msg);
-		}
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* Fills the TX FIFO as long as there is room in the FIFO or the bytes required
-* to be transmitted.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Msg is a pointer to the structure containing transfer data.
-* @param	Size is the number of bytes to be transmitted.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
-					XQspiPsu_Msg *Msg, s32 Size)
-{
-	s32 Count = 0;
-	u32 Data;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
-		if (InstancePtr->TxBytes >= 4) {
-			(void)memcpy(&Data, Msg->TxBfrPtr, 4);
-			Msg->TxBfrPtr += 4;
-			InstancePtr->TxBytes -= 4;
-			Count += 4;
-		} else {
-			(void)memcpy(&Data, Msg->TxBfrPtr, InstancePtr->TxBytes);
-			Msg->TxBfrPtr += InstancePtr->TxBytes;
-			Count += InstancePtr->TxBytes;
-			InstancePtr->TxBytes = 0;
-		}
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-				XQSPIPSU_TXD_OFFSET, Data);
-
-	}
-	if (InstancePtr->TxBytes < 0) {
-		InstancePtr->TxBytes = 0;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets up the RX DMA operation.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Msg is a pointer to the structure containing transfer data.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
-					XQspiPsu_Msg *Msg)
-{
-	s32 Remainder;
-	s32 DmaRxBytes;
-	u64 AddrTemp;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) &
-				XQSPIPSU_QSPIDMA_DST_ADDR_MASK);
-	/* Check for RXBfrPtr to be word aligned */
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET,
-			(u32)AddrTemp);
-
-	AddrTemp = AddrTemp >> 32;
-	if ((AddrTemp & 0xFFFU) != FALSE) {
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
-				(u32)AddrTemp &
-				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
-	}
-
-	Remainder = InstancePtr->RxBytes % 4;
-	DmaRxBytes = InstancePtr->RxBytes;
-	if (Remainder != 0) {
-		/* This is done to make Dma bytes aligned */
-		DmaRxBytes = InstancePtr->RxBytes - Remainder;
-		Msg->ByteCount = (u32)DmaRxBytes;
-	}
-
-	Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount);
-
-	/* Write no. of words to DMA DST SIZE */
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-			XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* This function writes the GENFIFO entry to assert CS.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
-{
-	u32 GenFifoEntry;
-
-	GenFifoEntry = 0x0U;
-	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
-	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
-	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
-	GenFifoEntry |= InstancePtr->GenFifoCS;
-	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
-	GenFifoEntry |= InstancePtr->GenFifoBus;
-	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
-			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
-	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_SETUP;
-
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function writes the GENFIFO entries to transmit the messages requested.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Msg is a pointer to the structure containing transfer data.
-* @param	Index of the current message to be handled.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if transfer fails.
-*		- XST_DEVICE_BUSY if a transfer is already in progress.
-*
-* @note		None.
-*
-******************************************************************************/
-static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
-						XQspiPsu_Msg *Msg, s32 Index)
-{
-	u32 GenFifoEntry;
-	u32 BaseAddress;
-	u32 TempCount;
-	u32 ImmData;
-
-	BaseAddress = InstancePtr->Config.BaseAddress;
-
-	GenFifoEntry = 0x0U;
-	/* Bus width */
-	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
-	GenFifoEntry |= XQspiPsu_SelectSpiMode((u8)Msg[Index].BusWidth);
-
-	GenFifoEntry |= InstancePtr->GenFifoCS;
-	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
-	GenFifoEntry |= InstancePtr->GenFifoBus;
-
-	/* Data */
-	if (((Msg[Index].Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE) {
-		GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
-	} else {
-		GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
-	}
-
-	/* If Byte Count is less than 8 bytes do the transfer in IO mode */
-	if ((Msg[Index].ByteCount < 8U) &&
-		(InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)) {
-			InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
-			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
-				(XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) &
-						~XQSPIPSU_CFG_MODE_EN_MASK));
-			InstancePtr->IsUnaligned = 1;
-	}
-
-	XQspiPsu_TXRXSetup(InstancePtr, &Msg[Index], &GenFifoEntry);
-
-	if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
-		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
-		GenFifoEntry |= Msg[Index].ByteCount;
-		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
-				GenFifoEntry);
-	} else {
-		TempCount = Msg[Index].ByteCount;
-		u32 Exponent = 8;	/* 2^8 = 256 */
-
-		ImmData = TempCount & 0xFFU;
-		/* Exponent entries */
-		GenFifoEntry |= XQSPIPSU_GENFIFO_EXP;
-		while (TempCount != 0U) {
-			if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) {
-				GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
-				GenFifoEntry |= Exponent;
-				XQspiPsu_WriteReg(BaseAddress,
-					XQSPIPSU_GEN_FIFO_OFFSET,
-					GenFifoEntry);
-			}
-			TempCount = TempCount >> 1;
-			Exponent++;
-		}
-
-		/* Immediate entry */
-		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_EXP);
-		if ((ImmData & 0xFFU) != FALSE) {
-			GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
-			GenFifoEntry |= ImmData & 0xFFU;
-			XQspiPsu_WriteReg(BaseAddress,
-				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
-		}
-	}
-
-	/* One dummy GenFifo entry in case of IO mode */
-	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) &&
-			((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
-		GenFifoEntry = 0x0U;
-		XQspiPsu_WriteReg(BaseAddress,
-				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function writes the GENFIFO entry to de-assert CS.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
-{
-	u32 GenFifoEntry;
-
-	GenFifoEntry = 0x0U;
-	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
-	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
-	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
-	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
-	GenFifoEntry |= InstancePtr->GenFifoBus;
-	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
-			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
-	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_HOLD;
-
-	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
-}
-
-/*****************************************************************************/
-/**
-*
-* Read the specified number of bytes from RX FIFO
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Msg is a pointer to the structure containing transfer data.
-* @param	Size is the number of bytes to be read.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
-					XQspiPsu_Msg *Msg, s32 Size)
-{
-	s32 Count = 0;
-	u32 Data;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(Msg != NULL);
-
-	while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
-		Data = XQspiPsu_ReadReg(InstancePtr->
-				Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
-		if (InstancePtr->RxBytes >= 4) {
-			(void)memcpy(Msg->RxBfrPtr, &Data, 4);
-			InstancePtr->RxBytes -= 4;
-			Msg->RxBfrPtr += 4;
-			Count += 4;
-		} else {
-			/* Read unaligned bytes (< 4 bytes) */
-			(void)memcpy(Msg->RxBfrPtr, &Data, InstancePtr->RxBytes);
-			Msg->RxBfrPtr += InstancePtr->RxBytes;
-			Count += InstancePtr->RxBytes;
-			InstancePtr->RxBytes = 0;
-		}
-	}
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h
deleted file mode 100644
index d34438df6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspipsu.h
-* @addtogroup qspipsu_v1_0
-* @{
-* @details
-*
-* This is the header file for the implementation of QSPIPSU driver.
-* Generic QSPI interface allows for communication to any QSPI slave device.
-* GQSPI contains a GENFIFO into which the bus transfers required are to be
-* pushed with appropriate configuration. The controller provides TX and RX
-* FIFO's and a DMA to be used for RX transfers. The controller executes each
-* GENFIFO entry noting the configuration and places data on the bus as required
-*
-* The different options in GENFIFO are as follows:
-* IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
-*            number of bytes in transfer.
-* DATA_XFER : Indicates that data/clocks need to be transmitted or received.
-* EXPONENT : e when 2^e bytes are involved in transfer.
-* SPI_MODE : SPI/Dual SPI/Quad SPI
-* CS : Lower or Upper CS or Both
-* Bus : Lower or Upper Bus or Both
-* TX : When selected, controller transmits data in IMM or fetches number of
-*      bytes mentioned form TX FIFO. If not selected, dummies are pumped.
-* RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
-*      of requested number of bytes. If not selected, RX data is discarded.
-* Stripe : Byte stripe over lower and upper bus or not.
-* Poll : Polls response to match for to a set value (used along with POLL_CFG
-*        registers) and then proceeds to next GENFIFO entry.
-*        This feature is not currently used in the driver.
-*
-* GENFIFO has manual and auto start options.
-* All DMA requests need a 4-byte aligned destination address buffer and
-* size of transfer should also be a multiple of 4.
-* This driver supports DMA RX and IO RX.
-*
-* Initialization:
-* This driver uses the GQSPI controller with RX DMA. It supports both
-* interrupt and polled transfers. Manual start of GENFIFO is used.
-* XQspiPsu_CfgInitialize() initializes the instance variables.
-* Additional setting can be done using SetOptions/ClearOptions functions
-* and SelectSlave function.
-*
-* Transfer:
-* Polled or Interrupt transfers can be done. The transfer function needs the
-* message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
-* This is supposed to contain the byte count and any TX/RX buffers as required.
-* Flags can be used indicate further information such as whether the message
-* should be striped. The transfer functions form and write GENFIFO entries,
-* check the status of the transfer and report back to the application
-* when done.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------.
-* 1.0   hk  08/21/14 First release
-*       sk  03/13/15 Added IO mode support.
-*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
-*                    Clear and disbale DMA interrupts/status in abort.
-*                    Use DMA DONE bit instead of BUSY as recommended.
-*       sk  04/24/15 Modified the code according to MISRAC-2012.
-*       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
-*                    writing/reading from 0x0 location is permitted.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XQSPIPSU_H_		/* prevent circular inclusions */
-#define XQSPIPSU_H_		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspipsu_hw.h"
-#include "xil_cache.h"
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPIPSU device.  The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode.  The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param	CallBackRef is the callback reference passed in by the upper
- *		layer when setting the callback functions, and passed back to
- *		the upper layer when the callback is invoked. Its type is
- *		not important to the driver, so it is a void pointer.
- * @param 	StatusEvent holds one or more status events that have occurred.
- *		See the XQspiPsu_SetStatusHandler() for details on the status
- *		events that can be passed in the callback.
- * @param	ByteCount indicates how many bytes of data were successfully
- *		transferred.  This may be less than the number of bytes
- *		requested if the status event indicates an error.
- */
-typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
-					u32 ByteCount);
-
-/**
- * This typedef contains configuration information for a flash message.
- */
-typedef struct {
-	u8 *TxBfrPtr;
-	u8 *RxBfrPtr;
-	u32 ByteCount;
-	u32 BusWidth;
-	u32 Flags;
-} XQspiPsu_Msg;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID  of device */
-	u32 BaseAddress;	/**< Base address of the device */
-	u32 InputClockHz;	/**< Input clock frequency */
-	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
-	u8  BusWidth; 	/**< Bus width available on board */
-} XQspiPsu_Config;
-
-/**
- * The XQspiPsu driver instance data. The user is required to allocate a
- * variable of this type for every QSPIPSU device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XQspiPsu_Config Config;	 /**< Configuration structure */
-	u32 IsReady;		 /**< Device is initialized and ready */
-
-	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
-	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
-	u8 *GenFifoBufferPtr;	 /**< Gen FIFO entries */
-	s32 TxBytes;	 /**< Number of bytes to transfer (state) */
-	s32 RxBytes;	 /**< Number of bytes left to transfer(state) */
-	s32 GenFifoEntries;	 /**< Number of Gen FIFO entries remaining */
-	u32 IsBusy;		 /**< A transfer is in progress (state) */
-	u32 ReadMode;		 /**< DMA or IO mode */
-	u32 GenFifoCS;
-	u32 GenFifoBus;
-	s32 NumMsg;
-	s32 MsgCnt;
-	s32 IsUnaligned;
-	u8 IsManualstart;
-	XQspiPsu_Msg *Msg;
-	XQspiPsu_StatusHandler StatusHandler;
-	void *StatusRef;  	 /**< Callback reference for status handler */
-} XQspiPsu;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQSPIPSU_READMODE_DMA	0x0U
-#define XQSPIPSU_READMODE_IO	0x1U
-
-#define XQSPIPSU_SELECT_FLASH_CS_LOWER	0x1U
-#define XQSPIPSU_SELECT_FLASH_CS_UPPER	0x2U
-#define XQSPIPSU_SELECT_FLASH_CS_BOTH	0x3U
-
-#define XQSPIPSU_SELECT_FLASH_BUS_LOWER	0x1U
-#define XQSPIPSU_SELECT_FLASH_BUS_UPPER	0x2U
-#define XQSPIPSU_SELECT_FLASH_BUS_BOTH	0x3U
-
-#define XQSPIPSU_SELECT_MODE_SPI	0x1U
-#define XQSPIPSU_SELECT_MODE_DUALSPI	0x2U
-#define XQSPIPSU_SELECT_MODE_QUADSPI	0x4U
-
-#define XQSPIPSU_GENFIFO_CS_SETUP	0x05U
-#define XQSPIPSU_GENFIFO_CS_HOLD	0x04U
-
-#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION	0x2U
-#define XQSPIPSU_CLK_PHASE_1_OPTION	0x4U
-#define XQSPIPSU_MANUAL_START_OPTION	0x8U
-
-#define XQSPIPSU_GENFIFO_EXP_START	0x100U
-
-#define XQSPIPSU_DMA_BYTES_MAX		0x10000000U
-
-#define XQSPIPSU_CLK_PRESCALE_2		0x00U
-#define XQSPIPSU_CLK_PRESCALE_4		0x01U
-#define XQSPIPSU_CLK_PRESCALE_8		0x02U
-#define XQSPIPSU_CLK_PRESCALE_16		0x03U
-#define XQSPIPSU_CLK_PRESCALE_32		0x04U
-#define XQSPIPSU_CLK_PRESCALE_64		0x05U
-#define XQSPIPSU_CLK_PRESCALE_128	0x06U
-#define XQSPIPSU_CLK_PRESCALE_256	0x07U
-#define XQSPIPSU_CR_PRESC_MAXIMUM	7U
-
-#define XQSPIPSU_CONNECTION_MODE_SINGLE		0U
-#define XQSPIPSU_CONNECTION_MODE_STACKED	1U
-#define XQSPIPSU_CONNECTION_MODE_PARALLEL	2U
-
-/* Add more flags as required */
-#define XQSPIPSU_MSG_FLAG_STRIPE	0x1U
-#define XQSPIPSU_MSG_FLAG_RX		0x2U
-#define XQSPIPSU_MSG_FLAG_TX		0x4U
-
-#define XQspiPsu_Select(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
-
-#define XQspiPsu_Enable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
-
-#define XQspiPsu_Disable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
-
-/************************** Function Prototypes ******************************/
-
-/* Initialization and reset */
-XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
-s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
-				u32 EffectiveAddr);
-void XQspiPsu_Reset(XQspiPsu *InstancePtr);
-void XQspiPsu_Abort(XQspiPsu *InstancePtr);
-
-/* Transfer functions and handlers */
-s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
-				u32 NumMsg);
-s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
-				u32 NumMsg);
-s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
-void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
-				XQspiPsu_StatusHandler FuncPointer);
-
-/* Configuration functions */
-s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
-void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
-s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
-s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
-u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
-s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* XQSPIPSU_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
deleted file mode 100644
index daa5bde27..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
+++ /dev/null
@@ -1,58 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xqspipsu.h"
-
-/*
-* The configuration table for devices
-*/
-
-XQspiPsu_Config XQspiPsu_ConfigTable[] =
-{
-	{
-		XPAR_PSU_QSPI_0_DEVICE_ID,
-		XPAR_PSU_QSPI_0_BASEADDR,
-		XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ,
-		XPAR_PSU_QSPI_0_QSPI_MODE,
-		XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h
deleted file mode 100644
index 508109019..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h
+++ /dev/null
@@ -1,841 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspipsu_hw.h
-* @addtogroup qspipsu_v1_0
-* @{
-*
-* This file contains low level access funcitons using the base address
-* directly without an instance.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------.
-* 1.0   hk  08/21/14 First release
-*       hk  03/18/15 Add DMA status register masks required.
-*       sk  04/24/15 Modified the code according to MISRAC-2012.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef _XQSPIPSU_HW_H_		/* prevent circular inclusions */
-#define _XQSPIPSU_HW_H_		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * QSPI Base Address
- */
-#define XQSPIPS_BASEADDR      0XFF0F0000U
-
-/**
- * GQSPI Base Address
- */
-#define XQSPIPSU_BASEADDR     0xFF0F0100U
-#define XQSPIPSU_OFFSET     0x100U
-
-/**
- * Register: XQSPIPS_EN_REG
- */
-#define XQSPIPS_EN_REG    ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
-
-#define XQSPIPS_EN_SHIFT   0
-#define XQSPIPS_EN_WIDTH   1
-#define XQSPIPS_EN_MASK    0X00000001U
-
-/**
- * Register: XQSPIPSU_CFG
- */
-#define XQSPIPSU_CFG_OFFSET    0X00000000U
-
-#define XQSPIPSU_CFG_MODE_EN_SHIFT   30
-#define XQSPIPSU_CFG_MODE_EN_WIDTH   2
-#define XQSPIPSU_CFG_MODE_EN_MASK    0XC0000000U
-#define XQSPIPSU_CFG_MODE_EN_DMA_MASK	0X80000000U
-
-#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT   29
-#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH   1
-#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK    0X20000000U
-
-#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT   28
-#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH   1
-#define XQSPIPSU_CFG_START_GEN_FIFO_MASK    0X10000000U
-
-#define XQSPIPSU_CFG_ENDIAN_SHIFT   26
-#define XQSPIPSU_CFG_ENDIAN_WIDTH   1
-#define XQSPIPSU_CFG_ENDIAN_MASK    0X04000000U
-
-#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT   20
-#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH   1
-#define XQSPIPSU_CFG_EN_POLL_TO_MASK    0X00100000U
-
-#define XQSPIPSU_CFG_WP_HOLD_SHIFT   19
-#define XQSPIPSU_CFG_WP_HOLD_WIDTH   1
-#define XQSPIPSU_CFG_WP_HOLD_MASK    0X00080000U
-
-#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT   3
-#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH   3
-#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK    0X00000038U
-
-#define XQSPIPSU_CFG_CLK_PHA_SHIFT   2
-#define XQSPIPSU_CFG_CLK_PHA_WIDTH   1
-#define XQSPIPSU_CFG_CLK_PHA_MASK    0X00000004U
-
-#define XQSPIPSU_CFG_CLK_POL_SHIFT   1
-#define XQSPIPSU_CFG_CLK_POL_WIDTH   1
-#define XQSPIPSU_CFG_CLK_POL_MASK    0X00000002U
-
-/**
- * Register: XQSPIPSU_ISR
- */
-#define XQSPIPSU_ISR_OFFSET	0X00000004U
-
-#define XQSPIPSU_ISR_RXEMPTY_SHIFT   11
-#define XQSPIPSU_ISR_RXEMPTY_WIDTH   1
-#define XQSPIPSU_ISR_RXEMPTY_MASK    0X00000800U
-
-#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT   10
-#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH   1
-#define XQSPIPSU_ISR_GENFIFOFULL_MASK    0X00000400U
-
-#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT   9
-#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH   1
-#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK    0X00000200U
-
-#define XQSPIPSU_ISR_TXEMPTY_SHIFT   8
-#define XQSPIPSU_ISR_TXEMPTY_WIDTH   1
-#define XQSPIPSU_ISR_TXEMPTY_MASK    0X00000100U
-
-#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT   7
-#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH   1
-#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK    0X00000080U
-
-#define XQSPIPSU_ISR_RXFULL_SHIFT   5
-#define XQSPIPSU_ISR_RXFULL_WIDTH   1
-#define XQSPIPSU_ISR_RXFULL_MASK    0X00000020U
-
-#define XQSPIPSU_ISR_RXNEMPTY_SHIFT   4
-#define XQSPIPSU_ISR_RXNEMPTY_WIDTH   1
-#define XQSPIPSU_ISR_RXNEMPTY_MASK    0X00000010U
-
-#define XQSPIPSU_ISR_TXFULL_SHIFT   3
-#define XQSPIPSU_ISR_TXFULL_WIDTH   1
-#define XQSPIPSU_ISR_TXFULL_MASK    0X00000008U
-
-#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT   2
-#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH   1
-#define XQSPIPSU_ISR_TXNOT_FULL_MASK    0X00000004U
-
-#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT   1
-#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH   1
-#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK    0X00000002U
-
-#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
-
-/**
- * Register: XQSPIPSU_IER
- */
-#define XQSPIPSU_IER_OFFSET    0X00000008U
-
-#define XQSPIPSU_IER_RXEMPTY_SHIFT   11
-#define XQSPIPSU_IER_RXEMPTY_WIDTH   1
-#define XQSPIPSU_IER_RXEMPTY_MASK    0X00000800U
-
-#define XQSPIPSU_IER_GENFIFOFULL_SHIFT   10
-#define XQSPIPSU_IER_GENFIFOFULL_WIDTH   1
-#define XQSPIPSU_IER_GENFIFOFULL_MASK    0X00000400U
-
-#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT   9
-#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH   1
-#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK    0X00000200U
-
-#define XQSPIPSU_IER_TXEMPTY_SHIFT   8
-#define XQSPIPSU_IER_TXEMPTY_WIDTH   1
-#define XQSPIPSU_IER_TXEMPTY_MASK    0X00000100U
-
-#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT   7
-#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH   1
-#define XQSPIPSU_IER_GENFIFOEMPTY_MASK    0X00000080U
-
-#define XQSPIPSU_IER_RXFULL_SHIFT   5
-#define XQSPIPSU_IER_RXFULL_WIDTH   1
-#define XQSPIPSU_IER_RXFULL_MASK    0X00000020U
-
-#define XQSPIPSU_IER_RXNEMPTY_SHIFT   4
-#define XQSPIPSU_IER_RXNEMPTY_WIDTH   1
-#define XQSPIPSU_IER_RXNEMPTY_MASK    0X00000010U
-
-#define XQSPIPSU_IER_TXFULL_SHIFT   3
-#define XQSPIPSU_IER_TXFULL_WIDTH   1
-#define XQSPIPSU_IER_TXFULL_MASK    0X00000008U
-
-#define XQSPIPSU_IER_TXNOT_FULL_SHIFT   2
-#define XQSPIPSU_IER_TXNOT_FULL_WIDTH   1
-#define XQSPIPSU_IER_TXNOT_FULL_MASK    0X00000004U
-
-#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT   1
-#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH   1
-#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK    0X00000002U
-
-/**
- * Register: XQSPIPSU_IDR
- */
-#define XQSPIPSU_IDR_OFFSET    0X0000000CU
-
-#define XQSPIPSU_IDR_RXEMPTY_SHIFT   11
-#define XQSPIPSU_IDR_RXEMPTY_WIDTH   1
-#define XQSPIPSU_IDR_RXEMPTY_MASK    0X00000800U
-
-#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT   10
-#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH   1
-#define XQSPIPSU_IDR_GENFIFOFULL_MASK    0X00000400U
-
-#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT   9
-#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH   1
-#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK    0X00000200U
-
-#define XQSPIPSU_IDR_TXEMPTY_SHIFT   8
-#define XQSPIPSU_IDR_TXEMPTY_WIDTH   1
-#define XQSPIPSU_IDR_TXEMPTY_MASK    0X00000100U
-
-#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT   7
-#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH   1
-#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK    0X00000080U
-
-#define XQSPIPSU_IDR_RXFULL_SHIFT   5
-#define XQSPIPSU_IDR_RXFULL_WIDTH   1
-#define XQSPIPSU_IDR_RXFULL_MASK    0X00000020U
-
-#define XQSPIPSU_IDR_RXNEMPTY_SHIFT   4
-#define XQSPIPSU_IDR_RXNEMPTY_WIDTH   1
-#define XQSPIPSU_IDR_RXNEMPTY_MASK    0X00000010U
-
-#define XQSPIPSU_IDR_TXFULL_SHIFT   3
-#define XQSPIPSU_IDR_TXFULL_WIDTH   1
-#define XQSPIPSU_IDR_TXFULL_MASK    0X00000008U
-
-#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT   2
-#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH   1
-#define XQSPIPSU_IDR_TXNOT_FULL_MASK    0X00000004U
-
-#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT   1
-#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH   1
-#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK    0X00000002U
-
-#define XQSPIPSU_IDR_ALL_MASK    0X0FBEU
-
-/**
- * Register: XQSPIPSU_IMR
- */
-#define XQSPIPSU_IMR_OFFSET    0X00000010U
-
-#define XQSPIPSU_IMR_RXEMPTY_SHIFT   11
-#define XQSPIPSU_IMR_RXEMPTY_WIDTH   1
-#define XQSPIPSU_IMR_RXEMPTY_MASK    0X00000800U
-
-#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT   10
-#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH   1
-#define XQSPIPSU_IMR_GENFIFOFULL_MASK    0X00000400U
-
-#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT   9
-#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH   1
-#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK    0X00000200U
-
-#define XQSPIPSU_IMR_TXEMPTY_SHIFT   8
-#define XQSPIPSU_IMR_TXEMPTY_WIDTH   1
-#define XQSPIPSU_IMR_TXEMPTY_MASK    0X00000100U
-
-#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT   7
-#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH   1
-#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK    0X00000080U
-
-#define XQSPIPSU_IMR_RXFULL_SHIFT   5
-#define XQSPIPSU_IMR_RXFULL_WIDTH   1
-#define XQSPIPSU_IMR_RXFULL_MASK    0X00000020U
-
-#define XQSPIPSU_IMR_RXNEMPTY_SHIFT   4
-#define XQSPIPSU_IMR_RXNEMPTY_WIDTH   1
-#define XQSPIPSU_IMR_RXNEMPTY_MASK    0X00000010U
-
-#define XQSPIPSU_IMR_TXFULL_SHIFT   3
-#define XQSPIPSU_IMR_TXFULL_WIDTH   1
-#define XQSPIPSU_IMR_TXFULL_MASK    0X00000008U
-
-#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT   2
-#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH   1
-#define XQSPIPSU_IMR_TXNOT_FULL_MASK    0X00000004U
-
-#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT   1
-#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH   1
-#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK    0X00000002U
-
-/**
- * Register: XQSPIPSU_EN_REG
- */
-#define XQSPIPSU_EN_OFFSET    0X00000014U
-
-#define XQSPIPSU_EN_SHIFT   0
-#define XQSPIPSU_EN_WIDTH   1
-#define XQSPIPSU_EN_MASK    0X00000001U
-
-/**
- * Register: XQSPIPSU_TXD
- */
-#define XQSPIPSU_TXD_OFFSET    0X0000001CU
-
-#define XQSPIPSU_TXD_SHIFT   0
-#define XQSPIPSU_TXD_WIDTH   32
-#define XQSPIPSU_TXD_MASK    0XFFFFFFFFU
-
-#define XQSPIPSU_TXD_DEPTH    64
-
-/**
- * Register: XQSPIPSU_RXD
- */
-#define XQSPIPSU_RXD_OFFSET    0X00000020U
-
-#define XQSPIPSU_RXD_SHIFT   0
-#define XQSPIPSU_RXD_WIDTH   32
-#define XQSPIPSU_RXD_MASK    0XFFFFFFFFU
-
-/**
- * Register: XQSPIPSU_TX_THRESHOLD
- */
-#define XQSPIPSU_TX_THRESHOLD_OFFSET    0X00000028U
-
-#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT   0
-#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH   6
-#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK    0X0000003FU
-#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL    0X01U
-
-/**
- * Register: XQSPIPSU_RX_THRESHOLD
- */
-#define XQSPIPSU_RX_THRESHOLD_OFFSET    0X0000002CU
-
-#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT   0
-#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH   6
-#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK    0X0000003FU
-#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL    0X01U
-
-#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
-
-/**
- * Register: XQSPIPSU_GPIO
- */
-#define XQSPIPSU_GPIO_OFFSET    0X00000030U
-
-#define XQSPIPSU_GPIO_WP_N_SHIFT   0
-#define XQSPIPSU_GPIO_WP_N_WIDTH   1
-#define XQSPIPSU_GPIO_WP_N_MASK    0X00000001U
-
-/**
- * Register: XQSPIPSU_LPBK_DLY_ADJ
- */
-#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET    0X00000038U
-
-#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT   5
-#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH   1
-#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK    0X00000020U
-
-#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT   3
-#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH   2
-#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK    0X00000018U
-
-#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT   0
-#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH   3
-#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK    0X00000007U
-
-/**
- * Register: XQSPIPSU_GEN_FIFO
- */
-#define XQSPIPSU_GEN_FIFO_OFFSET    0X00000040U
-
-#define XQSPIPSU_GEN_FIFO_DATA_SHIFT   0
-#define XQSPIPSU_GEN_FIFO_DATA_WIDTH   20
-#define XQSPIPSU_GEN_FIFO_DATA_MASK    0X000FFFFFU
-
-/**
- * Register: XQSPIPSU_SEL
- */
-#define XQSPIPSU_SEL_OFFSET    0X00000044U
-
-#define XQSPIPSU_SEL_SHIFT   0
-#define XQSPIPSU_SEL_WIDTH   1
-#define XQSPIPSU_SEL_MASK    0X00000001U
-
-/**
- * Register: XQSPIPSU_FIFO_CTRL
- */
-#define XQSPIPSU_FIFO_CTRL_OFFSET    0X0000004CU
-
-#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT   2
-#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH   1
-#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK    0X00000004U
-
-#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT   1
-#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH   1
-#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK    0X00000002U
-
-#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT   0
-#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH   1
-#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK    0X00000001U
-
-/**
- * Register: XQSPIPSU_GF_THRESHOLD
- */
-#define XQSPIPSU_GF_THRESHOLD_OFFSET    0X00000050U
-
-#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT   0
-#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH   5
-#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK    0X0000001F
-#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL    0X10U
-
-/**
- * Register: XQSPIPSU_POLL_CFG
- */
-#define XQSPIPSU_POLL_CFG_OFFSET    0X00000054U
-
-#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT   31
-#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH   1
-#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK    0X80000000U
-
-#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT   30
-#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH   1
-#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK    0X40000000U
-
-#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT   8
-#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH   8
-#define XQSPIPSU_POLL_CFG_MASK_EN_MASK    0X0000FF00U
-
-#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT   0
-#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH   8
-#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK    0X000000FFU
-
-/**
- * Register: XQSPIPSU_P_TIMEOUT
- */
-#define XQSPIPSU_P_TO_OFFSET    0X00000058U
-
-#define XQSPIPSU_P_TO_VALUE_SHIFT   0
-#define XQSPIPSU_P_TO_VALUE_WIDTH   32
-#define XQSPIPSU_P_TO_VALUE_MASK    0XFFFFFFFFU
-
-/**
- * Register: XQSPIPSU_XFER_STS
- */
-#define XQSPIPSU_XFER_STS_OFFSET	0X0000005CU
-
-#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT   0
-#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH   32
-#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK    0XFFFFFFFFU
-
-/**
- * Register: XQSPIPSU_GF_SNAPSHOT
- */
-#define XQSPIPSU_GF_SNAPSHOT_OFFSET    0X00000060U
-
-#define XQSPIPSU_GF_SNAPSHOT_SHIFT   0
-#define XQSPIPSU_GF_SNAPSHOT_WIDTH   20
-#define XQSPIPSU_GF_SNAPSHOT_MASK    0X000FFFFFU
-
-/**
- * Register: XQSPIPSU_RX_COPY
- */
-#define XQSPIPSU_RX_COPY_OFFSET    0X00000064U
-
-#define XQSPIPSU_RX_COPY_UPPER_SHIFT   8
-#define XQSPIPSU_RX_COPY_UPPER_WIDTH   8
-#define XQSPIPSU_RX_COPY_UPPER_MASK    0X0000FF00U
-
-#define XQSPIPSU_RX_COPY_LOWER_SHIFT   0
-#define XQSPIPSU_RX_COPY_LOWER_WIDTH   8
-#define XQSPIPSU_RX_COPY_LOWER_MASK    0X000000FFU
-
-/**
- * Register: XQSPIPSU_MOD_ID
- */
-#define XQSPIPSU_MOD_ID_OFFSET    0X000000FCU
-
-#define XQSPIPSU_MOD_ID_SHIFT   0
-#define XQSPIPSU_MOD_ID_WIDTH   32
-#define XQSPIPSU_MOD_ID_MASK    0XFFFFFFFFU
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_ADDR
- */
-#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET    0X00000700U
-
-#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT   2
-#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH   30
-#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK    0XFFFFFFFCU
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_SIZE
- */
-#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET    0X00000704U
-
-#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT   2
-#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH   27
-#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK    0X1FFFFFFCU
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_STS
- */
-#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET    0X00000708U
-
-#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT   13
-#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH   3
-#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK    0X0000E000U
-
-#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5
-#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8
-#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK    0X00001FE0U
-
-#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1
-#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4
-#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK    0X0000001EU
-
-#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT   0
-#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK    0X00000001U
-
-#define XQSPIPSU_QSPIDMA_DST_STS_WTC	0xE000U
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_CTRL
- */
-#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET    0X0000070CU
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT   25
-#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH   7
-#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK    0XFE000000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24
-#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK    0X01000000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT   23
-#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK    0X00800000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22
-#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK    0X00400000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT   10
-#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH   12
-#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK    0X003FFC00U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT   2
-#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH   8
-#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK    0X000003FCU
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK    0X00000002U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0
-#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK    0X00000001U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL	0x403FFA00U
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_I_STS
- */
-#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET    0X00000714U
-
-#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT   7
-#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK    0X00000080U
-
-#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6
-#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK    0X00000040U
-
-#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT   5
-#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK    0X00000020U
-
-#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT   4
-#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK    0X00000010U
-
-#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT   3
-#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK    0X00000008U
-
-#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2
-#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK    0X00000004U
-
-#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK    0X00000002U
-
-#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK    0X000000FCU
-#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK    0X000000FEU
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_I_EN
- */
-#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET    0X00000718U
-
-#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT   7
-#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK    0X00000080U
-
-#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6
-#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK    0X00000040U
-
-#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT   5
-#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK    0X00000020U
-
-#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT   4
-#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK    0X00000010U
-
-#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT   3
-#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK    0X00000008U
-
-#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2
-#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK    0X00000004U
-
-#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK    0X00000002U
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_I_DIS
- */
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET    0X0000071CU
-
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT   7
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK    0X00000080U
-
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK    0X00000040U
-
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT   5
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK    0X00000020U
-
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT   4
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK    0X00000010U
-
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT   3
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK    0X00000008U
-
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK    0X00000004U
-
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK    0X00000002U
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_IMR
- */
-#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET    0X00000720U
-
-#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT   7
-#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK    0X00000080U
-
-#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT   6
-#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK    0X00000040U
-
-#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT   5
-#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK    0X00000020U
-
-#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT   4
-#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK    0X00000010U
-
-#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT   3
-#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK    0X00000008U
-
-#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT   2
-#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK    0X00000004U
-
-#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK    0X00000002U
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_CTRL2
- */
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET    0X00000724U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK    0X08000000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK    0X07000000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT   22
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH   1
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK    0X00400000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK    0X00380000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK    0X00070000U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT   4
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH   12
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK    0X0000FFF0U
-
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4
-#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK    0X0000000FU
-
-/**
- * Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
- */
-#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET    0X00000728U
-
-#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT   0
-#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH   12
-#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK    0X00000FFFU
-
-/**
- * Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
- */
-#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET    0X00000EFCU
-
-#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT   0
-#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH   32
-#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK    0XFFFFFFFFU
-
-/*
- * Generic FIFO masks
- */
-#define XQSPIPSU_GENFIFO_IMM_DATA_MASK	0xFFU
-#define XQSPIPSU_GENFIFO_DATA_XFER	0x100U
-#define XQSPIPSU_GENFIFO_EXP		0x200U
-#define XQSPIPSU_GENFIFO_MODE_SPI	0x400U
-#define XQSPIPSU_GENFIFO_MODE_DUALSPI	0x800U
-#define XQSPIPSU_GENFIFO_MODE_QUADSPI	0xC00U
-#define XQSPIPSU_GENFIFO_MODE_MASK	0xC00U	/* And with ~MASK first */
-#define XQSPIPSU_GENFIFO_CS_LOWER	0x1000U
-#define XQSPIPSU_GENFIFO_CS_UPPER	0x2000U
-#define XQSPIPSU_GENFIFO_BUS_LOWER	0x4000U
-#define XQSPIPSU_GENFIFO_BUS_UPPER	0x8000U
-#define XQSPIPSU_GENFIFO_BUS_BOTH	0xC000U	/* inverse is no bus */
-#define XQSPIPSU_GENFIFO_BUS_MASK	0xC000U	/* And with ~MASK first */
-#define XQSPIPSU_GENFIFO_TX		0x10000U	/* inverse is zero pump */
-#define XQSPIPSU_GENFIFO_RX		0x20000U	/* inverse is RX discard */
-#define XQSPIPSU_GENFIFO_STRIPE		0x40000U
-#define XQSPIPSU_GENFIFO_POLL		0x80000U
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPsu_In32 Xil_In32
-#define XQspiPsu_Out32 Xil_Out32
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to the target register.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)
-*
-******************************************************************************/
-#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to target register.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset,
-*		u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* _XQSPIPSU_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c
deleted file mode 100644
index 97eee8cfd..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c
+++ /dev/null
@@ -1,449 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspipsu_options.c
-* @addtogroup qspipsu_v1_0
-* @{
-*
-* This file implements funcitons to configure the QSPIPSU component,
-* specifically some optional settings, clock and flash related information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------
-* 1.0   hk  08/21/14 First release
-*       sk  03/13/15 Added IO mode support.
-*       sk  04/24/15 Modified the code according to MISRAC-2012.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspipsu.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
-	u32 Option;
-	u32 Mask;
-} OptionsMap;
-
-static OptionsMap OptionsTable[] = {
-	{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
-	{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
-	{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
-};
-
-#define XQSPIPSU_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the QSPIPSU device driver.The options
-* control how the device behaves relative to the QSPIPSU bus. The device must be
-* idle rather than busy transferring data before setting these device options.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Options contains the specified options to be set. This is a bit
-*		mask where a 1 indicates the option should be turned ON and
-*		a 0 indicates no action. One or more bit values may be
-*		contained in the mask. See the bit definitions named
-*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
-*
-* @return
-*		- XST_SUCCESS if options are successfully set.
-*		- XST_DEVICE_BUSY if the device is currently transferring data.
-*		The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
-{
-	u32 ConfigReg;
-	u32 Index;
-	u32 QspiPsuOptions;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Do not allow to modify the Control Register while a transfer is in
-	 * progress. Not thread-safe.
-	 */
-	if (InstancePtr->IsBusy == TRUE) {
-		Status = (s32)XST_DEVICE_BUSY;
-	} else {
-
-		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-					      XQSPIPSU_CFG_OFFSET);
-
-		/*
-		 * Loop through the options table, turning the option on
-		 * depending on whether the bit is set in the incoming options flag.
-		 */
-		for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
-			if ((Options & OptionsTable[Index].Option) != FALSE) {
-				/* Turn it on */
-				ConfigReg |= OptionsTable[Index].Mask;
-			}
-		}
-
-		/*
-		 * Now write the control register. Leave it to the upper layers
-		 * to restart the device.
-		 */
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
-				 ConfigReg);
-
-		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
-			InstancePtr->IsManualstart = TRUE;
-		}
-
-		Status = XST_SUCCESS;
-	}
-
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function resets the options for the QSPIPSU device driver.The options
-* control how the device behaves relative to the QSPIPSU bus. The device must be
-* idle rather than busy transferring data before setting these device options.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Options contains the specified options to be set. This is a bit
-*		mask where a 1 indicates the option should be turned OFF and
-*		a 0 indicates no action. One or more bit values may be
-*		contained in the mask. See the bit definitions named
-*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
-*
-* @return
-*		- XST_SUCCESS if options are successfully set.
-*		- XST_DEVICE_BUSY if the device is currently transferring data.
-*		The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
-{
-	u32 ConfigReg;
-	u32 Index;
-	u32 QspiPsuOptions;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Do not allow to modify the Control Register while a transfer is in
-	 * progress. Not thread-safe.
-	 */
-	if (InstancePtr->IsBusy == TRUE) {
-		Status = (s32)XST_DEVICE_BUSY;
-	} else {
-
-		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-					      XQSPIPSU_CFG_OFFSET);
-
-		/*
-		 * Loop through the options table, turning the option on
-		 * depending on whether the bit is set in the incoming options flag.
-		 */
-		for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
-			if ((Options & OptionsTable[Index].Option) != FALSE) {
-				/* Turn it off */
-				ConfigReg &= ~OptionsTable[Index].Mask;
-			}
-		}
-
-		/*
-		 * Now write the control register. Leave it to the upper layers
-		 * to restart the device.
-		 */
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
-				 ConfigReg);
-
-		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
-			InstancePtr->IsManualstart = FALSE;
-		}
-
-		Status = XST_SUCCESS;
-	}
-
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the options for the QSPIPSU device. The options control how
-* the device behaves relative to the QSPIPSU bus.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-*
-* @return
-*
-* Options contains the specified options currently set. This is a bit value
-* where a 1 means the option is on, and a 0 means the option is off.
-* See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
-{
-	u32 OptionsFlag = 0;
-	u32 ConfigReg;
-	u32 Index;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Get the current options from QSPIPSU configuration register.
-	 */
-	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-				      XQSPIPSU_CFG_OFFSET);
-
-	/* Loop through the options table to grab options */
-	for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
-		if ((ConfigReg & OptionsTable[Index].Mask) != FALSE) {
-			OptionsFlag |= OptionsTable[Index].Option;
-		}
-	}
-
-	return OptionsFlag;
-}
-
-/*****************************************************************************/
-/**
-*
-* Configures the clock according to the prescaler passed.
-*
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Prescaler - clock prescaler to be set.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_DEVICE_IS_STARTED if the device is already started.
-*		It must be stopped to re-initialize.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
-{
-	u32 ConfigReg;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
-
-	/*
-	 * Do not allow the slave select to change while a transfer is in
-	 * progress. Not thread-safe.
-	 */
-	if (InstancePtr->IsBusy == TRUE) {
-		Status = (s32)XST_DEVICE_BUSY;
-	} else {
-
-		/*
-		 * Read the configuration register, mask out the relevant bits, and set
-		 * them with the shifted value passed into the function. Write the
-		 * results back to the configuration register.
-		 */
-		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-					      XQSPIPSU_CFG_OFFSET);
-
-		ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
-		ConfigReg |= (u32) ((u32)Prescaler & (u32)XQSPIPSU_CR_PRESC_MAXIMUM) <<
-				    XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
-
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-				  XQSPIPSU_CFG_OFFSET, ConfigReg);
-
-		Status = XST_SUCCESS;
-	}
-
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This funciton should be used to tell the QSPIPSU driver the HW flash
-* configuration being used. This API should be called atleast once in the
-* application. If desired, it can be called multiple times when switching
-* between communicating to different flahs devices/using different configs.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	FlashCS - Flash Chip Select.
-* @param	FlashBus - Flash Bus (Upper, Lower or Both).
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_DEVICE_IS_STARTED if the device is already started.
-*		It must be stopped to re-initialize.
-*
-* @note		If this funciton is not called atleast once in the application,
-*		the driver assumes there is a single flash connected to the
-*		lower bus and CS line.
-*
-******************************************************************************/
-void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	/*
-	 * Bus and CS lines selected here will be updated in the instance and
-	 * used for subsequent GENFIFO entries during transfer.
-	 */
-
-	/* Choose slave select line */
-	switch (FlashCS) {
-		case XQSPIPSU_SELECT_FLASH_CS_BOTH:
-			InstancePtr->GenFifoCS = (u32)XQSPIPSU_GENFIFO_CS_LOWER |
-						(u32)XQSPIPSU_GENFIFO_CS_UPPER;
-			break;
-		case XQSPIPSU_SELECT_FLASH_CS_UPPER:
-			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_UPPER;
-			break;
-		case XQSPIPSU_SELECT_FLASH_CS_LOWER:
-			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
-			break;
-		default:
-			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
-			break;
-	}
-
-	/* Choose bus */
-	switch (FlashBus) {
-		case XQSPIPSU_SELECT_FLASH_BUS_BOTH:
-			InstancePtr->GenFifoBus = (u32)XQSPIPSU_GENFIFO_BUS_LOWER |
-						(u32)XQSPIPSU_GENFIFO_BUS_UPPER;
-			break;
-		case XQSPIPSU_SELECT_FLASH_BUS_UPPER:
-			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_UPPER;
-			break;
-		case XQSPIPSU_SELECT_FLASH_BUS_LOWER:
-			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
-			break;
-		default:
-			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
-			break;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the Read mode for the QSPIPSU device driver.The device
-* must be idle rather than busy transferring data before setting Read mode
-* options.
-*
-* @param	InstancePtr is a pointer to the XQspiPsu instance.
-* @param	Mode contains the specified Mode to be set. See the
-* 		bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.
-*
-* @return
-*		- XST_SUCCESS if options are successfully set.
-*		- XST_DEVICE_BUSY if the device is currently transferring data.
-*		The transfer must complete or be aborted before setting Mode.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
-{
-	u32 ConfigReg;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Do not allow to modify the Control Register while a transfer is in
-	 * progress. Not thread-safe.
-	 */
-	if (InstancePtr->IsBusy == TRUE) {
-		Status = (s32)XST_DEVICE_BUSY;
-	} else {
-
-		InstancePtr->ReadMode = Mode;
-
-		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-					      XQSPIPSU_CFG_OFFSET);
-
-		if (Mode == XQSPIPSU_READMODE_DMA) {
-			ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
-			ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
-		} else {
-			ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
-		}
-
-		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
-				 ConfigReg);
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c
deleted file mode 100644
index 63aaed0bb..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspipsu_sinit.c
-* @addtogroup qspipsu_v1_0
-* @{
-*
-* The implementation of the XQspiPsu component's static initialization
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------
-* 1.0   hk  08/21/14 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspipsu.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param	DeviceId contains the ID of the device to look up the
-*		configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xqspipsu.h for the definition of XQspiPsu_Config.
-*
-* @note		None.
-*
-******************************************************************************/
-XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId)
-{
-	XQspiPsu_Config *CfgPtr = NULL;
-	s32 Index;
-
-	for (Index = 0; Index < XPAR_XQSPIPSU_NUM_INSTANCES; Index++) {
-		if (XQspiPsu_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XQspiPsu_ConfigTable[Index];
-			break;
-		}
-	}
-	return (XQspiPsu_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile
new file mode 100644
index 000000000..88a66dd93
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspipsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling qspipsu"
+
+xqspipsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspipsu_includes
+
+xqspipsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c
new file mode 100644
index 000000000..93fa53f75
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c
@@ -0,0 +1,1514 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu.c
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* This file implements the functions required to use the QSPIPSU hardware to
+* perform a transfer. These are accessible to the user via xqspipsu.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
+*                    Use DMA DONE bit instead of BUSY as recommended.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+*       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
+*                    writing/reading from 0x0 location is permitted.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Changed XQspiPsu_Select to support GQSPI and LQSPI
+*		     selection.
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*	nsk 08/05/16 Added example support PollData and PollTimeout
+* 1.3	nsk 09/16/16 Update PollData and PollTimeout support for dual
+*	             parallel configurations, modified XQspiPsu_PollData()
+*	             and XQspiPsu_Create_PollConfigData()
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspipsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+			u32 ByteCount);
+static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
+static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+			u32 *GenFifoEntry);
+static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, s32 Size);
+static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg);
+static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr);
+static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, s32 Index);
+static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr);
+static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, s32 Size);
+static inline void XQspiPsu_PollData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg);
+static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPsu instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific QSPIPSU device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	s32 Status;
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_IS_STARTED;
+	} else {
+
+		/* Set some default values. */
+		InstancePtr->IsBusy = FALSE;
+
+		InstancePtr->Config.BaseAddress = EffectiveAddr + XQSPIPSU_OFFSET;
+		InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+		InstancePtr->StatusHandler = StubStatusHandler;
+		InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+		InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+		/* Other instance variable initializations */
+		InstancePtr->SendBufferPtr = NULL;
+		InstancePtr->RecvBufferPtr = NULL;
+		InstancePtr->GenFifoBufferPtr = NULL;
+		InstancePtr->TxBytes = 0;
+		InstancePtr->RxBytes = 0;
+		InstancePtr->GenFifoEntries = 0;
+		InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+		InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+		InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+		InstancePtr->IsUnaligned = 0;
+		InstancePtr->IsManualstart = TRUE;
+
+		/* Select QSPIPSU */
+		XQspiPsu_Select(InstancePtr, XQSPIPSU_SEL_GQSPI_MASK);
+
+		/*
+		 * Reset the QSPIPSU device to get it into its initial state. It is
+		 * expected that device configuration will take place after this
+		 * initialization is done, but before the device is started.
+		 */
+		XQspiPsu_Reset(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPIPSU device. Reset must only be called after the driver has
+* been initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPIPSU device after the reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPsu_Reset(XQspiPsu *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Abort any transfer that is in progress */
+	XQspiPsu_Abort(InstancePtr);
+
+	/* Default value to config register */
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_CFG_OFFSET);
+
+	/* DMA mode */
+	ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+	ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+	/* Manual start */
+	ConfigReg |= XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK;
+	/* Little endain by default */
+	ConfigReg &= ~XQSPIPSU_CFG_ENDIAN_MASK;
+	/* Disable poll timeout */
+	ConfigReg &= ~XQSPIPSU_CFG_EN_POLL_TO_MASK;
+	/* Set hold bit */
+	ConfigReg |= XQSPIPSU_CFG_WP_HOLD_MASK;
+	/* Clear prescalar by default */
+	ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
+	/* CPOL CPHA 00 */
+	ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_PHA_MASK);
+	ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_POL_MASK);
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+	/* Set by default to allow for high frequencies */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_LPBK_DLY_ADJ_OFFSET,
+		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_LPBK_DLY_ADJ_OFFSET) |
+			XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK);
+
+	/* Reset thresholds */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_TX_THRESHOLD_OFFSET,
+		XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_RX_THRESHOLD_OFFSET,
+		XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GF_THRESHOLD_OFFSET,
+		XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL);
+
+	/* DMA init */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET,
+			XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None.
+*
+* @note
+*
+******************************************************************************/
+void XQspiPsu_Abort(XQspiPsu *InstancePtr)
+{
+
+	u32 IntrStatus, ConfigReg;
+
+	IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_ISR_OFFSET);
+
+	/* Clear and disable interrupts */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
+		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
+			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
+				XQSPIPSU_QSPIDMA_DST_STS_WTC);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
+			XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
+
+	/* Clear FIFO */
+	if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK) != FALSE) {
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_FIFO_CTRL_OFFSET,
+			XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
+			XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK);
+	}
+
+	/*
+	 * Switch to IO mode to Clear RX FIFO. This is becuase of DMA behaviour
+	 * where it waits on RX empty and goes busy assuming there is data
+	 * to be transfered even if there is no request.
+	 */
+	if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0U) {
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_CFG_OFFSET);
+		ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_FIFO_CTRL_OFFSET,
+				XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK);
+
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+			XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_CFG_OFFSET, ConfigReg);
+		}
+	}
+
+	/* Disable QSPIPSU */
+	XQspiPsu_Disable(InstancePtr);
+
+	InstancePtr->TxBytes = 0;
+	InstancePtr->RxBytes = 0;
+	InstancePtr->GenFifoEntries = 0;
+	InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs a transfer on the bus in polled mode. The messages
+* passed are all transferred on the bus between one CS assert and de-assert.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	NumMsg is the number of messages to be transferred.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg)
+{
+
+	s32 Index;
+	u32 QspiPsuStatusReg;
+	u32 BaseAddress;
+	s32 RxThr;
+	u32 IOPending = (u32)FALSE;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	for (Index = 0; Index < (s32)NumMsg; Index++) {
+		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+	}
+
+	/* Check whether there is another transfer in progress. Not thread-safe */
+	if (InstancePtr->IsBusy == TRUE) {
+		return (s32)XST_DEVICE_BUSY;
+	}
+
+	/* Check for ByteCount upper limit - 2^28 for DMA */
+	for (Index = 0; Index < (s32)NumMsg; Index++) {
+		if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
+				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	/* Enable */
+	XQspiPsu_Enable(InstancePtr);
+
+	/* Select slave */
+	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
+
+	/* list */
+	Index = 0;
+	while (Index < (s32)NumMsg) {
+		XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
+
+		if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+				XQspiPsu_ReadReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET) |
+					XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+		}
+
+		/* Use thresholds here */
+		/* If there is more data to be transmitted */
+		do {
+			QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_ISR_OFFSET);
+
+			/* Transmit more data if left */
+			if (((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
+				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+				(InstancePtr->TxBytes > 0)) {
+				XQspiPsu_FillTxFifo(InstancePtr, &Msg[Index],
+						XQSPIPSU_TXD_DEPTH);
+			}
+
+			/* Check if DMA RX is complete and update RxBytes */
+			if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
+				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+				u32 DmaIntrSts;
+				DmaIntrSts = XQspiPsu_ReadReg(BaseAddress,
+								XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
+				if ((DmaIntrSts & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
+					XQspiPsu_WriteReg(BaseAddress,
+						XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
+						DmaIntrSts);
+					/* Read remaining bytes using IO mode */
+					if((InstancePtr->RxBytes % 4) != 0 ) {
+						XQspiPsu_WriteReg(BaseAddress,
+							XQSPIPSU_CFG_OFFSET,
+							(XQspiPsu_ReadReg(BaseAddress,
+							XQSPIPSU_CFG_OFFSET) &
+							~XQSPIPSU_CFG_MODE_EN_MASK));
+						InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+						Msg[Index].ByteCount =
+							(InstancePtr->RxBytes % 4);
+						Msg[Index].RxBfrPtr += (InstancePtr->RxBytes -
+								(InstancePtr->RxBytes % 4));
+						InstancePtr->IsUnaligned = 1;
+						IOPending = (u32)TRUE;
+						break;
+					}
+					InstancePtr->RxBytes = 0;
+				}
+			} else {
+				if ((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE) {
+					/* Check if PIO RX is complete and update RxBytes */
+					RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
+							XQSPIPSU_RX_THRESHOLD_OFFSET);
+					if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
+									!= 0U) {
+						XQspiPsu_ReadRxFifo(InstancePtr,
+								&Msg[Index], RxThr*4);
+
+					} else {
+						if ((QspiPsuStatusReg &
+							XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U) {
+								XQspiPsu_ReadRxFifo(InstancePtr,
+									&Msg[Index], InstancePtr->RxBytes);
+						}
+					}
+				}
+			}
+		} while (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) ||
+			(InstancePtr->TxBytes != 0) ||
+			((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) == FALSE) ||
+			(InstancePtr->RxBytes != 0));
+
+		if((InstancePtr->IsUnaligned != 0) && (IOPending == (u32)FALSE)) {
+			InstancePtr->IsUnaligned = 0;
+			XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
+				BaseAddress,
+				XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_MODE_EN_DMA_MASK));
+			InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+		}
+
+		if (IOPending == (u32)TRUE) {
+			IOPending = (u32)FALSE;
+		} else {
+			Index++;
+		}
+	}
+
+	/* De-select slave */
+	XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
+
+	if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+	}
+
+	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
+	while ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) {
+		QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_ISR_OFFSET);
+	}
+
+	/* Clear the busy flag. */
+	InstancePtr->IsBusy = FALSE;
+
+	/* Disable the device. */
+	XQspiPsu_Disable(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initiates a transfer on the bus and enables interrupts.
+* The transfer is completed by the interrupt handler. The messages passed are
+* all transferred on the bus between one CS assert and de-assert.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	NumMsg is the number of messages to be transferred.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg)
+{
+
+	s32 Index;
+	u32 BaseAddress;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	for (Index = 0; Index < (s32)NumMsg; Index++) {
+		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+	}
+
+	/* Check whether there is another transfer in progress. Not thread-safe */
+	if (InstancePtr->IsBusy == TRUE) {
+		return (s32)XST_DEVICE_BUSY;
+	}
+
+	if (Msg[0].Flags & XQSPIPSU_MSG_FLAG_POLL) {
+		InstancePtr->IsBusy = TRUE;
+		XQspiPsu_PollData(InstancePtr, Msg);
+	} else {
+		/* Check for ByteCount upper limit - 2^28 for DMA */
+		for (Index = 0; Index < (s32)NumMsg; Index++) {
+			if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
+					((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	InstancePtr->Msg = Msg;
+	InstancePtr->NumMsg = (s32)NumMsg;
+	InstancePtr->MsgCnt = 0;
+
+	/* Enable */
+	XQspiPsu_Enable(InstancePtr);
+
+	/* Select slave */
+	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
+
+	/* This might not work if not manual start */
+	/* Put first message in FIFO along with the above slave select */
+	XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
+
+	if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+	}
+
+	/* Enable interrupts */
+	XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IER_OFFSET,
+		(u32)XQSPIPSU_IER_TXNOT_FULL_MASK | (u32)XQSPIPSU_IER_TXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXNEMPTY_MASK | (u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXEMPTY_MASK);
+
+	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
+				XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
+	}
+	}
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
+{
+	u32 QspiPsuStatusReg, DmaIntrStatusReg = 0;
+	u32 BaseAddress;
+	XQspiPsu_Msg *Msg;
+	s32 NumMsg;
+	s32 MsgCnt;
+	u8 DeltaMsgCnt = 0;
+	s32 RxThr;
+	u32 TxRxFlag;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+	Msg = InstancePtr->Msg;
+	NumMsg = InstancePtr->NumMsg;
+	MsgCnt = InstancePtr->MsgCnt;
+	TxRxFlag = Msg[MsgCnt].Flags;
+
+	/* QSPIPSU Intr cleared on read */
+	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
+	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+		/* DMA Intr write to clear */
+		DmaIntrStatusReg = XQspiPsu_ReadReg(BaseAddress,
+					XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
+
+		XQspiPsu_WriteReg(BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrStatusReg);
+	}
+	if (((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
+		/* Call status handler to indicate error */
+		InstancePtr->StatusHandler(InstancePtr->StatusRef,
+					XST_SPI_COMMAND_ERROR, 0);
+	}
+
+	/* Fill more data to be txed if required */
+	if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
+		(InstancePtr->TxBytes > 0)) {
+		XQspiPsu_FillTxFifo(InstancePtr, &Msg[MsgCnt],
+				XQSPIPSU_TXD_DEPTH);
+	}
+
+	/*
+	 * Check if the entry is ONLY TX and increase MsgCnt.
+	 * This is to allow TX and RX together in one entry - corner case.
+	 */
+	if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) != FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
+		(InstancePtr->TxBytes == 0) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
+		MsgCnt += 1;
+		DeltaMsgCnt = 1U;
+	}
+
+	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
+		(MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+		if ((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
+				/* Read remaining bytes using IO mode */
+			if((InstancePtr->RxBytes % 4) != 0 ) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
+					BaseAddress, XQSPIPSU_CFG_OFFSET) &
+					~XQSPIPSU_CFG_MODE_EN_MASK));
+				InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+				Msg[MsgCnt].ByteCount = (InstancePtr->RxBytes % 4);
+				Msg[MsgCnt].RxBfrPtr += (InstancePtr->RxBytes -
+						(InstancePtr->RxBytes % 4));
+				InstancePtr->IsUnaligned = 1;
+				XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
+						MsgCnt);
+				if(InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
+					XQspiPsu_WriteReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET,
+						XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+				}
+			}
+			else {
+				InstancePtr->RxBytes = 0;
+				MsgCnt += 1;
+				DeltaMsgCnt = 1U;
+			}
+		}
+	} else {
+		if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+			if (InstancePtr->RxBytes != 0) {
+				if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
+								!= FALSE) {
+					RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
+								XQSPIPSU_RX_THRESHOLD_OFFSET);
+					XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
+						RxThr*4);
+				} else {
+					if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
+						((QspiPsuStatusReg & XQSPIPSU_ISR_RXEMPTY_MASK) == FALSE)) {
+						XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
+							InstancePtr->RxBytes);
+					}
+				}
+				if (InstancePtr->RxBytes == 0) {
+					MsgCnt += 1;
+					DeltaMsgCnt = 1U;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Dummy byte transfer
+	 * MsgCnt < NumMsg check is to ensure is it a valid dummy cycle message
+	 * If one of the above conditions increased MsgCnt, then
+	 * the new message is yet to be placed in the FIFO; hence !DeltaMsgCnt.
+	 */
+	if ((MsgCnt < NumMsg) && (DeltaMsgCnt == FALSE) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) == FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE)) {
+		MsgCnt += 1;
+		DeltaMsgCnt = 1U;
+	}
+	InstancePtr->MsgCnt = MsgCnt;
+
+	/*
+	 * DeltaMsgCnt is to handle conditions where genfifo empty can be set
+	 * while tx is still not empty or rx dma is not yet done.
+	 * MsgCnt > NumMsg indicates CS de-assert entry was also executed.
+	 */
+	if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
+		((DeltaMsgCnt != FALSE) || (MsgCnt > NumMsg))) {
+		if (MsgCnt < NumMsg) {
+			if(InstancePtr->IsUnaligned != 0) {
+				InstancePtr->IsUnaligned = 0;
+				XQspiPsu_WriteReg(InstancePtr->Config.
+					BaseAddress, XQSPIPSU_CFG_OFFSET,
+					(XQspiPsu_ReadReg(InstancePtr->Config.
+					BaseAddress, XQSPIPSU_CFG_OFFSET) |
+					XQSPIPSU_CFG_MODE_EN_DMA_MASK));
+				InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+			}
+			/* This might not work if not manual start */
+			XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
+
+			if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET,
+					XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+			}
+		} else if (MsgCnt == NumMsg) {
+			/* This is just to keep track of the de-assert entry */
+			MsgCnt += 1;
+			InstancePtr->MsgCnt = MsgCnt;
+
+			/* De-select slave */
+			XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
+
+			if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET,
+					XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+			}
+		} else {
+			/* Disable interrupts */
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
+					(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+					(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+					(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXEMPTY_MASK);
+			if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
+					XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
+			}
+
+			/* Clear the busy flag. */
+			InstancePtr->IsBusy = FALSE;
+
+			/* Disable the device. */
+			XQspiPsu_Disable(InstancePtr);
+
+			/* Call status handler to indicate completion */
+			InstancePtr->StatusHandler(InstancePtr->StatusRef,
+						XST_SPI_TRANSFER_DONE, 0);
+		}
+	}
+	if ((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) != FALSE){
+		 if (QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK){
+			 /*
+			  * Read data from RXFIFO, since when data from the flash device
+			  * (status data) matched with configured value in poll_cfg, then
+			  * controller writes the matched data into RXFIFO.
+			  */
+			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
+
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
+					(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+					(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+					(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
+			InstancePtr->StatusHandler(InstancePtr->StatusRef, XST_SPI_POLL_DONE, 0);
+
+			InstancePtr->IsBusy = FALSE;
+			/* Disable the device. */
+			XQspiPsu_Disable(InstancePtr);
+
+		 }
+		 if (QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK){
+			InstancePtr->StatusHandler(InstancePtr->StatusRef,
+					XST_FLASH_TIMEOUT_ERROR, 0);
+		 }
+	}
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* <pre>
+*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The QSPIPSU device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* </pre>
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPointer is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
+				XQspiPsu_StatusHandler FuncPointer)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPointer != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPointer;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				u32 ByteCount)
+{
+	(void *) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects SPI mode - x1 or x2 or x4.
+*
+* @param	SpiMode - spi or dual or quad.
+* @return	Mask to set desired SPI mode in GENFIFO entry.
+*
+* @note		None.
+*
+******************************************************************************/
+static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
+{
+	u32 Mask;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SelectSpiMode\r\n");
+#endif
+
+	switch (SpiMode) {
+		case XQSPIPSU_SELECT_MODE_DUALSPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
+			break;
+		case XQSPIPSU_SELECT_MODE_QUADSPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_QUADSPI;
+			break;
+		case XQSPIPSU_SELECT_MODE_SPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
+			break;
+		default:
+			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
+			break;
+	}
+#ifdef DEBUG
+	xil_printf("\nSPIMode is %08x\r\n", SpiMode);
+#endif
+
+	return Mask;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks the TX/RX buffers in the message and setups up the
+* GENFIFO entries, TX FIFO or RX DMA as required.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	GenFifoEntry is pointer to the variable in which GENFIFO mask
+*		is returned to calling function
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+					u32 *GenFifoEntry)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Transmit */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+			((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
+		/* Setup data to be TXed */
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_TX;
+		InstancePtr->TxBytes = (s32)Msg->ByteCount;
+		InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
+		InstancePtr->RecvBufferPtr = NULL;
+		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
+		/* Discard RX data */
+		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_RX;
+		InstancePtr->RxBytes = 0;
+	}
+
+	/* Receive */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE) &&
+			((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE)) {
+		/* TX auto fill */
+		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_TX;
+		InstancePtr->TxBytes = 0;
+		/* Setup RX */
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_RX;
+		InstancePtr->RxBytes = (s32)Msg->ByteCount;
+		InstancePtr->SendBufferPtr = NULL;
+		InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			XQspiPsu_SetupRxDma(InstancePtr, Msg);
+		}
+	}
+
+	/* If only dummy is requested as a separate entry */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
+			(Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE) {
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
+		InstancePtr->TxBytes = 0;
+		InstancePtr->RxBytes = 0;
+		InstancePtr->SendBufferPtr = NULL;
+		InstancePtr->RecvBufferPtr = NULL;
+	}
+
+	/* Dummy and cmd sent by upper layer to received data */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+			((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= (XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
+		InstancePtr->TxBytes = (s32)Msg->ByteCount;
+		InstancePtr->RxBytes = (s32)Msg->ByteCount;
+		InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
+		InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
+		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
+		/* Add check for DMA or PIO here */
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			XQspiPsu_SetupRxDma(InstancePtr, Msg);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Fills the TX FIFO as long as there is room in the FIFO or the bytes required
+* to be transmitted.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Size is the number of bytes to be transmitted.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg, s32 Size)
+{
+	s32 Count = 0;
+	u32 Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_FillTxFifo\r\n");
+#endif
+
+	while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
+		if (InstancePtr->TxBytes >= 4) {
+			(void)memcpy(&Data, Msg->TxBfrPtr, 4);
+			Msg->TxBfrPtr += 4;
+			InstancePtr->TxBytes -= 4;
+			Count += 4;
+		} else {
+			(void)memcpy(&Data, Msg->TxBfrPtr, InstancePtr->TxBytes);
+			Msg->TxBfrPtr += InstancePtr->TxBytes;
+			Count += InstancePtr->TxBytes;
+			InstancePtr->TxBytes = 0;
+		}
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_TXD_OFFSET, Data);
+#ifdef DEBUG
+	xil_printf("\nData is %08x\r\n", Data);
+#endif
+
+	}
+	if (InstancePtr->TxBytes < 0) {
+		InstancePtr->TxBytes = 0;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets up the RX DMA operation.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg)
+{
+	s32 Remainder;
+	s32 DmaRxBytes;
+	u64 AddrTemp;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) &
+				XQSPIPSU_QSPIDMA_DST_ADDR_MASK);
+	/* Check for RXBfrPtr to be word aligned */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET,
+			(u32)AddrTemp);
+
+	AddrTemp = AddrTemp >> 32;
+	if ((AddrTemp & 0xFFFU) != FALSE) {
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
+				(u32)AddrTemp &
+				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
+	}
+
+	Remainder = InstancePtr->RxBytes % 4;
+	DmaRxBytes = InstancePtr->RxBytes;
+	if (Remainder != 0) {
+		/* This is done to make Dma bytes aligned */
+		DmaRxBytes = InstancePtr->RxBytes - Remainder;
+		Msg->ByteCount = (u32)DmaRxBytes;
+	}
+
+	Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount);
+
+	/* Write no. of words to DMA DST SIZE */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entry to assert CS.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSAssert\r\n");
+#endif
+
+	GenFifoEntry = 0x0U;
+	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry |= InstancePtr->GenFifoCS;
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
+			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_SETUP;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entries to transmit the messages requested.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Index of the current message to be handled.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
+						XQspiPsu_Msg *Msg, s32 Index)
+{
+	u32 GenFifoEntry;
+	u32 BaseAddress;
+	u32 TempCount;
+	u32 ImmData;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryData\r\n");
+#endif
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	GenFifoEntry = 0x0U;
+	/* Bus width */
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
+	GenFifoEntry |= XQspiPsu_SelectSpiMode((u8)Msg[Index].BusWidth);
+
+	GenFifoEntry |= InstancePtr->GenFifoCS;
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+
+	/* Data */
+	if (((Msg[Index].Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE) {
+		GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
+	} else {
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
+	}
+
+	/* If Byte Count is less than 8 bytes do the transfer in IO mode */
+	if ((Msg[Index].ByteCount < 8U) &&
+		(InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)) {
+			InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+				(XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) &
+						~XQSPIPSU_CFG_MODE_EN_MASK));
+			InstancePtr->IsUnaligned = 1;
+	}
+
+	XQspiPsu_TXRXSetup(InstancePtr, &Msg[Index], &GenFifoEntry);
+
+	if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
+		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
+		GenFifoEntry |= Msg[Index].ByteCount;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
+				GenFifoEntry);
+	} else {
+		TempCount = Msg[Index].ByteCount;
+		u32 Exponent = 8;	/* 2^8 = 256 */
+
+		ImmData = TempCount & 0xFFU;
+		/* Exponent entries */
+		GenFifoEntry |= XQSPIPSU_GENFIFO_EXP;
+		while (TempCount != 0U) {
+			if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) {
+				GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
+				GenFifoEntry |= Exponent;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_GEN_FIFO_OFFSET,
+					GenFifoEntry);
+			}
+			TempCount = TempCount >> 1;
+			Exponent++;
+		}
+
+		/* Immediate entry */
+		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_EXP);
+		if ((ImmData & 0xFFU) != FALSE) {
+			GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
+			GenFifoEntry |= ImmData & 0xFFU;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
+			XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+		}
+	}
+
+	/* One dummy GenFifo entry in case of IO mode */
+	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) &&
+			((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+		GenFifoEntry = 0x0U;
+#ifdef DEBUG
+	xil_printf("\nDummy FifoEntry=%08x\r\n",GenFifoEntry);
+#endif
+		XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entry to de-assert CS.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSDeAssert\r\n");
+#endif
+
+	GenFifoEntry = 0x0U;
+	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
+			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_HOLD;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the specified number of bytes from RX FIFO
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Size is the number of bytes to be read.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg, s32 Size)
+{
+	s32 Count = 0;
+	u32 Data;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_ReadRxFifo\r\n");
+#endif
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Msg != NULL);
+
+	while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
+		Data = XQspiPsu_ReadReg(InstancePtr->
+				Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
+#ifdef DEBUG
+	xil_printf("\nData is %08x\r\n", Data);
+#endif
+		if (InstancePtr->RxBytes >= 4) {
+			(void)memcpy(Msg->RxBfrPtr, &Data, 4);
+			InstancePtr->RxBytes -= 4;
+			Msg->RxBfrPtr += 4;
+			Count += 4;
+		} else {
+			/* Read unaligned bytes (< 4 bytes) */
+			(void)memcpy(Msg->RxBfrPtr, &Data, InstancePtr->RxBytes);
+			Msg->RxBfrPtr += InstancePtr->RxBytes;
+			Count += InstancePtr->RxBytes;
+			InstancePtr->RxBytes = 0;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables the polling functionality of controller
+*
+* @param	QspiPsuPtr is a pointer to the XQspiPsu instance.
+*
+* @param	Statuscommand is the status command which send by controller.
+*
+* @param	FlashMsg is a pointer to the structure containing transfer data
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPsu_PollData(XQspiPsu *QspiPsuPtr, XQspiPsu_Msg *FlashMsg)
+{
+
+	u32 GenFifoEntry ;
+	u32 Value;
+
+	Xil_AssertVoid(QspiPsuPtr != NULL);
+	Xil_AssertVoid(FlashMsg != NULL );
+
+	Value = XQspiPsu_Create_PollConfigData(QspiPsuPtr, FlashMsg);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_POLL_CFG_OFFSET, Value);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_P_TO_OFFSET, FlashMsg->PollTimeout);
+
+	XQspiPsu_Enable(QspiPsuPtr);
+
+	GenFifoEntry = (u32)0;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_TX;
+	GenFifoEntry |= QspiPsuPtr->GenFifoBus;
+	GenFifoEntry |= QspiPsuPtr->GenFifoCS;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry |= (u32)FlashMsg->PollStatusCmd;
+
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				(XQSPIPSU_CFG_START_GEN_FIFO_MASK
+				| XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK));
+
+	GenFifoEntry = (u32)0;
+	GenFifoEntry = (u32)XQSPIPSU_GENFIFO_POLL;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_RX;
+	GenFifoEntry |= QspiPsuPtr->GenFifoBus;
+	GenFifoEntry |= QspiPsuPtr->GenFifoCS;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
+	if (((FlashMsg->Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE)
+		GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
+	else
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
+
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+
+	QspiPsuPtr->Msg = FlashMsg;
+	QspiPsuPtr->NumMsg = (s32)1;
+	QspiPsuPtr->MsgCnt = 0;
+
+	Value = XQspiPsu_ReadReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_CFG_OFFSET);
+	Value |= (XQSPIPSU_CFG_START_GEN_FIFO_MASK |
+			XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK |
+			XQSPIPSU_CFG_EN_POLL_TO_MASK);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+			Value);
+
+	/* Enable interrupts */
+	Value = ((u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+		(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+		(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_IER_OFFSET,
+			Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function creates Poll config register data to write
+*
+* @param	BusMask is mask to enable/disable upper/lower data bus masks.
+*
+* @param	DataBusMask is Data bus mask value during poll operation.
+*
+* @param	Data is the poll data value to write into config regsiter.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg)
+{
+	u32 ConfigData = 0;
+
+	if (QspiPsuPtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_UPPER)
+		ConfigData = XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
+			           XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT;
+	if (QspiPsuPtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_LOWER)
+		ConfigData |= XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
+			           XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT;
+	ConfigData |= ((FlashMsg->PollBusMask << XQSPIPSU_POLL_CFG_MASK_EN_SHIFT)
+			& XQSPIPSU_POLL_CFG_MASK_EN_MASK);
+	ConfigData |= ((FlashMsg->PollData << XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT)
+		          & XQSPIPSU_POLL_CFG_DATA_VALUE_MASK);
+	return ConfigData;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h
new file mode 100644
index 000000000..94801949c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h
@@ -0,0 +1,302 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu.h
+* @addtogroup qspipsu_v1_0
+* @{
+* @details
+*
+* This is the header file for the implementation of QSPIPSU driver.
+* Generic QSPI interface allows for communication to any QSPI slave device.
+* GQSPI contains a GENFIFO into which the bus transfers required are to be
+* pushed with appropriate configuration. The controller provides TX and RX
+* FIFO's and a DMA to be used for RX transfers. The controller executes each
+* GENFIFO entry noting the configuration and places data on the bus as required
+*
+* The different options in GENFIFO are as follows:
+* IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
+*            number of bytes in transfer.
+* DATA_XFER : Indicates that data/clocks need to be transmitted or received.
+* EXPONENT : e when 2^e bytes are involved in transfer.
+* SPI_MODE : SPI/Dual SPI/Quad SPI
+* CS : Lower or Upper CS or Both
+* Bus : Lower or Upper Bus or Both
+* TX : When selected, controller transmits data in IMM or fetches number of
+*      bytes mentioned form TX FIFO. If not selected, dummies are pumped.
+* RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
+*      of requested number of bytes. If not selected, RX data is discarded.
+* Stripe : Byte stripe over lower and upper bus or not.
+* Poll : Polls response to match for to a set value (used along with POLL_CFG
+*        registers) and then proceeds to next GENFIFO entry.
+*        This feature is not currently used in the driver.
+*
+* GENFIFO has manual and auto start options.
+* All DMA requests need a 4-byte aligned destination address buffer and
+* size of transfer should also be a multiple of 4.
+* This driver supports DMA RX and IO RX.
+*
+* Initialization:
+* This driver uses the GQSPI controller with RX DMA. It supports both
+* interrupt and polled transfers. Manual start of GENFIFO is used.
+* XQspiPsu_CfgInitialize() initializes the instance variables.
+* Additional setting can be done using SetOptions/ClearOptions functions
+* and SelectSlave function.
+*
+* Transfer:
+* Polled or Interrupt transfers can be done. The transfer function needs the
+* message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
+* This is supposed to contain the byte count and any TX/RX buffers as required.
+* Flags can be used indicate further information such as whether the message
+* should be striped. The transfer functions form and write GENFIFO entries,
+* check the status of the transfer and report back to the application
+* when done.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
+*                    Use DMA DONE bit instead of BUSY as recommended.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+*       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
+*                    writing/reading from 0x0 location is permitted.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Added LQSPI support
+*		     Modified XQspiPsu_Select() macro in xqspipsu.h
+*		     Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h
+*		     Added required macros in xqspipsu_hw.h
+*		     Modified XQspiPsu_SetOptions() to support
+*		     LQSPI options and updated OptionsTable in
+*		     xqspipsu_options.c
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*	nsk 08/05/16 Added example support PollData and PollTimeout
+*		     Added  XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h
+*		     Added XQspiPsu_Create_PollConfigData and
+*		     XQspiPsu_PollData() functions in xqspipsu.c
+* 1.3	nsk 09/16/16 Update PollData and Polltimeout support for dual parallel
+*	             configuration. Updated XQspiPsu_PollData() and
+*	             XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
+*                    and also modified the polldata example
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPSU_H_		/* prevent circular inclusions */
+#define XQSPIPSU_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspipsu_hw.h"
+#include "xil_cache.h"
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPIPSU device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPsu_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					u32 ByteCount);
+
+/**
+ * This typedef contains configuration information for a flash message.
+ */
+typedef struct {
+	u8 *TxBfrPtr;
+	u8 *RxBfrPtr;
+	u32 ByteCount;
+	u32 BusWidth;
+	u32 Flags;
+	u8 PollData;
+	u32 PollTimeout;
+	u8 PollStatusCmd;
+	u8 PollBusMask;
+} XQspiPsu_Msg;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+	u8  BusWidth; 	/**< Bus width available on board */
+} XQspiPsu_Config;
+
+/**
+ * The XQspiPsu driver instance data. The user is required to allocate a
+ * variable of this type for every QSPIPSU device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPsu_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	u8 *GenFifoBufferPtr;	 /**< Gen FIFO entries */
+	s32 TxBytes;	 /**< Number of bytes to transfer (state) */
+	s32 RxBytes;	 /**< Number of bytes left to transfer(state) */
+	s32 GenFifoEntries;	 /**< Number of Gen FIFO entries remaining */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	u32 ReadMode;		 /**< DMA or IO mode */
+	u32 GenFifoCS;
+	u32 GenFifoBus;
+	s32 NumMsg;
+	s32 MsgCnt;
+	s32 IsUnaligned;
+	u8 IsManualstart;
+	XQspiPsu_Msg *Msg;
+	XQspiPsu_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+} XQspiPsu;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQSPIPSU_READMODE_DMA	0x0U
+#define XQSPIPSU_READMODE_IO	0x1U
+
+#define XQSPIPSU_SELECT_FLASH_CS_LOWER	0x1U
+#define XQSPIPSU_SELECT_FLASH_CS_UPPER	0x2U
+#define XQSPIPSU_SELECT_FLASH_CS_BOTH	0x3U
+
+#define XQSPIPSU_SELECT_FLASH_BUS_LOWER	0x1U
+#define XQSPIPSU_SELECT_FLASH_BUS_UPPER	0x2U
+#define XQSPIPSU_SELECT_FLASH_BUS_BOTH	0x3U
+
+#define XQSPIPSU_SELECT_MODE_SPI	0x1U
+#define XQSPIPSU_SELECT_MODE_DUALSPI	0x2U
+#define XQSPIPSU_SELECT_MODE_QUADSPI	0x4U
+
+#define XQSPIPSU_GENFIFO_CS_SETUP	0x05U
+#define XQSPIPSU_GENFIFO_CS_HOLD	0x04U
+
+#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION	0x2U
+#define XQSPIPSU_CLK_PHASE_1_OPTION	0x4U
+#define XQSPIPSU_MANUAL_START_OPTION	0x8U
+#define XQSPIPSU_LQSPI_MODE_OPTION	0x20U
+
+#define XQSPIPSU_GENFIFO_EXP_START	0x100U
+
+#define XQSPIPSU_DMA_BYTES_MAX		0x10000000U
+
+#define XQSPIPSU_CLK_PRESCALE_2		0x00U
+#define XQSPIPSU_CLK_PRESCALE_4		0x01U
+#define XQSPIPSU_CLK_PRESCALE_8		0x02U
+#define XQSPIPSU_CLK_PRESCALE_16		0x03U
+#define XQSPIPSU_CLK_PRESCALE_32		0x04U
+#define XQSPIPSU_CLK_PRESCALE_64		0x05U
+#define XQSPIPSU_CLK_PRESCALE_128	0x06U
+#define XQSPIPSU_CLK_PRESCALE_256	0x07U
+#define XQSPIPSU_CR_PRESC_MAXIMUM	7U
+
+#define XQSPIPSU_CONNECTION_MODE_SINGLE		0U
+#define XQSPIPSU_CONNECTION_MODE_STACKED	1U
+#define XQSPIPSU_CONNECTION_MODE_PARALLEL	2U
+
+/*QSPI Frequencies*/
+#define XQSPIPSU_FREQ_40MHZ 40000000
+#define XQSPIPSU_FREQ_100MHZ 100000000
+#define XQSPIPSU_FREQ_150MHZ 150000000
+
+/* Add more flags as required */
+#define XQSPIPSU_MSG_FLAG_STRIPE	0x1U
+#define XQSPIPSU_MSG_FLAG_RX		0x2U
+#define XQSPIPSU_MSG_FLAG_TX		0x4U
+#define XQSPIPSU_MSG_FLAG_POLL		0x8U
+
+#define XQspiPsu_Select(InstancePtr, Mask)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask)
+
+#define XQspiPsu_Enable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
+
+#define XQspiPsu_Disable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
+
+#define XQspiPsu_GetLqspiConfigReg(InstancePtr)   XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/* Initialization and reset */
+XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
+s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
+				u32 EffectiveAddr);
+void XQspiPsu_Reset(XQspiPsu *InstancePtr);
+void XQspiPsu_Abort(XQspiPsu *InstancePtr);
+
+/* Transfer functions and handlers */
+s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg);
+s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg);
+s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
+void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
+				XQspiPsu_StatusHandler FuncPointer);
+
+/* Configuration functions */
+s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
+void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
+s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
+s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
+u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
+s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* XQSPIPSU_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c
new file mode 100644
index 000000000..969fa96b0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c
@@ -0,0 +1,58 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspipsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPsu_Config XQspiPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_QSPI_0_DEVICE_ID,
+		XPAR_PSU_QSPI_0_BASEADDR,
+		XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ,
+		XPAR_PSU_QSPI_0_QSPI_MODE,
+		XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h
new file mode 100644
index 000000000..40314d6e1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h
@@ -0,0 +1,878 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_hw.h
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* This file contains low level access funcitons using the base address
+* directly without an instance.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       hk  03/18/15 Add DMA status register masks required.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+* 1.2	nsk 07/01/16 Added LQSPI supported Masks
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef _XQSPIPSU_HW_H_		/* prevent circular inclusions */
+#define _XQSPIPSU_HW_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * QSPI Base Address
+ */
+#define XQSPIPS_BASEADDR      0XFF0F0000U
+
+/**
+ * GQSPI Base Address
+ */
+#define XQSPIPSU_BASEADDR     0xFF0F0100U
+#define XQSPIPSU_OFFSET     0x100U
+
+/**
+ * Register: XQSPIPS_EN_REG
+ */
+#define XQSPIPS_EN_REG    ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
+
+#define XQSPIPS_EN_SHIFT   0
+#define XQSPIPS_EN_WIDTH   1
+#define XQSPIPS_EN_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_CFG
+ */
+#define XQSPIPSU_CFG_OFFSET    0X00000000U
+#define XQSPIPSU_LQSPI_CR_OFFSET    0X000000A0U
+
+#define XQSPIPSU_CFG_MODE_EN_SHIFT   30
+#define XQSPIPSU_CFG_MODE_EN_WIDTH   2
+#define XQSPIPSU_CFG_MODE_EN_MASK    0XC0000000U
+#define XQSPIPSU_CFG_MODE_EN_DMA_MASK	0X80000000U
+
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT   29
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH   1
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK    0X20000000U
+
+#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT   28
+#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH   1
+#define XQSPIPSU_CFG_START_GEN_FIFO_MASK    0X10000000U
+
+#define XQSPIPSU_CFG_ENDIAN_SHIFT   26
+#define XQSPIPSU_CFG_ENDIAN_WIDTH   1
+#define XQSPIPSU_CFG_ENDIAN_MASK    0X04000000U
+
+#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT   20
+#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH   1
+#define XQSPIPSU_CFG_EN_POLL_TO_MASK    0X00100000U
+
+#define XQSPIPSU_CFG_WP_HOLD_SHIFT   19
+#define XQSPIPSU_CFG_WP_HOLD_WIDTH   1
+#define XQSPIPSU_CFG_WP_HOLD_MASK    0X00080000U
+
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT   3
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH   3
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK    0X00000038U
+
+#define XQSPIPSU_CFG_CLK_PHA_SHIFT   2
+#define XQSPIPSU_CFG_CLK_PHA_WIDTH   1
+#define XQSPIPSU_CFG_CLK_PHA_MASK    0X00000004U
+
+#define XQSPIPSU_CFG_CLK_POL_SHIFT   1
+#define XQSPIPSU_CFG_CLK_POL_WIDTH   1
+#define XQSPIPSU_CFG_CLK_POL_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_CFG
+ */
+#define XQSPIPSU_LQSPI_CR_OFFSET	0X000000A0U
+#define XQSPIPSU_LQSPI_CR_LINEAR_MASK     0x80000000 /**< LQSPI mode enable */
+#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK    0x40000000 /**< Both memories or one */
+#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK    0x20000000 /**< Seperate memory bus */
+#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK     0x10000000 /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK     0x01000000 /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK    0x02000000 /**< Enable mode bits */
+#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK    0x01000000 /**< Mode on */
+#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+                                                         or quad I/O */
+#define XQSPIPS_LQSPI_CR_INST_MASK       0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE       0x80000003 /**< Default LQSPI CR value */
+#define XQSPIPS_LQSPI_CFG_RST_STATE       0x800238C1 /**< Default LQSPI CFG value */
+/**
+ * Register: XQSPIPSU_ISR
+ */
+#define XQSPIPSU_ISR_OFFSET	0X00000004U
+
+#define XQSPIPSU_ISR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_ISR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_ISR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_ISR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_ISR_RXFULL_SHIFT   5
+#define XQSPIPSU_ISR_RXFULL_WIDTH   1
+#define XQSPIPSU_ISR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_ISR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_ISR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_ISR_TXFULL_SHIFT   3
+#define XQSPIPSU_ISR_TXFULL_WIDTH   1
+#define XQSPIPSU_ISR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_ISR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
+
+/**
+ * Register: XQSPIPSU_IER
+ */
+#define XQSPIPSU_IER_OFFSET    0X00000008U
+
+#define XQSPIPSU_IER_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IER_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IER_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IER_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IER_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IER_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IER_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IER_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IER_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IER_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IER_RXFULL_SHIFT   5
+#define XQSPIPSU_IER_RXFULL_WIDTH   1
+#define XQSPIPSU_IER_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IER_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IER_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IER_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IER_TXFULL_SHIFT   3
+#define XQSPIPSU_IER_TXFULL_WIDTH   1
+#define XQSPIPSU_IER_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IER_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IER_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IER_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_IDR
+ */
+#define XQSPIPSU_IDR_OFFSET    0X0000000CU
+
+#define XQSPIPSU_IDR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IDR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IDR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IDR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IDR_RXFULL_SHIFT   5
+#define XQSPIPSU_IDR_RXFULL_WIDTH   1
+#define XQSPIPSU_IDR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IDR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IDR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IDR_TXFULL_SHIFT   3
+#define XQSPIPSU_IDR_TXFULL_WIDTH   1
+#define XQSPIPSU_IDR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IDR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+#define XQSPIPSU_IDR_ALL_MASK    0X0FBEU
+
+/**
+ * Register: XQSPIPSU_IMR
+ */
+#define XQSPIPSU_IMR_OFFSET    0X00000010U
+
+#define XQSPIPSU_IMR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IMR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IMR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IMR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IMR_RXFULL_SHIFT   5
+#define XQSPIPSU_IMR_RXFULL_WIDTH   1
+#define XQSPIPSU_IMR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IMR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IMR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IMR_TXFULL_SHIFT   3
+#define XQSPIPSU_IMR_TXFULL_WIDTH   1
+#define XQSPIPSU_IMR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IMR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_EN_REG
+ */
+#define XQSPIPSU_EN_OFFSET    0X00000014U
+
+#define XQSPIPSU_EN_SHIFT   0
+#define XQSPIPSU_EN_WIDTH   1
+#define XQSPIPSU_EN_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_TXD
+ */
+#define XQSPIPSU_TXD_OFFSET    0X0000001CU
+
+#define XQSPIPSU_TXD_SHIFT   0
+#define XQSPIPSU_TXD_WIDTH   32
+#define XQSPIPSU_TXD_MASK    0XFFFFFFFFU
+
+#define XQSPIPSU_TXD_DEPTH    64
+
+/**
+ * Register: XQSPIPSU_RXD
+ */
+#define XQSPIPSU_RXD_OFFSET    0X00000020U
+
+#define XQSPIPSU_RXD_SHIFT   0
+#define XQSPIPSU_RXD_WIDTH   32
+#define XQSPIPSU_RXD_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_TX_THRESHOLD
+ */
+#define XQSPIPSU_TX_THRESHOLD_OFFSET    0X00000028U
+
+#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH   6
+#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK    0X0000003FU
+#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL    0X01U
+
+/**
+ * Register: XQSPIPSU_RX_THRESHOLD
+ */
+#define XQSPIPSU_RX_THRESHOLD_OFFSET    0X0000002CU
+
+#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH   6
+#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK    0X0000003FU
+#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL    0X01U
+
+#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
+
+/**
+ * Register: XQSPIPSU_GPIO
+ */
+#define XQSPIPSU_GPIO_OFFSET    0X00000030U
+
+#define XQSPIPSU_GPIO_WP_N_SHIFT   0
+#define XQSPIPSU_GPIO_WP_N_WIDTH   1
+#define XQSPIPSU_GPIO_WP_N_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_LPBK_DLY_ADJ
+ */
+#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET    0X00000038U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT   5
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH   1
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK    0X00000020U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT   3
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH   2
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK    0X00000018U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT   0
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH   3
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK    0X00000007U
+
+/**
+ * Register: XQSPIPSU_GEN_FIFO
+ */
+#define XQSPIPSU_GEN_FIFO_OFFSET    0X00000040U
+
+#define XQSPIPSU_GEN_FIFO_DATA_SHIFT   0
+#define XQSPIPSU_GEN_FIFO_DATA_WIDTH   20
+#define XQSPIPSU_GEN_FIFO_DATA_MASK    0X000FFFFFU
+
+/**
+ * Register: XQSPIPSU_SEL
+ */
+#define XQSPIPSU_SEL_OFFSET    0X00000044U
+
+#define XQSPIPSU_SEL_SHIFT   0
+#define XQSPIPSU_SEL_WIDTH   1
+#define XQSPIPSU_SEL_LQSPI_MASK    0X0U
+#define XQSPIPSU_SEL_GQSPI_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_FIFO_CTRL
+ */
+#define XQSPIPSU_FIFO_CTRL_OFFSET    0X0000004CU
+
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT   2
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK    0X00000004U
+
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT   1
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK    0X00000002U
+
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT   0
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_GF_THRESHOLD
+ */
+#define XQSPIPSU_GF_THRESHOLD_OFFSET    0X00000050U
+
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH   5
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK    0X0000001F
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL    0X10U
+
+/**
+ * Register: XQSPIPSU_POLL_CFG
+ */
+#define XQSPIPSU_POLL_CFG_OFFSET    0X00000054U
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT   31
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH   1
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK    0X80000000U
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT   30
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH   1
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK    0X40000000U
+
+#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT   8
+#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH   8
+#define XQSPIPSU_POLL_CFG_MASK_EN_MASK    0X0000FF00U
+
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT   0
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH   8
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK    0X000000FFU
+
+/**
+ * Register: XQSPIPSU_P_TIMEOUT
+ */
+#define XQSPIPSU_P_TO_OFFSET    0X00000058U
+
+#define XQSPIPSU_P_TO_VALUE_SHIFT   0
+#define XQSPIPSU_P_TO_VALUE_WIDTH   32
+#define XQSPIPSU_P_TO_VALUE_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_XFER_STS
+ */
+#define XQSPIPSU_XFER_STS_OFFSET	0X0000005CU
+
+#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT   0
+#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH   32
+#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_GF_SNAPSHOT
+ */
+#define XQSPIPSU_GF_SNAPSHOT_OFFSET    0X00000060U
+
+#define XQSPIPSU_GF_SNAPSHOT_SHIFT   0
+#define XQSPIPSU_GF_SNAPSHOT_WIDTH   20
+#define XQSPIPSU_GF_SNAPSHOT_MASK    0X000FFFFFU
+
+/**
+ * Register: XQSPIPSU_RX_COPY
+ */
+#define XQSPIPSU_RX_COPY_OFFSET    0X00000064U
+
+#define XQSPIPSU_RX_COPY_UPPER_SHIFT   8
+#define XQSPIPSU_RX_COPY_UPPER_WIDTH   8
+#define XQSPIPSU_RX_COPY_UPPER_MASK    0X0000FF00U
+
+#define XQSPIPSU_RX_COPY_LOWER_SHIFT   0
+#define XQSPIPSU_RX_COPY_LOWER_WIDTH   8
+#define XQSPIPSU_RX_COPY_LOWER_MASK    0X000000FFU
+
+/**
+ * Register: XQSPIPSU_MOD_ID
+ */
+#define XQSPIPSU_MOD_ID_OFFSET    0X000000FCU
+
+#define XQSPIPSU_MOD_ID_SHIFT   0
+#define XQSPIPSU_MOD_ID_WIDTH   32
+#define XQSPIPSU_MOD_ID_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_ADDR
+ */
+#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET    0X00000700U
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH   30
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK    0XFFFFFFFCU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_SIZE
+ */
+#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET    0X00000704U
+
+#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH   27
+#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK    0X1FFFFFFCU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_STS
+ */
+#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET    0X00000708U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT   13
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK    0X0000E000U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK    0X00001FE0U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK    0X0000001EU
+
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK    0X00000001U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WTC	0xE000U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_CTRL
+ */
+#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET    0X0000070CU
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT   25
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH   7
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK    0XFE000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK    0X01000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT   23
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK    0X00800000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK    0X00400000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT   10
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK    0X003FFC00U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH   8
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK    0X000003FCU
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK    0X00000001U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL	0x403FFA00U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_STS
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET    0X00000714U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK    0X000000FCU
+#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK    0X000000FEU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_EN
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET    0X00000718U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_DIS
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET    0X0000071CU
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_IMR
+ */
+#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET    0X00000720U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_CTRL2
+ */
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET    0X00000724U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK    0X08000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK    0X07000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT   22
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK    0X00400000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK    0X00380000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK    0X00070000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK    0X0000FFF0U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK    0X0000000FU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
+ */
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET    0X00000728U
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK    0X00000FFFU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
+ */
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET    0X00000EFCU
+
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT   0
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH   32
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK    0XFFFFFFFFU
+
+/*
+ * Generic FIFO masks
+ */
+#define XQSPIPSU_GENFIFO_IMM_DATA_MASK	0xFFU
+#define XQSPIPSU_GENFIFO_DATA_XFER	0x100U
+#define XQSPIPSU_GENFIFO_EXP		0x200U
+#define XQSPIPSU_GENFIFO_MODE_SPI	0x400U
+#define XQSPIPSU_GENFIFO_MODE_DUALSPI	0x800U
+#define XQSPIPSU_GENFIFO_MODE_QUADSPI	0xC00U
+#define XQSPIPSU_GENFIFO_MODE_MASK	0xC00U	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_CS_LOWER	0x1000U
+#define XQSPIPSU_GENFIFO_CS_UPPER	0x2000U
+#define XQSPIPSU_GENFIFO_BUS_LOWER	0x4000U
+#define XQSPIPSU_GENFIFO_BUS_UPPER	0x8000U
+#define XQSPIPSU_GENFIFO_BUS_BOTH	0xC000U	/* inverse is no bus */
+#define XQSPIPSU_GENFIFO_BUS_MASK	0xC000U	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_TX		0x10000U	/* inverse is zero pump */
+#define XQSPIPSU_GENFIFO_RX		0x20000U	/* inverse is RX discard */
+#define XQSPIPSU_GENFIFO_STRIPE		0x40000U
+#define XQSPIPSU_GENFIFO_POLL		0x80000U
+
+/*QSPI Data delay register*/
+#define XQSPIPSU_DATA_DLY_ADJ_OFFSET    0X000000F8U
+
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT   31
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH   1
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK    0X80000000U
+
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT   28
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH   3
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK    0X70000000U
+
+/* Tapdelay Bypass register*/
+#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPsu_In32 Xil_In32
+#define XQspiPsu_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)
+*
+******************************************************************************/
+#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _XQSPIPSU_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c
new file mode 100644
index 000000000..2c77a0881
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c
@@ -0,0 +1,621 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_options.c
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* This file implements funcitons to configure the QSPIPSU component,
+* specifically some optional settings, clock and flash related information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Modified XQspiPsu_SetOptions() to support
+*		     LQSPI options and updated OptionsTable
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspipsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if defined (ARMR5) || (__aarch64__)
+#define TAPDLY_BYPASS_VALVE_40MHZ 0x01
+#define TAPDLY_BYPASS_VALVE_100MHZ 0x01
+#define USE_DLY_LPBK  0x01
+#define USE_DATA_DLY_ADJ 0x01
+#define DATA_DLY_ADJ_DLY 0X02
+#define LPBK_DLY_ADJ_DLY0 0X02
+#endif
+
+/************************** Function Prototypes ******************************/
+
+#if defined (ARMR5) || (__aarch64__)
+s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass,
+						u32 LPBKDelay,u32 Datadelay);
+static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler);
+#endif
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
+	{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
+	{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
+	{XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_CFG_WP_HOLD_MASK},
+};
+
+#define XQSPIPSU_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPIPSU device driver.The options
+* control how the device behaves relative to the QSPIPSU bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 indicates the option should be turned ON and
+*		a 0 indicates no action. One or more bit values may be
+*		contained in the mask. See the bit definitions named
+*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	u32 Index;
+	u32 QspiPsuOptions;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+		QspiPsuOptions = Options & XQSPIPSU_LQSPI_MODE_OPTION;
+		Options &= ~XQSPIPSU_LQSPI_MODE_OPTION;
+		/*
+		 * Loop through the options table, turning the option on
+		 * depending on whether the bit is set in the incoming options flag.
+		 */
+		for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+			if ((Options & OptionsTable[Index].Option) != FALSE) {
+				/* Turn it on */
+				ConfigReg |= OptionsTable[Index].Mask;
+			} else {
+                /* Turn it off */
+                ConfigReg &= ~(OptionsTable[Index].Mask);
+        }
+
+		}
+		/*
+		 * Now write the control register. Leave it to the upper layers
+		 * to restart the device.
+		 */
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				 ConfigReg);
+
+		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
+			InstancePtr->IsManualstart = TRUE;
+		}
+		/*
+		 * Check for the LQSPI configuration options.
+		 */
+		ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET);
+
+			if (QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) {
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE);
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE);
+			/* Enable the QSPI controller */
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK);
+		}
+		 else {
+			ConfigReg &= ~(XQSPIPSU_LQSPI_CR_LINEAR_MASK);
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET, ConfigReg);
+		}
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the options for the QSPIPSU device driver.The options
+* control how the device behaves relative to the QSPIPSU bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 indicates the option should be turned OFF and
+*		a 0 indicates no action. One or more bit values may be
+*		contained in the mask. See the bit definitions named
+*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	u32 Index;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+
+		/*
+		 * Loop through the options table, turning the option on
+		 * depending on whether the bit is set in the incoming options flag.
+		 */
+		for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+			if ((Options & OptionsTable[Index].Option) != FALSE) {
+				/* Turn it off */
+				ConfigReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+
+		/*
+		 * Now write the control register. Leave it to the upper layers
+		 * to restart the device.
+		 */
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				 ConfigReg);
+
+		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
+			InstancePtr->IsManualstart = FALSE;
+		}
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPIPSU device. The options control how
+* the device behaves relative to the QSPIPSU bus.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ConfigReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options from QSPIPSU configuration register.
+	 */
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPSU_CFG_OFFSET);
+
+	/* Loop through the options table to grab options */
+	for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+		if ((ConfigReg & OptionsTable[Index].Mask) != FALSE) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+
+#if defined (ARMR5) || (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This function sets the Tapdelay values for the QSPIPSU device driver.The device
+* must be idle rather than busy transferring data before setting Tapdelay.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	TapdelayBypss contains the IOU_TAPDLY_BYPASS register value.
+* @param	LPBKDelay contains the GQSPI_LPBK_DLY_ADJ register value.
+* @param	Datadelay contains the QSPI_DATA_DLY_ADJ register value.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting TapDelay.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass,
+						u32 LPBKDelay,u32 Datadelay)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = XST_DEVICE_BUSY;
+	} else {
+		XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR,IOU_TAPDLY_BYPASS_OFFSET,
+				TapdelayBypass);
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_LPBK_DLY_ADJ_OFFSET,LPBKDelay);
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_DATA_DLY_ADJ_OFFSET,Datadelay);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Configures the clock according to the prescaler passed.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Prescaler - clock prescaler.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting Tapdelay.
+*
+* @note		None.
+*
+******************************************************************************/
+static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler)
+{
+	u32 FreqDiv, Divider, Tapdelay, LBkModeReg, delayReg;
+	s32 Status;
+
+	Divider = (1 << (Prescaler+1));
+
+	FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;
+	Tapdelay = XQspiPsu_ReadReg(XPS_SYS_CTRL_BASEADDR,
+					IOU_TAPDLY_BYPASS_OFFSET);
+
+	Tapdelay = Tapdelay & (~IOU_TAPDLY_BYPASS_LQSPI_RX_MASK);
+
+	LBkModeReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_LPBK_DLY_ADJ_OFFSET);
+
+	LBkModeReg = (LBkModeReg &
+			(~(XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK))) &
+			(LBkModeReg & (~(XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK))) &
+			(LBkModeReg & (~(XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK)));
+
+	delayReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_DATA_DLY_ADJ_OFFSET);
+
+	delayReg = (delayReg &
+			(~(XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK))) &
+			(delayReg & (~( XQSPIPSU_DATA_DLY_ADJ_DLY_MASK)));
+
+	if(FreqDiv < XQSPIPSU_FREQ_40MHZ){
+		Tapdelay = Tapdelay |
+				(TAPDLY_BYPASS_VALVE_40MHZ << IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
+	} else if (FreqDiv <= XQSPIPSU_FREQ_100MHZ) {
+		Tapdelay = Tapdelay | (TAPDLY_BYPASS_VALVE_100MHZ << IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
+		LBkModeReg = LBkModeReg |
+				(USE_DLY_LPBK <<  XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT);
+		delayReg = delayReg |
+				(USE_DATA_DLY_ADJ  << XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT) |
+				(DATA_DLY_ADJ_DLY  << XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT);
+	} else if (FreqDiv <= XQSPIPSU_FREQ_150MHZ) {
+		LBkModeReg = LBkModeReg |
+				(USE_DLY_LPBK  <<  XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT ) |
+				(LPBK_DLY_ADJ_DLY0  << XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT);
+	}
+	Status = XQspi_Set_TapDelay(InstancePtr, Tapdelay, LBkModeReg, delayReg);
+
+	return Status;
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Configures the clock according to the prescaler passed.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Prescaler - clock prescaler to be set.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		/*
+		 * Read the configuration register, mask out the relevant bits, and set
+		 * them with the shifted value passed into the function. Write the
+		 * results back to the configuration register.
+		 */
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+
+		ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
+		ConfigReg |= (u32) ((u32)Prescaler & (u32)XQSPIPSU_CR_PRESC_MAXIMUM) <<
+				    XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
+
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+#if defined (ARMR5) || (__aarch64__)
+		Status = XQspipsu_Calculate_Tapdelay(InstancePtr,Prescaler);
+#else
+		Status = XST_SUCCESS;
+#endif
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This funciton should be used to tell the QSPIPSU driver the HW flash
+* configuration being used. This API should be called atleast once in the
+* application. If desired, it can be called multiple times when switching
+* between communicating to different flahs devices/using different configs.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	FlashCS - Flash Chip Select.
+* @param	FlashBus - Flash Bus (Upper, Lower or Both).
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		If this funciton is not called atleast once in the application,
+*		the driver assumes there is a single flash connected to the
+*		lower bus and CS line.
+*
+******************************************************************************/
+void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SelectFlash\r\n");
+#endif
+
+	/*
+	 * Bus and CS lines selected here will be updated in the instance and
+	 * used for subsequent GENFIFO entries during transfer.
+	 */
+
+	/* Choose slave select line */
+	switch (FlashCS) {
+		case XQSPIPSU_SELECT_FLASH_CS_BOTH:
+			InstancePtr->GenFifoCS = (u32)XQSPIPSU_GENFIFO_CS_LOWER |
+						(u32)XQSPIPSU_GENFIFO_CS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_CS_UPPER:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_CS_LOWER:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+			break;
+		default:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+			break;
+	}
+
+	/* Choose bus */
+	switch (FlashBus) {
+		case XQSPIPSU_SELECT_FLASH_BUS_BOTH:
+			InstancePtr->GenFifoBus = (u32)XQSPIPSU_GENFIFO_BUS_LOWER |
+						(u32)XQSPIPSU_GENFIFO_BUS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_BUS_UPPER:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_BUS_LOWER:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+			break;
+		default:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+			break;
+	}
+#ifdef DEBUG
+	xil_printf("\nGenFifoCS is %08x and GenFifoBus is %08x\r\n",
+				InstancePtr->GenFifoCS, InstancePtr->GenFifoBus);
+#endif
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the Read mode for the QSPIPSU device driver.The device
+* must be idle rather than busy transferring data before setting Read mode
+* options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Mode contains the specified Mode to be set. See the
+* 		bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting Mode.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
+{
+	u32 ConfigReg;
+	s32 Status;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SetReadMode\r\n");
+#endif
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		InstancePtr->ReadMode = Mode;
+
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+
+		if (Mode == XQSPIPSU_READMODE_DMA) {
+			ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+			ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+		} else {
+			ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+		}
+
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				 ConfigReg);
+
+		Status = XST_SUCCESS;
+	}
+#ifdef DEBUG
+	xil_printf("\nRead Mode is %08x\r\n", InstancePtr->ReadMode);
+#endif
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c
new file mode 100644
index 000000000..63aaed0bb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_sinit.c
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* The implementation of the XQspiPsu component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspipsu.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspipsu.h for the definition of XQspiPsu_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId)
+{
+	XQspiPsu_Config *CfgPtr = NULL;
+	s32 Index;
+
+	for (Index = 0; Index < XPAR_XQSPIPSU_NUM_INSTANCES; Index++) {
+		if (XQspiPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XQspiPsu_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XQspiPsu_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile
deleted file mode 100644
index dc8cbdf6b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xrtcpsu_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling rtcpsu"
-
-xrtcpsu_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xrtcpsu_includes
-
-xrtcpsu_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c
deleted file mode 100644
index 58163eb34..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xrtcpsu.c
-* @addtogroup rtcpsu_v1_0
-* @{
-*
-* Functions in this file are the minimum required functions for the XRtcPsu
-* driver. See xrtcpsu.h for a detailed description of the driver.
-*
-* @note 	None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    04/21/15 First release
-* 1.1   kvn    09/25/15 Modify control register to enable battery
-*                       switching when vcc_psaux is not available.
-* 1.2          02/15/16 Corrected Calibration mask and Fractional
-*                       mask in CalculateCalibration API.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xrtcpsu.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-static const u32 DaysInMonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
-
-/************************** Function Prototypes ******************************/
-
-static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event);
-
-/*****************************************************************************/
-/*
-*
-* This function initializes a XRtcPsu instance/driver.
-*
-* The initialization entails:
-* - Initialize all members of the XRtcPsu structure.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-* @param	ConfigPtr points to the XRtcPsu device configuration structure.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. If the address translation is not used then the
-*		physical address is passed.
-*		Unexpected errors may occur if the address mapping is changed
-*		after this function is invoked.
-*
-* @return	XST_SUCCESS always.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
-				u32 EffectiveAddr)
-{
-	s32 Status;
-	u32 ControlRegister;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	/*
-	 * Set some default values for instance data, don't indicate the device
-	 * is ready to use until everything has been initialized successfully.
-	 */
-	InstancePtr->IsReady = 0U;
-	InstancePtr->RtcConfig.BaseAddr = EffectiveAddr;
-	InstancePtr->RtcConfig.DeviceId = ConfigPtr->DeviceId;
-
-	if(InstancePtr->OscillatorFreq == 0U) {
-		InstancePtr->CalibrationValue = XRTC_CALIBRATION_VALUE;
-		InstancePtr->OscillatorFreq = XRTC_TYPICAL_OSC_FREQ;
-	}
-
-	/* Set all handlers to stub values, let user configure this data later. */
-	InstancePtr->Handler = XRtcPsu_StubHandler;
-
-	InstancePtr->IsPeriodicAlarm = 0U;
-
-	/* Set the calibration value in calibration register. */
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CALIB_WR_OFFSET,
-				InstancePtr->CalibrationValue);
-
-	/* Set the Oscillator crystal and Battery switch enable in control register. */
-	ControlRegister = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CTL_OFFSET);
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CTL_OFFSET,
-			(ControlRegister | (u32)XRTCPSU_CRYSTAL_OSC_EN | (u32)XRTC_CTL_BATTERY_EN_MASK));
-
-	/* Clear the Interrupt Status and Disable the interrupts. */
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
-			((u32)XRTC_INT_STS_ALRM_MASK | (u32)XRTC_INT_STS_SECS_MASK));
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_DIS_OFFSET,
-			((u32)XRTC_INT_DIS_ALRM_MASK | (u32)XRTC_INT_DIS_SECS_MASK));
-
-	/* Indicate the component is now ready to use. */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-	Status = XST_SUCCESS;
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is a stub handler that is the default handler such that if the
-* application has not set the handler when interrupts are enabled, this
-* function will be called.
-*
-* @param	CallBackRef is unused by this function.
-* @param	Event is unused by this function.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event)
-{
-	(void *) CallBackRef;
-	(void) Event;
-	/* Assert occurs always since this is a stub and should never be called */
-	Xil_AssertVoidAlways();
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the alarm value of RTC device.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance
-* @param	Alarm is the desired alarm time for RTC.
-* @param	Periodic says whether the alarm need to set at periodic
-* 			Intervals or a one-time alarm.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic)
-{
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(Alarm != 0U);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((Alarm - XRtcPsu_GetCurrentTime(InstancePtr)) > (u32)0);
-
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_ALRM_OFFSET, Alarm);
-	if(Periodic != 0U) {
-		InstancePtr->IsPeriodicAlarm = 1U;
-		InstancePtr->PeriodicAlarmTime =
-				Alarm - XRtcPsu_GetCurrentTime(InstancePtr);
-	}
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function translates time in seconds to a YEAR:MON:DAY HR:MIN:SEC
-* format and saves it in the DT structure variable. It also reports the weekday.
-*
-* @param	Seconds is the time value that has to be shown in DateTime
-* 			format.
-* @param	dt is the DateTime format variable that stores the translated
-* 			time.
-*
-* @return	None.
-*
-* @note		This API supports this century i.e., 2000 - 2099 years only.
-*
-*****************************************************************************/
-void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt)
-{
-	u32 CurrentTime, TempDays, Leap, DaysPerMonth;
-
-	CurrentTime = Seconds;
-	dt->Sec = CurrentTime % 60U;
-	CurrentTime /= 60U;
-	dt->Min = CurrentTime % 60U;
-	CurrentTime /= 60U;
-	dt->Hour = CurrentTime % 24U;
-	TempDays = CurrentTime / 24U;
-
-	if (TempDays == 0U) {
-		TempDays = 1U;
-	}
-	dt->WeekDay = TempDays % 7U;
-
-	for (dt->Year = 0U; dt->Year <= 99U; ++(dt->Year)) {
-		if ((dt->Year % 4U) == 0U ) {
-			Leap = 1U;
-		}
-		else {
-			Leap = 0U;
-		}
-		if (TempDays < (365U + Leap)) {
-			break;
-		}
-		TempDays -= (365U + Leap);
-	}
-
-	for (dt->Month = 1U; dt->Month >= 1U; ++(dt->Month)) {
-		DaysPerMonth = DaysInMonth[dt->Month - 1];
-		if ((Leap == 1U) && (dt->Month == 2U)) {
-			DaysPerMonth++;
-		}
-		if (TempDays < DaysPerMonth) {
-			break;
-		}
-		TempDays -= DaysPerMonth;
-	}
-
-	dt->Day = TempDays;
-	dt->Year += 2000U;
-}
-
-/****************************************************************************/
-/**
-*
-* This function translates time in YEAR:MON:DAY HR:MIN:SEC format to
-* seconds.
-*
-* @param	dt is a pointer to a DatetTime format structure variable
-* 			of time that has to be shown in seconds.
-*
-* @return	Seconds value of provided in dt time.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt)
-{
-	u32 i, Days;
-	u32 Seconds;
-	Xil_AssertNonvoid(dt != NULL);
-
-	if (dt->Year >= 2000U) {
-		dt->Year -= 2000U;
-	}
-
-	for (i = 1U; i < dt->Month; i++) {
-		dt->Day += (u32)DaysInMonth[i-1];
-	}
-
-	if ((dt->Month > 2U) && ((dt->Year % 4U) == 0U)) {
-		dt->Day++;
-	}
-	Days = dt->Day + (365U * dt->Year) + ((dt->Year + 3U) / 4U);
-	Seconds = (((((Days * 24U) + dt->Hour) * 60U) + dt->Min) * 60U) + dt->Sec;
-	return Seconds;
-}
-
-/****************************************************************************/
-/**
-*
-* This function calculates the calibration value depending on the actual
-* realworld time and also helps in deriving new calibration value if
-* the user wishes to change his oscillator frequency.TimeReal is generally the
-* internet time with EPOCH time as reference i.e.,1/1/1970 1st second.
-* But this RTC driver assumes start time from 1/1/2000 1st second. Hence,if
-* the user maps the internet time InternetTimeInSecs, then he has to use
-* 	XRtcPsu_SecToDateTime(InternetTimeInSecs,&InternetTime),
-* 	TimeReal = XRtcPsu_DateTimeToSec(InternetTime)
-* 	consecutively to arrive at TimeReal value.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-* @param	TimeReal is the actual realworld time generally an
-* 		network time / Internet time in seconds.
-*
-* @param	CrystalOscFreq is the Oscillator new frequency. Say, If the user
-* 		is going with the typical 32768Hz, then he inputs the same
-* 		frequency value.
-*
-* @return	None.
-*
-* @note		After Calculating the calibration register, user / application has to
-* 			call again CfgInitialize API to bring the new calibration into effect.
-*
-*****************************************************************************/
-void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
-		u32 CrystalOscFreq)
-{
-	u32 ReadTime, SetTime;
-	u32 Cprev,Fprev,Cnew,Fnew,Xf,Calibration;
-	Xil_AssertVoid(TimeReal != 0U);
-	Xil_AssertVoid(CrystalOscFreq != 0U);
-
-	ReadTime = XRtcPsu_GetCurrentTime(InstancePtr);
-	SetTime = XRtcPsu_GetLastSetTime(InstancePtr);
-	Calibration = XRtcPsu_GetCalibration(InstancePtr);
-	/*
-	 * When board gets reseted, Calibration value is zero
-	 * and Last setTime will be marked as 1st  second. This implies
-	 * CurrentTime to be in few seconds say something in tens. TimeReal will
-	 * be huge, say something in thousands. So to prevent such reset case, Cnew
-	 * and Fnew will not be calculated.
-	 */
-	if((Calibration == 0U) || (CrystalOscFreq != InstancePtr->OscillatorFreq)) {
-		Cnew = CrystalOscFreq - (u32)1;
-		Fnew = 0U;
-	} else {
-		Cprev = Calibration & XRTC_CALIB_RD_MAX_TCK_MASK;
-		Fprev = Calibration & XRTC_CALIB_RD_FRACTN_DATA_MASK;
-
-		Xf = ((ReadTime - SetTime) * ((Cprev+1U) + ((Fprev+1U)/16U))) / (TimeReal - SetTime);
-		Cnew = (u32)(Xf) - (u32)1;
-		Fnew = XRtcPsu_RoundOff((Xf - Cnew) * 16U) - (u32)1;
-	}
-
-	Calibration = (Fnew << XRTC_CALIB_RD_FRACTN_DATA_SHIFT) + Cnew;
-	Calibration |= XRTC_CALIB_RD_FRACTN_EN_MASK;
-
-	InstancePtr->CalibrationValue = Calibration;
-	InstancePtr->OscillatorFreq = CrystalOscFreq;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the seconds event status by reading
-* interrupt status register.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-*
-* @return	Returns 1 if a new second event is generated.Else 0..
-*
-* @note		This API is used in polled mode operation of RTC.
-* 			This also clears interrupt status seconds bit.
-*
-*****************************************************************************/
-u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr)
-{
-	u32 Status;
-
-	/* Loop the interrupt status register for Seconds Event */
-	if ((XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
-			XRTC_INT_STS_OFFSET) & (XRTC_INT_STS_SECS_MASK)) == 0U) {
-		Status = 0U;
-	} else {
-		/* Clear the interrupt status register */
-		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr +
-				XRTC_INT_STS_OFFSET, XRTC_INT_STS_SECS_MASK);
-		Status = 1U;
-	}
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the alarm event status by reading
-* interrupt status register.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-*
-* @return	Returns 1 if the alarm event is generated.Else 0.
-*
-* @note		This API is used in polled mode operation of RTC.
-* 			This also clears interrupt status alarm bit.
-*
-*****************************************************************************/
-u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr)
-{
-	u32 Status;
-
-	/* Loop the interrupt status register for Alarm Event */
-	if ((XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
-			XRTC_INT_STS_OFFSET) & (XRTC_INT_STS_ALRM_MASK)) == 0U) {
-		Status = 0U;
-	} else {
-		/* Clear the interrupt status register */
-		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr +
-				XRTC_INT_STS_OFFSET, XRTC_INT_STS_ALRM_MASK);
-		Status = 1U;
-	}
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h
deleted file mode 100644
index 98e668911..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xrtcpsu.h
-* @addtogroup rtcpsu_v1_0
-* @{
-* @details
-*
-* The Xilinx RTC driver component.  This component supports the Xilinx
-* RTC Controller. RTC Core and RTC controller are the two main important sub-
-* components for this RTC module. RTC core can run even in the battery powered
-* domain when the power from auxiliary source is down. Because of this, RTC core
-* latches the calibration,programmed time. This core interfaces with the crystal
-* oscillator and maintains current time in seconds.Calibration circuitry
-* calculates a second with maximum 1 PPM inaccuracy using a crystal oscillator
-* with arbitrary static inaccuracy. Core also responsible to maintain control
-* value used by the oscillator and power switching circuitry.
-*
-* RTC controller includes an APB interface responsible for register access with
-* in controller and core. It contains alarm generation logic including the alarm
-* register to hold alarm time in seconds.Interrupt management using Interrupt
-* status, Interrupt mask, Interrupt enable, Interrupt disable registers are
-* included to manage alarm and seconds interrupts. Address Slave error interrupts
-* are not being handled by this driver component.
-*
-* This driver supports the following features:
-* - Setting the RTC time.
-* - Setting the Alarm value that can be one-time alarm or a periodic alarm.
-* - Modifying the calibration value.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XRtcPsu_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XRtcPsu based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-*   - XRtcPsu_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-*	 configuration structure provided by the caller. If running in a system
-*	 with address translation, the parameter EffectiveAddr should be the
-* 	  virtual address.
-*
-* <b>Interrupts</b>
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - Alarm is generated.
-* - A new second is generated.
-*
-* The application can control which interrupts are enabled using the
-* XRtcPsu_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XRtcPsu_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XRtcPsu_SetHandler() function.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    04/21/15 First release
-* 1.1   kvn    09/25/15 Modify control register to enable battery
-*                       switching when vcc_psaux is not available.
-* </pre>
-*
-******************************************************************************/
-
-
-#ifndef XRTC_H_			/* prevent circular inclusions */
-#define XRTC_H_			/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xrtcpsu_hw.h"
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XRTCPSU_EVENT_ALARM_GEN		1U /**< Alarm generated event */
-#define XRTCPSU_EVENT_SECS_GEN		2U /**< A new second generated event */
-/*@}*/
-
-#define XRTCPSU_CRYSTAL_OSC_EN		(u32)1 << XRTC_CTL_OSC_SHIFT
-/**< Separate Mask for Crystal oscillator bit Enable */
-
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the handler, and is passed back to the upper layer
- *		when the handler is called. It is used to find the device driver
- *		instance.
- * @param	Event contains one of the event constants indicating events that
- *		have occurred.
- * @param	EventData contains the number of bytes sent or received at the
- *		time of the call for send and receive events and contains the
- *		modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XRtcPsu_Handler) (void *CallBackRef, u32 Event);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID of device */
-	u32 BaseAddr;		/**< Register base address */
-} XRtcPsu_Config;
-
-/**
- * The XRtcPsu driver instance data. The user is required to allocate a
- * variable of this type for the RTC device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XRtcPsu_Config RtcConfig; 	/**< Device configuration */
-	u32 IsReady;				/**< Device is initialized and ready */
-	u32 PeriodicAlarmTime;
-	u8 IsPeriodicAlarm;
-	u32 OscillatorFreq;
-	u32 CalibrationValue;
-	XRtcPsu_Handler Handler;
-	void *CallBackRef;			/**< Callback reference for event handler */
-} XRtcPsu;
-
-/**
- * This typedef contains DateTime format structure.
- */
-typedef struct {
-	u32 Year;
-	u32 Month;
-	u32 Day;
-	u32 Hour;
-	u32 Min;
-	u32 Sec;
-	u32 WeekDay;
-} XRtcPsu_DT;
-
-
-/************************* Variable Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XRTC_CALIBRATION_VALUE 0x00198231U
-#define XRTC_TYPICAL_OSC_FREQ 33330U
-
-/****************************************************************************/
-/**
-*
-* This macro updates the current time of RTC device.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-* @param	Time is the desired time for RTC in seconds.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-* 		void XRtcPsu_SetTime(XRtcPsu *InstancePtr, u32 Time)
-*
-*****************************************************************************/
-#define XRtcPsu_SetTime(InstancePtr,Time) \
-	XRtcPsu_WriteReg(((InstancePtr)->RtcConfig.BaseAddr + \
-				XRTC_SET_TIME_WR_OFFSET),(Time))
-
-/****************************************************************************/
-/**
-*
-* This macro returns the last set time of RTC device. Whenever a reset
-* happens, the last set time will be zeroth day first sec.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-*
-* @return	The last set time in seconds.
-*
-* @note		C-Style signature:
-* 		u32 XRtcPsu_GetLastSetTime(XRtcPsu *InstancePtr)
-*
-*****************************************************************************/
-#define XRtcPsu_GetLastSetTime(InstancePtr) \
-	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr + XRTC_SET_TIME_RD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* This macro returns the calibration value of RTC device.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-*
-* @return	Calibration value for RTC.
-*
-* @note		C-Style signature:
-* 		u32 XRtcPsu_GetCalibration(XRtcPsu *InstancePtr)
-*
-*****************************************************************************/
-#define XRtcPsu_GetCalibration(InstancePtr) \
-	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CALIB_RD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* This macro returns the current time of RTC device.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-*
-* @return	Current Time. This current time will be in seconds.
-*
-* @note		C-Style signature:
-* 		u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr)
-*
-*****************************************************************************/
-#define XRtcPsu_GetCurrentTime(InstancePtr) \
-	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CUR_TIME_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* This macro sets the control register value of RTC device.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-* @param	Value is the desired control register value for RTC.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-* 		void XRtcPsu_SetControlRegister(XRtcPsu *InstancePtr, u32 Value)
-*
-*****************************************************************************/
-#define XRtcPsu_SetControlRegister(InstancePtr, Value) \
-	XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
-			XRTC_CTL_OFFSET,(Value))
-
-/****************************************************************************/
-/**
-*
-* This macro returns the safety check register value of RTC device.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-*
-* @return	Safety check register value.
-*
-* @note		C-Style signature:
-* 		u32 XRtcPsu_GetSafetyCheck(XRtcPsu *InstancePtr)
-*
-*****************************************************************************/
-#define XRtcPsu_GetSafetyCheck(InstancePtr)	\
-	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_SFTY_CHK_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* This macro sets the safety check register value of RTC device.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-* @param	Value is a safety check value to be written in register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-* 		void XRtcPsu_SetSafetyCheck(XRtcPsu *InstancePtr, u32 Value)
-*
-*****************************************************************************/
-#define XRtcPsu_SetSafetyCheck(InstancePtr, Value)	\
-	XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
-			XRTC_SFTY_CHK_OFFSET,(Value))
-
-/****************************************************************************/
-/**
-*
-* This macro resets the alarm register
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-* 		u32 XRtcPsu_ResetAlarm(XRtcPsu *InstancePtr)
-*
-*****************************************************************************/
-#define XRtcPsu_ResetAlarm(InstancePtr) \
-		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
-				XRTC_ALRM_OFFSET,XRTC_ALRM_RSTVAL)
-
-/****************************************************************************/
-/**
-*
-* This macro rounds off the given number
-*
-* @param	Number is the one that needs to be rounded off..
-*
-* @return	The rounded off value of the input number.
-*
-* @note		C-Style signature:
-* 		u32 XRtcPsu_RoundOff(float Number)
-*
-*****************************************************************************/
-#define XRtcPsu_RoundOff(Number) \
-	(u32)(((Number) < (u32)0) ? ((Number) - (u32)0.5) : ((Number) + (u32)0.5))
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xrtcpsu.c */
-s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
-				u32 EffectiveAddr);
-
-void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic);
-void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt);
-u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt);
-void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
-		u32 CrystalOscFreq);
-u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr);
-u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr);
-
-/* interrupt functions in xrtcpsu_intr.c */
-void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask);
-void XRtcPsu_ClearInterruptMask(XRtcPsu *InstancePtr, u32 Mask);
-void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr);
-void XRtcPsu_SetHandler(XRtcPsu *InstancePtr, XRtcPsu_Handler FuncPtr,
-			 void *CallBackRef);
-
-/* Functions in xrtcpsu_selftest.c */
-s32 XRtcPsu_SelfTest(XRtcPsu *InstancePtr);
-
-/* Functions in xrtcpsu_sinit.c */
-XRtcPsu_Config *XRtcPsu_LookupConfig(u16 DeviceId);
-
-
-#endif /* XRTC_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
deleted file mode 100644
index 8dc37775a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xrtcpsu.h"
-
-/*
-* The configuration table for devices
-*/
-
-XRtcPsu_Config XRtcPsu_ConfigTable[] =
-{
-	{
-		XPAR_PSU_RTC_DEVICE_ID,
-		XPAR_PSU_RTC_BASEADDR
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h
deleted file mode 100644
index 532ef7e3c..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xrtcpsu_hw.h
-* @addtogroup rtcpsu_v1_0
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xrtcpsu.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00a kvn	  04/21/15 First release
-* 1.1   kvn   09/25/15 Modify control register to enable battery
-*                      switching when vcc_psaux is not available.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XRTC_HW_H_		/* prevent circular inclusions */
-#define XRTC_HW_H_		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * Xrtc Base Address
- */
-#define XRTC_BASEADDR      0xFFA60000U
-
-/**
- * Register: XrtcSetTimeWr
- */
-#define XRTC_SET_TIME_WR_OFFSET    0x00000000U
-#define XRTC_SET_TIME_WR_RSTVAL   0x00000000U
-
-#define XRTC_SET_TIME_WR_VAL_SHIFT   0U
-#define XRTC_SET_TIME_WR_VAL_WIDTH   32U
-#define XRTC_SET_TIME_WR_VAL_MASK    0xffffffffU
-#define XRTC_SET_TIME_WR_VAL_DEFVAL  0x0U
-
-/**
- * Register: XrtcSetTimeRd
- */
-#define XRTC_SET_TIME_RD_OFFSET    0x00000004U
-#define XRTC_SET_TIME_RD_RSTVAL   0x00000000U
-
-#define XRTC_SET_TIME_RD_VAL_SHIFT   0U
-#define XRTC_SET_TIME_RD_VAL_WIDTH   32U
-#define XRTC_SET_TIME_RD_VAL_MASK    0xffffffffU
-#define XRTC_SET_TIME_RD_VAL_DEFVAL  0x0U
-
-/**
- * Register: XrtcCalibWr
- */
-#define XRTC_CALIB_WR_OFFSET    0x00000008U
-#define XRTC_CALIB_WR_RSTVAL   0x00000000U
-
-#define XRTC_CALIB_WR_FRACTN_EN_SHIFT   20U
-#define XRTC_CALIB_WR_FRACTN_EN_WIDTH   1U
-#define XRTC_CALIB_WR_FRACTN_EN_MASK    0x00100000U
-#define XRTC_CALIB_WR_FRACTN_EN_DEFVAL  0x0U
-
-#define XRTC_CALIB_WR_FRACTN_DATA_SHIFT   16U
-#define XRTC_CALIB_WR_FRACTN_DATA_WIDTH   4U
-#define XRTC_CALIB_WR_FRACTN_DATA_MASK    0x000f0000U
-#define XRTC_CALIB_WR_FRACTN_DATA_DEFVAL  0x0U
-
-#define XRTC_CALIB_WR_MAX_TCK_SHIFT   0U
-#define XRTC_CALIB_WR_MAX_TCK_WIDTH   16U
-#define XRTC_CALIB_WR_MAX_TCK_MASK    0x0000ffffU
-#define XRTC_CALIB_WR_MAX_TCK_DEFVAL  0x0U
-
-/**
- * Register: XrtcCalibRd
- */
-#define XRTC_CALIB_RD_OFFSET    0x0000000CU
-#define XRTC_CALIB_RD_RSTVAL   0x00000000U
-
-#define XRTC_CALIB_RD_FRACTN_EN_SHIFT   20U
-#define XRTC_CALIB_RD_FRACTN_EN_WIDTH   1U
-#define XRTC_CALIB_RD_FRACTN_EN_MASK    0x00100000U
-#define XRTC_CALIB_RD_FRACTN_EN_DEFVAL  0x0U
-
-#define XRTC_CALIB_RD_FRACTN_DATA_SHIFT   16U
-#define XRTC_CALIB_RD_FRACTN_DATA_WIDTH   4U
-#define XRTC_CALIB_RD_FRACTN_DATA_MASK    0x000f0000U
-#define XRTC_CALIB_RD_FRACTN_DATA_DEFVAL  0x0U
-
-#define XRTC_CALIB_RD_MAX_TCK_SHIFT   0U
-#define XRTC_CALIB_RD_MAX_TCK_WIDTH   16U
-#define XRTC_CALIB_RD_MAX_TCK_MASK    0x0000ffffU
-#define XRTC_CALIB_RD_MAX_TCK_DEFVAL  0x0U
-
-/**
- * Register: XrtcCurTime
- */
-#define XRTC_CUR_TIME_OFFSET    0x00000010U
-#define XRTC_CUR_TIME_RSTVAL   0x00000000U
-
-#define XRTC_CUR_TIME_VAL_SHIFT   0U
-#define XRTC_CUR_TIME_VAL_WIDTH   32U
-#define XRTC_CUR_TIME_VAL_MASK    0xffffffffU
-#define XRTC_CUR_TIME_VAL_DEFVAL  0x0U
-
-/**
- * Register: XrtcCurTck
- */
-#define XRTC_CUR_TCK_OFFSET    0x00000014U
-#define XRTC_CUR_TCK_RSTVAL   0x00000000U
-
-#define XRTC_CUR_TCK_VAL_SHIFT   0U
-#define XRTC_CUR_TCK_VAL_WIDTH   16U
-#define XRTC_CUR_TCK_VAL_MASK    0x0000ffffU
-#define XRTC_CUR_TCK_VAL_DEFVAL  0x0U
-
-/**
- * Register: XrtcAlrm
- */
-#define XRTC_ALRM_OFFSET    0x00000018U
-#define XRTC_ALRM_RSTVAL   0x00000000U
-
-#define XRTC_ALRM_VAL_SHIFT   0U
-#define XRTC_ALRM_VAL_WIDTH   32U
-#define XRTC_ALRM_VAL_MASK    0xffffffffU
-#define XRTC_ALRM_VAL_DEFVAL  0x0U
-
-/**
- * Register: XrtcIntSts
- */
-#define XRTC_INT_STS_OFFSET    0x00000020U
-#define XRTC_INT_STS_RSTVAL   0x00000000U
-
-#define XRTC_INT_STS_ALRM_SHIFT   1U
-#define XRTC_INT_STS_ALRM_WIDTH   1U
-#define XRTC_INT_STS_ALRM_MASK    0x00000002U
-#define XRTC_INT_STS_ALRM_DEFVAL  0x0U
-
-#define XRTC_INT_STS_SECS_SHIFT   0U
-#define XRTC_INT_STS_SECS_WIDTH   1U
-#define XRTC_INT_STS_SECS_MASK    0x00000001U
-#define XRTC_INT_STS_SECS_DEFVAL  0x0U
-
-/**
- * Register: XrtcIntMsk
- */
-#define XRTC_INT_MSK_OFFSET    0x00000024U
-#define XRTC_INT_MSK_RSTVAL   0x00000003U
-
-#define XRTC_INT_MSK_ALRM_SHIFT   1U
-#define XRTC_INT_MSK_ALRM_WIDTH   1U
-#define XRTC_INT_MSK_ALRM_MASK    0x00000002U
-#define XRTC_INT_MSK_ALRM_DEFVAL  0x1U
-
-#define XRTC_INT_MSK_SECS_SHIFT   0U
-#define XRTC_INT_MSK_SECS_WIDTH   1U
-#define XRTC_INT_MSK_SECS_MASK    0x00000001U
-#define XRTC_INT_MSK_SECS_DEFVAL  0x1U
-
-/**
- * Register: XrtcIntEn
- */
-#define XRTC_INT_EN_OFFSET    0x00000028U
-#define XRTC_INT_EN_RSTVAL   0x00000000U
-
-#define XRTC_INT_EN_ALRM_SHIFT   1U
-#define XRTC_INT_EN_ALRM_WIDTH   1U
-#define XRTC_INT_EN_ALRM_MASK    0x00000002U
-#define XRTC_INT_EN_ALRM_DEFVAL  0x0U
-
-#define XRTC_INT_EN_SECS_SHIFT   0U
-#define XRTC_INT_EN_SECS_WIDTH   1U
-#define XRTC_INT_EN_SECS_MASK    0x00000001U
-#define XRTC_INT_EN_SECS_DEFVAL  0x0U
-
-/**
- * Register: XrtcIntDis
- */
-#define XRTC_INT_DIS_OFFSET    0x0000002CU
-#define XRTC_INT_DIS_RSTVAL   0x00000000U
-
-#define XRTC_INT_DIS_ALRM_SHIFT   1U
-#define XRTC_INT_DIS_ALRM_WIDTH   1U
-#define XRTC_INT_DIS_ALRM_MASK    0x00000002U
-#define XRTC_INT_DIS_ALRM_DEFVAL  0x0U
-
-#define XRTC_INT_DIS_SECS_SHIFT   0U
-#define XRTC_INT_DIS_SECS_WIDTH   1U
-#define XRTC_INT_DIS_SECS_MASK    0x00000001U
-#define XRTC_INT_DIS_SECS_DEFVAL  0x0U
-
-/**
- * Register: XrtcAddErr
- */
-#define XRTC_ADD_ERR_OFFSET    0x00000030U
-#define XRTC_ADD_ERR_RSTVAL   0x00000000U
-
-#define XRTC_ADD_ERR_STS_SHIFT   0U
-#define XRTC_ADD_ERR_STS_WIDTH   1U
-#define XRTC_ADD_ERR_STS_MASK    0x00000001U
-#define XRTC_ADD_ERR_STS_DEFVAL  0x0U
-
-/**
- * Register: XrtcAddErrIntMsk
- */
-#define XRTC_ADD_ERR_INT_MSK_OFFSET    0x00000034U
-#define XRTC_ADD_ERR_INT_MSK_RSTVAL   0x00000001U
-
-#define XRTC_ADD_ERR_INT_MSK_SHIFT   0U
-#define XRTC_ADD_ERR_INT_MSK_WIDTH   1U
-#define XRTC_ADD_ERR_INT_MSK_MASK    0x00000001U
-#define XRTC_ADD_ERR_INT_MSK_DEFVAL  0x1U
-
-/**
- * Register: XrtcAddErrIntEn
- */
-#define XRTC_ADD_ERR_INT_EN_OFFSET    0x00000038U
-#define XRTC_ADD_ERR_INT_EN_RSTVAL   0x00000000U
-
-#define XRTC_ADD_ERR_INT_EN_MSK_SHIFT   0U
-#define XRTC_ADD_ERR_INT_EN_MSK_WIDTH   1U
-#define XRTC_ADD_ERR_INT_EN_MSK_MASK    0x00000001U
-#define XRTC_ADD_ERR_INT_EN_MSK_DEFVAL  0x0U
-
-/**
- * Register: XrtcAddErrIntDis
- */
-#define XRTC_ADD_ERR_INT_DIS_OFFSET    0x0000003CU
-#define XRTC_ADD_ERR_INT_DIS_RSTVAL   0x00000000U
-
-#define XRTC_ADD_ERR_INT_DIS_MSK_SHIFT   0U
-#define XRTC_ADD_ERR_INT_DIS_MSK_WIDTH   1U
-#define XRTC_ADD_ERR_INT_DIS_MSK_MASK    0x00000001U
-#define XRTC_ADD_ERR_INT_DIS_MSK_DEFVAL  0x0U
-
-/**
- * Register: XrtcCtl
- */
-#define XRTC_CTL_OFFSET    0x00000040U
-#define XRTC_CTL_RSTVAL   0x01000000U
-
-#define XRTC_CTL_BATTERY_EN_SHIFT   31U
-#define XRTC_CTL_BATTERY_EN_WIDTH   1U
-#define XRTC_CTL_BATTERY_EN_MASK    0x80000000U
-#define XRTC_CTL_BATTERY_EN_DEFVAL  0x0U
-
-#define XRTC_CTL_OSC_SHIFT   24U
-#define XRTC_CTL_OSC_WIDTH   4U
-#define XRTC_CTL_OSC_MASK    0x0f000000U
-#define XRTC_CTL_OSC_DEFVAL  0x1U
-
-#define XRTC_CTL_SLVERR_EN_SHIFT   0U
-#define XRTC_CTL_SLVERR_EN_WIDTH   1U
-#define XRTC_CTL_SLVERR_EN_MASK    0x00000001U
-#define XRTC_CTL_SLVERR_EN_DEFVAL  0x0U
-
-/**
- * Register: XrtcSftyChk
- */
-#define XRTC_SFTY_CHK_OFFSET    0x00000050U
-#define XRTC_SFTY_CHK_RSTVAL   0x00000000U
-
-#define XRTC_SFTY_CHK_REG_SHIFT   0U
-#define XRTC_SFTY_CHK_REG_WIDTH   32U
-#define XRTC_SFTY_CHK_REG_MASK    0xffffffffU
-#define XRTC_SFTY_CHK_REG_DEFVAL  0x0U
-
-/**
- * Register: XrtcEco
- */
-#define XRTC_ECO_OFFSET    0x00000060U
-#define XRTC_ECO_RSTVAL   0x00000000U
-
-#define XRTC_ECO_REG_SHIFT   0U
-#define XRTC_ECO_REG_WIDTH   32U
-#define XRTC_ECO_REG_MASK    0xffffffffU
-#define XRTC_ECO_REG_DEFVAL  0x0U
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param	RegisterAddr is the register address in the address
-* 			space of the RTC device.
-*
-* @return	The 32-bit value of the register
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XRtcPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param	RegisterAddr is the register address in the address
-* 			space of the RTC device.
-* @param	Data is the 32-bit value to write to the register.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XRtcPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XRTC_HW_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c
deleted file mode 100644
index bca20af12..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xrtcpsu_intr.c
-* @addtogroup rtcpsu_v1_0
-* @{
-*
-* This file contains functions related to RTC interrupt handling.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    04/21/15 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xrtcpsu.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* This function sets the interrupt mask.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance
-* @param	Mask contains the interrupts to be enabled.
-*		A '1' enables an interupt, and a '0' disables.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask)
-{
-	/*
-	 * Clear the Status register to be sure of no pending interrupts.
-	 * Writing mask values to interrupt bits as it is a WTC register.
-	 */
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
-			((u32)XRTC_INT_STS_ALRM_MASK | (u32)XRTC_INT_STS_SECS_MASK));
-
-	/*
-	 * XRTC_INT_MSK_RSTVAL contains the valid interrupts
-	 * for the RTC device. The AND operation on Mask makes sure one
-	 * of the valid bits are only set.
-	 */
-
-	/* Write the mask to the IER Register */
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_INT_EN_OFFSET,
-					(Mask & (u32)XRTC_INT_MSK_RSTVAL));
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the interrupt mask.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance
-* @param	Mask contains the interrupts to be disabled.
-*		A '1' enables an interrupt, and a '0' disables.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XRtcPsu_ClearInterruptMask(XRtcPsu *InstancePtr, u32 Mask)
-{
-	/*
-	 * XRTC_INT_MSK_RSTVAL contains the valid interrupts
-	 * for the RTC device. The AND operation on mask makes sure one
-	 * of the valid bits are only cleared.
-	 */
-
-	/* Write the Mask to the IDR register */
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_INT_DIS_OFFSET,
-					(Mask & (u32)XRTC_INT_MSK_RSTVAL));
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance
-* @param	FuncPtr is the pointer to the callback function.
-* @param	CallBackRef is the upper layer callback reference passed back
-*		when the callback function is invoked.
-*
-* @return	None.
-*
-* @note
-*
-* There is no assert on the CallBackRef since the driver doesn't know what it
-* is (nor should it)
-*
-*****************************************************************************/
-void XRtcPsu_SetHandler(XRtcPsu *InstancePtr, XRtcPsu_Handler FuncPtr,
-		 void *CallBackRef)
-{
-	/*
-	 * Asserts validate the input arguments
-	 * CallBackRef not checked, no way to know what is valid
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(FuncPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	InstancePtr->Handler = FuncPtr;
-	InstancePtr->CallBackRef = CallBackRef;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is the interrupt handler for the driver.
-* It must be connected to an interrupt system by the application such that it
-* can be called when an interrupt occurs.
-*
-* @param	InstancePtr contains a pointer to the driver instance
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr)
-{
-	u32 IsrStatus;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read the interrupt ID register to determine which
-	 * interrupt is active.
-	 */
-	IsrStatus = ~(XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
-			XRTC_INT_MSK_OFFSET));
-
-	IsrStatus &= XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
-			XRTC_INT_STS_OFFSET);
-
-	/*
-	 * Clear the interrupt status to allow future
-	 * interrupts before this generated interrupt is serviced.
-	 */
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr +
-			XRTC_INT_STS_OFFSET, IsrStatus);
-
-	/* Handle the generated interrupts appropriately. */
-
-	/* Alarm interrupt */
-	if((IsrStatus & XRTC_INT_STS_ALRM_MASK) != (u32)0) {
-
-		if(InstancePtr->IsPeriodicAlarm != 0U) {
-			XRtcPsu_SetAlarm(InstancePtr,
-					(XRtcPsu_GetCurrentTime(InstancePtr)+InstancePtr->PeriodicAlarmTime),1U);
-		}
-
-		/*
-		 * Call the application handler to indicate that there is an
-		 * alarm interrupt. If the application cares about this alarm,
-		 * it will act accordingly through its own handler.
-		 */
-		InstancePtr->Handler(InstancePtr->CallBackRef,
-					XRTCPSU_EVENT_ALARM_GEN);
-	}
-
-	/* Seconds interrupt */
-	if((IsrStatus & XRTC_INT_STS_SECS_MASK) != (u32)0) {
-		/*
-		 * Call the application handler to indicate that there is an
-		 * seconds interrupt. If the application cares about this seconds
-		 * interrupt, it will act accordingly through its own handler.
-		 */
-		InstancePtr->Handler(InstancePtr->CallBackRef,
-					XRTCPSU_EVENT_SECS_GEN);
-	}
-
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c
deleted file mode 100644
index 67c562c64..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xrtcpsu_selftest.c
-* @addtogroup rtcpsu_v1_0
-* @{
-*
-* This file contains the self-test functions for the XRtcPsu driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00  kvn    04/21/15 First release.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xrtcpsu.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test writes reset value into safety check register and read backs the same.
-* If mismatch offers, returns the failure.
-*
-* @param	InstancePtr is a pointer to the XRtcPsu instance
-*
-* @return
-*		 - XST_SUCCESS if the test was successful
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-s32 XRtcPsu_SelfTest(XRtcPsu *InstancePtr)
-{
-	s32 Status = XST_SUCCESS;
-	u32 SafetyCheck;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Write the reset value in safety check register and
-	 * try reading back. If mismatch happens, return failure.
-	 */
-	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_SFTY_CHK_OFFSET,
-			XRTC_SFTY_CHK_RSTVAL);
-	SafetyCheck = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
-			XRTC_SFTY_CHK_OFFSET);
-
-	if (SafetyCheck != XRTC_SFTY_CHK_RSTVAL) {
-		Status = XST_FAILURE;
-	}
-
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c
deleted file mode 100644
index d3a8b7dfc..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xrtcpsu_sinit.c
-* @addtogroup rtcpsu_v1_0
-* @{
-*
-* This file contains the implementation of the XRtcPsu driver's static
-* initialization functionality.
-*
-* @note		None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    04/21/15 First release.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xrtcpsu.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern XRtcPsu_Config XRtcPsu_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* This function looks for the device configuration based on the unique device
-* ID. The table XRtcPsu_ConfigTable[] contains the configuration information for
-* each device in the system.
-*
-* @param	DeviceId is the unique device ID of the device being looked up.
-*
-* @return	A pointer to the configuration table entry corresponding to the
-*		given device ID, or NULL if no match is found.
-*
-* @note		None.
-*
-******************************************************************************/
-XRtcPsu_Config *XRtcPsu_LookupConfig(u16 DeviceId)
-{
-	XRtcPsu_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index = 0U; Index < (u32)XPAR_XRTCPSU_NUM_INSTANCES; Index++) {
-		if (XRtcPsu_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XRtcPsu_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XRtcPsu_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile
new file mode 100644
index 000000000..dc8cbdf6b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xrtcpsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling rtcpsu"
+
+xrtcpsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xrtcpsu_includes
+
+xrtcpsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c
new file mode 100644
index 000000000..c91f61279
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c
@@ -0,0 +1,512 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* Functions in this file are the minimum required functions for the XRtcPsu
+* driver. See xrtcpsu.h for a detailed description of the driver.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release
+* 1.1   kvn    09/25/15 Modify control register to enable battery
+*                       switching when vcc_psaux is not available.
+* 1.2          02/15/16 Corrected Calibration mask and Fractional
+*                       mask in CalculateCalibration API.
+* 1.3   vak    04/25/16 Corrected the RTC read and write time logic(cr#948833).
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xrtcpsu.h"
+#include "xrtcpsu_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+static const u32 DaysInMonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
+
+/************************** Function Prototypes ******************************/
+
+static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XRtcPsu instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XRtcPsu structure.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	ConfigPtr points to the XRtcPsu device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ControlRegister;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->RtcConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->RtcConfig.DeviceId = ConfigPtr->DeviceId;
+
+	if(InstancePtr->OscillatorFreq == 0U) {
+		InstancePtr->CalibrationValue = XRTC_CALIBRATION_VALUE;
+		InstancePtr->OscillatorFreq = XRTC_TYPICAL_OSC_FREQ;
+	}
+
+	/* Set all handlers to stub values, let user configure this data later. */
+	InstancePtr->Handler = XRtcPsu_StubHandler;
+
+	InstancePtr->IsPeriodicAlarm = 0U;
+
+	/* Set the calibration value in calibration register. */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CALIB_WR_OFFSET,
+				InstancePtr->CalibrationValue);
+
+	/* Set the Oscillator crystal and Battery switch enable in control register. */
+	ControlRegister = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CTL_OFFSET);
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CTL_OFFSET,
+			(ControlRegister | (u32)XRTCPSU_CRYSTAL_OSC_EN | (u32)XRTC_CTL_BATTERY_EN_MASK));
+
+	/* Clear the Interrupt Status and Disable the interrupts. */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
+			((u32)XRTC_INT_STS_ALRM_MASK | (u32)XRTC_INT_STS_SECS_MASK));
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_DIS_OFFSET,
+			((u32)XRTC_INT_DIS_ALRM_MASK | (u32)XRTC_INT_DIS_SECS_MASK));
+
+	/* Indicate the component is now ready to use. */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/* Clear TimeUpdated and CurrTimeUpdated */
+	InstancePtr->TimeUpdated = 0;
+	InstancePtr->CurrTimeUpdated = 0;
+
+	Status = XST_SUCCESS;
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event)
+{
+	(void *) CallBackRef;
+	(void) Event;
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the RTC time by writing into rtc write register.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Time that should be updated into RTC write register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time)
+{
+	/* Set the calibration value in calibration register, so that
+	 * next Second is triggered exactly at 1 sec period
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CALIB_WR_OFFSET,
+							InstancePtr->CalibrationValue);
+	/* clear the RTC secs interrupt from status register */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
+								XRTC_INT_STS_SECS_MASK);
+	InstancePtr->CurrTimeUpdated = 0;
+	/* Update the flag before setting the time */
+	InstancePtr->TimeUpdated = 1;
+	/* Since RTC takes 1 sec to update the time into current time register, write
+	 * load time + 1sec into the set time register.
+	 */
+	XRtcPsu_WriteSetTime(InstancePtr, Time + 1);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the current RTC time.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	RTC Current time.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr)
+{
+	u32 Status, IntMask, CurrTime;
+
+	IntMask = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_MSK_OFFSET);
+
+	if((IntMask & XRTC_INT_STS_SECS_MASK) != (u32)0) {
+		/* We come here if interrupts are disabled */
+		Status = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET);
+		if((InstancePtr->TimeUpdated == (u32)1) &&
+			(Status & XRTC_INT_STS_SECS_MASK) == (u32)0) {
+			/* Give the previous written time */
+			CurrTime = XRtcPsu_GetLastSetTime(InstancePtr) - 1;
+		} else {
+			/* Clear TimeUpdated */
+			if((InstancePtr->TimeUpdated == (u32)1) &&
+				((Status & XRTC_INT_STS_SECS_MASK) == (u32)1)) {
+				InstancePtr->TimeUpdated = (u32)0;
+			}
+
+			/* RTC time got updated */
+			CurrTime = XRtcPsu_ReadCurrentTime(InstancePtr);
+		}
+	} else {
+		/* We come here if interrupts are enabled */
+		if((InstancePtr->TimeUpdated == (u32)1) &&
+			(InstancePtr->CurrTimeUpdated == (u32)0)) {
+			/* Give the previous written time -1 sec */
+			CurrTime = XRtcPsu_GetLastSetTime(InstancePtr) - 1;
+		} else {
+			/* Clear TimeUpdated */
+			if(InstancePtr->TimeUpdated == (u32)1)
+				InstancePtr->TimeUpdated = (u32)0;
+			/* RTC time got updated */
+			CurrTime = XRtcPsu_ReadCurrentTime(InstancePtr);
+		}
+	}
+	return CurrTime;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the alarm value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	Alarm is the desired alarm time for RTC.
+* @param	Periodic says whether the alarm need to set at periodic
+* 			Intervals or a one-time alarm.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Alarm != 0U);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Alarm - XRtcPsu_GetCurrentTime(InstancePtr)) > (u32)0);
+
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_ALRM_OFFSET, Alarm);
+	if(Periodic != 0U) {
+		InstancePtr->IsPeriodicAlarm = 1U;
+		InstancePtr->PeriodicAlarmTime =
+				Alarm - XRtcPsu_GetCurrentTime(InstancePtr);
+	}
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function translates time in seconds to a YEAR:MON:DAY HR:MIN:SEC
+* format and saves it in the DT structure variable. It also reports the weekday.
+*
+* @param	Seconds is the time value that has to be shown in DateTime
+* 			format.
+* @param	dt is the DateTime format variable that stores the translated
+* 			time.
+*
+* @return	None.
+*
+* @note		This API supports this century i.e., 2000 - 2099 years only.
+*
+*****************************************************************************/
+void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt)
+{
+	u32 CurrentTime, TempDays, Leap, DaysPerMonth;
+
+	CurrentTime = Seconds;
+	dt->Sec = CurrentTime % 60U;
+	CurrentTime /= 60U;
+	dt->Min = CurrentTime % 60U;
+	CurrentTime /= 60U;
+	dt->Hour = CurrentTime % 24U;
+	TempDays = CurrentTime / 24U;
+
+	if (TempDays == 0U) {
+		TempDays = 1U;
+	}
+	dt->WeekDay = TempDays % 7U;
+
+	for (dt->Year = 0U; dt->Year <= 99U; ++(dt->Year)) {
+		if ((dt->Year % 4U) == 0U ) {
+			Leap = 1U;
+		}
+		else {
+			Leap = 0U;
+		}
+		if (TempDays < (365U + Leap)) {
+			break;
+		}
+		TempDays -= (365U + Leap);
+	}
+
+	for (dt->Month = 1U; dt->Month >= 1U; ++(dt->Month)) {
+		DaysPerMonth = DaysInMonth[dt->Month - 1];
+		if ((Leap == 1U) && (dt->Month == 2U)) {
+			DaysPerMonth++;
+		}
+		if (TempDays < DaysPerMonth) {
+			break;
+		}
+		TempDays -= DaysPerMonth;
+	}
+
+	dt->Day = TempDays;
+	dt->Year += 2000U;
+}
+
+/****************************************************************************/
+/**
+*
+* This function translates time in YEAR:MON:DAY HR:MIN:SEC format to
+* seconds.
+*
+* @param	dt is a pointer to a DatetTime format structure variable
+* 			of time that has to be shown in seconds.
+*
+* @return	Seconds value of provided in dt time.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt)
+{
+	u32 i, Days;
+	u32 Seconds;
+	Xil_AssertNonvoid(dt != NULL);
+
+	if (dt->Year >= 2000U) {
+		dt->Year -= 2000U;
+	}
+
+	for (i = 1U; i < dt->Month; i++) {
+		dt->Day += (u32)DaysInMonth[i-1];
+	}
+
+	if ((dt->Month > 2U) && ((dt->Year % 4U) == 0U)) {
+		dt->Day++;
+	}
+	Days = dt->Day + (365U * dt->Year) + ((dt->Year + 3U) / 4U);
+	Seconds = (((((Days * 24U) + dt->Hour) * 60U) + dt->Min) * 60U) + dt->Sec;
+	return Seconds;
+}
+
+/****************************************************************************/
+/**
+*
+* This function calculates the calibration value depending on the actual
+* realworld time and also helps in deriving new calibration value if
+* the user wishes to change his oscillator frequency.TimeReal is generally the
+* internet time with EPOCH time as reference i.e.,1/1/1970 1st second.
+* But this RTC driver assumes start time from 1/1/2000 1st second. Hence,if
+* the user maps the internet time InternetTimeInSecs, then he has to use
+* 	XRtcPsu_SecToDateTime(InternetTimeInSecs,&InternetTime),
+* 	TimeReal = XRtcPsu_DateTimeToSec(InternetTime)
+* 	consecutively to arrive at TimeReal value.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	TimeReal is the actual realworld time generally an
+* 		network time / Internet time in seconds.
+*
+* @param	CrystalOscFreq is the Oscillator new frequency. Say, If the user
+* 		is going with the typical 32768Hz, then he inputs the same
+* 		frequency value.
+*
+* @return	None.
+*
+* @note		After Calculating the calibration register, user / application has to
+* 			call again CfgInitialize API to bring the new calibration into effect.
+*
+*****************************************************************************/
+void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
+		u32 CrystalOscFreq)
+{
+	u32 ReadTime, SetTime;
+	u32 Cprev,Fprev,Cnew,Fnew,Xf,Calibration;
+	Xil_AssertVoid(TimeReal != 0U);
+	Xil_AssertVoid(CrystalOscFreq != 0U);
+
+	ReadTime = XRtcPsu_GetCurrentTime(InstancePtr);
+	SetTime = XRtcPsu_GetLastSetTime(InstancePtr);
+	Calibration = XRtcPsu_GetCalibration(InstancePtr);
+	/*
+	 * When board gets reseted, Calibration value is zero
+	 * and Last setTime will be marked as 1st  second. This implies
+	 * CurrentTime to be in few seconds say something in tens. TimeReal will
+	 * be huge, say something in thousands. So to prevent such reset case, Cnew
+	 * and Fnew will not be calculated.
+	 */
+	if((Calibration == 0U) || (CrystalOscFreq != InstancePtr->OscillatorFreq)) {
+		Cnew = CrystalOscFreq - (u32)1;
+		Fnew = 0U;
+	} else {
+		Cprev = Calibration & XRTC_CALIB_RD_MAX_TCK_MASK;
+		Fprev = Calibration & XRTC_CALIB_RD_FRACTN_DATA_MASK;
+
+		Xf = ((ReadTime - SetTime) * ((Cprev+1U) + ((Fprev+1U)/16U))) / (TimeReal - SetTime);
+		Cnew = (u32)(Xf) - (u32)1;
+		Fnew = XRtcPsu_RoundOff((Xf - Cnew) * 16U) - (u32)1;
+	}
+
+	Calibration = (Fnew << XRTC_CALIB_RD_FRACTN_DATA_SHIFT) + Cnew;
+	Calibration |= XRTC_CALIB_RD_FRACTN_EN_MASK;
+
+	InstancePtr->CalibrationValue = Calibration;
+	InstancePtr->OscillatorFreq = CrystalOscFreq;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the seconds event status by reading
+* interrupt status register.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Returns 1 if a new second event is generated.Else 0..
+*
+* @note		This API is used in polled mode operation of RTC.
+* 			This also clears interrupt status seconds bit.
+*
+*****************************************************************************/
+u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr)
+{
+	u32 Status;
+
+	/* Loop the interrupt status register for Seconds Event */
+	if ((XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET) & (XRTC_INT_STS_SECS_MASK)) == 0U) {
+		Status = 0U;
+	} else {
+		/* Clear the interrupt status register */
+		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr +
+				XRTC_INT_STS_OFFSET, XRTC_INT_STS_SECS_MASK);
+		Status = 1U;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the alarm event status by reading
+* interrupt status register.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Returns 1 if the alarm event is generated.Else 0.
+*
+* @note		This API is used in polled mode operation of RTC.
+* 			This also clears interrupt status alarm bit.
+*
+*****************************************************************************/
+u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr)
+{
+	u32 Status;
+
+	/* Loop the interrupt status register for Alarm Event */
+	if ((XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET) & (XRTC_INT_STS_ALRM_MASK)) == 0U) {
+		Status = 0U;
+	} else {
+		/* Clear the interrupt status register */
+		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr +
+				XRTC_INT_STS_OFFSET, XRTC_INT_STS_ALRM_MASK);
+		Status = 1U;
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h
new file mode 100644
index 000000000..164ddf64a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h
@@ -0,0 +1,392 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xrtcpsu.h
+* @addtogroup rtcpsu_v1_0
+* @{
+* @details
+*
+* The Xilinx RTC driver component.  This component supports the Xilinx
+* RTC Controller. RTC Core and RTC controller are the two main important sub-
+* components for this RTC module. RTC core can run even in the battery powered
+* domain when the power from auxiliary source is down. Because of this, RTC core
+* latches the calibration,programmed time. This core interfaces with the crystal
+* oscillator and maintains current time in seconds.Calibration circuitry
+* calculates a second with maximum 1 PPM inaccuracy using a crystal oscillator
+* with arbitrary static inaccuracy. Core also responsible to maintain control
+* value used by the oscillator and power switching circuitry.
+*
+* RTC controller includes an APB interface responsible for register access with
+* in controller and core. It contains alarm generation logic including the alarm
+* register to hold alarm time in seconds.Interrupt management using Interrupt
+* status, Interrupt mask, Interrupt enable, Interrupt disable registers are
+* included to manage alarm and seconds interrupts. Address Slave error interrupts
+* are not being handled by this driver component.
+*
+* This driver supports the following features:
+* - Setting the RTC time.
+* - Setting the Alarm value that can be one-time alarm or a periodic alarm.
+* - Modifying the calibration value.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XRtcPsu_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XRtcPsu based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XRtcPsu_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* <b>Interrupts</b>
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - Alarm is generated.
+* - A new second is generated.
+*
+* The application can control which interrupts are enabled using the
+* XRtcPsu_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XRtcPsu_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XRtcPsu_SetHandler() function.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release
+* 1.1   kvn    09/25/15 Modify control register to enable battery
+*                       switching when vcc_psaux is not available.
+* 1.3   vak    04/25/16 Corrected the RTC read and write time logic(cr#948833).
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef XRTC_H_			/* prevent circular inclusions */
+#define XRTC_H_			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xrtcpsu_hw.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XRTCPSU_EVENT_ALARM_GEN		1U /**< Alarm generated event */
+#define XRTCPSU_EVENT_SECS_GEN		2U /**< A new second generated event */
+/*@}*/
+
+#define XRTCPSU_CRYSTAL_OSC_EN		(u32)1 << XRTC_CTL_OSC_SHIFT
+/**< Separate Mask for Crystal oscillator bit Enable */
+
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XRtcPsu_Handler) (void *CallBackRef, u32 Event);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XRtcPsu_Config;
+
+/**
+ * The XRtcPsu driver instance data. The user is required to allocate a
+ * variable of this type for the RTC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XRtcPsu_Config RtcConfig; 	/**< Device configuration */
+	u32 IsReady;				/**< Device is initialized and ready */
+	u32 PeriodicAlarmTime;
+	u8 IsPeriodicAlarm;
+	u32 OscillatorFreq;
+	u32 CalibrationValue;
+	XRtcPsu_Handler Handler;
+	void *CallBackRef;			/**< Callback reference for event handler */
+	u32 TimeUpdated;
+	u32 CurrTimeUpdated;
+} XRtcPsu;
+
+/**
+ * This typedef contains DateTime format structure.
+ */
+typedef struct {
+	u32 Year;
+	u32 Month;
+	u32 Day;
+	u32 Hour;
+	u32 Min;
+	u32 Sec;
+	u32 WeekDay;
+} XRtcPsu_DT;
+
+
+/************************* Variable Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XRTC_CALIBRATION_VALUE 0x00198231U
+#define XRTC_TYPICAL_OSC_FREQ 33330U
+
+/****************************************************************************/
+/**
+*
+* This macro updates the current time of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Time is the desired time for RTC in seconds.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XRtcPsu_SetTime(XRtcPsu *InstancePtr, u32 Time)
+*
+*****************************************************************************/
+#define XRtcPsu_WriteSetTime(InstancePtr,Time) \
+	XRtcPsu_WriteReg(((InstancePtr)->RtcConfig.BaseAddr + \
+				XRTC_SET_TIME_WR_OFFSET),(Time))
+
+/****************************************************************************/
+/**
+*
+* This macro returns the last set time of RTC device. Whenever a reset
+* happens, the last set time will be zeroth day first sec.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	The last set time in seconds.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_GetLastSetTime(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_GetLastSetTime(InstancePtr) \
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr + XRTC_SET_TIME_RD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro returns the calibration value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Calibration value for RTC.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_GetCalibration(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_GetCalibration(InstancePtr) \
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CALIB_RD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro returns the current time of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Current Time. This current time will be in seconds.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_ReadCurrentTime(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_ReadCurrentTime(InstancePtr) \
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CUR_TIME_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro sets the control register value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Value is the desired control register value for RTC.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XRtcPsu_SetControlRegister(XRtcPsu *InstancePtr, u32 Value)
+*
+*****************************************************************************/
+#define XRtcPsu_SetControlRegister(InstancePtr, Value) \
+	XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
+			XRTC_CTL_OFFSET,(Value))
+
+/****************************************************************************/
+/**
+*
+* This macro returns the safety check register value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Safety check register value.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_GetSafetyCheck(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_GetSafetyCheck(InstancePtr)	\
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_SFTY_CHK_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro sets the safety check register value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Value is a safety check value to be written in register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XRtcPsu_SetSafetyCheck(XRtcPsu *InstancePtr, u32 Value)
+*
+*****************************************************************************/
+#define XRtcPsu_SetSafetyCheck(InstancePtr, Value)	\
+	XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
+			XRTC_SFTY_CHK_OFFSET,(Value))
+
+/****************************************************************************/
+/**
+*
+* This macro resets the alarm register
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_ResetAlarm(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_ResetAlarm(InstancePtr) \
+		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
+				XRTC_ALRM_OFFSET,XRTC_ALRM_RSTVAL)
+
+/****************************************************************************/
+/**
+*
+* This macro rounds off the given number
+*
+* @param	Number is the one that needs to be rounded off..
+*
+* @return	The rounded off value of the input number.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_RoundOff(float Number)
+*
+*****************************************************************************/
+#define XRtcPsu_RoundOff(Number) \
+	(u32)(((Number) < (u32)0) ? ((Number) - (u32)0.5) : ((Number) + (u32)0.5))
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xrtcpsu.c */
+s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic);
+void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt);
+u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt);
+void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
+		u32 CrystalOscFreq);
+u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr);
+u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr);
+u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr);
+void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time);
+
+/* interrupt functions in xrtcpsu_intr.c */
+void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask);
+void XRtcPsu_ClearInterruptMask(XRtcPsu *InstancePtr, u32 Mask);
+void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr);
+void XRtcPsu_SetHandler(XRtcPsu *InstancePtr, XRtcPsu_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* Functions in xrtcpsu_selftest.c */
+s32 XRtcPsu_SelfTest(XRtcPsu *InstancePtr);
+
+/* Functions in xrtcpsu_sinit.c */
+XRtcPsu_Config *XRtcPsu_LookupConfig(u16 DeviceId);
+
+
+#endif /* XRTC_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c
new file mode 100644
index 000000000..5913cd8d4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xrtcpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XRtcPsu_Config XRtcPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_RTC_DEVICE_ID,
+		XPAR_PSU_RTC_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h
new file mode 100644
index 000000000..532ef7e3c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h
@@ -0,0 +1,362 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu_hw.h
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xrtcpsu.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a kvn	  04/21/15 First release
+* 1.1   kvn   09/25/15 Modify control register to enable battery
+*                      switching when vcc_psaux is not available.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XRTC_HW_H_		/* prevent circular inclusions */
+#define XRTC_HW_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * Xrtc Base Address
+ */
+#define XRTC_BASEADDR      0xFFA60000U
+
+/**
+ * Register: XrtcSetTimeWr
+ */
+#define XRTC_SET_TIME_WR_OFFSET    0x00000000U
+#define XRTC_SET_TIME_WR_RSTVAL   0x00000000U
+
+#define XRTC_SET_TIME_WR_VAL_SHIFT   0U
+#define XRTC_SET_TIME_WR_VAL_WIDTH   32U
+#define XRTC_SET_TIME_WR_VAL_MASK    0xffffffffU
+#define XRTC_SET_TIME_WR_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcSetTimeRd
+ */
+#define XRTC_SET_TIME_RD_OFFSET    0x00000004U
+#define XRTC_SET_TIME_RD_RSTVAL   0x00000000U
+
+#define XRTC_SET_TIME_RD_VAL_SHIFT   0U
+#define XRTC_SET_TIME_RD_VAL_WIDTH   32U
+#define XRTC_SET_TIME_RD_VAL_MASK    0xffffffffU
+#define XRTC_SET_TIME_RD_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCalibWr
+ */
+#define XRTC_CALIB_WR_OFFSET    0x00000008U
+#define XRTC_CALIB_WR_RSTVAL   0x00000000U
+
+#define XRTC_CALIB_WR_FRACTN_EN_SHIFT   20U
+#define XRTC_CALIB_WR_FRACTN_EN_WIDTH   1U
+#define XRTC_CALIB_WR_FRACTN_EN_MASK    0x00100000U
+#define XRTC_CALIB_WR_FRACTN_EN_DEFVAL  0x0U
+
+#define XRTC_CALIB_WR_FRACTN_DATA_SHIFT   16U
+#define XRTC_CALIB_WR_FRACTN_DATA_WIDTH   4U
+#define XRTC_CALIB_WR_FRACTN_DATA_MASK    0x000f0000U
+#define XRTC_CALIB_WR_FRACTN_DATA_DEFVAL  0x0U
+
+#define XRTC_CALIB_WR_MAX_TCK_SHIFT   0U
+#define XRTC_CALIB_WR_MAX_TCK_WIDTH   16U
+#define XRTC_CALIB_WR_MAX_TCK_MASK    0x0000ffffU
+#define XRTC_CALIB_WR_MAX_TCK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCalibRd
+ */
+#define XRTC_CALIB_RD_OFFSET    0x0000000CU
+#define XRTC_CALIB_RD_RSTVAL   0x00000000U
+
+#define XRTC_CALIB_RD_FRACTN_EN_SHIFT   20U
+#define XRTC_CALIB_RD_FRACTN_EN_WIDTH   1U
+#define XRTC_CALIB_RD_FRACTN_EN_MASK    0x00100000U
+#define XRTC_CALIB_RD_FRACTN_EN_DEFVAL  0x0U
+
+#define XRTC_CALIB_RD_FRACTN_DATA_SHIFT   16U
+#define XRTC_CALIB_RD_FRACTN_DATA_WIDTH   4U
+#define XRTC_CALIB_RD_FRACTN_DATA_MASK    0x000f0000U
+#define XRTC_CALIB_RD_FRACTN_DATA_DEFVAL  0x0U
+
+#define XRTC_CALIB_RD_MAX_TCK_SHIFT   0U
+#define XRTC_CALIB_RD_MAX_TCK_WIDTH   16U
+#define XRTC_CALIB_RD_MAX_TCK_MASK    0x0000ffffU
+#define XRTC_CALIB_RD_MAX_TCK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCurTime
+ */
+#define XRTC_CUR_TIME_OFFSET    0x00000010U
+#define XRTC_CUR_TIME_RSTVAL   0x00000000U
+
+#define XRTC_CUR_TIME_VAL_SHIFT   0U
+#define XRTC_CUR_TIME_VAL_WIDTH   32U
+#define XRTC_CUR_TIME_VAL_MASK    0xffffffffU
+#define XRTC_CUR_TIME_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCurTck
+ */
+#define XRTC_CUR_TCK_OFFSET    0x00000014U
+#define XRTC_CUR_TCK_RSTVAL   0x00000000U
+
+#define XRTC_CUR_TCK_VAL_SHIFT   0U
+#define XRTC_CUR_TCK_VAL_WIDTH   16U
+#define XRTC_CUR_TCK_VAL_MASK    0x0000ffffU
+#define XRTC_CUR_TCK_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAlrm
+ */
+#define XRTC_ALRM_OFFSET    0x00000018U
+#define XRTC_ALRM_RSTVAL   0x00000000U
+
+#define XRTC_ALRM_VAL_SHIFT   0U
+#define XRTC_ALRM_VAL_WIDTH   32U
+#define XRTC_ALRM_VAL_MASK    0xffffffffU
+#define XRTC_ALRM_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcIntSts
+ */
+#define XRTC_INT_STS_OFFSET    0x00000020U
+#define XRTC_INT_STS_RSTVAL   0x00000000U
+
+#define XRTC_INT_STS_ALRM_SHIFT   1U
+#define XRTC_INT_STS_ALRM_WIDTH   1U
+#define XRTC_INT_STS_ALRM_MASK    0x00000002U
+#define XRTC_INT_STS_ALRM_DEFVAL  0x0U
+
+#define XRTC_INT_STS_SECS_SHIFT   0U
+#define XRTC_INT_STS_SECS_WIDTH   1U
+#define XRTC_INT_STS_SECS_MASK    0x00000001U
+#define XRTC_INT_STS_SECS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcIntMsk
+ */
+#define XRTC_INT_MSK_OFFSET    0x00000024U
+#define XRTC_INT_MSK_RSTVAL   0x00000003U
+
+#define XRTC_INT_MSK_ALRM_SHIFT   1U
+#define XRTC_INT_MSK_ALRM_WIDTH   1U
+#define XRTC_INT_MSK_ALRM_MASK    0x00000002U
+#define XRTC_INT_MSK_ALRM_DEFVAL  0x1U
+
+#define XRTC_INT_MSK_SECS_SHIFT   0U
+#define XRTC_INT_MSK_SECS_WIDTH   1U
+#define XRTC_INT_MSK_SECS_MASK    0x00000001U
+#define XRTC_INT_MSK_SECS_DEFVAL  0x1U
+
+/**
+ * Register: XrtcIntEn
+ */
+#define XRTC_INT_EN_OFFSET    0x00000028U
+#define XRTC_INT_EN_RSTVAL   0x00000000U
+
+#define XRTC_INT_EN_ALRM_SHIFT   1U
+#define XRTC_INT_EN_ALRM_WIDTH   1U
+#define XRTC_INT_EN_ALRM_MASK    0x00000002U
+#define XRTC_INT_EN_ALRM_DEFVAL  0x0U
+
+#define XRTC_INT_EN_SECS_SHIFT   0U
+#define XRTC_INT_EN_SECS_WIDTH   1U
+#define XRTC_INT_EN_SECS_MASK    0x00000001U
+#define XRTC_INT_EN_SECS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcIntDis
+ */
+#define XRTC_INT_DIS_OFFSET    0x0000002CU
+#define XRTC_INT_DIS_RSTVAL   0x00000000U
+
+#define XRTC_INT_DIS_ALRM_SHIFT   1U
+#define XRTC_INT_DIS_ALRM_WIDTH   1U
+#define XRTC_INT_DIS_ALRM_MASK    0x00000002U
+#define XRTC_INT_DIS_ALRM_DEFVAL  0x0U
+
+#define XRTC_INT_DIS_SECS_SHIFT   0U
+#define XRTC_INT_DIS_SECS_WIDTH   1U
+#define XRTC_INT_DIS_SECS_MASK    0x00000001U
+#define XRTC_INT_DIS_SECS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAddErr
+ */
+#define XRTC_ADD_ERR_OFFSET    0x00000030U
+#define XRTC_ADD_ERR_RSTVAL   0x00000000U
+
+#define XRTC_ADD_ERR_STS_SHIFT   0U
+#define XRTC_ADD_ERR_STS_WIDTH   1U
+#define XRTC_ADD_ERR_STS_MASK    0x00000001U
+#define XRTC_ADD_ERR_STS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAddErrIntMsk
+ */
+#define XRTC_ADD_ERR_INT_MSK_OFFSET    0x00000034U
+#define XRTC_ADD_ERR_INT_MSK_RSTVAL   0x00000001U
+
+#define XRTC_ADD_ERR_INT_MSK_SHIFT   0U
+#define XRTC_ADD_ERR_INT_MSK_WIDTH   1U
+#define XRTC_ADD_ERR_INT_MSK_MASK    0x00000001U
+#define XRTC_ADD_ERR_INT_MSK_DEFVAL  0x1U
+
+/**
+ * Register: XrtcAddErrIntEn
+ */
+#define XRTC_ADD_ERR_INT_EN_OFFSET    0x00000038U
+#define XRTC_ADD_ERR_INT_EN_RSTVAL   0x00000000U
+
+#define XRTC_ADD_ERR_INT_EN_MSK_SHIFT   0U
+#define XRTC_ADD_ERR_INT_EN_MSK_WIDTH   1U
+#define XRTC_ADD_ERR_INT_EN_MSK_MASK    0x00000001U
+#define XRTC_ADD_ERR_INT_EN_MSK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAddErrIntDis
+ */
+#define XRTC_ADD_ERR_INT_DIS_OFFSET    0x0000003CU
+#define XRTC_ADD_ERR_INT_DIS_RSTVAL   0x00000000U
+
+#define XRTC_ADD_ERR_INT_DIS_MSK_SHIFT   0U
+#define XRTC_ADD_ERR_INT_DIS_MSK_WIDTH   1U
+#define XRTC_ADD_ERR_INT_DIS_MSK_MASK    0x00000001U
+#define XRTC_ADD_ERR_INT_DIS_MSK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCtl
+ */
+#define XRTC_CTL_OFFSET    0x00000040U
+#define XRTC_CTL_RSTVAL   0x01000000U
+
+#define XRTC_CTL_BATTERY_EN_SHIFT   31U
+#define XRTC_CTL_BATTERY_EN_WIDTH   1U
+#define XRTC_CTL_BATTERY_EN_MASK    0x80000000U
+#define XRTC_CTL_BATTERY_EN_DEFVAL  0x0U
+
+#define XRTC_CTL_OSC_SHIFT   24U
+#define XRTC_CTL_OSC_WIDTH   4U
+#define XRTC_CTL_OSC_MASK    0x0f000000U
+#define XRTC_CTL_OSC_DEFVAL  0x1U
+
+#define XRTC_CTL_SLVERR_EN_SHIFT   0U
+#define XRTC_CTL_SLVERR_EN_WIDTH   1U
+#define XRTC_CTL_SLVERR_EN_MASK    0x00000001U
+#define XRTC_CTL_SLVERR_EN_DEFVAL  0x0U
+
+/**
+ * Register: XrtcSftyChk
+ */
+#define XRTC_SFTY_CHK_OFFSET    0x00000050U
+#define XRTC_SFTY_CHK_RSTVAL   0x00000000U
+
+#define XRTC_SFTY_CHK_REG_SHIFT   0U
+#define XRTC_SFTY_CHK_REG_WIDTH   32U
+#define XRTC_SFTY_CHK_REG_MASK    0xffffffffU
+#define XRTC_SFTY_CHK_REG_DEFVAL  0x0U
+
+/**
+ * Register: XrtcEco
+ */
+#define XRTC_ECO_OFFSET    0x00000060U
+#define XRTC_ECO_RSTVAL   0x00000000U
+
+#define XRTC_ECO_REG_SHIFT   0U
+#define XRTC_ECO_REG_WIDTH   32U
+#define XRTC_ECO_REG_MASK    0xffffffffU
+#define XRTC_ECO_REG_DEFVAL  0x0U
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the RTC device.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XRtcPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the RTC device.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XRtcPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XRTC_HW_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c
new file mode 100644
index 000000000..89d3cd990
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c
@@ -0,0 +1,242 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu_intr.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This file contains functions related to RTC interrupt handling.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release
+* 1.3   vak    04/25/16 Changed the XRtcPsu_InterruptHandler() for updating RTC
+*                       read and write time logic(cr#948833).
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xrtcpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	Mask contains the interrupts to be enabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask)
+{
+	/*
+	 * Clear the Status register to be sure of no pending interrupts.
+	 * Writing mask values to interrupt bits as it is a WTC register.
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
+			((u32)XRTC_INT_STS_ALRM_MASK | (u32)XRTC_INT_STS_SECS_MASK));
+
+	/*
+	 * XRTC_INT_MSK_RSTVAL contains the valid interrupts
+	 * for the RTC device. The AND operation on Mask makes sure one
+	 * of the valid bits are only set.
+	 */
+
+	/* Write the mask to the IER Register */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_INT_EN_OFFSET,
+					(Mask & (u32)XRTC_INT_MSK_RSTVAL));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	Mask contains the interrupts to be disabled.
+*		A '1' enables an interrupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_ClearInterruptMask(XRtcPsu *InstancePtr, u32 Mask)
+{
+	/*
+	 * XRTC_INT_MSK_RSTVAL contains the valid interrupts
+	 * for the RTC device. The AND operation on mask makes sure one
+	 * of the valid bits are only cleared.
+	 */
+
+	/* Write the Mask to the IDR register */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_INT_DIS_OFFSET,
+					(Mask & (u32)XRTC_INT_MSK_RSTVAL));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XRtcPsu_SetHandler(XRtcPsu *InstancePtr, XRtcPsu_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active.
+	 */
+	IsrStatus = ~(XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_MSK_OFFSET));
+
+	IsrStatus &= XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET);
+
+	/*
+	 * Clear the interrupt status to allow future
+	 * interrupts before this generated interrupt is serviced.
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET, IsrStatus);
+
+	/* Handle the generated interrupts appropriately. */
+
+	/* Alarm interrupt */
+	if((IsrStatus & XRTC_INT_STS_ALRM_MASK) != (u32)0) {
+
+		if(InstancePtr->IsPeriodicAlarm != 0U) {
+			XRtcPsu_SetAlarm(InstancePtr,
+					(XRtcPsu_GetCurrentTime(InstancePtr)+InstancePtr->PeriodicAlarmTime),1U);
+		}
+
+		/*
+		 * Call the application handler to indicate that there is an
+		 * alarm interrupt. If the application cares about this alarm,
+		 * it will act accordingly through its own handler.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XRTCPSU_EVENT_ALARM_GEN);
+	}
+
+	/* Seconds interrupt */
+	if((IsrStatus & XRTC_INT_STS_SECS_MASK) != (u32)0) {
+		/* Set the CurrTimeUpdated flag to 1 */
+		InstancePtr->CurrTimeUpdated = 1;
+
+		if(InstancePtr->TimeUpdated == (u32)1) {
+			/* Clear the TimeUpdated */
+			InstancePtr->TimeUpdated = (u32)0;
+		}
+
+		/*
+		 * Call the application handler to indicate that there is an
+		 * seconds interrupt. If the application cares about this seconds
+		 * interrupt, it will act accordingly through its own handler.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XRTCPSU_EVENT_SECS_GEN);
+	}
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c
new file mode 100644
index 000000000..67c562c64
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xrtcpsu_selftest.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This file contains the self-test functions for the XRtcPsu driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xrtcpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test writes reset value into safety check register and read backs the same.
+* If mismatch offers, returns the failure.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XRtcPsu_SelfTest(XRtcPsu *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 SafetyCheck;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write the reset value in safety check register and
+	 * try reading back. If mismatch happens, return failure.
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_SFTY_CHK_OFFSET,
+			XRTC_SFTY_CHK_RSTVAL);
+	SafetyCheck = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_SFTY_CHK_OFFSET);
+
+	if (SafetyCheck != XRTC_SFTY_CHK_RSTVAL) {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c
new file mode 100644
index 000000000..d3a8b7dfc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu_sinit.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This file contains the implementation of the XRtcPsu driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xrtcpsu.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XRtcPsu_Config XRtcPsu_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XRtcPsu_ConfigTable[] contains the configuration information for
+* each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XRtcPsu_Config *XRtcPsu_LookupConfig(u16 DeviceId)
+{
+	XRtcPsu_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XRTCPSU_NUM_INSTANCES; Index++) {
+		if (XRtcPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XRtcPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XRtcPsu_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile
deleted file mode 100644
index 04867a484..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner scugic_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling scugic"
-
-scugic_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: scugic_includes
-
-scugic_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c
deleted file mode 100644
index 1806274c7..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c
+++ /dev/null
@@ -1,769 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic.c
-* @addtogroup scugic_v3_1
-* @{
-*
-* Contains required functions for the XScuGic driver for the Interrupt
-* Controller. See xscugic.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a drg  01/19/10 First release
-* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
-*		      "Config" entry is now made as pointer in the XScuGic
-*		      structure, necessary changes are made.
-*		      The HandlerTable can now be populated through the low
-*		      level routine XScuGic_RegisterHandler added in this
-*		      release. Hence necessary checks are added not to
-*		      overwrite the HandlerTable entriesin function
-*		      XScuGic_CfgInitialize.
-* 1.03a srt  02/27/13 Added APIs
-*			- XScuGic_SetPriTrigTypeByDistAddr()
-*			- XScuGic_GetPriTrigTypeByDistAddr()
-* 		      Removed Offset calculation macros, defined in _hw.h
-*		      (CR 702687)
-*			  Added support to direct interrupts to the appropriate CPU. Earlier
-*			  interrupts were directed to CPU1 (hard coded). Now depending
-*			  upon the CPU selected by the user (xparameters.h), interrupts
-*			  will be directed to the relevant CPU. This fixes CR 699688.
-*
-* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-*			  This is fix for CR#705621.
-* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
-*			  in function XScuGic_CfgInitialize is removed as it was
-*		      a bug.
-* 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.01	pkp	 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
-*			  target CPU mapping
-* 3.02	pkp	 11/09/15 Modified DistributorInit function for AMP case to add
-*					  the current cpu to interrupt processor targets registers
-* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
-*			  distributor is left uninitialized for Zynq AMP. It is assumed
-*             that the distributor will be initialized by Linux master. However
-*             for CortexR5 case, the earlier code is left unchanged where the
-*             the interrupt processor target registers in the distributor is
-*             initialized with the corresponding CPU ID on which the application
-*             built over the scugic driver runs.
-*             These changes fix CR#937243.
-*
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void *CallBackRef);
-
-/*****************************************************************************/
-/**
-*
-* DistributorInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority and target CPU
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-* @param	CpuID is the Cpu ID to be initialized.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
-{
-	u32 Int_Id;
-	u32 LocalCpuID = CpuID;
-
-#if USE_AMP==1
-	#warning "Building GIC for AMP"
-#ifdef ARMR5
-    u32 RegValue;
-
-	/*
-	 * The overall distributor should not be initialized in AMP case where
-	 * another CPU is taking care of it.
-	 */
-	LocalCpuID |= LocalCpuID << 8U;
-	LocalCpuID |= LocalCpuID << 16U;
-	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
-		RegValue = XScuGic_DistReadReg(InstancePtr,
-						XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-		RegValue |= LocalCpuID;
-		XScuGic_DistWriteReg(InstancePtr,
-				     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
-				     RegValue);
-	}
-#endif
-	return;
-#endif
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
-
-	/*
-	 * Set the security domains in the int_security registers for
-	 * non-secure interrupts
-	 * All are secure, so leave at the default. Set to 1 for non-secure
-	 * interrupts.
-	 */
-
-	/*
-	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
-	 */
-
-	/*
-	 * 1. The trigger mode in the int_config register
-	 * Only write to the SPI interrupts, so start at 32
-	 */
-	for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
-		/*
-		 * Each INT_ID uses two bits, or 16 INT_ID per register
-		 * Set them all to be level sensitive, active HIGH.
-		 */
-		XScuGic_DistWriteReg(InstancePtr,
-					XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
-					0U);
-	}
-
-
-#define DEFAULT_PRIORITY    0xa0a0a0a0U
-	for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
-		/*
-		 * 2. The priority using int the priority_level register
-		 * The priority_level and spi_target registers use one byte per
-		 * INT_ID.
-		 * Write a default value that can be changed elsewhere.
-		 */
-		XScuGic_DistWriteReg(InstancePtr,
-					XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
-					DEFAULT_PRIORITY);
-	}
-
-	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
-		/*
-		 * 3. The CPU interface in the spi_target register
-		 * Only write to the SPI interrupts, so start at 32
-		 */
-		LocalCpuID |= LocalCpuID << 8U;
-		LocalCpuID |= LocalCpuID << 16U;
-
-		XScuGic_DistWriteReg(InstancePtr,
-				     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
-				     LocalCpuID);
-	}
-
-	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
-		/*
-		 * 4. Enable the SPI using the enable_set register. Leave all
-		 * disabled for now.
-		 */
-		XScuGic_DistWriteReg(InstancePtr,
-		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
-			0xFFFFFFFFU);
-
-	}
-
-	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
-						XSCUGIC_EN_INT_MASK);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* CPUInitialize initializes the CPU Interface of the GIC. The initialization entails:
-*
-*	- Set the priority of the CPU
-*	- Enable the CPU interface
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static void CPUInitialize(XScuGic *InstancePtr)
-{
-	/*
-	 * Program the priority mask of the CPU using the Priority mask register
-	 */
-	XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
-
-
-	/*
-	 * If the CPU operates in both security domains, set parameters in the
-	 * control_s register.
-	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
-	 * 2. Program the AckCtl bit
-	 * 3. Program the SBPR bit to select the binary pointer behavior
-	 * 4. Set EnableS = 1 to enable secure interrupts
-	 * 5. Set EnbleNS = 1 to enable non secure interrupts
-	 */
-
-	/*
-	 * If the CPU operates only in the secure domain, setup the
-	 * control_s register.
-	 * 1. Set FIQen=1,
-	 * 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
-	 * Only enable the IRQ output unless secure interrupts are needed.
-	 */
-	XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* CfgInitialize a specific interrupt controller instance/driver. The
-* initialization entails:
-*
-* - Initialize fields of the XScuGic structure
-* - Initial vector table with stub function calls
-* - All interrupt sources are disabled
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-* @param	ConfigPtr is a pointer to a config table for the particular
-*		device this driver is associated with.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the address
-*		mapping from EffectiveAddr to the device physical base address
-*		unchanged once this function is invoked. Unexpected errors may
-*		occur if the address mapping changes after this function is
-*		called. If address translation is not used, use
-*		Config->BaseAddress for this parameters, passing the physical
-*		address instead.
-*
-* @return
-*		- XST_SUCCESS if initialization was successful
-*
-* @note		None.
-*
-******************************************************************************/
-s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
-				XScuGic_Config *ConfigPtr,
-				u32 EffectiveAddr)
-{
-	u32 Int_Id;
-	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
-	(void) EffectiveAddr;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
-
-		InstancePtr->IsReady = 0;
-		InstancePtr->Config = ConfigPtr;
-
-
-		for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id++) {
-			/*
-			* Initalize the handler to point to a stub to handle an
-			* interrupt which has not been connected to a handler. Only
-			* initialize it if the handler is 0 which means it was not
-			* initialized statically by the tools/user. Set the callback
-			* reference to this instance so that unhandled interrupts
-			* can be tracked.
-			*/
-			if 	((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) {
-				InstancePtr->Config->HandlerTable[Int_Id].Handler =
-									StubHandler;
-			}
-			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
-								InstancePtr;
-		}
-
-		DistributorInit(InstancePtr, Cpu_Id);
-		CPUInitialize(InstancePtr);
-
-		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-	}
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Int_Id of the interrupt source and the
-* associated handler that is to run when the interrupt is recognized. The
-* argument provided in this call as the Callbackref is used as the argument
-* for the handler when it is called.
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-* @param	Int_Id contains the ID of the interrupt source and should be
-*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-* @param	Handler to the handler for that interrupt.
-* @param	CallBackRef is the callback reference, usually the instance
-*		pointer of the connecting driver.
-*
-* @return
-*
-*		- XST_SUCCESS if the handler was connected correctly.
-*
-* @note
-*
-* WARNING: The handler provided as an argument will overwrite any handler
-* that was previously connected.
-*
-****************************************************************************/
-s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
-                      Xil_InterruptHandler Handler, void *CallBackRef)
-{
-	/*
-	 * Assert the arguments
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertNonvoid(Handler != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * The Int_Id is used as an index into the table to select the proper
-	 * handler
-	 */
-	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
-	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Updates the interrupt table with the Null Handler and NULL arguments at the
-* location pointed at by the Int_Id. This effectively disconnects that interrupt
-* source from any handler. The interrupt is disabled also.
-*
-* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
-* @param	Int_Id contains the ID of the interrupt source and should
-*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
-{
-	u32 Mask;
-
-	/*
-	 * Assert the arguments
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * The Int_Id is used to create the appropriate mask for the
-	 * desired bit position. Int_Id currently limited to 0 - 31
-	 */
-	Mask = 0x00000001U << (Int_Id % 32U);
-
-	/*
-	 * Disable the interrupt such that it won't occur while disconnecting
-	 * the handler, only disable the specified interrupt id without modifying
-	 * the other interrupt ids
-	 */
-	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
-						((Int_Id / 32U) * 4U), Mask);
-
-	/*
-	 * Disconnect the handler and connect a stub, the callback reference
-	 * must be set to this instance to allow unhandled interrupts to be
-	 * tracked
-	 */
-	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
-	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Enables the interrupt source provided as the argument Int_Id. Any pending
-* interrupt condition for the specified Int_Id will occur after this function is
-* called.
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-* @param	Int_Id contains the ID of the interrupt source and should be
-*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
-{
-	u32 Mask;
-
-	/*
-	 * Assert the arguments
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * The Int_Id is used to create the appropriate mask for the
-	 * desired bit position. Int_Id currently limited to 0 - 31
-	 */
-	Mask = 0x00000001U << (Int_Id % 32U);
-
-	/*
-	 * Enable the selected interrupt source by setting the
-	 * corresponding bit in the Enable Set register.
-	 */
-	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
-						((Int_Id / 32U) * 4U), Mask);
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupt source provided as the argument Int_Id such that the
-* interrupt controller will not cause interrupts for the specified Int_Id. The
-* interrupt controller will continue to hold an interrupt condition for the
-* Int_Id, but will not cause an interrupt.
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-* @param	Int_Id contains the ID of the interrupt source and should be
-*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
-{
-	u32 Mask;
-
-	/*
-	 * Assert the arguments
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * The Int_Id is used to create the appropriate mask for the
-	 * desired bit position. Int_Id currently limited to 0 - 31
-	 */
-	Mask = 0x00000001U << (Int_Id % 32U);
-
-	/*
-	 * Disable the selected interrupt source by setting the
-	 * corresponding bit in the IDR.
-	 */
-	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
-						((Int_Id / 32U) * 4U), Mask);
-}
-
-/*****************************************************************************/
-/**
-*
-* Allows software to simulate an interrupt in the interrupt controller.  This
-* function will only be successful when the interrupt controller has been
-* started in simulation mode.  A simulated interrupt allows the interrupt
-* controller to be tested without any device to drive an interrupt input
-* signal into it.
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-* @param	Int_Id is the software interrupt ID to simulate an interrupt.
-* @param	Cpu_Id is the list of CPUs to send the interrupt.
-*
-* @return
-*
-* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
-* simulated
-*
-* @note		None.
-*
-******************************************************************************/
-s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
-{
-	u32 Mask;
-
-	/*
-	 * Assert the arguments
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Int_Id <= 15U) ;
-	Xil_AssertNonvoid(Cpu_Id <= 255U) ;
-
-
-	/*
-	 * The Int_Id is used to create the appropriate mask for the
-	 * desired interrupt. Int_Id currently limited to 0 - 15
-	 * Use the target list for the Cpu ID.
-	 */
-	Mask = ((Cpu_Id << 16U) | Int_Id) &
-		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
-
-	/*
-	 * Write to the Software interrupt trigger register. Use the appropriate
-	 * CPU Int_Id.
-	 */
-	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
-
-	/* Indicate the interrupt was successfully simulated */
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* A stub for the asynchronous callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param	CallBackRef is a pointer to the upper layer callback reference
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-static void StubHandler(void *CallBackRef) {
-	/*
-	 * verify that the inputs are valid
-	 */
-	Xil_AssertVoid(CallBackRef != NULL);
-
-	/*
-	 * Indicate another unhandled interrupt for stats
-	 */
-	((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Int_Id is the IRQ source number to modify
-* @param	Priority is the new priority for the IRQ source. 0 is highest
-* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
-*			supported with a step of 8. Hence the supported priorities are
-*			0, 8, 16, 32, 40 ..., 248.
-* @param	Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI    Read Only    b10 always
-* PPI    Read Only    depending on how the PPIs are configured.
-*                    b01    Active HIGH level sensitive
-*                    b11 Rising edge sensitive
-* SPI                LSB is read only.
-*                    b01    Active HIGH level sensitive
-*                    b11 Rising edge sensitive/
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
-					u8 Priority, u8 Trigger)
-{
-	u32 RegValue;
-	u8 LocalPriority;
-	LocalPriority = Priority;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
-	Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
-
-	/*
-	 * Determine the register to write to using the Int_Id.
-	 */
-	RegValue = XScuGic_DistReadReg(InstancePtr,
-			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
-	/*
-	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
-	 * means the number of priority levels supported are 32 and they are
-	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
-	 * The lower order 3 bits are masked before putting it in the register.
-	 */
-	LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
-	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
-	/*
-	 * Write the value back to the register.
-	 */
-	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
-				RegValue);
-
-	/*
-	 * Determine the register to write to using the Int_Id.
-	 */
-	RegValue = XScuGic_DistReadReg(InstancePtr,
-			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
-	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
-	/*
-	 * Write the value back to the register.
-	 */
-	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
-				RegValue);
-
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Int_Id is the IRQ source number to modify
-* @param	Priority is a pointer to the value of the priority of the IRQ
-*		source. This is a return value.
-* @param	Trigger is pointer to the value of the trigger of the IRQ
-*		source. This is a return value.
-*
-* @return	None.
-*
-* @note		None
-*
-*****************************************************************************/
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
-					u8 *Priority, u8 *Trigger)
-{
-	u32 RegValue;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertVoid(Priority != NULL);
-	Xil_AssertVoid(Trigger != NULL);
-
-	/*
-	 * Determine the register to read to using the Int_Id.
-	 */
-	RegValue = XScuGic_DistReadReg(InstancePtr,
-	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue = RegValue >> ((Int_Id%4U)*8U);
-	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
-	/*
-	 * Determine the register to read to using the Int_Id.
-	 */
-	RegValue = XScuGic_DistReadReg(InstancePtr,
-	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue = RegValue >> ((Int_Id%16U)*2U);
-
-	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-/****************************************************************************/
-/**
-* Sets the target CPU for the interrupt of a peripheral
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Cpu_Id is a CPU number for which the interrupt has to be targeted
-* @param	Int_Id is the IRQ source number to modify
-*
-* @return	None.
-*
-* @note		None
-*
-*****************************************************************************/
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
-{
-	u32 RegValue, Offset;
-	RegValue = XScuGic_DistReadReg(InstancePtr,
-			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
-	Offset =  (Int_Id & 0x3);
-
-	RegValue = (RegValue | (~(0xFF << (Offset*8))) );
-	RegValue |= ((Cpu_Id) << (Offset*8));
-
-	XScuGic_DistWriteReg(InstancePtr,
-						 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
-						 RegValue);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h
deleted file mode 100644
index d8efce92e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic.h
-* @addtogroup scugic_v3_1
-* @{
-* @details
-*
-* The generic interrupt controller driver component.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 1 and 31 inclusive with
-* default of 1 being the highest priority interrupt source. The priorities
-* of the various sources can be dynamically altered as needed through
-* hardware configuration.
-*
-* The generic interrupt controller supports the following
-* features:
-*
-*   - specific individual interrupt enabling/disabling
-*   - specific individual interrupt acknowledging
-*   - attaching specific callback function to handle interrupt source
-*   - assigning desired priority to interrupt source if default is not
-*     acceptable.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xscugic_intr.c.
-*
-* This driver is intended to be RTOS and processor independent.  It works with
-* physical addresses only.  Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <b>Interrupt Vector Tables</b>
-*
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table. The user should populate the
-* vector table with handlers and callbacks at run-time using the
-* XScuGic_Connect() and XScuGic_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an
-* argument to be passed to the handler when an interrupt occurs.  The
-* user must use XScuGic_Connect() when the interrupt handler takes an
-* argument other than the base address.
-*
-* <b>Nested Interrupts Processing</b>
-*
-* Nested interrupts are not supported by this driver.
-*
-* NOTE:
-* The generic interrupt controller is not a part of the snoop control unit
-* as indicated by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg  01/19/00 First release
-* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
-*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
-*		      moved to XScuGic_Config structure from XScuGic structure.
-*
-*		      The "Config" entry in XScuGic structure is made as
-*		      pointer for better efficiency.
-*
-*		      A new file named as xscugic_hw.c is now added. It is
-*		      to implement low level driver routines without using
-*		      any xscugic instance pointer. They are useful when the
-*		      user wants to use xscugic through device id or
-*		      base address. The driver routines provided are explained
-*		      below.
-*		      XScuGic_DeviceInitialize that takes device id as
-*		      argument and initializes the device (without calling
-*		      XScuGic_CfgInitialize).
-*		      XScuGic_DeviceInterruptHandler that takes device id
-*		      as argument and calls appropriate handlers from the
-*		      HandlerTable.
-*		      XScuGic_RegisterHandler that registers a new handler
-*		      by taking xscugic hardware base address as argument.
-*		      LookupConfigByBaseAddress is used to return the
-*		      corresponding config structure from XScuGic_ConfigTable
-*		      based on the scugic base address passed.
-* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
-*		      structure.
-* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-*		      *_hw.h
-*		      Added APIs
-*			- XScuGic_SetPriTrigTypeByDistAddr()
-*			- XScuGic_GetPriTrigTypeByDistAddr()
-*		      (CR 702687)
-*			Added support to direct interrupts to the appropriate CPU. Earlier
-*			  interrupts were directed to CPU1 (hard coded). Now depending
-*			  upon the CPU selected by the user (xparameters.h), interrupts
-*			  will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-*			  This is fix for CR#705621.
-* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
-*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0   adk  12/10/13 Updated as per the New Tcl API's
-* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
-*			  distributor is left uninitialized for Zynq AMP. It is assumed
-*             that the distributor will be initialized by Linux master. However
-*             for CortexR5 case, the earlier code is left unchanged where the
-*             the interrupt processor target registers in the distributor is
-*             initialized with the corresponding CPU ID on which the application
-*             built over the scugic driver runs.
-*             These changes fix CR#937243.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
-	Xil_InterruptHandler Handler;
-	void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
-	u16 DeviceId;		/**< Unique ID  of device */
-	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
-	u32 DistBaseAddress;	/**< Distributor Register base address */
-	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
-				 Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
-	XScuGic_Config *Config;  /**< Configuration table entry */
-	u32 IsReady;		 /**< Device is initialized and ready */
-	u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be written
-* @param    Data is the 32-bit value to write to the register
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
-					((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be read
-*
-* @return   The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
-	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be written
-* @param    Data is the 32-bit value to write to the register
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
-					((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be read
-*
-* @return   The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
-			Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
-							u32 EffectiveAddr);
-
-s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
-					u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
-					u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32  XScuGic_SelfTest(XScuGic *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif            /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c
deleted file mode 100644
index 2457f6b23..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c
+++ /dev/null
@@ -1,56 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xscugic.h"
-
-/*
-* The configuration table for devices
-*/
-
-XScuGic_Config XScuGic_ConfigTable[] =
-{
-	{
-		XPAR_PSU_RCPU_GIC_DEVICE_ID,
-		XPAR_PSU_RCPU_GIC_BASEADDR,
-		XPAR_PSU_RCPU_GIC_DIST_BASEADDR
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c
deleted file mode 100644
index 626779720..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.c
-* @addtogroup scugic_v3_1
-* @{
-*
-* This file contains low-level driver functions that can be used to access the
-* device.  The user should refer to the hardware device specification for more
-* details of the device operation.
-* These routines are used when the user does not want to create an instance of
-* XScuGic structure but still wants to use the ScuGic device. Hence the
-* routines provided here take device id or scugic base address as arguments.
-* Separate static versions of DistInit and CPUInit are provided to implement
-* the low level driver routines.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.01a sdm  07/18/11 First release
-* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
-*		      702687).
-*					  Added support to direct interrupts to the appropriate CPU.
-*			  Earlier interrupts were directed to CPU1 (hard coded). Now
-*			  depending upon the CPU selected by the user (xparameters.h),
-*			  interrupts will be directed to the relevant CPU.
-*			  This fixes CR 699688.
-* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
-*			  XScuGic_SetPriTrigTypeByDistAddr and
-*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static void DistInit(XScuGic_Config *Config, u32 CpuID);
-static void CPUInit(XScuGic_Config *Config);
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* DistInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority and target CPU
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-* @param	CpuID is the Cpu ID to be initialized.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static void DistInit(XScuGic_Config *Config, u32 CpuID)
-{
-	u32 Int_Id;
-	u32 LocalCpuID = CpuID;
-
-#if USE_AMP==1
-	#warning "Building GIC for AMP"
-
-	/*
-	 * The distrubutor should not be initialized by FreeRTOS in the case of
-	 * AMP -- it is assumed that Linux is the master of this device in that
-	 * case.
-	 */
-	return;
-#endif
-
-	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
-
-	/*
-	 * Set the security domains in the int_security registers for non-secure
-	 * interrupts. All are secure, so leave at the default. Set to 1 for
-	 * non-secure interrupts.
-	 */
-
-
-	/*
-	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
-	 */
-
-	/*
-	 * 1. The trigger mode in the int_config register
-	 * Only write to the SPI interrupts, so start at 32
-	 */
-	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+16U) {
-	/*
-	 * Each INT_ID uses two bits, or 16 INT_ID per register
-	 * Set them all to be level sensitive, active HIGH.
-	 */
-		XScuGic_WriteReg(Config->DistBaseAddress,
-			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
-	}
-
-
-#define DEFAULT_PRIORITY	0xa0a0a0a0U
-	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
-		/*
-		 * 2. The priority using int the priority_level register
-		 * The priority_level and spi_target registers use one byte per
-		 * INT_ID.
-		 * Write a default value that can be changed elsewhere.
-		 */
-		XScuGic_WriteReg(Config->DistBaseAddress,
-				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
-				DEFAULT_PRIORITY);
-	}
-
-	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
-		/*
-		 * 3. The CPU interface in the spi_target register
-		 * Only write to the SPI interrupts, so start at 32
-		 */
-		LocalCpuID |= LocalCpuID << 8U;
-		LocalCpuID |= LocalCpuID << 16U;
-
-		XScuGic_WriteReg(Config->DistBaseAddress,
-				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
-	}
-
-	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
-	/*
-	 * 4. Enable the SPI using the enable_set register. Leave all disabled
-	 * for now.
-	 */
-		XScuGic_WriteReg(Config->DistBaseAddress,
-		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
-		Int_Id),
-		0xFFFFFFFFU);
-
-	}
-
-	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
-						XSCUGIC_EN_INT_MASK);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
-*
-* - Set the priority of the CPU.
-* - Enable the CPU interface
-*
-* @param	ConfigPtr is a pointer to a config table for the particular
-*		device this driver is associated with.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-static void CPUInit(XScuGic_Config *Config)
-{
-	/*
-	 * Program the priority mask of the CPU using the Priority mask
-	 * register
-	 */
-	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
-									0xF0U);
-
-	/*
-	 * If the CPU operates in both security domains, set parameters in the
-	 * control_s register.
-	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
-	 * 2. Program the AckCtl bit
-	 * 3. Program the SBPR bit to select the binary pointer behavior
-	 * 4. Set EnableS = 1 to enable secure interrupts
-	 * 5. Set EnbleNS = 1 to enable non secure interrupts
-	 */
-
-	/*
-	 * If the CPU operates only in the secure domain, setup the
-	 * control_s register.
-	 * 1. Set FIQen=1,
-	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
-	 * interrupts Only enable the IRQ output unless secure interrupts
-	 * are needed.
-	 */
-	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* CfgInitialize a specific interrupt controller instance/driver. The
-* initialization entails:
-*
-* - Initialize fields of the XScuGic structure
-* - Initial vector table with stub function calls
-* - All interrupt sources are disabled
-*
-* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
-* @param ConfigPtr is a pointer to a config table for the particular device
-*        this driver is associated with.
-* @param EffectiveAddr is the device base address in the virtual memory address
-*        space. The caller is responsible for keeping the address mapping
-*        from EffectiveAddr to the device physical base address unchanged
-*        once this function is invoked. Unexpected errors may occur if the
-*        address mapping changes after this function is called. If address
-*        translation is not used, use Config->BaseAddress for this parameters,
-*        passing the physical address instead.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-s32 XScuGic_DeviceInitialize(u32 DeviceId)
-{
-	XScuGic_Config *Config;
-	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
-
-	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
-
-	DistInit(Config, Cpu_Id);
-
-	CPUInit(Config);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver.  It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the
-* interrupt.Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized.  It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-* @param	DeviceId is the unique identifier for the ScuGic device.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XScuGic_DeviceInterruptHandler(void *DeviceId)
-{
-
-	u32 InterruptID;
-	u32 IntIDFull;
-	XScuGic_VectorTableEntry *TablePtr;
-	XScuGic_Config *CfgPtr;
-
-	CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
-
-	/*
-	 * Read the int_ack register to identify the highest priority
-	 * interrupt ID and make sure it is valid. Reading Int_Ack will
-	 * clear the interrupt in the GIC.
-	 */
-	IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
-	InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
-	if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
-		goto IntrExit;
-	}
-
-	/*
-	 * If the interrupt is shared, do some locking here if there are
-	 * multiple processors.
-	 */
-	/*
-	 * If pre-eption is required:
-	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
-	 * interrupts or the F bit for secure interrupts
-	 */
-
-	/*
-	 * If we need to change security domains, issue a SMC instruction here.
-	 */
-
-	/*
-	 * Execute the ISR. Jump into the Interrupt service routine based on
-	 * the IRQSource. A software trigger is cleared by the ACK.
-	 */
-	TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
-	if(TablePtr != NULL) {
-		TablePtr->Handler(TablePtr->CallBackRef);
-	}
-
-IntrExit:
-	/*
-	 * Write to the EOI register, we are all done here.
-	 * Let this function return, the boot code will restore the stack.
-	 */
-	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
-
-	/*
-	 * Return from the interrupt. Change security domains could happen
-	 * here.
-	 */
-}
-
-/*****************************************************************************/
-/**
-*
-* Register a handler function for a specific interrupt ID.  The vector table
-* of the interrupt controller is updated, overwriting any previous handler.
-* The handler function will be called when an interrupt occurs for the given
-* interrupt ID.
-*
-* @param	BaseAddress is the CPU Interface Register base address of the
-*		interrupt controller whose vector table will be modified.
-* @param	InterruptId is the interrupt ID to be associated with the input
-*		handler.
-* @param	Handler is the function pointer that will be added to
-*		the vector table for the given interrupt ID.
-* @param	CallBackRef is the argument that will be passed to the new
-*		handler function when it is called. This is user-specific.
-*
-* @return	None.
-*
-* @note
-*
-* Note that this function has no effect if the input base address is invalid.
-*
-******************************************************************************/
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
-			     Xil_InterruptHandler IntrHandler, void *CallBackRef)
-{
-	XScuGic_Config *CfgPtr;
-	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
-
-	if(CfgPtr != NULL) {
-		if( IntrHandler != NULL) {
-			CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
-		}
-		if( CallBackRef != NULL) {
-			CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
-		}
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the CPU interface base address of
-* the device. A table contains the configuration info for each device in the
-* system.
-*
-* @param	CpuBaseAddress is the CPU Interface Register base address.
-*
-* @return 	A pointer to the configuration structure for the specified
-*		device, or NULL if the device was not found.
-*
-* @note		None.
-*
-******************************************************************************/
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
-{
-	XScuGic_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
-		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
-				CpuBaseAddress) {
-			CfgPtr = &XScuGic_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XScuGic_Config *)CfgPtr;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param	BaseAddr is the device base address
-* @param	Int_Id is the IRQ source number to modify
-* @param	Priority is the new priority for the IRQ source. 0 is highest
-* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
-*			supported with a step of 8. Hence the supported priorities are
-*			0, 8, 16, 32, 40 ..., 248.
-* @param	Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI    Read Only    b10 always
-* PPI    Read Only    depending on how the PPIs are configured.
-*                    b01    Active HIGH level sensitive
-*                    b11 Rising edge sensitive
-* SPI                LSB is read only.
-*                    b01    Active HIGH level sensitive
-*                    b11 Rising edge sensitive/
-*
-* @return	None.
-*
-* @note		This API has the similar functionality of XScuGic_SetPriority
-*	        TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
-					u8 Priority, u8 Trigger)
-{
-	u32 RegValue;
-	u8 LocalPriority = Priority;
-
-	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
-	Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
-
-	/*
-	 * Determine the register to write to using the Int_Id.
-	 */
-	RegValue = XScuGic_ReadReg(DistBaseAddress,
-			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
-	/*
-	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
-	 * means the number of priority levels supported are 32 and they are
-	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
-	 * The lower order 3 bits are masked before putting it in the register.
-	 */
-	LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
-	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
-	/*
-	 * Write the value back to the register.
-	 */
-	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
-					RegValue);
-	/*
-	 * Determine the register to write to using the Int_Id.
-	 */
-	RegValue = XScuGic_ReadReg(DistBaseAddress,
-			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
-	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
-	/*
-	 * Write the value back to the register.
-	 */
-	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
-				RegValue);
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param	BaseAddr is the device base address
-* @param	Int_Id is the IRQ source number to modify
-* @param	Priority is a pointer to the value of the priority of the IRQ
-*		source. This is a return value.
-* @param	Trigger is pointer to the value of the trigger of the IRQ
-*		source. This is a return value.
-*
-* @return	None.
-*
-* @note		This API has the similar functionality of XScuGic_GetPriority
-*	        TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
-					u8 *Priority, u8 *Trigger)
-{
-	u32 RegValue;
-
-	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-	Xil_AssertVoid(Priority != NULL);
-	Xil_AssertVoid(Trigger != NULL);
-
-	/*
-	 * Determine the register to read to using the Int_Id.
-	 */
-	RegValue = XScuGic_ReadReg(DistBaseAddress,
-	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue = RegValue >> ((Int_Id%4U)*8U);
-	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
-	/*
-	 * Determine the register to read to using the Int_Id.
-	 */
-	RegValue = XScuGic_ReadReg(DistBaseAddress,
-	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
-	/*
-	 * Shift and Mask the correct bits for the priority and trigger in the
-	 * register
-	 */
-	RegValue = RegValue >> ((Int_Id%16U)*2U);
-
-	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h
deleted file mode 100644
index 5eaa633e3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h
+++ /dev/null
@@ -1,642 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v3_1
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device.  The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg  01/19/10 First release
-* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
-*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-*		      added to enable or disable interrupts based on
-*		      Distributor Register base address. Normally users use
-*		      XScuGic instance and call XScuGic_Enable or
-*		      XScuGic_Disable to enable/disable interrupts. These
-*		      new macros are provided when user does not want to
-*		      use an instance pointer but still wants to enable or
-*		      disable interrupts.
-*		      Function prototypes for functions (present in newly
-*		      added file xscugic_hw.c) are added.
-* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
-*		      702687).
-* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
-*		      XScuGic_SetPriTrigTypeByDistAddr and
-*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-*		      Zynq Ultrascale Mp
-* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
-*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef __ARM_NEON__
-#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
-#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
-							Register */
-#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
-							Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
-							Register */
-#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
-							Register */
-#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
-							Register */
-#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
-							Register */
-#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
-							Register */
-#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
-							Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
-							Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
-							0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
-							Register */
-#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
-							Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
-#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
-/* @} */
-
-/** @name  Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
-/* @} */
-
-/** @name  Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
-						Shared Peripheral
-						Interrupts*/
-#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name  Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name  Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080.  A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
-					      INT_ID */
-/* @} */
-
-/** @name  Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
-						INT_ID */
-#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
-						actually the lowest priority*/
-/* @} */
-
-/** @name  SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name  Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI    Read Only    b10 always
- * PPI    Read Only    depending on how the PPIs are configured.
- *                    b01    Active HIGH level sensitive
- *                    b11 Rising edge sensitive
- * SPI                LSB is read only.
- *                    b01    Active HIGH level sensitive
- *                    b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
-/* @} */
-
-/** @name  PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
-/* @} */
-
-/** @name  SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
-					     input */
-/* @} */
-
-/** @name  AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianess
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
-                                                  1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
-                                                  1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name  Software Triggered Interrupt Register
- * Controls issueing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
-                                                            b00-Use the target List
-                                                            b01-All CPUs except requester
-                                                            b10-To Requester
-                                                            b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
-                                                        signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
-							Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
-							Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
-						        Binary Point Register */
-
-/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
-                                                 0=separate registers,
-                                                 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
-                                                  interrupts,
-                                                  0= use IRQ for both,
-                                                  1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-/** @name Priority Mask Register
- * Priority Mask register definitions
- * The CPU interface does not send interrupt if the level of the interrupt is
- * lower than the level of the register.
- * @{
- */
-/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
-/* @} */
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
-						Value  Secure  Non-secure
-						b000    0xFE    0xFF
-						b001    0xFC    0xFE
-						b010    0xF8    0xFC
-						b011    0xF0    0xF8
-						b100    0xE0    0xF0
-						b101    0xC0    0xE0
-						b110    0x80    0xC0
-						b111    0x00    0x80
-						*/
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
-/* @} */
-
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interupt
- */
-#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
-/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param	Register is the register offset for the clear/enable bank.
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
-		((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param	BaseAddress is the base address of the device.
-* @param	RegOffset is the register offset to be read
-*
-* @return	The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
-	(Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param	BaseAddress is the base address of the device.
-* @param	RegOffset is the register offset to be written
-* @param	Data is the 32-bit value to write to the register
-*
-* @return	None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
-	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/****************************************************************************/
-/**
-*
-* Enable specific interrupt(s) in the interrupt controller.
-*
-* @param	DistBaseAddress is the Distributor Register base address of the
-*		device
-* @param	Int_Id is the ID of the interrupt source and should be in the
-*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
-	XScuGic_WriteReg((DistBaseAddress), \
-			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
-			 (0x00000001U << ((Int_Id) % 32U)))
-
-/****************************************************************************/
-/**
-*
-* Disable specific interrupt(s) in the interrupt controller.
-*
-* @param	DistBaseAddress is the Distributor Register base address of the
-*		device
-* @param	Int_Id is the ID of the interrupt source and should be in the
-*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
-	XScuGic_WriteReg((DistBaseAddress), \
-			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
-			 (0x00000001U << ((Int_Id) % 32U)))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32  XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
-			     Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
-                                        u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
-					u8 *Priority, u8 *Trigger);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif            /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c
deleted file mode 100644
index d05a51c5e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_intr.c
-* @addtogroup scugic_v3_1
-* @{
-*
-* This file contains the interrupt processing for the driver for the Xilinx
-* Interrupt Controller.  The interrupt processing is partitioned separately such
-* that users are not required to use the provided interrupt processing.  This
-* file requires other files of the driver to be linked in also.
-*
-* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
-* is an instance pointer to an interrupt controller driver such that multiple
-* interrupt controllers can be supported.  This handler requires the calling
-* function to pass it the appropriate argument, so another level of indirection
-* may be required.
-*
-* The interrupt processing may be used by connecting the interrupt handler to
-* the interrupt system.  The handler does not save and restore the processor
-* context but only handles the processing of the Interrupt Controller. The user
-* is encouraged to supply their own interrupt handler when performance tuning is
-* deemed necessary.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg  01/19/10 First release
-* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
-*		      since the HandlerTable has now moved to XScuGic_Config.
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-* @internal
-*
-* This driver assumes that the context of the processor has been saved prior to
-* the calling of the Interrupt Controller interrupt handler and then restored
-* after the handler returns. This requires either the running RTOS to save the
-* state of the machine or that a wrapper be used as the destination of the
-* interrupt vector to save the state of the processor and restore the state
-* after the interrupt handler returns.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver.  It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the interrupt.
-* Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized.  It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XScuGic_InterruptHandler(XScuGic *InstancePtr)
-{
-
-	u32 InterruptID;
-	    u32 IntIDFull;
-	    XScuGic_VectorTableEntry *TablePtr;
-
-	    /* Assert that the pointer to the instance is valid
-	     */
-	    Xil_AssertVoid(InstancePtr != NULL);
-
-	    /*
-	     * Read the int_ack register to identify the highest priority interrupt ID
-	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
-	     * in the GIC.
-	     */
-	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
-	    InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
-
-	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
-		goto IntrExit;
-	    }
-
-	    /*
-	     * If the interrupt is shared, do some locking here if there are multiple
-	     * processors.
-	     */
-	    /*
-	     * If pre-eption is required:
-	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
-	     * interrupts or the F bit for secure interrupts
-	     */
-
-	    /*
-	     * If we need to change security domains, issue a SMC instruction here.
-	     */
-
-	    /*
-	     * Execute the ISR. Jump into the Interrupt service routine based on the
-	     * IRQSource. A software trigger is cleared by the ACK.
-	     */
-	    TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
-		if(TablePtr != NULL) {
-	        TablePtr->Handler(TablePtr->CallBackRef);
-		}
-
-	IntrExit:
-	    /*
-	     * Write to the EOI register, we are all done here.
-	     * Let this function return, the boot code will restore the stack.
-	     */
-	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
-
-	    /*
-	     * Return from the interrupt. Change security domains could happen here.
-     */
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c
deleted file mode 100644
index 47620d644..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_selftest.c
-* @addtogroup scugic_v3_1
-* @{
-*
-* Contains diagnostic self-test functions for the XScuGic driver.
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a drg  01/19/10 First release
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-#define	XSCUGIC_PCELL_ID	0xB105F00DU
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. This test reads the ID registers and
-* compares them.
-*
-* @param	InstancePtr is a pointer to the XScuGic instance.
-*
-* @return
-*
-* 		- XST_SUCCESS if self-test is successful.
-* 		- XST_FAILURE if the self-test is not successful.
-*
-* @note		None.
-*
-******************************************************************************/
-s32  XScuGic_SelfTest(XScuGic *InstancePtr)
-{
-	u32 RegValue1 = 0U;
-	u32 Index;
-	s32 Status;
-
-	/*
-	 * Assert the arguments
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read the ID registers.
-	 */
-	for(Index=0U; Index<=3U; Index++) {
-		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
-			((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
-	}
-
-	if(XSCUGIC_PCELL_ID != RegValue1){
-		Status = XST_FAILURE;
-	} else {
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c
deleted file mode 100644
index d30390ab8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_sinit.c
-* @addtogroup scugic_v3_1
-* @{
-*
-* Contains static init functions for the XScuGic driver for the Interrupt
-* Controller. See xscugic.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a drg  01/19/10 First release
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param	DeviceId is the unique identifier for a device.
-*
-* @return	A pointer to the XScuGic configuration structure for the
-*		specified device, or NULL if the device was not found.
-*
-* @note		None.
-*
-******************************************************************************/
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
-{
-	XScuGic_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
-		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XScuGic_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XScuGic_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile
new file mode 100644
index 000000000..04867a484
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c
new file mode 100644
index 000000000..bf7ac12e8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c
@@ -0,0 +1,830 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+*		      		  "Config" entry is now made as pointer in the XScuGic
+*		      		  structure, necessary changes are made.
+*		      		  The HandlerTable can now be populated through the low
+*		      		  level routine XScuGic_RegisterHandler added in this
+*		      		  release. Hence necessary checks are added not to
+*		      		  overwrite the HandlerTable entriesin function
+*		      		  XScuGic_CfgInitialize.
+* 1.03a srt  02/27/13 Added APIs
+*					  - XScuGic_SetPriTrigTypeByDistAddr()
+*					  - XScuGic_GetPriTrigTypeByDistAddr()
+* 		    		  Removed Offset calculation macros, defined in _hw.h
+*		      		  (CR 702687)
+*			  		  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  		  interrupts were directed to CPU1 (hard coded). Now depending
+*			  		  upon the CPU selected by the user (xparameters.h), interrupts
+*			  		  will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  		  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  		  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             		  XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  		  This is fix for CR#705621.
+* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+*			  		  in function XScuGic_CfgInitialize is removed as it was
+*		      		  a bug.
+* 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+*			  		  target CPU mapping
+* 3.02	pkp	 11/09/15 Modified DistributorInit function for AMP case to add
+*					  the current cpu to interrupt processor targets registers
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  		  distributor is left uninitialized for Zynq AMP. It is assumed
+*             		  that the distributor will be initialized by Linux master. However
+*             		  for CortexR5 case, the earlier code is left unchanged where the
+*             		  the interrupt processor target registers in the distributor is
+*             		  initialized with the corresponding CPU ID on which the application
+*             		  built over the scugic driver runs.
+*             		  These changes fix CR#937243.
+* 3.3	pkp  05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+*					  to interrupt target register to fix CR#951848
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*                     the flow and avoid code duplication. Changes are made for
+*                     USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*                     one R5 is operating with A53 in open amp config and other
+*                     R5 running baremetal app, the existing code
+*                     had the potential to stop the whole AMP solution to work (if
+*                     for some reason the R5 running the baremetal app tasked to
+*                     initialize the Distributor hangs or crashes before initializing).
+*                     Changes are made so that the R5 under AMP first checks if
+*                     the distributor is enabled or not and if not, it does the
+*                     standard Distributor initialization.
+*                     This fixes the CR#952962.
+* 3.4   mus  09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+*                     for single core zynq-7000s
+* 3.5   mus  10/05/16 Modified DistributorInit function to avoid re-initialization of
+*                     distributor,If it is already initialized by other CPU.
+* 3.5	pkp	 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
+*					  and properly mask interrupt target processor value to modify
+*					  interrupt target processor register for a given interrupt ID
+*					  and cpu ID
+*
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DoDistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for
+	 * non-secure interrupts
+	 * All are secure, so leave at the default. Set to 1 for non-secure
+	 * interrupts.
+	 */
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
+		/*
+		 * Each INT_ID uses two bits, or 16 INT_ID per register
+		 * Set them all to be level sensitive, active HIGH.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+					0U);
+	}
+
+
+#define DEFAULT_PRIORITY    0xa0a0a0a0U
+	for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		/*
+		 * 3. The CPU interface in the spi_target register
+		 * Only write to the SPI interrupts, so start at 32
+		 */
+		LocalCpuID |= LocalCpuID << 8U;
+		LocalCpuID |= LocalCpuID << 16U;
+
+		XScuGic_DistWriteReg(InstancePtr,
+					 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+					 LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+		/*
+		 * 4. Enable the SPI using the enable_set register. Leave all
+		 * disabled for now.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
+			0xFFFFFFFFU);
+
+	}
+
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
+					XSCUGIC_EN_INT_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* DistributorInit initializes the distributor of the GIC. It calls
+* DoDistributorInit to finish the initialization.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+	u32 RegValue;
+
+#if USE_AMP==1 && (defined (ARMA9) || defined(__aarch64__))
+#warning "Building GIC for AMP"
+	/*
+	 * GIC initialization is taken care by master CPU in
+	 * openamp configuration, so do nothing and return.
+	 */
+	return;
+#endif
+
+	RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+	if (!(RegValue & XSCUGIC_EN_INT_MASK)) {
+		Xil_AssertVoid(InstancePtr != NULL);
+		DoDistributorInit(InstancePtr, CpuID);
+		return;
+	}
+
+	/*
+	 * The overall distributor should not be initialized in AMP case where
+	 * another CPU is taking care of it.
+	 */
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		RegValue = XScuGic_DistReadReg(InstancePtr,
+						XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+		RegValue |= LocalCpuID;
+		XScuGic_DistWriteReg(InstancePtr,
+				     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+				     RegValue);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInitialize initializes the CPU Interface of the GIC. The initialization entails:
+*
+*	- Set the priority of the CPU
+*	- Enable the CPU interface
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInitialize(XScuGic *InstancePtr)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask register
+	 */
+	XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
+
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
+	 * Only enable the IRQ output unless secure interrupts are needed.
+	 */
+	XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		Config->BaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
+				XScuGic_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 Int_Id;
+	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+	(void) EffectiveAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	/*
+     * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+     * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+	 */
+#ifdef ARMA9
+	if ( XPAR_CPU_ID == 0x01 )
+	{
+		Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
+		 & EFUSE_STATUS_CPU_MASK ) == 0);
+	}
+#endif
+
+	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+		InstancePtr->IsReady = 0U;
+		InstancePtr->Config = ConfigPtr;
+
+
+		for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id++) {
+			/*
+			* Initalize the handler to point to a stub to handle an
+			* interrupt which has not been connected to a handler. Only
+			* initialize it if the handler is 0 which means it was not
+			* initialized statically by the tools/user. Set the callback
+			* reference to this instance so that unhandled interrupts
+			* can be tracked.
+			*/
+			if 	((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) {
+				InstancePtr->Config->HandlerTable[Int_Id].Handler =
+									StubHandler;
+			}
+			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+								InstancePtr;
+		}
+
+		DistributorInit(InstancePtr, Cpu_Id);
+		CPUInitialize(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+*		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+                      Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used as an index into the table to select the proper
+	 * handler
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param	Int_Id contains the ID of the interrupt source and should
+*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without modifying
+	 * the other interrupt ids
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+
+	/*
+	 * Disconnect the handler and connect a stub, the callback reference
+	 * must be set to this instance to allow unhandled interrupts to be
+	 * tracked
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Enable the selected interrupt source by setting the
+	 * corresponding bit in the Enable Set register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the selected interrupt source by setting the
+	 * corresponding bit in the IDR.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller.  This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode.  A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id is the software interrupt ID to simulate an interrupt.
+* @param	Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Int_Id <= 15U) ;
+	Xil_AssertNonvoid(Cpu_Id <= 255U) ;
+
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired interrupt. Int_Id currently limited to 0 - 15
+	 * Use the target list for the Cpu ID.
+	 */
+	Mask = ((Cpu_Id << 16U) | Int_Id) &
+		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+	/*
+	 * Write to the Software interrupt trigger register. Use the appropriate
+	 * CPU Int_Id.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+	/* Indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+	/*
+	 * verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority;
+	LocalPriority = Priority;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				RegValue);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param	Int_Id is the IRQ source number to modify
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+	u32 RegValue, Offset;
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+	Offset = (Int_Id & 0x3U);
+	Cpu_Id = (0x1U << Cpu_Id);
+
+	RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
+	RegValue |= ((Cpu_Id) << (Offset*8U));
+
+	XScuGic_DistWriteReg(InstancePtr,
+						 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+						 RegValue);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h
new file mode 100644
index 000000000..1f02a73ff
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_1
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - assigning desired priority to interrupt source if default is not
+*     acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* <b>Nested Interrupts Processing</b>
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET   0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c
new file mode 100644
index 000000000..4bb186e5a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[] =
+{
+	{
+		XPAR_PSU_RCPU_GIC_DEVICE_ID,
+		XPAR_PSU_RCPU_GIC_BASEADDR,
+		XPAR_PSU_RCPU_GIC_DIST_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c
new file mode 100644
index 000000000..626779720
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c
@@ -0,0 +1,570 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm  07/18/11 First release
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+*					  Added support to direct interrupts to the appropriate CPU.
+*			  Earlier interrupts were directed to CPU1 (hard coded). Now
+*			  depending upon the CPU selected by the user (xparameters.h),
+*			  interrupts will be directed to the relevant CPU.
+*			  This fixes CR 699688.
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for non-secure
+	 * interrupts. All are secure, so leave at the default. Set to 1 for
+	 * non-secure interrupts.
+	 */
+
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+16U) {
+	/*
+	 * Each INT_ID uses two bits, or 16 INT_ID per register
+	 * Set them all to be level sensitive, active HIGH.
+	 */
+		XScuGic_WriteReg(Config->DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+	}
+
+
+#define DEFAULT_PRIORITY	0xa0a0a0a0U
+	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_WriteReg(Config->DistBaseAddress,
+				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		/*
+		 * 3. The CPU interface in the spi_target register
+		 * Only write to the SPI interrupts, so start at 32
+		 */
+		LocalCpuID |= LocalCpuID << 8U;
+		LocalCpuID |= LocalCpuID << 16U;
+
+		XScuGic_WriteReg(Config->DistBaseAddress,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+	/*
+	 * 4. Enable the SPI using the enable_set register. Leave all disabled
+	 * for now.
+	 */
+		XScuGic_WriteReg(Config->DistBaseAddress,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+		Int_Id),
+		0xFFFFFFFFU);
+
+	}
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+						XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask
+	 * register
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+									0xF0U);
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+	 * interrupts Only enable the IRQ output unless secure interrupts
+	 * are needed.
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+*        this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+*        space. The caller is responsible for keeping the address mapping
+*        from EffectiveAddr to the device physical base address unchanged
+*        once this function is invoked. Unexpected errors may occur if the
+*        address mapping changes after this function is called. If address
+*        translation is not used, use Config->BaseAddress for this parameters,
+*        passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+	XScuGic_Config *Config;
+	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+
+	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	DistInit(Config, Cpu_Id);
+
+	CPUInit(Config);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param	DeviceId is the unique identifier for the ScuGic device.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+	u32 InterruptID;
+	u32 IntIDFull;
+	XScuGic_VectorTableEntry *TablePtr;
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
+
+	/*
+	 * Read the int_ack register to identify the highest priority
+	 * interrupt ID and make sure it is valid. Reading Int_Ack will
+	 * clear the interrupt in the GIC.
+	 */
+	IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+	InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+	if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	}
+
+	/*
+	 * If the interrupt is shared, do some locking here if there are
+	 * multiple processors.
+	 */
+	/*
+	 * If pre-eption is required:
+	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	 * interrupts or the F bit for secure interrupts
+	 */
+
+	/*
+	 * If we need to change security domains, issue a SMC instruction here.
+	 */
+
+	/*
+	 * Execute the ISR. Jump into the Interrupt service routine based on
+	 * the IRQSource. A software trigger is cleared by the ACK.
+	 */
+	TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+	if(TablePtr != NULL) {
+		TablePtr->Handler(TablePtr->CallBackRef);
+	}
+
+IntrExit:
+	/*
+	 * Write to the EOI register, we are all done here.
+	 * Let this function return, the boot code will restore the stack.
+	 */
+	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	/*
+	 * Return from the interrupt. Change security domains could happen
+	 * here.
+	 */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param	BaseAddress is the CPU Interface Register base address of the
+*		interrupt controller whose vector table will be modified.
+* @param	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+	XScuGic_Config *CfgPtr;
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+	if(CfgPtr != NULL) {
+		if( IntrHandler != NULL) {
+			CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+		}
+		if( CallBackRef != NULL) {
+			CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param	CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return 	A pointer to the configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+				CpuBaseAddress) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_SetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority = Priority;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					RegValue);
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_GetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h
new file mode 100644
index 000000000..5eaa633e3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h
@@ -0,0 +1,642 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_1
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
+#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
+							Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
+							Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
+							Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
+							Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
+							Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+		((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c
new file mode 100644
index 000000000..d05a51c5e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller.  The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing.  This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported.  This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system.  The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
+*		      since the HandlerTable has now moved to XScuGic_Config.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+	u32 InterruptID;
+	    u32 IntIDFull;
+	    XScuGic_VectorTableEntry *TablePtr;
+
+	    /* Assert that the pointer to the instance is valid
+	     */
+	    Xil_AssertVoid(InstancePtr != NULL);
+
+	    /*
+	     * Read the int_ack register to identify the highest priority interrupt ID
+	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
+	     * in the GIC.
+	     */
+	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+	    InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	    }
+
+	    /*
+	     * If the interrupt is shared, do some locking here if there are multiple
+	     * processors.
+	     */
+	    /*
+	     * If pre-eption is required:
+	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	     * interrupts or the F bit for secure interrupts
+	     */
+
+	    /*
+	     * If we need to change security domains, issue a SMC instruction here.
+	     */
+
+	    /*
+	     * Execute the ISR. Jump into the Interrupt service routine based on the
+	     * IRQSource. A software trigger is cleared by the ACK.
+	     */
+	    TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+		if(TablePtr != NULL) {
+	        TablePtr->Handler(TablePtr->CallBackRef);
+		}
+
+	IntrExit:
+	    /*
+	     * Write to the EOI register, we are all done here.
+	     * Let this function return, the boot code will restore the stack.
+	     */
+	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	    /*
+	     * Return from the interrupt. Change security domains could happen here.
+     */
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c
new file mode 100644
index 000000000..47620d644
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define	XSCUGIC_PCELL_ID	0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_FAILURE if the self-test is not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+	u32 RegValue1 = 0U;
+	u32 Index;
+	s32 Status;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ID registers.
+	 */
+	for(Index=0U; Index<=3U; Index++) {
+		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+			((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
+	}
+
+	if(XSCUGIC_PCELL_ID != RegValue1){
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c
new file mode 100644
index 000000000..d30390ab8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XScuGic configuration structure for the
+*		specified device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile
deleted file mode 100644
index f57081af6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xsdps_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling sdps"
-
-xsdps_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xsdps_includes
-
-xsdps_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c
deleted file mode 100644
index 6425a791b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c
+++ /dev/null
@@ -1,1507 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps.c
-* @addtogroup sdps_v2_5
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ---    -------- -----------------------------------------------
-* 1.00a hk/sg  10/17/13 Initial release
-* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
-* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
-* 2.2   hk     07/28/14 Make changes to enable use of data cache.
-* 2.3   sk     09/23/14 Send command for relative card address
-*                       when re-initialization is done.CR# 819614.
-*						Use XSdPs_Change_ClkFreq API whenever changing
-*						clock.CR# 816586.
-* 2.4	sk	   12/04/14 Added support for micro SD without
-* 						WP/CD. CR# 810655.
-*						Checked for DAT Inhibit mask instead of CMD
-* 						Inhibit mask in Cmd Transfer API.
-*						Added Support for SD Card v1.0
-* 2.5 	sg	   07/09/15 Added SD 3.0 features
-*       kvn    07/15/15 Modified the code according to MISRAC-2012.
-* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
-*       sk     12/10/15 Added support for MMC cards.
-*       sk     02/16/16 Corrected the Tuning logic.
-*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps.h"
-/*
- * The header sleep.h and API usleep() can only be used with an arm design.
- * MB_Sleep() is used for microblaze design.
- */
-#if defined (__arm__) || defined (__aarch64__)
-
-#include "sleep.h"
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-#include "microblaze_sleep.h"
-
-#endif
-
-/************************** Constant Definitions *****************************/
-#define XSDPS_CMD8_VOL_PATTERN	0x1AAU
-#define XSDPS_RESPOCR_READY	0x80000000U
-#define XSDPS_ACMD41_HCS	0x40000000U
-#define XSDPS_ACMD41_3V3	0x00300000U
-#define XSDPS_CMD1_HIGH_VOL	0x00FF8000U
-#define XSDPS_CMD1_DUAL_VOL	0x00FF8010U
-#define HIGH_SPEED_SUPPORT	0x2U
-#define WIDTH_4_BIT_SUPPORT	0x4U
-#define SD_CLK_25_MHZ		25000000U
-#define SD_CLK_26_MHZ		26000000U
-#define EXT_CSD_DEVICE_TYPE_BYTE	196U
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
-#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
-#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200		0x10U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200		0x20U
-#define CSD_SPEC_VER_3		0x3U
-
-/* Note: Remove this once fixed */
-#define UHS_BROKEN
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
-static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
-static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XSdPs instance such that the driver is ready to use.
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	ConfigPtr is a reference to a structure containing information
-*		about a specific SD device. This function initializes an
-*		InstancePtr object for a specific device specified by the
-*		contents of Config.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the address
-*		mapping from EffectiveAddr to the device physical base address
-*		unchanged once this function is invoked. Unexpected errors may
-*		occur if the address mapping changes after this function is
-*		called. If address translation is not used, use
-*		ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_DEVICE_IS_STARTED if the device is already started.
-*		It must be stopped to re-initialize.
-*
-* @note		This function initializes the host controller.
-*		Initial clock of 400KHz is set.
-*		Voltage of 3.3V is selected as that is supported by host.
-*		Interrupts status is enabled and signal disabled by default.
-*		Default data direction is card to host and
-*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
-*
-******************************************************************************/
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
-				u32 EffectiveAddr)
-{
-	s32 Status;
-	u8 PowerLevel;
-	u8 ReadReg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	/* Set some default values. */
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
-	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
-
-	/* Disable bus power */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_POWER_CTRL_OFFSET, 0U);
-
-	/* Delay to poweroff card */
-#if defined (__arm__) || defined (__aarch64__)
-
-    (void)sleep(1U);
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-    MB_Sleep(1000U);
-
-#endif
-
-	/* "Software reset for all" is initiated */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
-			XSDPS_SWRST_ALL_MASK);
-
-	/* Proceed with initialization only after reset is complete */
-	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-				XSDPS_SW_RST_OFFSET);
-	while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
-		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-				XSDPS_SW_RST_OFFSET);
-	}
-	/* Host Controller version is read. */
-	 InstancePtr->HC_Version =
-			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
-
-	/*
-	 * Read capabilities register and update it in Instance pointer.
-	 * It is sufficient to read this once on power on.
-	 */
-	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-						XSDPS_CAPS_OFFSET);
-
-	/* Select voltage and enable bus power. */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_POWER_CTRL_OFFSET,
-			XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
-
-	/* Change the clock frequency to 400 KHz */
-	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH ;
-	}
-
-    if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
-		PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
-	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
-		PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
-	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
-		PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
-	} else {
-		PowerLevel = 0U;
-	}
-
-	/* Select voltage based on capability and enable bus power. */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_POWER_CTRL_OFFSET,
-			PowerLevel | XSDPS_PC_BUS_PWR_MASK);
-	/* Enable ADMA2 in 64bit mode. */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL1_OFFSET,
-			XSDPS_HC_DMA_ADMA2_32_MASK);
-
-	/* Enable all interrupt status except card interrupt initially */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_EN_OFFSET,
-			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_ERR_INTR_STS_EN_OFFSET,
-			XSDPS_ERROR_INTR_ALL_MASK);
-
-	/* Disable all interrupt signals by default. */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
-
-	/*
-	 * Transfer mode register - default value
-	 * DMA enabled, block count enabled, data direction card to host(read)
-	 */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
-			XSDPS_TM_DAT_DIR_SEL_MASK);
-
-	/* Set block size to 512 by default */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
-
-	Status = XST_SUCCESS;
-
-RETURN_PATH:
-	return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* SD initialization is done in this function
-*
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because
-* 			a) SD is already initialized
-* 			b) There is no card inserted
-* 			c) One of the steps (commands) in the
-			   initialization cycle failed
-*
-* @note		This function initializes the SD card by following its
-*		initialization and identification state diagram.
-*		CMD0 is sent to reset card.
-*		CMD8 and ACDM41 are sent to identify voltage and
-*		high capacity support
-*		CMD2 and CMD3 are sent to obtain Card ID and
-*		Relative card address respectively.
-*		CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
-{
-	u32 PresentStateReg;
-	s32 Status;
-	u32 RespOCR;
-	u32 CSD[4];
-	u32 Arg;
-	u8 ReadReg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
-				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
-				!= XSDPS_CAPS_EMB_SLOT)) {
-		if(InstancePtr->Config.CardDetect != 0U) {
-			/*
-			 * Check the present state register to make sure
-			 * card is inserted and detected by host controller
-			 */
-			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XSDPS_PRES_STATE_OFFSET);
-			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		}
-	}
-
-	/* CMD0 no response expected */
-	Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * CMD8; response expected
-	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
-	 */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
-			XSDPS_CMD8_VOL_PATTERN, 0U);
-	if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	if (Status == XSDPS_CT_ERROR) {
-		 /* "Software reset for all" is initiated */
-		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
-				XSDPS_SWRST_CMD_LINE_MASK);
-
-		/* Proceed with initialization only after reset is complete */
-		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-						XSDPS_SW_RST_OFFSET);
-		while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
-			ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-						XSDPS_SW_RST_OFFSET);
-		}
-	}
-
-	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-						XSDPS_RESP0_OFFSET);
-	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
-		InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
-	}
-	else {
-		InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
-	}
-
-	RespOCR = 0U;
-	/* Send ACMD41 while card is still busy with power up */
-	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-        Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
-		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
-		    Arg |= XSDPS_OCR_S18;
-		}
-
-		/* 0x40300000 - Host High Capacity support & 3.3V window */
-		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
-				Arg, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/* Response with card capacity */
-		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XSDPS_RESP0_OFFSET);
-
-	}
-
-	/* Update HCS support flag based on card capacity response */
-	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
-		InstancePtr->HCS = 1U;
-	}
-
-	/* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */
-#ifndef UHS_BROKEN
-    if ((RespOCR & XSDPS_OCR_S18) != 0U) {
-		InstancePtr->Switch1v8 = 1U;
-		Status = XSdPs_Switch_Voltage(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-	}
-#endif
-
-	/* CMD2 for Card ID */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	InstancePtr->CardID[0] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-	InstancePtr->CardID[1] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP1_OFFSET);
-	InstancePtr->CardID[2] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP2_OFFSET);
-	InstancePtr->CardID[3] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP3_OFFSET);
-	do {
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/*
-		 * Relative card address is stored as the upper 16 bits
-		 * This is to avoid shifting when sending commands
-		 */
-		InstancePtr->RelCardAddr =
-				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
-	} while (InstancePtr->RelCardAddr == 0U);
-
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * Card specific data is read.
-	 * Currently not used for any operation.
-	 */
-	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP1_OFFSET);
-	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP2_OFFSET);
-	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP3_OFFSET);
-
-	Status = XST_SUCCESS;
-
-RETURN_PATH:
-	return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Initialize Card with Identification mode sequence
-*
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because
-* 			a) SD is already initialized
-* 			b) There is no card inserted
-* 			c) One of the steps (commands) in the
-*			   initialization cycle failed
-*
-*
-******************************************************************************/
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr) {
-	u8 Tmp;
-	u32 Cnt;
-	u32 PresentStateReg;
-	u32 CtrlReg;
-	u32 CSD[4];
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-static u8 ExtCsd[512];
-#pragma data_alignment = 4
-#else
-static u8 ExtCsd[512] __attribute__ ((aligned(32)));
-#endif
-	u8 SCR[8] = { 0U };
-	u8 ReadBuff[64] = { 0U };
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Default settings */
-	InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
-	InstancePtr->CardType = XSDPS_CARD_SD;
-	InstancePtr->Switch1v8 = 0U;
-	InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
-
-	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
-			((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
-			== XSDPS_CAPS_EMB_SLOT)) {
-		InstancePtr->CardType = XSDPS_CHIP_EMMC;
-	} else {
-		Status = XSdPs_IdentifyCard(InstancePtr);
-		if (Status == XST_FAILURE) {
-			goto RETURN_PATH;
-		}
-	}
-
-	if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
-		(InstancePtr->CardType != XSDPS_CARD_MMC) &&
-		(InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	if (InstancePtr->CardType == XSDPS_CARD_SD) {
-		Status = XSdPs_SdCardInitialize(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/* Change clock to default clock 25MHz */
-		InstancePtr->BusSpeed = SD_CLK_25_MHZ;
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-	} else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
-			|| (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
-		Status = XSdPs_MmcCardInitialize(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-		/* Change clock to default clock 26MHz */
-		InstancePtr->BusSpeed = SD_CLK_26_MHZ;
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} else {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	Status = XSdPs_Select_Card(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	if (InstancePtr->CardType == XSDPS_CARD_SD) {
-		/* Pull-up disconnected during data transfer */
-		Status = XSdPs_Pullup(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
-			Status = XSdPs_Change_BusWidth(InstancePtr);
-			if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		}
-
-		if ((InstancePtr->Switch1v8 != 0U) &&
-				(InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) {
-			/* Set UHS-I SDR104 mode */
-			Status = XSdPs_Uhs_ModeInit(InstancePtr,
-					XSDPS_UHS_SPEED_MODE_SDR104);
-			if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-
-		} else {
-
-			/*
-			 * card supports CMD6 when SD_SPEC field in SCR register
-			 * indicates that the Physical Layer Specification Version
-			 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
-			 */
-			if (SCR[0] != 0U) {
-				/* Get speed supported by device */
-				Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
-				if (Status != XST_SUCCESS) {
-					Status = XST_FAILURE;
-					goto RETURN_PATH;
-				}
-
-				/* Check for high speed support */
-				if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) {
-					Status = XSdPs_Change_BusSpeed(InstancePtr);
-					if (Status != XST_SUCCESS) {
-						Status = XST_FAILURE;
-						goto RETURN_PATH;
-					}
-				}
-			}
-		}
-
-	} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
-				(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
-				(InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
-
-		Status = XSdPs_Change_BusWidth(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
-				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) {
-			Status = XSdPs_Change_BusSpeed(InstancePtr);
-			if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-
-			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
-			if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-
-			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		}
-	} else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
-		/* Change bus width to 8-bit */
-		Status = XSdPs_Change_BusWidth(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/* Get Extended CSD */
-		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
-				(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
-				EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) {
-			Status = XSdPs_Change_BusSpeed(InstancePtr);
-			if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-
-			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
-			if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-
-			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		}
-	}
-
-	Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-RETURN_PATH:
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Identify type of card using CMD0 + CMD1 sequence
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
-{
-	s32 Status;
-	u32 OperCondReg;
-	u8 ReadReg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* 74 CLK delay after card is powered up, before the first command. */
-#if defined (__arm__) || defined (__aarch64__)
-
-	usleep(XSDPS_INIT_DELAY);
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-	/* 2 msec delay */
-	MB_Sleep(2);
-
-#endif
-
-	/* CMD0 no response expected */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/* Host High Capacity support & High voltage window */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
-			XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
-	if (Status != XST_SUCCESS) {
-		InstancePtr->CardType = XSDPS_CARD_SD;
-	} else {
-		InstancePtr->CardType = XSDPS_CARD_MMC;
-	}
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-
-	/* "Software reset for all" is initiated */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
-			XSDPS_SWRST_CMD_LINE_MASK);
-
-	/* Proceed with initialization only after reset is complete */
-	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-					XSDPS_SW_RST_OFFSET);
-	while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
-		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-					XSDPS_SW_RST_OFFSET);
-	}
-
-	Status = XST_SUCCESS;
-
-RETURN_PATH:
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Switches the SD card voltage from 3v3 to 1v8
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
-{
-	s32 Status;
-	u16 CtrlReg;
-	u32 ReadReg;
-
-	/* Send switch voltage command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-	}
-
-	/* Wait for CMD and DATA line to go low */
-	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XSDPS_PRES_STATE_OFFSET);
-	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
-					XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
-		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XSDPS_PRES_STATE_OFFSET);
-	}
-
-	/* Stop the clock */
-	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_CLK_CTRL_OFFSET);
-	CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
-			CtrlReg);
-
-	/* Wait minimum 5mSec */
-#if defined (__arm__) || defined (__aarch64__)
-
-	(void)usleep(5000U);
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-	MB_Sleep(5U);
-
-#endif
-
-	/* Enabling 1.8V in controller */
-	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL2_OFFSET);
-	CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
-			CtrlReg);
-
-	/* Start clock */
-	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/* Wait for CMD and DATA line to go high */
-	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XSDPS_PRES_STATE_OFFSET);
-	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
-			!= (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
-		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XSDPS_PRES_STATE_OFFSET);
-	}
-
-RETURN_PATH:
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-
-* This function does SD command generation.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Cmd is the command to be sent.
-* @param	Arg is the argument to be sent along with the command.
-* 		This could be address or any other information
-* @param	BlkCnt - Block count passed by the user.
-*
-* @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because another transfer
-* 			is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
-{
-	u32 PresentStateReg;
-	u32 CommandReg;
-	u32 StatusReg;
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Check the command inhibit to make sure no other
-	 * command transfer is in progress
-	 */
-	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_PRES_STATE_OFFSET);
-	if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/* Write block count register */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
-
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
-
-	/* Write argument register */
-	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XSDPS_ARGMT_OFFSET, Arg);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-	/* Command register is set to trigger transfer of command */
-	CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
-
-	/*
-	 * Mask to avoid writing to reserved bits 31-30
-	 * This is necessary because 0x80000000 is used  by this software to
-	 * distinguish between ACMD and CMD of same number
-	 */
-	CommandReg = CommandReg & 0x3FFFU;
-
-	/*
-	 * Check for data inhibit in case of command using DAT lines.
-	 * For Tuning Commands DAT lines check can be ignored.
-	 */
-	if ((Cmd != CMD21) && (Cmd != CMD19)) {
-		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XSDPS_PRES_STATE_OFFSET);
-		if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
-									XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
-				((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	}
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
-			(u16)CommandReg);
-
-	/* Polling for response for now */
-	do {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET);
-		if ((Cmd == CMD21) || (Cmd == CMD19)) {
-			if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
-				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
-				break;
-			}
-		}
-
-		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-			Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-									XSDPS_ERR_INTR_STS_OFFSET);
-			if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
-				Status = XSDPS_CT_ERROR;
-			}
-			 /* Write to clear error bits */
-			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_ERR_INTR_STS_OFFSET,
-					XSDPS_ERROR_INTR_ALL_MASK);
-			goto RETURN_PATH;
-		}
-	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
-	/* Write to clear bit */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET,
-			XSDPS_INTR_CC_MASK);
-
-	Status = XST_SUCCESS;
-
-RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* This function frames the Command register for a particular command.
-* Note that this generates only the command register value i.e.
-* the upper 16 bits of the transfer mode and command register.
-* This value is already shifted to be upper 16 bits and can be directly
-* OR'ed with transfer mode register value.
-*
-* @param	Command to be sent.
-*
-* @return	Command register value complete with response type and
-* 		data, CRC and index related flags.
-*
-******************************************************************************/
-u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
-{
-		u32 RetVal;
-
-		RetVal = Cmd;
-
-		switch(Cmd) {
-		case CMD0:
-			RetVal |= RESP_NONE;
-		break;
-		case CMD1:
-			RetVal |= RESP_R3;
-		break;
-		case CMD2:
-			RetVal |= RESP_R2;
-		break;
-		case CMD3:
-			RetVal |= RESP_R6;
-		break;
-		case CMD4:
-			RetVal |= RESP_NONE;
-			break;
-		case CMD5:
-			RetVal |= RESP_R1B;
-		break;
-		case CMD6:
-			if (InstancePtr->CardType == XSDPS_CARD_SD) {
-				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
-			} else {
-				RetVal |= RESP_R1B;
-			}
-			break;
-		case ACMD6:
-			RetVal |= RESP_R1;
-		break;
-		case CMD7:
-			RetVal |= RESP_R1;
-		break;
-		case CMD8:
-			if (InstancePtr->CardType == XSDPS_CARD_SD) {
-				RetVal |= RESP_R1;
-			} else {
-				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
-			}
-			break;
-		case CMD9:
-			RetVal |= RESP_R2;
-		break;
-		case CMD11:
-		case CMD10:
-		case CMD12:
-		case ACMD13:
-		case CMD16:
-			RetVal |= RESP_R1;
-		break;
-		case CMD17:
-		case CMD18:
-		case CMD19:
-		case CMD21:
-			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
-		break;
-		case CMD23:
-		case ACMD23:
-		case CMD24:
-		case CMD25:
-			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
-		case ACMD41:
-			RetVal |= RESP_R3;
-		break;
-		case ACMD42:
-			RetVal |= RESP_R1;
-		break;
-		case ACMD51:
-			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
-		break;
-		case CMD52:
-		case CMD55:
-			RetVal |= RESP_R1;
-		break;
-		case CMD58:
-		break;
-		default :
-			RetVal |= Cmd;
-		break;
-		}
-
-		return RetVal;
-}
-
-/*****************************************************************************/
-/**
-* This function performs SD read in polled mode.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Arg is the address passed by the user that is to be sent as
-* 		argument along with the command.
-* @param	BlkCnt - Block count passed by the user.
-* @param	Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because another transfer
-* 		is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
-	s32 Status;
-	u32 PresentStateReg;
-	u32 StatusReg;
-
-	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
-				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
-				!= XSDPS_CAPS_EMB_SLOT)) {
-		if(InstancePtr->Config.CardDetect != 0U) {
-			/* Check status to ensure card is initialized */
-			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XSDPS_PRES_STATE_OFFSET);
-			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		}
-	}
-
-	/* Set block size to 512 if not already set */
-	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
-		Status = XSdPs_SetBlkSize(InstancePtr,
-			XSDPS_BLK_SIZE_512_MASK);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	}
-
-	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_AUTO_CMD12_EN_MASK |
-			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
-			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
-
-	Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
-
-	/* Send block read command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/* Check for transfer complete */
-	do {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET);
-		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-			/* Write to clear error bits */
-			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_ERR_INTR_STS_OFFSET,
-					XSDPS_ERROR_INTR_ALL_MASK);
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-	/* Write to clear bit */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-
-	Status = XST_SUCCESS;
-
-RETURN_PATH:
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-* This function performs SD write in polled mode.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Arg is the address passed by the user that is to be sent as
-* 		argument along with the command.
-* @param	BlkCnt - Block count passed by the user.
-* @param	Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because another transfer
-* 		is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
-{
-	s32 Status;
-	u32 PresentStateReg;
-	u32 StatusReg;
-
-	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
-				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
-				!= XSDPS_CAPS_EMB_SLOT)) {
-		if(InstancePtr->Config.CardDetect != 0U) {
-			/* Check status to ensure card is initialized */
-			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XSDPS_PRES_STATE_OFFSET);
-			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		}
-	}
-
-	/* Set block size to 512 if not already set */
-	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
-		Status = XSdPs_SetBlkSize(InstancePtr,
-			XSDPS_BLK_SIZE_512_MASK);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-	}
-
-	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
-	Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_AUTO_CMD12_EN_MASK |
-			XSDPS_TM_BLK_CNT_EN_MASK |
-			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
-
-	/* Send block write command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * Check for transfer complete
-	 * Polling for response for now
-	 */
-	do {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET);
-		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-			/* Write to clear error bits */
-			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_ERR_INTR_STS_OFFSET,
-					XSDPS_ERROR_INTR_ALL_MASK);
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-	/* Write to clear bit */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Selects card and sets default block size
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Select_Card (XSdPs *InstancePtr)
-{
-	s32 Status = 0;
-
-	/* Send CMD7 - Select card */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
-			InstancePtr->RelCardAddr, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to setup ADMA2 descriptor table
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	BlkCnt - block count.
-* @param	Buff pointer to data buffer.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
-	u32 TotalDescLines = 0U;
-	u32 DescNum = 0U;
-	u32 BlkSize = 0U;
-
-	/* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
-	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_BLK_SIZE_OFFSET);
-	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
-
-	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
-
-		TotalDescLines = 1U;
-
-	}else {
-
-		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
-		if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
-			TotalDescLines += 1U;
-		}
-
-	}
-
-	for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
-		InstancePtr->Adma2_DescrTbl[DescNum].Address =
-				(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
-				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
-		/* This will write '0' to length field which indicates 65536 */
-		InstancePtr->Adma2_DescrTbl[DescNum].Length =
-				(u16)XSDPS_DESC_MAX_LENGTH;
-	}
-
-	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
-			(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-
-	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
-			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
-	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
-			(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
-
-
-	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
-			(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
-
-	Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
-			sizeof(XSdPs_Adma2Descriptor) * 32U);
-
-}
-
-/*****************************************************************************/
-/**
-* Mmc initialization is done in this function
-*
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because
-* 			a) MMC is already initialized
-* 			b) There is no card inserted
-* 			c) One of the steps (commands) in the initialization
-*			   cycle failed
-* @note 	This function initializes the SD card by following its
-*		initialization and identification state diagram.
-*		CMD0 is sent to reset card.
-*		CMD1 sent to identify voltage and high capacity support
-*		CMD2 and CMD3 are sent to obtain Card ID and
-*		Relative card address respectively.
-*		CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
-{
-	u32 PresentStateReg;
-	s32 Status;
-	u32 RespOCR;
-	u32 CSD[4];
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
-				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
-				!= XSDPS_CAPS_EMB_SLOT)) {
-		if(InstancePtr->Config.CardDetect != 0U) {
-			/*
-			 * Check the present state register to make sure
-			 * card is inserted and detected by host controller
-			 */
-			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XSDPS_PRES_STATE_OFFSET);
-			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		}
-	}
-
-	/* CMD0 no response expected */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	RespOCR = 0U;
-	/* Send CMD1 while card is still busy with power up */
-	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
-
-		/* Host High Capacity support & High volage window */
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
-				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/* Response with card capacity */
-		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XSDPS_RESP0_OFFSET);
-
-	}
-
-	/* Update HCS support flag based on card capacity response */
-	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
-		InstancePtr->HCS = 1U;
-	}
-
-	/* CMD2 for Card ID */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	InstancePtr->CardID[0] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-	InstancePtr->CardID[1] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP1_OFFSET);
-	InstancePtr->CardID[2] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP2_OFFSET);
-	InstancePtr->CardID[3] =
-			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP3_OFFSET);
-
-	/* Set relative card address */
-	InstancePtr->RelCardAddr = 0x12340000U;
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * Card specific data is read.
-	 * Currently not used for any operation.
-	 */
-	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP1_OFFSET);
-	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP2_OFFSET);
-	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP3_OFFSET);
-
-	InstancePtr->Card_Version =  (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
-
-	Status = XST_SUCCESS;
-
-RETURN_PATH:
-	return Status;
-
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h
deleted file mode 100644
index 409653891..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v2_5
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Intialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in tranfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesytem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ---    -------- -----------------------------------------------
-* 1.00a hk/sg  10/17/13 Initial release
-* 2.0   hk      03/07/14 Version number revised.
-* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
-*                       Add sleep for microblaze designs. CR# 781117.
-* 2.2   hk     07/28/14 Make changes to enable use of data cache.
-* 2.3   sk     09/23/14 Send command for relative card address
-*                       when re-initialization is done.CR# 819614.
-*						Use XSdPs_Change_ClkFreq API whenever changing
-*						clock.CR# 816586.
-* 2.4	sk	   12/04/14 Added support for micro SD without
-* 						WP/CD. CR# 810655.
-*						Checked for DAT Inhibit mask instead of CMD
-* 						Inhibit mask in Cmd Transfer API.
-*						Added Support for SD Card v1.0
-* 2.5 	sg		07/09/15 Added SD 3.0 features
-*       kvn     07/15/15 Modified the code according to MISRAC-2012.
-* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
-*       sk     12/10/15 Added support for MMC cards.
-*              01/08/16 Added workaround for issue in auto tuning mode
-*                       of SDR50, SDR104 and HS200.
-*       sk     02/16/16 Corrected the Tuning logic.
-*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-*
-* </pre>
-*
-******************************************************************************/
-
-
-#ifndef SDPS_H_
-#define SDPS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_printf.h"
-#include "xil_cache.h"
-#include "xstatus.h"
-#include "xsdps_hw.h"
-#include <string.h>
-
-/************************** Constant Definitions *****************************/
-
-#define XSDPS_CT_ERROR	0x2U	/**< Command timeout flag */
-#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
-
-/**************************** Type Definitions *******************************/
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;			/**< Unique ID  of device */
-	u32 BaseAddress;		/**< Base address of the device */
-	u32 InputClockHz;		/**< Input clock frequency */
-	u32 CardDetect;			/**< Card Detect */
-	u32 WriteProtect;			/**< Write Protect */
-} XSdPs_Config;
-
-/* ADMA2 descriptor table */
-typedef struct {
-	u16 Attribute;		/**< Attributes of descriptor */
-	u16 Length;		/**< Length of current dma transfer */
-	u32 Address;		/**< Address of current dma transfer */
-} XSdPs_Adma2Descriptor;
-
-/**
- * The XSdPs driver instance data. The user is required to allocate a
- * variable of this type for every SD device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XSdPs_Config Config;	/**< Configuration structure */
-	u32 IsReady;		/**< Device is initialized and ready */
-	u32 Host_Caps;		/**< Capabilities of host controller */
-	u32 Host_CapsExt;	/**< Extended Capabilities */
-	u32 HCS;		/**< High capacity support in card */
-	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
-	u8  Card_Version;	/**< Card version */
-	u8  HC_Version;		/**< Host controller version */
-	u8  BusWidth;		/**< Current operating bus width */
-	u32 BusSpeed;		/**< Current operating bus speed */
-	u8  Switch1v8;		/**< 1.8V Switch support */
-	u32 CardID[4];		/**< Card ID Register */
-	u32 RelCardAddr;	/**< Relative Card Address */
-	u32 CardSpecData[4];	/**< Card Specific Data Register */
-	u32 SdCardConfig;	/**< Sd Card Configuration Register */
-	/**< ADMA Descriptors */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
-#pragma data_alignment = 4
-#else
-	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
-} XSdPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
-				u32 EffectiveAddr);
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
-s32 XSdPs_Select_Card (XSdPs *InstancePtr);
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Pullup(XSdPs *InstancePtr);
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c
deleted file mode 100644
index b5d2e4be8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c
+++ /dev/null
@@ -1,58 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xsdps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XSdPs_Config XSdPs_ConfigTable[] =
-{
-	{
-		XPAR_PSU_SD_1_DEVICE_ID,
-		XPAR_PSU_SD_1_BASEADDR,
-		XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
-		XPAR_PSU_SD_1_HAS_CD,
-		XPAR_PSU_SD_1_HAS_WP
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h
deleted file mode 100644
index c797e8216..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h
+++ /dev/null
@@ -1,1186 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v2_5
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or  macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ---    -------- -----------------------------------------------
-* 1.00a hk/sg  10/17/13 Initial release
-* 2.5 	sg	   07/09/15 Added SD 3.0 features
-*       kvn    07/15/15 Modified the code according to MISRAC-2012.
-* 2.7   sk     12/10/15 Added support for MMC cards.
-*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00U	/**< SDMA System Address
-							Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET	XSDPS_SDMA_SYS_ADDR_OFFSET
-						/**< SDMA System Address
-							Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET		0x00U	/**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET	0x02U	/**< SDMA System Address
-							High Register */
-#define XSDPS_ARGMT2_HI_OFFSET		0x02U	/**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET		0x04U	/**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET		0x06U	/**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET		0x08U	/**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET		XSDPS_ARGMT_OFFSET
-						/**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET		0x0AU	/**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET		0x0CU	/**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET		0x0EU	/**< Command Register */
-#define XSDPS_RESP0_OFFSET		0x10U	/**< Response0 Register */
-#define XSDPS_RESP1_OFFSET		0x14U	/**< Response1 Register */
-#define XSDPS_RESP2_OFFSET		0x18U	/**< Response2 Register */
-#define XSDPS_RESP3_OFFSET		0x1CU	/**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET	0x20U	/**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET		0x24U	/**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET		0x28U	/**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET		0x29U	/**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2AU	/**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2BU	/**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET		0x2CU	/**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2EU	/**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET		0x2FU	/**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 	0x30U	/**< Normal Interrupt
-							Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 	0x32U	/**< Error Interrupt
-							Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34U	/**< Normal Interrupt
-						Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36U	/**< Error Interrupt
-						Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38U	/**< Normal Interrupt
-						Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3AU	/**< Error Interrupt
-						Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3CU	/**< Auto CMD12 Error Status
-							Register */
-#define XSDPS_HOST_CTRL2_OFFSET		0x3EU	/**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 		0x40U	/**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 		0x44U	/**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48U	/**< Maximum Current
-						Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4CU	/**< Maximum Current
-						Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52U	/**< Force Event for
-						Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50U	/**< Auto CM12 Error Interrupt
-							Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET	0x54U	/**< ADMA Error Status
-							Register */
-#define XSDPS_ADMA_SAR_OFFSET		0x58U	/**< ADMA System Address
-							Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5CU	/**< ADMA System Address
-							Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET		0x60U	/**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET		0x64U	/**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET		0x68U	/**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET		0x6CU	/**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET	0x70U	/**< Boot timeout control
-							register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0U	/**< Shared Bus Control
-							Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET	0xFCU	/**< Slot Interrupt Status
-							Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET	0xFEU	/**< Host Controller Version
-							Register */
-
-/* @} */
-
-/** @name Control Register - Host control, Power control,
- * 			Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK		0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK		0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4		0x00000002U
-#define XSDPS_HC_SPEED_MASK		0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK		0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK		0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK		0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK		0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK	0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK		0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK		0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK		0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK		0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK		0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK		0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004U /**< Wakeup Card Removal */
-
-/* @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001U
-#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002U
-#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004U
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020U
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0U
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00U
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000U
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000U
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000U
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000U
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800U
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400U
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200U
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100U
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000U
-#define XSDPS_CC_MAX_DIV_CNT			256U
-#define XSDPS_CC_EXT_MAX_DIV_CNT		2046U
-#define XSDPS_CC_EXT_DIV_SHIFT			6U
-
-#define XSDPS_TC_CNTR_VAL_MASK			0x0000000FU
-
-#define XSDPS_SWRST_ALL_MASK			0x00000001U
-#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002U
-#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004U
-
-#define XSDPS_CC_MAX_NUM_OF_DIV		9U
-#define XSDPS_CC_DIV_SHIFT		8U
-
-/* @} */
-
-/** @name SD Interrupt Registers
- *
- * <b> Normal and Error Interrupt Status Register </b>
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * <b> Normal and Error Interrupt Status Enable Register </b>
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * <b> Normal and Error Interrupt Signal Enable Register </b>
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK		0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK		0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK		0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK		0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK		0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK		0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK	0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK		0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK		0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK		0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK		0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK	0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00002000U /**< Boot Ack Recv
-							Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK	0x00004000U /**< Boot Terminate
-							Interrupt */
-#define XSDPS_INTR_ERR_MASK		0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK		0x00000001U /**< Command Timeout
-							Error */
-#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK		0x00000004U /**< Command End Bit
-							Error */
-#define XSDPS_INTR_ERR_CI_MASK		0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK		0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK		0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK	0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK		0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000U /**< Vendor Specific
-							Error */
-#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FFU /**< Mask for error bits */
-/* @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK		0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024		0x400U
-#define XSDPS_BLK_SIZE_2048		0x800U
-#define XSDPS_BLK_CNT_MASK		0x0000FFFFU /**< Block Count for
-								Current Transfer */
-
-/* @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK		0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010U /**< Data Transfer
-							Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020U /**< Multi/Single
-							Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK		0x00000003U /**< Response Type
-							Select */
-#define XSDPS_CMD_RESP_NONE_MASK	0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK	0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK		0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003U /**< Response length 48 &
-							check busy after
-							response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008U /**< Command CRC Check
-							Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010U /**< Command Index Check
-							Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK		0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK			0x00003F00U /**< Command Index Mask -
-							Set to CMD0-63,
-							AMCD0-63 */
-
-/* @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
-							executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
-							Error */
-#define XSDPS_AUTO_CMD_CRC_MASK		0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK		0x0008U /**< Auto CMD End Bit
-							Error */
-#define XSDPS_AUTO_CMD_IND_MASK		0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
-							Auto CMD12 Error */
-/* @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK		0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK	0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK	0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK	0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK	0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK	0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK		0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK	0x0030U /**< Driver Strength
-							Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK	0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK	0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK	0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK	0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK		0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK	0x0080U /**< Sampling Clock
-							Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK	0x4000U /**< Asynchronous Interrupt
-							Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK	0x8000U /**< Preset Value Enable */
-
-/* @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003FU /**< Timeout clock freq
-							select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080U /**< Timeout clock unit -
-							MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK	0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK	0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK	0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK		0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK		0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000U /**< Suspend/Resume
-							support */
-#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000U /**< 64 bit system bus
-							support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK	0x08000000U /**< Interrupt mode
-							support */
-#define XSDPS_CAP_SPI_MODE_MASK		0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK	0x20000000U /**< Async Interrupt
-							support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK	0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD			0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT			0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS			0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK		0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK		0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK		0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK	0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK	0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK	0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK	0x00000F00U /**< Timer Count for
-							Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK	0x00002000U /**< SDR50 Mode needs
-							tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK	0x0000C000U /**< Re-tuning modes
-							support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK	0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK	0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK	0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK	0x00FF0000U /**< Clock Multiplier value
-							for Programmable clock
-							mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK	0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK	0x02000000U /**< SPI block mode */
-
-/* @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK	0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK		0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK		0x00080000U /**< Write protect switch
-								pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK	0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK	0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK	0x1E000000U /**< Data 7:4 signal lvl */
-
-/* @} */
-
-/** @name Maximum Current Capablities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK	0x00000F00U /**< Maximum Current
-							Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK	0x000000F0U /**< Maximum Current
-							Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK	0x0000000FU /**< Maximum Current
-							Capability at 3.3V */
-/* @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
-							executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
-							Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK	0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK	0x0008U /**< Auto CMD End Bit
-							Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK	0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
-							Auto CMD12 Error */
-/* @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK	0x0001U /**< Command Timeout
-							Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK	0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK	0x0004U /**< Command End Bit
-							Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK	0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK	0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK	0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK	0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK	0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK	0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK	0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK	0x1000U /**< Target Reponse */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK	0xE000U /**< Vendor Specific
-							Error */
-
-/* @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK	0x04U /**< ADMA Length Mismatch
-							Error */
-#define XSDPS_ADMA_ERR_STATE_MASK	0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK	0x00U /**< ADMA Error State
-							STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK	0x01U /**< ADMA Error State
-							FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK	0x03U /**< ADMA Error State
-							TFR */
-/* @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK	0x03FFU /**< SDCLK Frequency
-							Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK	0x0400U /**< Clock Generator
-							Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK	0xC000U /**< Driver Strength
-							Select Value */
-
-/* @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK	0x0007U /**< Interrupt Signal
-							mask */
-
-/* @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER		0xFF00U /**< Vendor
-							Specification
-							version mask */
-#define XSDPS_HC_SPEC_VER_MASK		0x00FFU /**< Host
-							Specification
-							version mask */
-#define XSDPS_HC_SPEC_V3		0x0002U
-#define XSDPS_HC_SPEC_V2		0x0001U
-#define XSDPS_HC_SPEC_V1		0x0000U
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK	0x200U
-
-/* @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-
-#define XSDPS_APP_CMD_PREFIX	 0x8000U
-#define CMD0	 0x0000U
-#define CMD1	 0x0100U
-#define CMD2	 0x0200U
-#define CMD3	 0x0300U
-#define CMD4	 0x0400U
-#define CMD5	 0x0500U
-#define CMD6	 0x0600U
-#define ACMD6	(XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7	 0x0700U
-#define CMD8	 0x0800U
-#define CMD9	 0x0900U
-#define CMD10	 0x0A00U
-#define CMD11	 0x0B00U
-#define CMD12	 0x0C00U
-#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16	 0x1000U
-#define CMD17	 0x1100U
-#define CMD18	 0x1200U
-#define CMD19	 0x1300U
-#define CMD21	 0x1500U
-#define CMD23	 0x1700U
-#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24	 0x1800U
-#define CMD25	 0x1900U
-#define CMD41	 0x2900U
-#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52	 0x3400U
-#define CMD55	 0x3700U
-#define CMD58	 0x3A00U
-
-#define RESP_NONE	(u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1		(u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
-			(u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B	(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
-			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2		(u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3		(u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6		(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
-			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/* @} */
-
-/* Card Interface Conditions Definitions */
-#define XSDPS_CIC_CHK_PATTERN	0xAAU
-#define XSDPS_CIC_VOLT_MASK	(0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6	(1U<<8)
-#define XSDPS_CIC_VOLT_LOW	(1U<<9)
-
-/* Operation Conditions Register Definitions */
-#define XSDPS_OCR_PWRUP_STS	(1U<<31)
-#define XSDPS_OCR_CC_STS	(1U<<30)
-#define XSDPS_OCR_S18		(1U<<24)
-#define XSDPS_OCR_3V5_3V6	(1U<<23)
-#define XSDPS_OCR_3V4_3V5	(1U<<22)
-#define XSDPS_OCR_3V3_3V4	(1U<<21)
-#define XSDPS_OCR_3V2_3V3	(1U<<20)
-#define XSDPS_OCR_3V1_3V2	(1U<<19)
-#define XSDPS_OCR_3V0_3V1	(1U<<18)
-#define XSDPS_OCR_2V9_3V0	(1U<<17)
-#define XSDPS_OCR_2V8_2V9	(1U<<16)
-#define XSDPS_OCR_2V7_2V8	(1U<<15)
-#define XSDPS_OCR_1V7_1V95	(1U<<7)
-#define XSDPS_OCR_HIGH_VOL	0x00FF8000U
-#define XSDPS_OCR_LOW_VOL	0x00000080U
-
-/* SD Card Configuration Register Definitions */
-#define XSDPS_SCR_REG_LEN		8U
-#define XSDPS_SCR_STRUCT_MASK		(0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK		(0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0		0U
-#define XSDPS_SCR_SPEC_1V1		(1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0		(2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE	(1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK		(7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE		0U
-#define XSDPS_SCR_SEC_SUPP_1V1		(2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0		(3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0		(4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK	(0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1		(1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4		(4U<<16)
-#define XSDPS_SCR_SPEC3_MASK		(1U<<12)
-#define XSDPS_SCR_SPEC3_2V0		0U
-#define XSDPS_SCR_SPEC3_3V0		(1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK		0x3U
-#define XSDPS_SCR_CMD23_SUPP		(1U<<1)
-#define XSDPS_SCR_CMD20_SUPP		(1U<<0)
-
-/* Card Status Register Definitions */
-#define XSDPS_CD_STS_OUT_OF_RANGE	(1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR		(1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR	(1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR		(1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR		(1U<<27)
-#define XSDPS_CD_STS_WP_VIO		(1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED		(1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL	(1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR	(1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD		(1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL	(1U<<21)
-#define XSDPS_CD_STS_CC_ERR		(1U<<20)
-#define XSDPS_CD_STS_ERR		(1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR		(1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP		(1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS	(1U<<14)
-#define XSDPS_CD_STS_ER_RST		(1U<<13)
-#define XSDPS_CD_STS_CUR_STATE		(0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA	(1U<<8)
-#define XSDPS_CD_STS_APP_CMD		(1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR	(1U<<2)
-
-/* Switch Function Definitions CMD6 */
-#define XSDPS_SWITCH_SD_RESP_LEN	64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH	(1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK		0U
-
-#define XSDPS_MODE_FUNC_GRP1		1U
-#define XSDPS_MODE_FUNC_GRP2		2U
-#define XSDPS_MODE_FUNC_GRP3		3U
-#define XSDPS_MODE_FUNC_GRP4		4U
-#define XSDPS_MODE_FUNC_GRP5		5U
-#define XSDPS_MODE_FUNC_GRP6		6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL		0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL	0xFFFFFFU
-
-#define XSDPS_ACC_MODE_DEF_SDR12	0U
-#define XSDPS_ACC_MODE_HS_SDR25		1U
-#define XSDPS_ACC_MODE_SDR50		2U
-#define XSDPS_ACC_MODE_SDR104		3U
-#define XSDPS_ACC_MODE_DDR50		4U
-
-#define XSDPS_CMD_SYS_ARG_SHIFT		4U
-#define XSDPS_CMD_SYS_DEF		0U
-#define XSDPS_CMD_SYS_eC		1U
-#define XSDPS_CMD_SYS_OTP		3U
-#define XSDPS_CMD_SYS_ASSD		4U
-#define XSDPS_CMD_SYS_VEND		5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT	8U
-#define XSDPS_DRV_TYPE_B		0U
-#define XSDPS_DRV_TYPE_A		1U
-#define XSDPS_DRV_TYPE_C		2U
-#define XSDPS_DRV_TYPE_D		3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT		12U
-#define XSDPS_CUR_LIM_200		0U
-#define XSDPS_CUR_LIM_400		1U
-#define XSDPS_CUR_LIM_600		2U
-#define XSDPS_CUR_LIM_800		3U
-
-#define CSD_SPEC_VER_MASK		0x3C0000U
-
-/* EXT_CSD field definitions */
-#define XSDPS_EXT_CSD_SIZE		512U
-
-#define EXT_CSD_WR_REL_PARAM_EN		(1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN     (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0     (0x4U)
-
-#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL          (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE          (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE        (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26    	(1U<<0)  /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52    	(1U<<1)  /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK  	0x3FU    /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1U<<2)   /* Card can run at 52MHz */
-                                             /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1U<<3)   /* Card can run at 52MHz */
-                                             /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V  \
-                                        | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V      (1U<<4)  /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V      (1U<<5)  /* Card can run at 200MHz */
-                                                /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE			183U
-#define EXT_CSD_BUS_WIDTH_1_BIT			0U	/* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT			1U	/* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT			2U	/* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT		5U	/* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT		6U	/* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE		185U
-#define EXT_CSD_HS_TIMING_DEF		0U
-#define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
-
-
-#define XSDPS_EXT_CSD_CMD_SET		0U
-#define XSDPS_EXT_CSD_SET_BITS		1U
-#define XSDPS_EXT_CSD_CLR_BITS		2U
-#define XSDPS_EXT_CSD_WRITE_BYTE	3U
-
-#define XSDPS_MMC_DEF_SPEED_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
-					| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG	(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
-					 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
-					 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
-					 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
-					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
-
-/* @} */
-
-/* @400KHz, in usec */
-#define XSDPS_74CLK_DELAY	2960U
-#define XSDPS_100CLK_DELAY	4000U
-#define XSDPS_INIT_DELAY	10000U
-
-#define XSDPS_DEF_VOLT_LVL	XSDPS_PC_BUS_VSEL_3V0_MASK
-#define XSDPS_CARD_DEF_ADDR	0x1234U
-
-#define XSDPS_CARD_SD		1U
-#define XSDPS_CARD_MMC		2U
-#define XSDPS_CARD_SDIO		3U
-#define XSDPS_CARD_SDCOMBO	4U
-#define XSDPS_CHIP_EMMC		5U
-
-
-/** @name ADMA2 Descriptor related definitions
- *
- * ADMA2 Descriptor related definitions
- * @{
- */
-
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID     	(0x1U << 0)
-#define XSDPS_DESC_END       	(0x1U << 1)
-#define XSDPS_DESC_INT       	(0x1U << 2)
-#define XSDPS_DESC_TRAN  	(0x2U << 4)
-
-/* @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ		400000U		/**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ		50000000U	/**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ		52000000U	/**< 52 MHZ */
-#define XSDPS_SD_VER_1_0		0x1U		/**< SD ver 1 */
-#define XSDPS_SD_VER_2_0		0x2U		/**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT	1U
-#define XSDPS_SCR_BLKSIZE	8U
-#define XSDPS_1_BIT_WIDTH	0x1U
-#define XSDPS_4_BIT_WIDTH	0x2U
-#define XSDPS_8_BIT_WIDTH	0x3U
-#define XSDPS_UHS_SPEED_MODE_SDR12	0x0U
-#define XSDPS_UHS_SPEED_MODE_SDR25	0x1U
-#define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
-#define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
-#define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
-#define XSDPS_SWITCH_CMD_BLKCNT		1U
-#define XSDPS_SWITCH_CMD_BLKSIZE	64U
-#define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
-#define XSDPS_SWITCH_CMD_HS_SET		0x80FFFFF1U
-#define XSDPS_SWITCH_CMD_SDR12_SET		0x80FFFFF0U
-#define XSDPS_SWITCH_CMD_SDR25_SET		0x80FFFFF1U
-#define XSDPS_SWITCH_CMD_SDR50_SET		0x80FFFFF2U
-#define XSDPS_SWITCH_CMD_SDR104_SET		0x80FFFFF3U
-#define XSDPS_SWITCH_CMD_DDR50_SET		0x80FFFFF4U
-#define XSDPS_EXT_CSD_CMD_BLKCNT	1U
-#define XSDPS_EXT_CSD_CMD_BLKSIZE	512U
-#define XSDPS_TUNING_CMD_BLKCNT		1U
-#define XSDPS_TUNING_CMD_BLKSIZE	64U
-
-#define XSDPS_HIGH_SPEED_MAX_CLK	50000000U
-#define XSDPS_UHS_SDR104_MAX_CLK	208000000U
-#define XSDPS_UHS_SDR50_MAX_CLK		100000000U
-#define XSDPS_UHS_DDR50_MAX_CLK		50000000U
-#define XSDPS_UHS_SDR25_MAX_CLK		50000000U
-#define XSDPS_UHS_SDR12_MAX_CLK		25000000U
-
-#define SD_DRIVER_TYPE_B	0x01U
-#define SD_DRIVER_TYPE_A	0x02U
-#define SD_DRIVER_TYPE_C	0x04U
-#define SD_DRIVER_TYPE_D	0x08U
-#define SD_SET_CURRENT_LIMIT_200	0U
-#define SD_SET_CURRENT_LIMIT_400	1U
-#define SD_SET_CURRENT_LIMIT_600	2U
-#define SD_SET_CURRENT_LIMIT_800	3U
-
-#define SD_MAX_CURRENT_200	(1U << SD_SET_CURRENT_LIMIT_200)
-#define SD_MAX_CURRENT_400	(1U << SD_SET_CURRENT_LIMIT_400)
-#define SD_MAX_CURRENT_600	(1U << SD_SET_CURRENT_LIMIT_600)
-#define SD_MAX_CURRENT_800	(1U << SD_SET_CURRENT_LIMIT_800)
-
-#define XSDPS_SD_SDR12_MAX_CLK	25000000U
-#define XSDPS_SD_SDR25_MAX_CLK	50000000U
-#define XSDPS_SD_SDR50_MAX_CLK	100000000U
-#define XSDPS_SD_DDR50_MAX_CLK	50000000U
-#define XSDPS_SD_SDR104_MAX_CLK	208000000U
-#define XSDPS_MMC_HS200_MAX_CLK	200000000U
-
-#define XSDPS_CARD_STATE_IDLE		0U
-#define XSDPS_CARD_STATE_RDY		1U
-#define XSDPS_CARD_STATE_IDEN		2U
-#define XSDPS_CARD_STATE_STBY		3U
-#define XSDPS_CARD_STATE_TRAN		4U
-#define XSDPS_CARD_STATE_DATA		5U
-#define XSDPS_CARD_STATE_RCV		6U
-#define XSDPS_CARD_STATE_PROG		7U
-#define XSDPS_CARD_STATE_DIS		8U
-#define XSDPS_CARD_STATE_BTST		9U
-#define XSDPS_CARD_STATE_SLP		10U
-
-#define XSDPS_SLOT_REM			0U
-#define XSDPS_SLOT_EMB			1U
-
-#if defined (__arm__) || defined (__aarch64__)
-#define SD_DLL_CTRL 			0x00000358U
-#define SD_ITAPDLY				0x00000314U
-#define SD_OTAPDLYSEL			0x00000318U
-#define SD0_DLL_RST				0x00000004U
-#define SD0_ITAPCHGWIN			0x00000200U
-#define SD0_ITAPDLYENA			0x00000100U
-#define SD0_OTAPDLYENA			0x00000040U
-#define SD0_OTAPDLYSEL_HS200	0x00000003U
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64
-#define XSdPs_Out64 Xil_Out64
-
-#define XSdPs_In32 Xil_In32
-#define XSdPs_Out32 Xil_Out32
-
-#define XSdPs_In16 Xil_In16
-#define XSdPs_Out16 Xil_Out16
-
-#define XSdPs_In8 Xil_In8
-#define XSdPs_Out8 Xil_Out8
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to the target register.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
-	XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to target register.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-*		u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
-	XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
-		(RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to the target register.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
-	XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to target register.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-*		u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
-	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to the target register.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
-	XSdPs_In16((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to target register.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-*		u16 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
-	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to the target register.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
-	XSdPs_In8((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to target register.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-*		u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
-	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
-
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-*		u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
-		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c
deleted file mode 100644
index 8151eef1b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c
+++ /dev/null
@@ -1,1152 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps_options.c
-* @addtogroup sdps_v2_5
-* @{
-*
-* Contains API's for changing the various options in host and card.
-* See xsdps.h for a detailed description of the device and driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ---    -------- -----------------------------------------------
-* 1.00a hk/sg  10/17/13 Initial release
-* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
-*                       Add sleep for microblaze designs. CR# 781117.
-* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
-*						clock.CR# 816586.
-* 2.5 	sg	   07/09/15 Added SD 3.0 features
-*       kvn    07/15/15 Modified the code according to MISRAC-2012.
-* 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
-*                       of SDR50, SDR104 and HS200.
-*       sk     02/16/16 Corrected the Tuning logic.
-*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps.h"
-/*
- * The header sleep.h and API usleep() can only be used with an arm design.
- * MB_Sleep() is used for microblaze design.
- */
-#if defined (__arm__) || defined (__aarch64__)
-
-#include "sleep.h"
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-#include "microblaze_sleep.h"
-
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
-static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
-s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
-#if defined (__arm__) || defined (__aarch64__)
-void XSdPs_SetTapDelay(XSdPs *InstancePtr);
-#endif
-
-/*****************************************************************************/
-/**
-* Update Block size for read/write operations.
-*
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	BlkSize - Block size passed by the user.
-*
-* @return	None
-*
-******************************************************************************/
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
-{
-	s32 Status;
-	u32 PresentStateReg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_PRES_STATE_OFFSET);
-
-	if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
-			(u32)XSDPS_PSR_INHIBIT_DAT_MASK |
-			(u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-
-	/* Send block write command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-
-	/* Set block size to the value passed */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
-			 BlkSize & XSDPS_BLK_SIZE_MASK);
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to get bus width support by card.
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	SCR - buffer to store SCR register returned by card.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
-{
-	s32 Status;
-	u32 StatusReg;
-	u16 BlkCnt;
-	u16 BlkSize;
-	s32 LoopCnt;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
-		SCR[LoopCnt] = 0U;
-	}
-
-	/* Send block write command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-			InstancePtr->RelCardAddr, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	BlkCnt = XSDPS_SCR_BLKCNT;
-	BlkSize = XSDPS_SCR_BLKSIZE;
-
-	/* Set block size to the value passed */
-	BlkSize &= XSDPS_BLK_SIZE_MASK;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
-	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
-
-	Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
-
-	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * Check for transfer complete
-	 * Polling for response for now
-	 */
-	do {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET);
-		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-			/* Write to clear error bits */
-			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_ERR_INTR_STS_OFFSET,
-					XSDPS_ERROR_INTR_ALL_MASK);
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-	/* Write to clear bit */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set bus width to 4-bit in card and host
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
-{
-	s32 Status;
-	u32 StatusReg;
-	u32 Arg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
-	if (InstancePtr->CardType == XSDPS_CARD_SD) {
-
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
-				0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
-
-		Arg = ((u32)InstancePtr->BusWidth);
-
-		Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} else {
-
-		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
-				&& (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
-			/* in case of eMMC data width 8-bit */
-			InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
-		} else {
-			InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
-		}
-
-		if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
-			Arg = XSDPS_MMC_8_BIT_BUS_ARG;
-		} else {
-			Arg = XSDPS_MMC_4_BIT_BUS_ARG;
-		}
-
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/* Check for transfer complete */
-		do {
-			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_NORM_INTR_STS_OFFSET);
-			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-				/* Write to clear error bits */
-				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_ERR_INTR_STS_OFFSET,
-						XSDPS_ERROR_INTR_ALL_MASK);
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-		/* Write to clear bit */
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-	}
-
-#if defined (__arm__) || defined (__aarch64__)
-
-	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-	/* 2 msec delay */
-	MB_Sleep(2);
-
-#endif
-
-	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-					XSDPS_HOST_CTRL1_OFFSET);
-
-	/* Width setting in controller */
-	if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
-		StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
-	} else {
-		StatusReg |= XSDPS_HC_WIDTH_MASK;
-	}
-
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL1_OFFSET,
-			(u8)StatusReg);
-
-	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to get bus speed supported by card.
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	ReadBuff - buffer to store function group support data
-*		returned by card.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
-{
-	s32 Status;
-	u32 StatusReg;
-	u32 Arg;
-	u16 BlkCnt;
-	u16 BlkSize;
-	s32 LoopCnt;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
-		ReadBuff[LoopCnt] = 0U;
-	}
-
-	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
-	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
-	BlkSize &= XSDPS_BLK_SIZE_MASK;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
-	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
-
-	Arg = XSDPS_SWITCH_CMD_HS_GET;
-
-	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
-
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * Check for transfer complete
-	 * Polling for response for now
-	 */
-	do {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET);
-		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-			/* Write to clear error bits */
-			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_ERR_INTR_STS_OFFSET,
-					XSDPS_ERROR_INTR_ALL_MASK);
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-	/* Write to clear bit */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set high speed in card and host. Changes clock in host accordingly.
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
-{
-	s32 Status;
-	u32 StatusReg;
-	u32 Arg;
-	u32 ClockReg;
-	u16 BlkCnt;
-	u16 BlkSize;
-	u8 ReadBuff[64];
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	if (InstancePtr->CardType == XSDPS_CARD_SD) {
-
-		BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
-		BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
-		BlkSize &= XSDPS_BLK_SIZE_MASK;
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
-		XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
-		Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
-
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_XFER_MODE_OFFSET,
-				XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
-
-		Arg = XSDPS_SWITCH_CMD_HS_SET;
-
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/*
-		 * Check for transfer complete
-		 * Polling for response for now
-		 */
-		do {
-			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_NORM_INTR_STS_OFFSET);
-			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-				/* Write to clear error bits */
-				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_ERR_INTR_STS_OFFSET,
-						XSDPS_ERROR_INTR_ALL_MASK);
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-		/* Write to clear bit */
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-		/* Change the clock frequency to 50 MHz */
-		InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-		if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-		}
-
-	} else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
-		Arg = XSDPS_MMC_HIGH_SPEED_ARG;
-
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/*
-		 * Check for transfer complete
-		 */
-		do {
-			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_NORM_INTR_STS_OFFSET);
-			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-				/*
-				 * Write to clear error bits
-				 */
-				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_ERR_INTR_STS_OFFSET,
-						XSDPS_ERROR_INTR_ALL_MASK);
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-		/*
-		 * Write to clear bit
-		 */
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-		/* Change the clock frequency to 52 MHz */
-		InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
-		Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} else {
-		Arg = XSDPS_MMC_HS200_ARG;
-
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		/*
-		 * Check for transfer complete
-		 */
-		do {
-			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_NORM_INTR_STS_OFFSET);
-			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-				/*
-				 * Write to clear error bits
-				 */
-				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-						XSDPS_ERR_INTR_STS_OFFSET,
-						XSDPS_ERROR_INTR_ALL_MASK);
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-			}
-		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-		/*
-		 * Write to clear bit
-		 */
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-		/* Change the clock frequency to 200 MHz */
-		InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
-
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-		Status = XSdPs_Execute_Tuning(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-#if defined (__arm__) || defined (__aarch64__)
-		/* Program the Tap delays */
-		XSdPs_SetTapDelay(InstancePtr);
-#endif
-	}
-
-#if defined (__arm__) || defined (__aarch64__)
-
-	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-	/* 2 msec delay */
-	MB_Sleep(2);
-
-#endif
-
-	StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-					XSDPS_HOST_CTRL1_OFFSET);
-	StatusReg |= XSDPS_HC_SPEED_MASK;
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
-
-	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to change clock freq to given value.
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	SelFreq - Clock frequency in Hz.
-*
-* @return	None
-*
-* @note		This API will change clock frequency to the value less than
-*		or equal to the given value using the permissible dividors.
-*
-******************************************************************************/
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
-{
-	u16 ClockReg;
-	u16 DivCnt;
-	u16 Divisor = 0U;
-	u16 ExtDivisor;
-	u16 ClkLoopCnt;
-	s32 Status;
-	u16 ReadReg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Disable clock */
-	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_CLK_CTRL_OFFSET);
-	ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_CLK_CTRL_OFFSET, ClockReg);
-
-	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
-		/* Calculate divisor */
-		for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
-			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
-				Divisor = DivCnt >> 1;
-				break;
-			}
-		}
-
-		if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
-			/* No valid divisor found for given frequency */
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} else {
-		/* Calculate divisor */
-		DivCnt = 0x1U;
-		while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
-			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
-				Divisor = DivCnt / 2U;
-				break;
-			}
-			DivCnt = DivCnt << 1U;
-		}
-
-		if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
-			/* No valid divisor found for given frequency */
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	}
-
-	/* Set clock divisor */
-	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
-		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_CLK_CTRL_OFFSET);
-		ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
-		XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
-
-		ExtDivisor = Divisor >> 8;
-		ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
-		ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
-
-		Divisor <<= XSDPS_CC_DIV_SHIFT;
-		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
-		ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
-				ClockReg);
-	} else {
-		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_CLK_CTRL_OFFSET);
-		ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
-
-		Divisor <<= XSDPS_CC_DIV_SHIFT;
-		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
-		ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
-				ClockReg);
-	}
-
-	/* Wait for internal clock to stabilize */
-	ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_CLK_CTRL_OFFSET);
-	while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
-		ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_CLK_CTRL_OFFSET);;
-	}
-
-	/* Enable SD clock */
-	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_CLK_CTRL_OFFSET);
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_CLK_CTRL_OFFSET,
-			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
-
-	Status = XST_SUCCESS;
-
-RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to send pullup command to card before using DAT line 3(using 4-bit bus)
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Pullup(XSdPs *InstancePtr)
-{
-	s32 Status;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-			InstancePtr->RelCardAddr, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to get EXT_CSD register of eMMC.
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	ReadBuff - buffer to store EXT_CSD
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
-{
-	s32 Status;
-	u32 StatusReg;
-	u32 Arg = 0U;
-	u16 BlkCnt;
-	u16 BlkSize;
-	s32 LoopCnt;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
-		ReadBuff[LoopCnt] = 0U;
-	}
-
-	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
-	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
-	BlkSize &= XSDPS_BLK_SIZE_MASK;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
-	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
-	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
-
-
-	/* Send SEND_EXT_CSD command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * Check for transfer complete
-	 * Polling for response for now
-	 */
-	do {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_NORM_INTR_STS_OFFSET);
-		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-			/* Write to clear error bits */
-			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_ERR_INTR_STS_OFFSET,
-					XSDPS_ERROR_INTR_ALL_MASK);
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-	/* Write to clear bit */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XSDPS_RESP0_OFFSET);
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-
-}
-
-
-/*****************************************************************************/
-/**
-*
-* API to UHS-I mode initialization
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	Mode UHS-I mode
-*
-* @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*
-* @note		None.
-*
-******************************************************************************/
-s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
-{
-	s32 Status;
-	u16 StatusReg;
-	u16 CtrlReg;
-	u32 Arg;
-	u16 BlkCnt;
-	u16 BlkSize;
-	u8 ReadBuff[64];
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Drive strength */
-
-	/* Bus speed mode selection */
-	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
-	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
-	BlkSize &= XSDPS_BLK_SIZE_MASK;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
-			BlkSize);
-
-	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
-	Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
-
-	switch (Mode) {
-	case 0U:
-		Arg = XSDPS_SWITCH_CMD_SDR12_SET;
-		InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
-		break;
-	case 1U:
-		Arg = XSDPS_SWITCH_CMD_SDR25_SET;
-		InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
-		break;
-	case 2U:
-		Arg = XSDPS_SWITCH_CMD_SDR50_SET;
-		InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
-		break;
-	case 3U:
-		Arg = XSDPS_SWITCH_CMD_SDR104_SET;
-		InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
-		break;
-	case 4U:
-		Arg = XSDPS_SWITCH_CMD_DDR50_SET;
-		InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
-		break;
-	default:
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-		break;
-	}
-
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * Check for transfer complete
-	 * Polling for response for now
-	 */
-	do {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_NORM_INTR_STS_OFFSET);
-		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
-			/* Write to clear error bits */
-			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
-	/* Write to clear bit */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-
-	/* Current limit */
-
-	/* Set UHS mode in controller */
-	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL2_OFFSET);
-	CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
-	CtrlReg |= Mode;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
-
-	/* Change the clock frequency */
-	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-	if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-	}
-
-	if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
-			(Mode == XSDPS_UHS_SPEED_MODE_DDR50)) {
-		/* Send tuning pattern */
-		Status = XSdPs_Execute_Tuning(InstancePtr);
-		if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
-				goto RETURN_PATH;
-		}
-	}
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH:
-		return Status;
-}
-
-static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
-{
-	s32 Status;
-	u32 StatusReg;
-	u32 Arg;
-	u16 BlkCnt;
-	u16 BlkSize;
-	s32 LoopCnt;
-	u16 CtrlReg;
-	u8 TuningCount;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	BlkCnt = XSDPS_TUNING_CMD_BLKCNT;
-	BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
-	if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
-	{
-		BlkSize = BlkSize*2U;
-	}
-	BlkSize &= XSDPS_BLK_SIZE_MASK;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
-			BlkSize);
-
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
-			XSDPS_TM_DAT_DIR_SEL_MASK);
-
-	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_HOST_CTRL2_OFFSET);
-	CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
-
-	for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
-
-		if (InstancePtr->CardType == XSDPS_CARD_SD) {
-			Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
-		} else {
-			Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
-		}
-
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
-		}
-
-		if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
-			break;
-		}
-	}
-
-	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
-	}
-
-	/*
-	 * As per controller erratum, program the "SDCLK Frequency
-	 * Select" of clock control register with a value, say
-	 * clock/2. Wait for the Internal clock stable and program
-	 * the desired frequency.
-	 */
-	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_HOST_CTRL2_OFFSET);
-	if ((CtrlReg & XSDPS_HC2_SAMP_CLK_SEL_MASK) != 0U) {
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed/2);
-		if (Status != XST_SUCCESS) {
-			goto RETURN_PATH ;
-		}
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-		if (Status != XST_SUCCESS) {
-			goto RETURN_PATH ;
-		}
-
-	}
-
-	Status = XST_SUCCESS;
-
-	RETURN_PATH: return Status;
-
-}
-
-#if defined (__arm__) || defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* API to set Tap Delay w.r.t speed modes
-*
-*
-* @param	InstancePtr is a pointer to the XSdPs instance.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-void XSdPs_SetTapDelay(XSdPs *InstancePtr)
-{
-	u32 DllCtrl, TapDelay;
-	if (InstancePtr->Config.DeviceId == XPAR_XSDPS_0_DEVICE_ID) {
-		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
-		DllCtrl |= SD0_DLL_RST;
-		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-		if(InstancePtr->BusSpeed == XSDPS_MMC_HS200_MAX_CLK) {
-			/* Program the ITAPDLY */
-			TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
-			TapDelay |= SD0_ITAPCHGWIN;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
-			TapDelay |= SD0_ITAPDLYENA;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
-			TapDelay &= ~SD0_ITAPCHGWIN;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
-			/* Program the OTAPDLY */
-			TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL);
-			TapDelay |= SD0_OTAPDLYENA;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
-			TapDelay |= SD0_OTAPDLYSEL_HS200;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
-		}
-		DllCtrl &= ~SD0_DLL_RST;
-		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-	}
-}
-#endif
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c
deleted file mode 100644
index 59657a7b3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps_sinit.c
-* @addtogroup sdps_v2_5
-* @{
-*
-* The implementation of the XSdPs component's static initialization
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ---    -------- -----------------------------------------------
-* 1.00a hk/sg  10/17/13 Initial release
-*       kvn    07/15/15 Modified the code according to MISRAC-2012.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xstatus.h"
-#include "xsdps.h"
-#include "xparameters.h"
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XSdPs_Config XSdPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param	DeviceId contains the ID of the device to look up the
-*		configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xsdps.h for the definition of XSdPs_Config.
-*
-* @note		None.
-*
-******************************************************************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
-{
-	XSdPs_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
-		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XSdPs_ConfigTable[Index];
-			break;
-		}
-	}
-	return (XSdPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile
new file mode 100644
index 000000000..f57081af6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c
new file mode 100644
index 000000000..ac3f9469e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c
@@ -0,0 +1,1559 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN	0x1AAU
+#define XSDPS_RESPOCR_READY	0x80000000U
+#define XSDPS_ACMD41_HCS	0x40000000U
+#define XSDPS_ACMD41_3V3	0x00300000U
+#define XSDPS_CMD1_HIGH_VOL	0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL	0x00FF8010U
+#define HIGH_SPEED_SUPPORT	0x2U
+#define WIDTH_4_BIT_SUPPORT	0x4U
+#define SD_CLK_25_MHZ		25000000U
+#define SD_CLK_19_MHZ		19000000U
+#define SD_CLK_26_MHZ		26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE	196U
+#define EXT_CSD_SEC_COUNT	212U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200		0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200		0x20U
+#define CSD_SPEC_VER_3		0x3U
+
+/* Note: Remove this once fixed */
+#define UHS_BROKEN
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+#ifndef UHS_BROKEN
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SD device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		This function initializes the host controller.
+*		Initial clock of 400KHz is set.
+*		Voltage of 3.3V is selected as that is supported by host.
+*		Interrupts status is enabled and signal disabled by default.
+*		Default data direction is card to host and
+*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	u8 PowerLevel;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/* Set some default values. */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
+	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
+	InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+	InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+	InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+	InstancePtr->SectorCount = 0;
+	InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+	InstancePtr->Config_TapDelay = NULL;
+
+	/* Disable bus power and issue emmc hw reset */
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+			XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, 0x0);
+
+	/* Delay to poweroff card */
+    (void)usleep(1000U);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_ALL_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	}
+	/* Host Controller version is read. */
+	 InstancePtr->HC_Version =
+			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+	/*
+	 * Read capabilities register and update it in Instance pointer.
+	 * It is sufficient to read this once on power on.
+	 */
+	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_CAPS_OFFSET);
+
+	/* Select voltage and enable bus power. */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				(XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+				~XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	/* Delay before issuing the command after emmc reset */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+				XSDPS_CAPS_EMB_SLOT)
+			usleep(200);
+
+	/* Change the clock frequency to 400 KHz */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH ;
+	}
+
+    if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+	} else {
+		PowerLevel = 0U;
+	}
+
+	/* Select voltage based on capability and enable bus power. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+	/* Enable ADMA2 in 64bit mode. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_32_MASK);
+
+	/* Enable all interrupt status except card interrupt initially */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_EN_OFFSET,
+			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_EN_OFFSET,
+			XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* Disable all interrupt signals by default. */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+	/*
+	 * Transfer mode register - default value
+	 * DMA enabled, block count enabled, data direction card to host(read)
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	/* Set block size to 512 by default */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+			   initialization cycle failed
+*
+* @note		This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD8 and ACDM41 are sent to identify voltage and
+*		high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 Arg;
+	u8 ReadReg;
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * CMD8; response expected
+	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+			XSDPS_CMD8_VOL_PATTERN, 0U);
+	if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (Status == XSDPS_CT_ERROR) {
+		 /* "Software reset for all" is initiated */
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+				XSDPS_SWRST_CMD_LINE_MASK);
+
+		/* Proceed with initialization only after reset is complete */
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+			ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		}
+	}
+
+	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_RESP0_OFFSET);
+	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+		InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+	}
+	else {
+		InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+	}
+
+	RespOCR = 0U;
+	/* Send ACMD41 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+        Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		    Arg |= XSDPS_OCR_S18;
+		}
+
+		/* 0x40300000 - Host High Capacity support & 3.3V window */
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+				Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */
+#ifndef UHS_BROKEN
+    if ((RespOCR & XSDPS_OCR_S18) != 0U) {
+		InstancePtr->Switch1v8 = 1U;
+		Status = XSdPs_Switch_Voltage(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+#endif
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+	do {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Relative card address is stored as the upper 16 bits
+		 * This is to avoid shifting when sending commands
+		 */
+		InstancePtr->RelCardAddr =
+				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+	} while (InstancePtr->RelCardAddr == 0U);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+		BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+		Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+		DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+		DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+		DeviceSize = (DeviceSize + 1U) * Mult;
+		DeviceSize =  DeviceSize * BlkLen;
+		InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+	} else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+		InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+										1U) * 1024U;
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+*			   initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+static u8 ExtCsd[512];
+#pragma data_alignment = 4
+#else
+static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+#endif
+	u8 SCR[8] = { 0U };
+	u8 ReadBuff[64] = { 0U };
+	s32 Status;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Default settings */
+	InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+	InstancePtr->CardType = XSDPS_CARD_SD;
+	InstancePtr->Switch1v8 = 0U;
+	InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+			== XSDPS_CAPS_EMB_SLOT)) {
+		InstancePtr->CardType = XSDPS_CHIP_EMMC;
+	} else {
+		Status = XSdPs_IdentifyCard(InstancePtr);
+		if (Status == XST_FAILURE) {
+			goto RETURN_PATH;
+		}
+	}
+
+	if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+		(InstancePtr->CardType != XSDPS_CARD_MMC) &&
+		(InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		Status = XSdPs_SdCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Change clock to default clock 25MHz */
+		/*
+		 * SD default speed mode timing should be closed at 19 MHz.
+		 * The reason for this is SD requires a voltage level shifter.
+		 * This limitation applies to ZynqMPSoC.
+		 */
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+			InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+		else
+			InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	} else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+			|| (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+		Status = XSdPs_MmcCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+		/* Change clock to default clock 26MHz */
+		InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_Select_Card(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		/* Pull-up disconnected during data transfer */
+		Status = XSdPs_Pullup(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+			Status = XSdPs_Change_BusWidth(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+
+		/* Get speed supported by device */
+		Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+		if (Status != XST_SUCCESS) {
+			goto RETURN_PATH;
+		}
+
+#if defined (ARMR5) || defined (__aarch64__)
+		if ((InstancePtr->Switch1v8 != 0U) &&
+				(InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) {
+
+			/* Identify the UHS mode supported by card */
+			XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
+			/* Set UHS-I SDR104 mode */
+			Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
+			if (Status != XST_SUCCESS) {
+				goto RETURN_PATH;
+			}
+
+		} else {
+#endif
+			/*
+			 * card supports CMD6 when SD_SPEC field in SCR register
+			 * indicates that the Physical Layer Specification Version
+			 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+			 */
+			if (SCR[0] != 0U) {
+				/* Check for high speed support */
+				if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) {
+					InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__)
+					InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+					Status = XSdPs_Change_BusSpeed(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+#if defined (ARMR5) || defined (__aarch64__)
+		}
+#endif
+
+	} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+				(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+				(InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT];
+
+		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	} else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+		/* Change bus width to 8-bit */
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Get Extended CSD */
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT];
+
+		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+				EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) {
+			InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__)
+			InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+#endif
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+
+		/* Enable Rst_n_Fun bit if it is disabled */
+		if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+			Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+			Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* 74 CLK delay after card is powered up, before the first command. */
+	usleep(XSDPS_INIT_DELAY);
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Host High Capacity support & High voltage window */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+			XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->CardType = XSDPS_CARD_SD;
+	} else {
+		InstancePtr->CardType = XSDPS_CARD_MMC;
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_CMD_LINE_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+#ifndef UHS_BROKEN
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 CtrlReg;
+	u32 ReadReg;
+
+	/* Send switch voltage command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+	}
+
+	/* Wait for CMD and DATA line to go low */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+					XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+	/* Stop the clock */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+			CtrlReg);
+
+	/* Wait minimum 5mSec */
+	(void)usleep(5000U);
+
+	/* Enabling 1.8V in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+			CtrlReg);
+
+	/* Start clock */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for CMD and DATA line to go high */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+			!= (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+RETURN_PATH:
+	return Status;
+}
+#endif
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cmd is the command to be sent.
+* @param	Arg is the argument to be sent along with the command.
+* 		This could be address or any other information
+* @param	BlkCnt - Block count passed by the user.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 			is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+	u32 PresentStateReg;
+	u32 CommandReg;
+	u32 StatusReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the command inhibit to make sure no other
+	 * command transfer is in progress
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Write block count register */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+	/* Write argument register */
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSDPS_ARGMT_OFFSET, Arg);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+	/* Command register is set to trigger transfer of command */
+	CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+	/*
+	 * Mask to avoid writing to reserved bits 31-30
+	 * This is necessary because 0x80000000 is used  by this software to
+	 * distinguish between ACMD and CMD of same number
+	 */
+	CommandReg = CommandReg & 0x3FFFU;
+
+	/*
+	 * Check for data inhibit in case of command using DAT lines.
+	 * For Tuning Commands DAT lines check can be ignored.
+	 */
+	if ((Cmd != CMD21) && (Cmd != CMD19)) {
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+									XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+				((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
+			(u16)CommandReg);
+
+	/* Polling for response for now */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((Cmd == CMD21) || (Cmd == CMD19)) {
+			if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+				break;
+			}
+		}
+
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+									XSDPS_ERR_INTR_STS_OFFSET);
+			if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
+				Status = XSDPS_CT_ERROR;
+			}
+			 /* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET,
+			XSDPS_INTR_CC_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param	Command to be sent.
+*
+* @return	Command register value complete with response type and
+* 		data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+		u32 RetVal;
+
+		RetVal = Cmd;
+
+		switch(Cmd) {
+		case CMD0:
+			RetVal |= RESP_NONE;
+		break;
+		case CMD1:
+			RetVal |= RESP_R3;
+		break;
+		case CMD2:
+			RetVal |= RESP_R2;
+		break;
+		case CMD3:
+			RetVal |= RESP_R6;
+		break;
+		case CMD4:
+			RetVal |= RESP_NONE;
+			break;
+		case CMD5:
+			RetVal |= RESP_R1B;
+		break;
+		case CMD6:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			} else {
+				RetVal |= RESP_R1B;
+			}
+			break;
+		case ACMD6:
+			RetVal |= RESP_R1;
+		break;
+		case CMD7:
+			RetVal |= RESP_R1;
+		break;
+		case CMD8:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1;
+			} else {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			}
+			break;
+		case CMD9:
+			RetVal |= RESP_R2;
+		break;
+		case CMD11:
+		case CMD10:
+		case CMD12:
+		case ACMD13:
+		case CMD16:
+			RetVal |= RESP_R1;
+		break;
+		case CMD17:
+		case CMD18:
+		case CMD19:
+		case CMD21:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD23:
+		case ACMD23:
+		case CMD24:
+		case CMD25:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		case ACMD41:
+			RetVal |= RESP_R3;
+		break;
+		case ACMD42:
+			RetVal |= RESP_R1;
+		break;
+		case ACMD51:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD52:
+		case CMD55:
+			RetVal |= RESP_R1;
+		break;
+		case CMD58:
+		break;
+		default :
+			RetVal |= Cmd;
+		break;
+		}
+
+		return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
+
+	Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	/* Send block read command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Check for transfer complete */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+	Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+	s32 Status = 0;
+
+	/* Send CMD7 - Select card */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	BlkCnt - block count.
+* @param	Buff pointer to data buffer.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+	u32 TotalDescLines = 0U;
+	u32 DescNum = 0U;
+	u32 BlkSize = 0U;
+
+	/* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_BLK_SIZE_OFFSET);
+	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+		TotalDescLines = 1U;
+
+	}else {
+
+		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+		if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+			TotalDescLines += 1U;
+		}
+
+	}
+
+	for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+		/* This will write '0' to length field which indicates 65536 */
+		InstancePtr->Adma2_DescrTbl[DescNum].Length =
+				(u16)XSDPS_DESC_MAX_LENGTH;
+	}
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+			(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+			(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+	Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+			sizeof(XSdPs_Adma2Descriptor) * 32U);
+
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) MMC is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the initialization
+*			   cycle failed
+* @note 	This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD1 sent to identify voltage and high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = 0U;
+	/* Send CMD1 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+		/* Host High Capacity support & High volage window */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	/* Set relative card address */
+	InstancePtr->RelCardAddr = 0x12340000U;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	InstancePtr->Card_Version =  (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
+
+	/* Calculating the memory capacity */
+	BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+	Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+	DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+	DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+	DeviceSize = (DeviceSize + 1U) * Mult;
+	DeviceSize =  DeviceSize * BlkLen;
+
+	InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h
new file mode 100644
index 000000000..46fe545d9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h
@@ -0,0 +1,257 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v2_5
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR	0x2U	/**< Command timeout flag */
+#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+	u32 CardDetect;			/**< Card Detect */
+	u32 WriteProtect;			/**< Write Protect */
+	u32 BusWidth;			/**< Bus Width */
+	u32 BankNumber;			/**< MIO Bank selection for SD */
+	u32 HasEMIO;			/**< If SD is connected to EMIO */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+	u32 Address;		/**< Address of current dma transfer */
+} XSdPs_Adma2Descriptor;
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 Host_CapsExt;	/**< Extended Capabilities */
+	u32 HCS;		/**< High capacity support in card */
+	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
+	u8  Card_Version;	/**< Card version */
+	u8  HC_Version;		/**< Host controller version */
+	u8  BusWidth;		/**< Current operating bus width */
+	u32 BusSpeed;		/**< Current operating bus speed */
+	u8  Switch1v8;		/**< 1.8V Switch support */
+	u32 CardID[4];		/**< Card ID Register */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	u32 CardSpecData[4];	/**< Card Specific Data Register */
+	u32 SectorCount;		/**< Sector Count */
+	u32 SdCardConfig;	/**< Sd Card Configuration Register */
+	u32 Mode;			/**< Bus Speed Mode */
+	XSdPs_ConfigTap Config_TapDelay;	/**< Configuring the tap delays */
+	/**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c
new file mode 100644
index 000000000..72981b551
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c
@@ -0,0 +1,61 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_SD_1_DEVICE_ID,
+		XPAR_PSU_SD_1_BASEADDR,
+		XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
+		XPAR_PSU_SD_1_HAS_CD,
+		XPAR_PSU_SD_1_HAS_WP,
+		XPAR_PSU_SD_1_BUS_WIDTH,
+		XPAR_PSU_SD_1_MIO_BANK,
+		XPAR_PSU_SD_1_HAS_EMIO
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h
new file mode 100644
index 000000000..2c5d712d2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h
@@ -0,0 +1,1237 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v2_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00U	/**< SDMA System Address
+							Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET	XSDPS_SDMA_SYS_ADDR_OFFSET
+						/**< SDMA System Address
+							Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET		0x00U	/**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET	0x02U	/**< SDMA System Address
+							High Register */
+#define XSDPS_ARGMT2_HI_OFFSET		0x02U	/**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET		0x04U	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06U	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08U	/**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET		XSDPS_ARGMT_OFFSET
+						/**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET		0x0AU	/**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET		0x0CU	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0EU	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10U	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14U	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18U	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1CU	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20U	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24U	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28U	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29U	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2AU	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2BU	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2CU	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2EU	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2FU	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30U	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32U	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34U	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36U	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38U	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3AU	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3CU	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3EU	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40U	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44U	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48U	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4CU	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52U	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50U	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54U	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58U	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5CU	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6CU	/**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET	0x70U	/**< Boot timeout control
+							register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0U	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFCU	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFEU	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4		0x00000002U
+#define XSDPS_HC_SPEED_MASK		0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK	0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT			256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT		2046U
+#define XSDPS_CC_EXT_DIV_SHIFT			6U
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9U
+#define XSDPS_CC_DIV_SHIFT		8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * <b> Normal and Error Interrupt Status Register </b>
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * <b> Normal and Error Interrupt Status Enable Register </b>
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * <b> Normal and Error Interrupt Signal Enable Register </b>
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00002000U /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00004000U /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001U /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004U /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK	0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000U /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024		0x400U
+#define XSDPS_BLK_SIZE_2048		0x800U
+#define XSDPS_BLK_CNT_MASK		0x0000FFFFU /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010U /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020U /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003U /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003U /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008U /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010U /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00U /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_AUTO_CMD_CRC_MASK		0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK		0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_AUTO_CMD_IND_MASK		0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK		0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK	0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK	0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK	0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK	0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK	0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK		0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK	0x0030U /**< Driver Strength
+							Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK	0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK	0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK	0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK	0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK		0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK	0x0080U /**< Sampling Clock
+							Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK	0x4000U /**< Asynchronous Interrupt
+							Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK	0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003FU /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080U /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK	0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK	0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK	0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000U /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000U /**< 64 bit system bus
+							support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000U /**< Interrupt mode
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK	0x20000000U /**< Async Interrupt
+							support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK	0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD			0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT			0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS			0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK		0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK		0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK		0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK	0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK	0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK	0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK	0x00000F00U /**< Timer Count for
+							Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK	0x00002000U /**< SDR50 Mode needs
+							tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK	0x0000C000U /**< Re-tuning modes
+							support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK	0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK	0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK	0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK	0x00FF0000U /**< Clock Multiplier value
+							for Programmable clock
+							mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK	0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK	0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK	0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000U /**< Write protect switch
+								pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK	0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK	0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK	0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK	0x00000F00U /**< Maximum Current
+							Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK	0x000000F0U /**< Maximum Current
+							Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK	0x0000000FU /**< Maximum Current
+							Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK	0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK	0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK	0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK	0x0001U /**< Command Timeout
+							Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK	0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK	0x0004U /**< Command End Bit
+							Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK	0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK	0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK	0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK	0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK	0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK	0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK	0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK	0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK	0xE000U /**< Vendor Specific
+							Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK	0x04U /**< ADMA Length Mismatch
+							Error */
+#define XSDPS_ADMA_ERR_STATE_MASK	0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK	0x00U /**< ADMA Error State
+							STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK	0x01U /**< ADMA Error State
+							FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK	0x03U /**< ADMA Error State
+							TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK	0x03FFU /**< SDCLK Frequency
+							Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK	0x0400U /**< Clock Generator
+							Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK	0xC000U /**< Driver Strength
+							Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK	0x0007U /**< Interrupt Signal
+							mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER		0xFF00U /**< Vendor
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_VER_MASK		0x00FFU /**< Host
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_V3		0x0002U
+#define XSDPS_HC_SPEC_V2		0x0001U
+#define XSDPS_HC_SPEC_V1		0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000U
+#define CMD0	 0x0000U
+#define CMD1	 0x0100U
+#define CMD2	 0x0200U
+#define CMD3	 0x0300U
+#define CMD4	 0x0400U
+#define CMD5	 0x0500U
+#define CMD6	 0x0600U
+#define ACMD6	(XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7	 0x0700U
+#define CMD8	 0x0800U
+#define CMD9	 0x0900U
+#define CMD10	 0x0A00U
+#define CMD11	 0x0B00U
+#define CMD12	 0x0C00U
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16	 0x1000U
+#define CMD17	 0x1100U
+#define CMD18	 0x1200U
+#define CMD19	 0x1300U
+#define CMD21	 0x1500U
+#define CMD23	 0x1700U
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24	 0x1800U
+#define CMD25	 0x1900U
+#define CMD41	 0x2900U
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52	 0x3400U
+#define CMD55	 0x3700U
+#define CMD58	 0x3A00U
+
+#define RESP_NONE	(u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		(u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+			(u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		(u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		(u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN	0xAAU
+#define XSDPS_CIC_VOLT_MASK	(0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6	(1U<<8)
+#define XSDPS_CIC_VOLT_LOW	(1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS	(1U<<31)
+#define XSDPS_OCR_CC_STS	(1U<<30)
+#define XSDPS_OCR_S18		(1U<<24)
+#define XSDPS_OCR_3V5_3V6	(1U<<23)
+#define XSDPS_OCR_3V4_3V5	(1U<<22)
+#define XSDPS_OCR_3V3_3V4	(1U<<21)
+#define XSDPS_OCR_3V2_3V3	(1U<<20)
+#define XSDPS_OCR_3V1_3V2	(1U<<19)
+#define XSDPS_OCR_3V0_3V1	(1U<<18)
+#define XSDPS_OCR_2V9_3V0	(1U<<17)
+#define XSDPS_OCR_2V8_2V9	(1U<<16)
+#define XSDPS_OCR_2V7_2V8	(1U<<15)
+#define XSDPS_OCR_1V7_1V95	(1U<<7)
+#define XSDPS_OCR_HIGH_VOL	0x00FF8000U
+#define XSDPS_OCR_LOW_VOL	0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN		8U
+#define XSDPS_SCR_STRUCT_MASK		(0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK		(0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0		0U
+#define XSDPS_SCR_SPEC_1V1		(1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0		(2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE	(1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK		(7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE		0U
+#define XSDPS_SCR_SEC_SUPP_1V1		(2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0		(3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0		(4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK	(0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1		(1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4		(4U<<16)
+#define XSDPS_SCR_SPEC3_MASK		(1U<<12)
+#define XSDPS_SCR_SPEC3_2V0		0U
+#define XSDPS_SCR_SPEC3_3V0		(1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK		0x3U
+#define XSDPS_SCR_CMD23_SUPP		(1U<<1)
+#define XSDPS_SCR_CMD20_SUPP		(1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE	(1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR		(1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR	(1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR		(1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR		(1U<<27)
+#define XSDPS_CD_STS_WP_VIO		(1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED		(1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL	(1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR	(1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD		(1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL	(1U<<21)
+#define XSDPS_CD_STS_CC_ERR		(1U<<20)
+#define XSDPS_CD_STS_ERR		(1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR		(1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP		(1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS	(1U<<14)
+#define XSDPS_CD_STS_ER_RST		(1U<<13)
+#define XSDPS_CD_STS_CUR_STATE		(0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA	(1U<<8)
+#define XSDPS_CD_STS_APP_CMD		(1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR	(1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN	64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH	(1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK		0U
+
+#define XSDPS_MODE_FUNC_GRP1		1U
+#define XSDPS_MODE_FUNC_GRP2		2U
+#define XSDPS_MODE_FUNC_GRP3		3U
+#define XSDPS_MODE_FUNC_GRP4		4U
+#define XSDPS_MODE_FUNC_GRP5		5U
+#define XSDPS_MODE_FUNC_GRP6		6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL		0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL	0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12	0U
+#define XSDPS_ACC_MODE_HS_SDR25		1U
+#define XSDPS_ACC_MODE_SDR50		2U
+#define XSDPS_ACC_MODE_SDR104		3U
+#define XSDPS_ACC_MODE_DDR50		4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT		4U
+#define XSDPS_CMD_SYS_DEF		0U
+#define XSDPS_CMD_SYS_eC		1U
+#define XSDPS_CMD_SYS_OTP		3U
+#define XSDPS_CMD_SYS_ASSD		4U
+#define XSDPS_CMD_SYS_VEND		5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT	8U
+#define XSDPS_DRV_TYPE_B		0U
+#define XSDPS_DRV_TYPE_A		1U
+#define XSDPS_DRV_TYPE_C		2U
+#define XSDPS_DRV_TYPE_D		3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT		12U
+#define XSDPS_CUR_LIM_200		0U
+#define XSDPS_CUR_LIM_400		1U
+#define XSDPS_CUR_LIM_600		2U
+#define XSDPS_CUR_LIM_800		3U
+
+#define CSD_SPEC_VER_MASK		0x3C0000U
+#define READ_BLK_LEN_MASK		0x00000F00U
+#define C_SIZE_MULT_MASK		0x00000380U
+#define C_SIZE_LOWER_MASK		0xFFC00000U
+#define C_SIZE_UPPER_MASK		0x00000003U
+#define CSD_STRUCT_MASK			0x00C00000U
+#define CSD_V2_C_SIZE_MASK		0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE		512U
+
+#define EXT_CSD_WR_REL_PARAM_EN		(1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN     (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0     (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL          (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE          (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE        (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26    	(1U<<0)  /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52    	(1U<<1)  /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK  	0x3FU    /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1U<<2)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1U<<3)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V  \
+                                        | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V      (1U<<4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V      (1U<<5)  /* Card can run at 200MHz */
+                                                /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE			183U
+#define EXT_CSD_BUS_WIDTH_1_BIT			0U	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT			1U	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT			2U	/* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT		5U	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT		6U	/* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE		185U
+#define EXT_CSD_HS_TIMING_DEF		0U
+#define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE		162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS	0U	/* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN	1U	/* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS	2U	/* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET		0U
+#define XSDPS_EXT_CSD_SET_BITS		1U
+#define XSDPS_EXT_CSD_CLR_BITS		2U
+#define XSDPS_EXT_CSD_WRITE_BYTE	3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG	(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+					 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY	2960U
+#define XSDPS_100CLK_DELAY	4000U
+#define XSDPS_INIT_DELAY	10000U
+
+#define XSDPS_DEF_VOLT_LVL	XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR	0x1234U
+
+#define XSDPS_CARD_SD		1U
+#define XSDPS_CARD_MMC		2U
+#define XSDPS_CARD_SDIO		3U
+#define XSDPS_CARD_SDCOMBO	4U
+#define XSDPS_CHIP_EMMC		5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID     	(0x1U << 0)
+#define XSDPS_DESC_END       	(0x1U << 1)
+#define XSDPS_DESC_INT       	(0x1U << 2)
+#define XSDPS_DESC_TRAN  	(0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ		400000U		/**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ		50000000U	/**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ		52000000U	/**< 52 MHZ */
+#define XSDPS_SD_VER_1_0		0x1U		/**< SD ver 1 */
+#define XSDPS_SD_VER_2_0		0x2U		/**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT	1U
+#define XSDPS_SCR_BLKSIZE	8U
+#define XSDPS_1_BIT_WIDTH	0x1U
+#define XSDPS_4_BIT_WIDTH	0x2U
+#define XSDPS_8_BIT_WIDTH	0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12	0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25	0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
+#define XSDPS_HIGH_SPEED_MODE		0x5U
+#define XSDPS_DEFAULT_SPEED_MODE	0x6U
+#define XSDPS_HS200_MODE			0x7U
+#define XSDPS_SWITCH_CMD_BLKCNT		1U
+#define XSDPS_SWITCH_CMD_BLKSIZE	64U
+#define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET		0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET		0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET		0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET		0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512U
+#define XSDPS_TUNING_CMD_BLKCNT		1U
+#define XSDPS_TUNING_CMD_BLKSIZE	64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK	50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK	208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK		100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK		25000000U
+
+#define SD_DRIVER_TYPE_B	0x01U
+#define SD_DRIVER_TYPE_A	0x02U
+#define SD_DRIVER_TYPE_C	0x04U
+#define SD_DRIVER_TYPE_D	0x08U
+#define SD_SET_CURRENT_LIMIT_200	0U
+#define SD_SET_CURRENT_LIMIT_400	1U
+#define SD_SET_CURRENT_LIMIT_600	2U
+#define SD_SET_CURRENT_LIMIT_800	3U
+
+#define SD_MAX_CURRENT_200	(1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400	(1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600	(1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800	(1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK	25000000U
+#define XSDPS_SD_SDR25_MAX_CLK	50000000U
+#define XSDPS_SD_SDR50_MAX_CLK	100000000U
+#define XSDPS_SD_DDR50_MAX_CLK	50000000U
+#define XSDPS_SD_SDR104_MAX_CLK	208000000U
+#define XSDPS_MMC_HS200_MAX_CLK	200000000U
+
+#define XSDPS_CARD_STATE_IDLE		0U
+#define XSDPS_CARD_STATE_RDY		1U
+#define XSDPS_CARD_STATE_IDEN		2U
+#define XSDPS_CARD_STATE_STBY		3U
+#define XSDPS_CARD_STATE_TRAN		4U
+#define XSDPS_CARD_STATE_DATA		5U
+#define XSDPS_CARD_STATE_RCV		6U
+#define XSDPS_CARD_STATE_PROG		7U
+#define XSDPS_CARD_STATE_DIS		8U
+#define XSDPS_CARD_STATE_BTST		9U
+#define XSDPS_CARD_STATE_SLP		10U
+
+#define XSDPS_SLOT_REM			0U
+#define XSDPS_SLOT_EMB			1U
+
+#if defined (ARMR5) || defined (__aarch64__)
+#define SD_DLL_CTRL 				0x00000358U
+#define SD_ITAPDLY					0x00000314U
+#define SD_OTAPDLY					0x00000318U
+#define SD0_DLL_RST					0x00000004U
+#define SD1_DLL_RST					0x00040000U
+#define SD0_ITAPCHGWIN				0x00000200U
+#define SD0_ITAPDLYENA				0x00000100U
+#define SD0_OTAPDLYENA				0x00000040U
+#define SD1_ITAPCHGWIN				0x02000000U
+#define SD1_ITAPDLYENA				0x01000000U
+#define SD1_OTAPDLYENA				0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0		0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2		0x00000002U
+#define SD0_ITAPDLYSEL_SD50			0x00000014U
+#define SD0_OTAPDLYSEL_SD50			0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50		0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50	0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50		0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50	0x00000006U
+#define SD0_ITAPDLYSEL_HSD			0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD		0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD		0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0		0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2		0x00020000U
+#define SD1_ITAPDLYSEL_SD50			0x00140000U
+#define SD1_OTAPDLYSEL_SD50			0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50		0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50	0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50		0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50	0x00060000U
+#define SD1_ITAPDLYSEL_HSD			0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD		0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD		0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+	XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+*		u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+	XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+		(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
+	XSdPs_In16((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
+	XSdPs_In8((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
+
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c
new file mode 100644
index 000000000..7dbc772f3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c
@@ -0,0 +1,1517 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define UHS_SDR12_SUPPORT	0x1U
+#define UHS_SDR25_SUPPORT	0x2U
+#define UHS_SDR50_SUPPORT	0x4U
+#define UHS_SDR104_SUPPORT	0x8U
+#define UHS_DDR50_SUPPORT	0x10U
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__)
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+static void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+static void XSdPs_DllReset(XSdPs *InstancePtr);
+#endif
+
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	BlkSize - Block size passed by the user.
+*
+* @return	None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+	s32 Status;
+	u32 PresentStateReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+
+	if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+			(u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+			(u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/* Set block size to the value passed */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			 BlkSize & XSDPS_BLK_SIZE_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SCR - buffer to store SCR register returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+	s32 Status;
+	u32 StatusReg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+		SCR[LoopCnt] = 0U;
+	}
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	BlkCnt = XSDPS_SCR_BLKCNT;
+	BlkSize = XSDPS_SCR_BLKSIZE;
+
+	/* Set block size to the value passed */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+				0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+		Arg = ((u32)InstancePtr->BusWidth);
+
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+
+		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+				&& (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+			/* in case of eMMC data width 8-bit */
+			InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+		} else {
+			InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+		}
+
+		if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+			Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+		} else {
+			Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Check for transfer complete */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+
+	/* Width setting in controller */
+	if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+		StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+	} else {
+		StatusReg |= XSDPS_HC_WIDTH_MASK;
+	}
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			(u8)StatusReg);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store function group support data
+*		returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+		BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+		BlkSize &= XSDPS_BLK_SIZE_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+		XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+		Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_XFER_MODE_OFFSET,
+				XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+		Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 * Polling for response for now
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 50 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+
+	} else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+		Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 52 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		Arg = XSDPS_MMC_HS200_ARG;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 200 MHz */
+		InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+		Status = XSdPs_Execute_Tuning(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SelFreq - Clock frequency in Hz.
+*
+* @return	None
+*
+* @note		This API will change clock frequency to the value less than
+*		or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+	u16 ClockReg;
+	u16 DivCnt;
+	u16 Divisor = 0U;
+	u16 ExtDivisor;
+	s32 Status;
+	u16 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__)
+	if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+			(InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
+		/* Program the Tap delays */
+		XSdPs_SetTapDelay(InstancePtr);
+#endif
+		/* Calculate divisor */
+		for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt >> 1;
+				break;
+			}
+		}
+
+		if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		/* Calculate divisor */
+		DivCnt = 0x1U;
+		while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt / 2U;
+				break;
+			}
+			DivCnt = DivCnt << 1U;
+		}
+
+		if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* Set clock divisor */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+		XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+		ExtDivisor = Divisor >> 8;
+		ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+		ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	} else {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	}
+
+	/* Wait for internal clock to stabilize */
+	ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);;
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store EXT_CSD
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg = 0U;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+
+	/* Send SEND_EXT_CSD command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Arg is the argument to be sent along with the command
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+	s32 Status;
+	u32 StatusReg;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff contains the response for CMD6
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+		InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+		InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+		InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+		InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+	}
+	else
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+}
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Mode UHS-I mode
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+	s32 Status;
+	u16 StatusReg;
+	u16 CtrlReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Drive strength */
+
+	/* Bus speed mode selection */
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	switch (Mode) {
+	case 0U:
+		Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+		break;
+	case 1U:
+		Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+		break;
+	case 2U:
+		Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+		break;
+	case 3U:
+		Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+		break;
+	case 4U:
+		Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+		break;
+	default:
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+		break;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+	/* Current limit */
+
+	/* Set UHS mode in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+	CtrlReg |= Mode;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/* Change the clock frequency */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+	if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+	}
+
+	if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+			(Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+		/* Send tuning pattern */
+		Status = XSdPs_Execute_Tuning(InstancePtr);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+#endif
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 BlkSize;
+	u16 CtrlReg;
+	u8 TuningCount;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+	if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+	{
+		BlkSize = BlkSize*2U;
+	}
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/*
+	 * workaround which can work for 1.0/2.0 silicon for auto tuning.
+	 * This can be revisited for 3.0 silicon if necessary.
+	 */
+	/* Wait for ~60 clock cycles to reset the tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+		if (InstancePtr->CardType == XSDPS_CARD_SD) {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+		} else {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+		}
+
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+			break;
+		}
+
+		if (TuningCount == 31) {
+#if defined (ARMR5) || defined (__aarch64__)
+			/* Issue DLL Reset to load new SDHC tuned tap values */
+			XSdPs_DllReset(InstancePtr);
+#endif
+		}
+	}
+
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for ~12 clock cycles to synchronize the new tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH: return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR104 and HS200 modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (Bank == 2)
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (Bank == 2)
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		TapDelay |= SD0_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		TapDelay |= SD1_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for DDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType== XSDPS_CARD_SD)
+			TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for HSD and SDR25 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD0_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD1_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+	u32 DllCtrl, BankNum, DeviceId, CardType;
+
+	BankNum = InstancePtr->Config.BankNumber;
+	DeviceId = InstancePtr->Config.DeviceId ;
+	CardType = InstancePtr->CardType ;
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+	} else {
+#endif
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+	u32 ClockReg, DllCtrl;
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/* Issue DLL Reset to load zero tap values */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+		DllCtrl |= SD0_DLL_RST;
+	} else {
+		DllCtrl |= SD1_DLL_RST;
+	}
+	XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+
+	/* Wait for 2 micro seconds */
+	(void)usleep(2U);
+
+	/* Release the DLL out of reset */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+		DllCtrl &= ~SD0_DLL_RST;
+	} else {
+		DllCtrl &= ~SD1_DLL_RST;
+	}
+	XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+}
+#endif
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c
new file mode 100644
index 000000000..e0936b308
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile
deleted file mode 100644
index ca8621a76..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile
+++ /dev/null
@@ -1,74 +0,0 @@
-###############################################################################
-#
-# Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# Use of the Software is limited solely to applications:
-# (a) running on a Xilinx device, or
-# (b) that interact with a Xilinx device through a bus or interconnect.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-#
-# Except as contained in this notice, the name of the Xilinx shall not be used
-# in advertising or otherwise to promote the sale, use or other dealings in
-# this Software without prior written authorization from Xilinx.
-#
-###############################################################################
-
-include config.make
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
-
-ifeq ($(notdir $(CC)), armr5-none-eabi-gcc)
-ECC_FLAGS	+= -nostartfiles\
-		  -mfloat-abi=soft\
-		  -mfpu=vfpv3-d16
-endif
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-INCLUDEFILES=*.h
-INCLUDEFILES+=includes_ps/*.h
-
-libs: $(LIBS)
-
-standalone_libs: $(LIBSOURCES)
-	echo "Compiling standalone R5"
-	$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
-	$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
-
-.PHONY: include
-include: standalone_includes
-
-standalone_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OUTS}
-	$(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c
deleted file mode 100644
index 0086c59b0..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <unistd.h>
-#include "xil_types.h"
-
-/*
- * _exit - Does not return.
- *
- * If R5 application runs in lock-step mode, the comparators are enabled by
- * boot code after resetting the debug logic. The debugger does not have access
- * while the R5 application is being run to avoid any intervention. After the
- * application runs, the debug logic need to be taken out of reset for the
- * debugger to gain access. Therefore the debug logic is enabled and
- * comparators are disabled in case of R5 running in lock-step mode with
- * debug logic reset in JTAG boot mode.
- */
-
-#define RPU_GLBL_CNTL_REG	0xFF9A0000U
-#define RPU_ERR_INJ_REG		0xFF9A0020U
-#define RST_LPD_DBG_REG		0xFF5E0240U
-#define BOOT_MODE_USER_REG	0xFF5E0200U
-
-#define lock_step 			0x00000008U
-#define fault_log_enable	0x00000101U
-#define debug_reset 		0x00000032U
-#define jtag_boot			0x0000000FU
-__attribute__((weak)) void _exit (sint32 status)
-{
-
-	/*
-	 * Enables the debug logic and disable the comparators
-	 * when in JTAG boot mode and R5 is in lock-step mode
-	 * if the fault log is enabled
-	 */
-	u32 debug_reg, err_inj_reg;
-	if((Xil_In32(BOOT_MODE_USER_REG) & jtag_boot) == 0){
-		if((Xil_In32(RPU_GLBL_CNTL_REG) & lock_step) == 0){
-			if((Xil_In32(RPU_ERR_INJ_REG) & fault_log_enable) != 0) {
-				if((Xil_In32(RST_LPD_DBG_REG) & debug_reset) != 0) {
-					err_inj_reg = Xil_In32(RPU_ERR_INJ_REG);
-					err_inj_reg = err_inj_reg & (~fault_log_enable);
-					Xil_Out32(RPU_ERR_INJ_REG, err_inj_reg);
-
-					debug_reg = Xil_In32(RST_LPD_DBG_REG);
-					debug_reg = debug_reg & (~debug_reset);
-					Xil_Out32(RST_LPD_DBG_REG, debug_reg);
-				}
-			}
-		}
-	}
-
-  (void)status;
-  while (1)
-  {
-     __asm__("wfi");
-  }
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c
deleted file mode 100644
index b2809c5d0..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
-}
-#endif
-
-/*
- * _open -- open a file descriptor. We don't have a filesystem, so
- *         we return an error.
- */
-__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
-{
-  (void *)buf;
-  (void)flags;
-  (void)mode;
-  errno = EIO;
-  return (-1);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c
deleted file mode 100644
index bcec069c8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <sys/types.h>
-#include "xil_types.h"
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) caddr_t _sbrk ( s32 incr );
-}
-#endif
-
-__attribute__((weak)) caddr_t _sbrk ( s32 incr )
-{
-  static u8 *heap = NULL;
-  u8 *prev_heap;
-  static u8 *HeapEndPtr = (u8 *)&_heap_end;
-  caddr_t Status;
-
-  if (heap == NULL) {
-    heap = (u8 *)&_heap_start;
-  }
-  prev_heap = heap;
-
-  heap += incr;
-
-  if (heap > HeapEndPtr){
-	  Status = (caddr_t) -1;
-  }
-  else if (prev_heap != NULL) {
-	  Status = (caddr_t) ((void *)prev_heap);
-  }
-  else {
-	  Status = (caddr_t) -1;
-  }
-
-  return Status;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c
deleted file mode 100644
index 122c25bbd..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <stdlib.h>
-#include <unistd.h>
-
-/*
- * abort -- go out via exit...
- */
-__attribute__((weak)) void abort(void)
-{
-  _exit(1);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S
deleted file mode 100644
index 138c22e89..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S
+++ /dev/null
@@ -1,121 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.s
-*
-* This file contains the initial vector table for the Cortex R5 processor
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00  pkp	02/10/14 Initial version
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-.org 0
-.text
-
-.globl _boot
-.globl _vector_table
-
-.globl FIQInterrupt
-.globl IRQInterrupt
-.globl SWInterrupt
-.globl DataAbortInterrupt
-.globl PrefetchAbortInterrupt
-
-.globl IRQHandler
-.globl prof_pc
-
-.section .vectors, "a"
-_vector_table:
-	ldr	pc,=_boot
-	ldr	pc,=Undefined
-	ldr	pc,=SVCHandler
-	ldr	pc,=PrefetchAbortHandler
-	ldr	pc,=DataAbortHandler
-	NOP	/* Placeholder for address exception vector*/
-	ldr	pc,=IRQHandler
-	ldr	pc,=FIQHandler
-
-.text
-IRQHandler:					/* IRQ vector handler */
-	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code*/
-	bl	IRQInterrupt			/* IRQ vector */
-	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
-	subs	pc, lr, #4			/* adjust return */
-
-FIQHandler:					/* FIQ vector handler */
-	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
-FIQLoop:
-	bl	FIQInterrupt			/* FIQ vector */
-	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
-	subs	pc, lr, #4			/* adjust return */
-
-Undefined:					/* Undefined handler */
-	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
-	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
-	b	_prestart
-	movs	pc, lr
-
-SVCHandler:					/* SWI handler */
-	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
-	tst	r0, #0x20			/* check the T bit */
-	ldrneh	r0, [lr,#-2]			/* Thumb mode */
-	bicne	r0, r0, #0xff00			/* Thumb mode */
-	ldreq	r0, [lr,#-4]			/* ARM mode */
-	biceq	r0, r0, #0xff000000		/* ARM mode */
-	bl	SWInterrupt			/* SWInterrupt: call C function here */
-	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
-	movs	pc, lr				/* adjust return */
-
-DataAbortHandler:				/* Data Abort handler */
-	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
-	bl	DataAbortInterrupt		/*DataAbortInterrupt :call C function here */
-	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
-	subs	pc, lr, #8			/* adjust return */
-
-PrefetchAbortHandler:				/* Prefetch Abort handler */
-	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
-	bl	PrefetchAbortInterrupt		/* PrefetchAbortInterrupt: call C function here */
-	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
-	subs	pc, lr, #4			/* adjust return */
-
-
-.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S
deleted file mode 100644
index 724f9616f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S
+++ /dev/null
@@ -1,300 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* This file contains the initial startup code for the Cortex R5 processor
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* 5.04	pkp  09/11/15 Disabled ACTLR.DBWR bit to avoid potential R5 deadlock
-*		      for errata 780125
-* 5.04 pkp   02/04/16 Enabled the fault log for lock-step mode
-* 5.04 pkp   02/25/16 Initialized the banked registers for various modes,
-*		      initialized floating point registers and enabled the
-*		      cache ECC check before enabling the fault log for
-*		      lock step mode
-* 5.04 pkp   03/24/16 Reset the dbg_lpd_reset before enabling the fault log
-*		      to avoid intervention for lock-step mode
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
-
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack,	__undef_stack
-.set FIQ_stack,		__fiq_stack
-.set Abort_stack,	__abort_stack
-.set SPV_stack,		__supervisor_stack
-.set IRQ_stack,		__irq_stack
-.set SYS_stack,		__stack
-
-.set vector_base,	_vector_table
-
-.set RPU_GLBL_CNTL,	0xFF9A0000
-.set RPU_ERR_INJ,	0xFF9A0020
-.set RST_LPD_DBG,	0xFF5E0240
-.set fault_log_enable,	0x101
-
-.section .boot,"axS"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-OKToRun:
-
-/* Initialize processor registers to 0 */
-	mov	r0,#0
-	mov	r1,#0
-	mov	r2,#0
-	mov	r3,#0
-	mov	r4,#0
-	mov	r5,#0
-	mov	r6,#0
-	mov	r7,#0
-	mov	r8,#0
-	mov	r9,#0
-	mov	r10,#0
-	mov	r11,#0
-	mov	r12,#0
-
-/* Initialize stack pointer and banked registers for various mode */
-	mrs	r0, cpsr			/* get the current PSR */
-	mvn	r1, #0x1f			/* set up the irq stack pointer */
-	and	r2, r1, r0
-	orr	r2, r2, #0x12			/* IRQ mode */
-	msr	cpsr, r2
-	ldr	r13,=IRQ_stack			/* IRQ stack pointer */
-	mov 	r14,#0
-
-	mrs	r0, cpsr			/* get the current PSR */
-	mvn	r1, #0x1f			/* set up the supervisor stack pointer */
-	and	r2, r1, r0
-	orr	r2, r2, #0x13			/* supervisor mode */
-	msr	cpsr, r2
-	ldr	r13,=SPV_stack			/* Supervisor stack pointer */
-	mov 	r14,#0
-
-	mrs	r0, cpsr			/* get the current PSR */
-	mvn	r1, #0x1f			/* set up the Abort  stack pointer */
-	and	r2, r1, r0
-	orr	r2, r2, #0x17			/* Abort mode */
-	msr	cpsr, r2
-	ldr	r13,=Abort_stack		/* Abort stack pointer */
-	mov 	r14,#0
-
-	mrs	r0, cpsr			/* get the current PSR */
-	mvn	r1, #0x1f			/* set up the FIQ stack pointer */
-	and	r2, r1, r0
-	orr	r2, r2, #0x11			/* FIQ mode */
-	msr	cpsr, r2
-	mov 	r8, #0
-	mov 	r9, #0
-	mov 	r10, #0
-	mov 	r11, #0
-	mov 	r12, #0
-	ldr	r13,=FIQ_stack			/* FIQ stack pointer */
-	mov 	r14,#0
-
-	mrs	r0, cpsr			/* get the current PSR */
-	mvn	r1, #0x1f			/* set up the Undefine stack pointer */
-	and	r2, r1, r0
-	orr	r2, r2, #0x1b			/* Undefine mode */
-	msr	cpsr, r2
-	ldr	r13,=Undef_stack		/* Undefine stack pointer */
-	mov 	r14,#0
-
-	mrs	r0, cpsr			/* get the current PSR */
-	mvn	r1, #0x1f			/* set up the system stack pointer */
-	and	r2, r1, r0
-	orr	r2, r2, #0x1F			/* SYS mode */
-	msr	cpsr, r2
-	ldr	r13,=SYS_stack			/* SYS stack pointer */
-	mov 	r14,#0
-
-/*
- * Enable access to VFP by enabling access to Coprocessors 10 and 11.
- * Enables Full Access i.e. in both privileged and non privileged modes
- */
-	mrc     p15, 0, r0, c1, c0, 2      	/* Read Coprocessor Access Control Register (CPACR) */
-        orr     r0, r0, #(0xF << 20)       	/* Enable access to CP 10 & 11 */
-        mcr     p15, 0, r0, c1, c0, 2      	/* Write Coprocessor Access Control Register (CPACR) */
-        isb
-
-/* enable fpu access  */
-	vmrs	r3, FPEXC
-	orr	r1, r3, #(1<<30)
-	vmsr	FPEXC, r1
-
-/* clear the floating point register*/
-	mov	r1,#0
-	vmov	d0,r1,r1
-	vmov	d1,r1,r1
-	vmov	d2,r1,r1
-	vmov	d3,r1,r1
-	vmov	d4,r1,r1
-	vmov	d5,r1,r1
-	vmov	d6,r1,r1
-	vmov	d7,r1,r1
-	vmov	d8,r1,r1
-	vmov	d9,r1,r1
-	vmov	d10,r1,r1
-	vmov	d11,r1,r1
-	vmov	d12,r1,r1
-	vmov	d13,r1,r1
-	vmov	d14,r1,r1
-	vmov	d15,r1,r1
-
-/* restore previous value for fpu access */
-	vmsr	FPEXC,r3
-
-/* Disable MPU and caches */
-        mrc     p15, 0, r0, c1, c0, 0       	/* Read CP15 Control Register*/
-        bic     r0, r0, #0x05               	/* Disable MPU (M bit) and data cache (C bit) */
-        bic     r0, r0, #0x1000             	/* Disable instruction cache (I bit) */
-        dsb                                 	/* Ensure all previous loads/stores have completed */
-        mcr     p15, 0, r0, c1, c0, 0       	/* Write CP15 Control Register */
-        isb                                 	/* Ensure subsequent insts execute wrt new MPU settings */
-
-/* Disable Branch prediction, TCM ECC checks */
-        mrc     p15, 0, r0, c1, c0, 1       	/* Read ACTLR */
-        orr     r0, r0, #(0x1 << 17)        	/* Enable RSDIS bit 17 to disable the return stack */
-        orr     r0, r0, #(0x1 << 16)        	/* Clear BP bit 15 and set BP bit 16:*/
-        bic     r0, r0, #(0x1 << 15)        	/* Branch always not taken and history table updates disabled*/
-        bic     r0, r0, #(0x1 << 27)		/* Disable B1TCM ECC check */
-        bic     r0, r0, #(0x1 << 26)		/* Disable B0TCM ECC check */
-        bic     r0, r0, #(0x1 << 25)		/* Disable ATCM ECC check */
-	orr	r0, r0, #(0x1 << 5)		/* Enable ECC with no forced write through with [5:3]=b'101*/
-	bic 	r0, r0, #(0x1 << 4)
-	orr	r0, r0, #(0x1 << 3)
-        mcr     p15, 0, r0, c1, c0, 1       	/* Write ACTLR*/
-	dsb				    	/* Complete all outstanding explicit memory operations*/
-
-/* Invalidate caches */
-	mov	r0,#0				/* r0 = 0  */
-	dsb
-	mcr	p15, 0, r0, c7, c5, 0		/* invalidate icache */
-	mcr 	p15, 0, r0, c15, c5, 0      	/* Invalidate entire data cache*/
-	isb
-
-/* enable fault log for lock step */
-	ldr	r0,=RPU_GLBL_CNTL
-	ldr	r1, [r0]
-	ands	r1, r1, #0x8
-/* branch to initialization if split mode*/
-	bne 	init
-/* reset the debug logic */
-	ldr	r0,=RST_LPD_DBG
-	ldr	r1, [r0]
-	orr	r1, r1, #(0x1 << 1)
-	orr	r1, r1, #(0x1 << 4)
-	orr	r1, r1, #(0x1 << 5)
-	str	r1, [r0]
-/* enable fault log */
-	ldr	r0,=RPU_ERR_INJ
-	ldr	r1,=fault_log_enable
-	ldr	r2, [r0]
-	orr	r2, r2, r1
-	str	r2, [r0]
-	nop
-	nop
-
-init:
-	bl 	Init_MPU		/* Initialize MPU */
-
-/* Enable Branch prediction */
-	mrc     p15, 0, r0, c1, c0, 1       /* Read ACTLR*/
-        bic     r0, r0, #(0x1 << 17)        /* Clear RSDIS bit 17 to enable return stack*/
-        bic     r0, r0, #(0x1 << 16)        /* Clear BP bit 15 and BP bit 16:*/
-        bic     r0, r0, #(0x1 << 15)        /* Normal operation, BP is taken from the global history table.*/
-        orr	r0, r0, #(0x1 << 14)	    /* Disable DBWR for errata 780125 */
-	mcr     p15, 0, r0, c1, c0, 1       /* Write ACTLR*/
-
-/* Enable icahce and dcache */
-	mrc 	p15,0,r1,c1,c0,0
-	ldr	r0, =0x1005
-	orr 	r1,r1,r0
-	dsb
-	mcr	p15,0,r1,c1,c0,0		/* Enable cache  */
-	isb					/* isb	flush prefetch buffer */
-
-/* Warning message to be removed after 2016.1 */
-/* USEAMP was introduced in 2015.4 with ZynqMP and caused confusion with USE_AMP */
-#ifdef USEAMP
-#warning "-DUSEAMP=1 is deprecated, use -DVEC_TABLE_IN_OCM instead to set vector table in OCM"
-#endif
-
-/* Set vector table in TCM/LOVEC */
-#ifndef VEC_TABLE_IN_OCM
-	mrc	p15, 0, r0, c1, c0, 0
-	mvn	r1, #0x2000
-	and	r0, r0, r1
-	mcr	p15, 0, r0, c1, c0, 0
-#endif
-
-/* enable asynchronous abort exception */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x100
-	msr	cpsr_xsf, r0
-
-        b 	_startup                       /* jump to C startup code */
-
-
-.Ldone:	b	.Ldone				/* Paranoia: we should never get here */
-
-
-.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h
deleted file mode 100644
index 4dd178f04..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h
+++ /dev/null
@@ -1,40 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#define MICROBLAZE_PVR_NONE
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt
deleted file mode 100644
index ad9c771e1..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt
+++ /dev/null
@@ -1,324 +0,0 @@
-/*****************************************************************************
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- ---------------------------------------------------
-  * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
- * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
- * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
- *                     cacheable regions
- *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
- *                     generated by the cpu driver, for enabling caches
- * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
- *                     write-thru caches
- * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
- *		       Updated the MMU table to mark OCM in high address space
- *		       as inner cacheable and reserved space as Invalid
- * 3.03a sdm  08/20/11 Changes to support FreeRTOS
- *		       Updated the MMU table to mark upper half of the DDR as
- *		       non-cacheable
- *		       Setup supervisor and abort mode stacks
- *		       Do not initialize/enable L2CC in case of AMP
- *		       Initialize UART1 for 9600bps in case of AMP
- * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
- *		       in case of AMP
- * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
- *		       counters
- * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
- *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
- *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
- *		       for MicroBlaze will invalidate data in the cache instead
- *		       of flushing it for writeback caches
- * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
- * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
- *		       Remove redundant dsb/dmb instructions in cache maintenance
- *		       APIs
- *		       Remove redundant dsb in mcr instruction
- * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
- * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
- *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
- *                     for the QSPI complete address range - DT644567
- *                     Removed profile directory for armcc compiler and changed
- *                     profiling setting to false in standalone_v2_1_0.tcl file
- *                     Deleting boot.S file after preprocessing for armcc compiler
- * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
- *		       invalidate the caches before enabling back the MMU and
- *		       D cache.
- * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
- *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
- *		       array, flush the D-cache before changing the attributes
- *		       in translation table. The user need not call Xil_DisableMMU
- *		       before calling Xil_SetTlbAttributes.
- * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
- *	 sgd	       initialization is present. Changes for this were done in
- *		       uart.c and xil-crt0.s.
- *		       Made changes in xil_io.c to use volatile pointers.
- *		       Made changes in xil_mmu.c to correct the function
- *		       Xil_SetTlbAttributes.
- *		       Changes are made xil-crt0.s to initialize the static
- *		       C++ constructors.
- *		       Changes are made in boot.s, to fix the TTBR settings,
- *		       correct the L2 Cache Auxiliary register settings, L2 cache
- *		       latency settings.
- * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
- *	 sgd	       usleep.c to use global timer intstead of CP15.
- *		       Made changes in cortexa9/gcc/translation_table.s to map
- *		       the peripheral devices as shareable device memory.
- *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
- *		       the global timer.
- *		       Made changes in cortexa9/armcc/boot.S to initialize
- *		       the global timer.
- *		       Made changes in cortexa9/armcc/translation_table.s to
- *		       map the peripheral devices as shareable device memory.
- *		       Made changes in cortexa9/gcc/boot.S to optimize the
- *		       L2 cache settings. Changes the section properties for
- *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
- *			and cortexa9/gcc/translation_table.S.
- *		       Made changes in cortexa9/xil_cache.c to change the
- *		       cache invalidation order.
- * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
- *		       compilation/linking issues for C++ compiler.
- *		       Made changes in mb_interface.h to remove compilation/
- *		       linking issues for C++ compiler.
- *		       Added macros for swapb and swaph microblaze instructions
- *		       mb_interface.h
- *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
- *		       for CortexA9.
- * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
- * 3.07a asa  08/31/12 Added xil_printf.h include
- * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
- *				Corrected L2 cache sequence disable sequence
- * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
- * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
- *		       irq/fiq handling.
- *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
- *		       fixes the CR #692094.
- * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
- * 3.10a srt  04/18/13 Implemented ARM Erratas.
- *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
- *		       L2Cache PL310 Errata - 588369, 727915, 759370
- *		       Please refer to file 'xil_errata.h' for errata
- *		       description.
- * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
- *		       cache APIs were corresponding to only Layer 1 cache
- *		       memories. New APIs were now added and the existing cache
- *		       related APIs were changed to provide a uniform interface
- *		       to flush/invalidate/enable/disable the complete cache
- *		       system which includes both L1 and L2 caches. The changes
- *		       for these were done in:
- *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
- *		       files.
- *		       Four new files were added for supporting L2 cache. They are:
- *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
- *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
- *		       memory in L2 cache.
- *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
- *		       microblaze_invalidate_cache_ext_range -> Invalidates a
- *		       range of memory in L2 cache.
- *		       These changes are done to implement PR #697214.
- * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
- *		       fix the CR #706464. L2 cache disabling happens independent
- *		       of L1 data cache disable operation. Changes are done in the
- *		       same file in cache handling APIs to do a L2 cache sync
- *		       (poll reg7_?cache_?sync). This fixes CR #700542.
- * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested
- *		       interrupts for ARM. These are done to fix the CR#699680.
- * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
- *		       sync operation. This fixes the CR# 716781.
- * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
- *		       for armcc toolchain.
- *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
- *		       fix issues related to NEON context saving. The assembly
- *		       routines for IRQ and FIQ handling are modified.
- *		       Deprecated the older BSP (3.10a).
- * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
- *		       various potential issues. Made changes in the function
- *		       Xil_SetAttributes in file xil_mmu.c.
- * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
- *		       in src\cortexa9 and src\microblaze folders.
- * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
- *		       L2 cache sync operation and to fix issues around complete
- *		       L2 cache flush/invalidation by ways.
- * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
- *		       to fix linking issues with armcc/DS-5. Modified the armcc
- *		       makefile to fix issues.
- * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
- * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
- * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
- *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
- *		       src\cortexa9\armcc\) to fix CR#767251
- * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
- *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
- *		       Few cache lines were missed to invalidate when unaligned address
- *		       invalidation was accommodated in Xil_DCacheInvalidateRange.
- *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
- *		       stack memory (which contains return address) was invalidated. So
- *		       stack memory is flushed first and then L1D cache is invalidated.
- *		       This is done to fix CR #763829
- * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
- *			mblaze_nt_types.h file and replace uint32_t with u32 in the
- *			profile_hist.c to fix the above CR.
- * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
- * 		       instead of libxil.a and added prototypes for
- *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
- *		       mb_interface.h
- * 4.1 hk    04/18/14  Add sleep function.
- * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
- *		       some of the *.s files inMB BSP source to *.S.
- * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
- * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
- *			CR#794205
- * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
- *		       common/xil_testcache.c
- *	               Fix for CR#764881.
- * 4.1 srt   06/27/14  Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
- *                     output the DEBUG logs when -DDEBUG flag is enabled in BSP.
- * 4.2 pkp   06/27/14  Added support for IAR compiler in src/cortexa9/iccarm.
- *		       Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
- * 4.2 pkp   06/19/14  Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
- *		       cortexa9/armcc/boot.s. Added default exception handlers for data
- *		       abort and prefetch abort using handlers called
- *		       DataAbortHandler and PrefetchAbortHandler respectively in
- *		       cortexa9/xil_exception.c to fix CR#802862.
- * 4.2 pkp   06/30/14  MakeFile for cortexa9/armcc has been changed to fixes the
- *		       issue of improper linking of translation_table.s
- * 4.2 pkp   07/04/14  added weak attribute for the function in BSP which are also present
- *		       in tool chain to avoid conflicts into some special cases
- * 4.2 pkp   07/21/14  Corrected reset value of event counter in function
- *		       Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
- * 4.2 pkp   07/21/14  Included xil_types.h file in xil_mmu.h which had contained a function
- * 		       containing type def u32 defined in xil_types.g to resolve issue of
- *		       CR#805869
- * 4.2 pkp   08/04/14  Removed unimplemented nanosleep routine from cortexa9/usleep.c as
- *		       it is not possible to generate timer in nanosecond due to limited
- *		       cpu frequency
- * 4.2 pkp   08/04/14  Removed PEEP board related code which contained initialization of
- *		       uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
- *		       and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
- *		       removed function definition of XSmc_NorInit and XSmc_NorInit from
- *		       cortexa9/smc.h
- * 4.2 bss   08/11/14  Added microblaze_flush_cache_ext_range and microblaze_invalidate_
- *		       cache_ext_range declarations in mb_interface.h CR#783821.
- *		       Modified profile_mcount_mb.S to fix CR#808412.
- * 4.2 pkp   08/21/14  modified makefile of iccarm for proper linking of objectfiles in
- *		       cortexa9/iccarm to fix CR#816701
- * 4.2 pkp   09/02/14  modified translation table entries in cortexa9/gcc/translation_table.s,
- *		       armcc/translation_table.s and iccarm/translation_table.s
- *		       to properly defined reserved entries according to address map for
- *		       fixing CR#820146
- * 4.2 pkp   09/11/14  modified translation table entries in cortexa9/iccarm/translation_table.s
- *		       and  cortexa9/armcc/translation_table.s to resolve compilation
- *		       error for solving CR#822897
- * 5.0 kvn   12/9/14   Support for Zync Ultrascale Mp.Also modified code for
- *                     MISRA-C:2012 compliance.
- * 5.0 pkp   12/15/14  Added APIs to get information about the platforms running the code by
- *		       adding src/common/xplatform_info.*s
- * 5.0 pkp   16/12/14  Modified boot code to enable scu after MMU is enabled and
- *		       removed incorrect initialization of TLB lockdown register to fix
- *		       CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
- *		       and iccarm/boot.s
- * 5.0 pkp   25/02/15  Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
- *		       for iccarm and armcc compiler of cortexA9
- * 5.1 pkp   05/13/15  Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
- *		       and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
- *		       caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
- *		       of L2Cache is done later.
- * 5.1 pkp   12/05/15  Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
- *		       Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
- *		       taking long time to fix CR#853097. L2CacheSync is added into
- *		       Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
- *		       Xil_L2CacheInvalidate APIs are modified to flush the complete stack
- *		       instead of just System Stack
- * 5.1 pkp   14/05/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
- *		       to update ECC_FLAGS and also take the compiler and archiver as specified
- *		       in settings instead of hardcoding it.
- * 5.2 pkp   06/08/15  Modified cortexa9/gcc/translation_table.S to put a check for
- *		       XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
- *		       accordingly generate the	translation table
- * 5.2 pkp   23/07/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
- *		       to update ECC_FLAGS to fix a bug introduced during new version creation
- *		       of BSP.
- * 5.3 pkp   10/07/15  Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
- *		       functionalities are avoided for the OpenAMP slave application(when
- *		       USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
- *		       cache for its operation. Also file operations such as read, write,
- *		       close, open are also avoided for OpenAMP support(when USE_AMP flag is
- *		       defined for BSP) because XilOpenAMP library contains own file operation.
- *		       The xil-crt0.S file is modified for not initializing global timer for
- *		       OpenAMP application as it might be already in use by master CPU
- * 5.3 pkp   10/09/15  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
- *		       definition for dsb, isb and dmb to fix the compilation error when used
- *     kvn   16/10/15  Encapsulated assembly code into macros for R5 xil_cache file.
- * 5.4 pkp   09/11/15  Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
- *		       R5 deadlock for errata 780125
- * 5.4 pkp   09/11/15  Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
- *		       32 bit BSP in the initialization
- * 5.4 pkp   09/11/15  Modified cortexa9/xil_misc_psreset_api.c file to change the description
- *		       for XOcm_Remap function
- * 5.4 pkp   16/11/15  Modified microblaze/xil_misc_psreset_api.c file to change the description
- *		       for XOcm_Remap function
- *     kvn   21/11/15  Added volatile keyword for ADDR varibles in Xil_Out API
- *     kvn   21/11/15  Changed ADDR variable type from u32 to UINTPTR. This is
- *                     required for MISRA-C:2012 Compliance.
- * 5.4 pkp   23/11/15  Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
- *		       in cortexa9/xil_mmu.h
- * 5.4 pkp   23/11/15  Added default undefined exception handler for Cortex-A9
- * 5.4 pkp   11/12/15  Modified common/xplatform_info.h to add #defines for silicon for
- *		       checking the current executing platform
- * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
- *		       to initialize global constructor for C++ applications
- * 5.4 pkp   18/12/15  Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
- *		       C++ applications
- * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
- *		       translation_table.S to update the translation table according to proper
- *		       address map
- * 5.4 pkp   18/12/15  Modified cortexar5/mpu.c to initialize the MPU according to proper
- *		       address map
- * 5.4	pkp  05/01/16  Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
- *		       equivalent to vector table base address
- * 5.4 pkp   08/01/16  Modified cortexa9/gcc/Makefile to update the extra compiler flag
- *		       as per the toolchain update
- * 5.4 pkp   12/01/16  Changed common/xplatform_info.* to add platform information support
- *		       for Cortex-A53 32bit mode
- * 5.4 pkp   28/01/16  Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
- *		       and usleep.c to correct routines to avoid hardcoding the timer frequency,
- *		       instead take it from xparameters.h to properly configure the timestamp
- *		       clock frequency
- * 5.4 asa   29/01/16  Modified microblaze/mb_interface.h to add macros that support the
- *		       new instructions for MB address extension feature
- * 5.4 kvn   30/01/16  Modified xparameters_ps.h file to add interrupt ID number for
- *		       system monitor.
- * 5.4 pkp   04/02/16  Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
- * 5.4 pkp   19/02/16  Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
- *		       cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
- *		       cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
- *		       use set of assembly instructions to provide required delay to fix
- *		       CR#913249.
- * 5.4 asa   25/02/16  Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
- *		       _exit with exit. We should not be directly calling _exit and should
- *		       always use the library exit. This fixes the CR#937036.
- * 5.4 pkp   25/02/16  Made change to cortexr5/gcc/boot.S to initialize the floating point
- *		       registers, banked registers for various modes and enabled
- *		       the cache ECC check before enabling the fault log for lock step mode
- *		       Also modified the cortexr5/gcc/Makefile to support floating point
- *		       registers initialization in boot code.
- * 5.4 pkp   03/01/16  Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
- *		       logic in case of lock-step mode when fault log is enabled to fix
- *		       CR#938281
- * 5.4 pkp   03/02/16  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
- *		       header file instrinsics.h which contains assembly instructions
- *		       definitions which can be used by C
- * 5.4 asa   03/02/16  Added print.c in MB BSP. Made other cosmetic changes to have uniform
- *                     proto for all print.c across the BSPs. This patch fixes CR#938738.
- * 5.4 pkp   03/09/16  Modified cortexr5/sleep.c and usleep.c to avoid disabling the
- *		       interrupts when sleep/usleep is being executed using assembly
- *		       instructions to fix CR#913249.
- * 5.4 pkp   03/11/16  Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
- *		       instead modified cortexr5/sleep.c and usleep.c to poll the counter
- *		       value and compare it with previous value to detect the overflow
- *		       to fix CR#940209.
- * 5.4 pkp   03/24/16  Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
- *		       the fault log to avoid intervention for lock-step mode and cortexr5/
- *		       _exit.c to enable the dbg_lpd_reset once the fault log is disabled
- *		       to fix CR#947335
- *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c
deleted file mode 100644
index e42a1ff36..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 _close(s32 fd);
-}
-#endif
-
-/*
- * close -- We don't need to do anything, but pretend we did.
- */
-
-__attribute__((weak)) s32 _close(s32 fd)
-{
-  (void)fd;
-  return (0);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make
deleted file mode 100644
index 2b7dbb6f7..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make
+++ /dev/null
@@ -1,2 +0,0 @@
-LIBSOURCES = *.c *.S
-LIBS = standalone_libs
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S
deleted file mode 100644
index 40bbc2c7a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.s
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00  pkp	02/10/14 Initial version
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-	.text
-	.global __cpu_init
-	.align 2
-__cpu_init:
-
-/* Clear cp15 regs with unknown reset values */
-	mov	r0, #0x0
-	mcr	p15, 0, r0, c5, c0, 0	/* DFSR */
-	mcr	p15, 0, r0, c5, c0, 1	/* IFSR */
-	mcr	p15, 0, r0, c6, c0, 0	/* DFAR */
-	mcr	p15, 0, r0, c6, c0, 2	/* IFAR */
-	mcr	p15, 0, r0, c9, c13, 2	/* PMXEVCNTR */
-	mcr	p15, 0, r0, c13, c0, 2	/* TPIDRURW */
-	mcr	p15, 0, r0, c13, c0, 3	/* TPIDRURO */
-
-
-/* Reset and start Cycle Counter */
-	mov	r2, #0x80000000		/* clear overflow */
-	mcr	p15, 0, r2, c9, c12, 3
-	mov	r2, #0xd		/* D, C, E */
-	mcr	p15, 0, r2, c9, c12, 0
-	mov	r2, #0x80000000		/* enable cycle counter */
-	mcr	p15, 0, r2, c9, c12, 1
-
-	bx	lr
-
-.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c
deleted file mode 100644
index daaa1212d..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/* The errno variable is stored in the reentrancy structure.  This
-   function returns its address for use by the macro errno defined in
-   errno.h.  */
-
-#include <errno.h>
-#include <reent.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) sint32 * __errno (void);
-}
-#endif
-
-__attribute__((weak)) sint32 *
-__errno (void)
-{
-  return &_REENT->_errno;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c
deleted file mode 100644
index 4c5de40fd..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <stdio.h>
-#include "xil_types.h"
-
-/*
- * fcntl -- Manipulate a file descriptor.
- *          We don't have a filesystem, so we do nothing.
- */
-__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
-{
-  (void)fd;
-  (void)cmd;
-  (void)arg;
-  return 0;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c
deleted file mode 100644
index 6271cfa84..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <sys/stat.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
-}
-#endif
-/*
- * fstat -- Since we have no file system, we just return an error.
- */
-__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
-{
-  (void)fd;
-  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
-
-  return (0);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c
deleted file mode 100644
index c2a84cb7f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "xil_types.h"
-/*
- * getpid -- only one process, so just return 1.
- */
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 _getpid(void);
-}
-#endif
-
-__attribute__((weak)) s32 getpid(void)
-{
-  return 1;
-}
-
-__attribute__((weak)) s32 _getpid(void)
-{
-  return 1;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c
deleted file mode 100644
index a5a6448d4..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c
+++ /dev/null
@@ -1,14 +0,0 @@
-#include "xparameters.h"
-#include "xuartps_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-char inbyte(void);
-#ifdef __cplusplus
-}
-#endif 
-
-char inbyte(void) {
-	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h
deleted file mode 100644
index 9029bead8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XDDR_XMPU0_CFG_H__
-#define __XDDR_XMPU0_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XddrXmpu0Cfg Base Address
- */
-#define XDDR_XMPU0_CFG_BASEADDR      0xFD000000UL
-
-/**
- * Register: XddrXmpu0CfgCtrl
- */
-#define XDDR_XMPU0_CFG_CTRL    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL )
-#define XDDR_XMPU0_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu0CfgErrSts1
- */
-#define XDDR_XMPU0_CFG_ERR_STS1    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL )
-#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgErrSts2
- */
-#define XDDR_XMPU0_CFG_ERR_STS2    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL )
-#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgPoison
- */
-#define XDDR_XMPU0_CFG_POISON    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL )
-#define XDDR_XMPU0_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT   0UL
-#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH   20UL
-#define XDDR_XMPU0_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgIsr
- */
-#define XDDR_XMPU0_CFG_ISR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL )
-#define XDDR_XMPU0_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgImr
- */
-#define XDDR_XMPU0_CFG_IMR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL )
-#define XDDR_XMPU0_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu0CfgIen
- */
-#define XDDR_XMPU0_CFG_IEN    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL )
-#define XDDR_XMPU0_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT   0UL
-#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgIds
- */
-#define XDDR_XMPU0_CFG_IDS    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL )
-#define XDDR_XMPU0_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT   0UL
-#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH   1UL
-#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgLock
- */
-#define XDDR_XMPU0_CFG_LOCK    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL )
-#define XDDR_XMPU0_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR00Strt
- */
-#define XDDR_XMPU0_CFG_R00_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL )
-#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR00End
- */
-#define XDDR_XMPU0_CFG_R00_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL )
-#define XDDR_XMPU0_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR00Mstr
- */
-#define XDDR_XMPU0_CFG_R00_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL )
-#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR00
- */
-#define XDDR_XMPU0_CFG_R00    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL )
-#define XDDR_XMPU0_CFG_R00_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R00_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R00_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R00_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR01Strt
- */
-#define XDDR_XMPU0_CFG_R01_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL )
-#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR01End
- */
-#define XDDR_XMPU0_CFG_R01_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL )
-#define XDDR_XMPU0_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR01Mstr
- */
-#define XDDR_XMPU0_CFG_R01_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL )
-#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR01
- */
-#define XDDR_XMPU0_CFG_R01    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL )
-#define XDDR_XMPU0_CFG_R01_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R01_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R01_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R01_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR02Strt
- */
-#define XDDR_XMPU0_CFG_R02_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL )
-#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR02End
- */
-#define XDDR_XMPU0_CFG_R02_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL )
-#define XDDR_XMPU0_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR02Mstr
- */
-#define XDDR_XMPU0_CFG_R02_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL )
-#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR02
- */
-#define XDDR_XMPU0_CFG_R02    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL )
-#define XDDR_XMPU0_CFG_R02_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R02_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R02_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R02_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR03Strt
- */
-#define XDDR_XMPU0_CFG_R03_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL )
-#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR03End
- */
-#define XDDR_XMPU0_CFG_R03_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL )
-#define XDDR_XMPU0_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR03Mstr
- */
-#define XDDR_XMPU0_CFG_R03_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL )
-#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR03
- */
-#define XDDR_XMPU0_CFG_R03    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL )
-#define XDDR_XMPU0_CFG_R03_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R03_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R03_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R03_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR04Strt
- */
-#define XDDR_XMPU0_CFG_R04_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL )
-#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR04End
- */
-#define XDDR_XMPU0_CFG_R04_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL )
-#define XDDR_XMPU0_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR04Mstr
- */
-#define XDDR_XMPU0_CFG_R04_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL )
-#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR04
- */
-#define XDDR_XMPU0_CFG_R04    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL )
-#define XDDR_XMPU0_CFG_R04_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R04_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R04_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R04_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR05Strt
- */
-#define XDDR_XMPU0_CFG_R05_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL )
-#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR05End
- */
-#define XDDR_XMPU0_CFG_R05_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL )
-#define XDDR_XMPU0_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR05Mstr
- */
-#define XDDR_XMPU0_CFG_R05_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL )
-#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR05
- */
-#define XDDR_XMPU0_CFG_R05    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL )
-#define XDDR_XMPU0_CFG_R05_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R05_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R05_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R05_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR06Strt
- */
-#define XDDR_XMPU0_CFG_R06_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL )
-#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR06End
- */
-#define XDDR_XMPU0_CFG_R06_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL )
-#define XDDR_XMPU0_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR06Mstr
- */
-#define XDDR_XMPU0_CFG_R06_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL )
-#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR06
- */
-#define XDDR_XMPU0_CFG_R06    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL )
-#define XDDR_XMPU0_CFG_R06_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R06_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R06_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R06_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR07Strt
- */
-#define XDDR_XMPU0_CFG_R07_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL )
-#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR07End
- */
-#define XDDR_XMPU0_CFG_R07_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL )
-#define XDDR_XMPU0_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR07Mstr
- */
-#define XDDR_XMPU0_CFG_R07_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL )
-#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR07
- */
-#define XDDR_XMPU0_CFG_R07    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL )
-#define XDDR_XMPU0_CFG_R07_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R07_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R07_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R07_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR08Strt
- */
-#define XDDR_XMPU0_CFG_R08_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL )
-#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR08End
- */
-#define XDDR_XMPU0_CFG_R08_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL )
-#define XDDR_XMPU0_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR08Mstr
- */
-#define XDDR_XMPU0_CFG_R08_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL )
-#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR08
- */
-#define XDDR_XMPU0_CFG_R08    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL )
-#define XDDR_XMPU0_CFG_R08_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R08_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R08_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R08_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR09Strt
- */
-#define XDDR_XMPU0_CFG_R09_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL )
-#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR09End
- */
-#define XDDR_XMPU0_CFG_R09_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL )
-#define XDDR_XMPU0_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR09Mstr
- */
-#define XDDR_XMPU0_CFG_R09_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL )
-#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR09
- */
-#define XDDR_XMPU0_CFG_R09    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL )
-#define XDDR_XMPU0_CFG_R09_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R09_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R09_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R09_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR10Strt
- */
-#define XDDR_XMPU0_CFG_R10_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL )
-#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR10End
- */
-#define XDDR_XMPU0_CFG_R10_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL )
-#define XDDR_XMPU0_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR10Mstr
- */
-#define XDDR_XMPU0_CFG_R10_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL )
-#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR10
- */
-#define XDDR_XMPU0_CFG_R10    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL )
-#define XDDR_XMPU0_CFG_R10_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R10_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R10_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R10_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR11Strt
- */
-#define XDDR_XMPU0_CFG_R11_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL )
-#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR11End
- */
-#define XDDR_XMPU0_CFG_R11_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL )
-#define XDDR_XMPU0_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR11Mstr
- */
-#define XDDR_XMPU0_CFG_R11_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL )
-#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR11
- */
-#define XDDR_XMPU0_CFG_R11    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL )
-#define XDDR_XMPU0_CFG_R11_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R11_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R11_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R11_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR12Strt
- */
-#define XDDR_XMPU0_CFG_R12_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL )
-#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR12End
- */
-#define XDDR_XMPU0_CFG_R12_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL )
-#define XDDR_XMPU0_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR12Mstr
- */
-#define XDDR_XMPU0_CFG_R12_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL )
-#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR12
- */
-#define XDDR_XMPU0_CFG_R12    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL )
-#define XDDR_XMPU0_CFG_R12_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R12_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R12_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R12_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR13Strt
- */
-#define XDDR_XMPU0_CFG_R13_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL )
-#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR13End
- */
-#define XDDR_XMPU0_CFG_R13_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL )
-#define XDDR_XMPU0_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR13Mstr
- */
-#define XDDR_XMPU0_CFG_R13_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL )
-#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR13
- */
-#define XDDR_XMPU0_CFG_R13    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL )
-#define XDDR_XMPU0_CFG_R13_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R13_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R13_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R13_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR14Strt
- */
-#define XDDR_XMPU0_CFG_R14_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL )
-#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR14End
- */
-#define XDDR_XMPU0_CFG_R14_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL )
-#define XDDR_XMPU0_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR14Mstr
- */
-#define XDDR_XMPU0_CFG_R14_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL )
-#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR14
- */
-#define XDDR_XMPU0_CFG_R14    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL )
-#define XDDR_XMPU0_CFG_R14_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R14_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R14_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R14_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR15Strt
- */
-#define XDDR_XMPU0_CFG_R15_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL )
-#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR15End
- */
-#define XDDR_XMPU0_CFG_R15_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL )
-#define XDDR_XMPU0_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR15Mstr
- */
-#define XDDR_XMPU0_CFG_R15_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL )
-#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu0CfgR15
- */
-#define XDDR_XMPU0_CFG_R15    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL )
-#define XDDR_XMPU0_CFG_R15_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT   3UL
-#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT   2UL
-#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT   1UL
-#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU0_CFG_R15_EN_SHIFT   0UL
-#define XDDR_XMPU0_CFG_R15_EN_WIDTH   1UL
-#define XDDR_XMPU0_CFG_R15_EN_MASK    0x00000001UL
-#define XDDR_XMPU0_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XDDR_XMPU0_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h
deleted file mode 100644
index e2fa6d4aa..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XDDR_XMPU1_CFG_H__
-#define __XDDR_XMPU1_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XddrXmpu1Cfg Base Address
- */
-#define XDDR_XMPU1_CFG_BASEADDR      0xFD010000UL
-
-/**
- * Register: XddrXmpu1CfgCtrl
- */
-#define XDDR_XMPU1_CFG_CTRL    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL )
-#define XDDR_XMPU1_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu1CfgErrSts1
- */
-#define XDDR_XMPU1_CFG_ERR_STS1    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL )
-#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgErrSts2
- */
-#define XDDR_XMPU1_CFG_ERR_STS2    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL )
-#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgPoison
- */
-#define XDDR_XMPU1_CFG_POISON    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL )
-#define XDDR_XMPU1_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT   0UL
-#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH   20UL
-#define XDDR_XMPU1_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgIsr
- */
-#define XDDR_XMPU1_CFG_ISR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL )
-#define XDDR_XMPU1_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgImr
- */
-#define XDDR_XMPU1_CFG_IMR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL )
-#define XDDR_XMPU1_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu1CfgIen
- */
-#define XDDR_XMPU1_CFG_IEN    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL )
-#define XDDR_XMPU1_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT   0UL
-#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgIds
- */
-#define XDDR_XMPU1_CFG_IDS    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL )
-#define XDDR_XMPU1_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT   0UL
-#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH   1UL
-#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgLock
- */
-#define XDDR_XMPU1_CFG_LOCK    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL )
-#define XDDR_XMPU1_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR00Strt
- */
-#define XDDR_XMPU1_CFG_R00_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL )
-#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR00End
- */
-#define XDDR_XMPU1_CFG_R00_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL )
-#define XDDR_XMPU1_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR00Mstr
- */
-#define XDDR_XMPU1_CFG_R00_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL )
-#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR00
- */
-#define XDDR_XMPU1_CFG_R00    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL )
-#define XDDR_XMPU1_CFG_R00_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R00_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R00_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R00_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR01Strt
- */
-#define XDDR_XMPU1_CFG_R01_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL )
-#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR01End
- */
-#define XDDR_XMPU1_CFG_R01_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL )
-#define XDDR_XMPU1_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR01Mstr
- */
-#define XDDR_XMPU1_CFG_R01_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL )
-#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR01
- */
-#define XDDR_XMPU1_CFG_R01    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL )
-#define XDDR_XMPU1_CFG_R01_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R01_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R01_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R01_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR02Strt
- */
-#define XDDR_XMPU1_CFG_R02_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL )
-#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR02End
- */
-#define XDDR_XMPU1_CFG_R02_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL )
-#define XDDR_XMPU1_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR02Mstr
- */
-#define XDDR_XMPU1_CFG_R02_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL )
-#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR02
- */
-#define XDDR_XMPU1_CFG_R02    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL )
-#define XDDR_XMPU1_CFG_R02_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R02_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R02_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R02_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR03Strt
- */
-#define XDDR_XMPU1_CFG_R03_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL )
-#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR03End
- */
-#define XDDR_XMPU1_CFG_R03_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL )
-#define XDDR_XMPU1_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR03Mstr
- */
-#define XDDR_XMPU1_CFG_R03_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL )
-#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR03
- */
-#define XDDR_XMPU1_CFG_R03    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL )
-#define XDDR_XMPU1_CFG_R03_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R03_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R03_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R03_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR04Strt
- */
-#define XDDR_XMPU1_CFG_R04_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL )
-#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR04End
- */
-#define XDDR_XMPU1_CFG_R04_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL )
-#define XDDR_XMPU1_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR04Mstr
- */
-#define XDDR_XMPU1_CFG_R04_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL )
-#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR04
- */
-#define XDDR_XMPU1_CFG_R04    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL )
-#define XDDR_XMPU1_CFG_R04_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R04_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R04_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R04_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR05Strt
- */
-#define XDDR_XMPU1_CFG_R05_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL )
-#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR05End
- */
-#define XDDR_XMPU1_CFG_R05_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL )
-#define XDDR_XMPU1_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR05Mstr
- */
-#define XDDR_XMPU1_CFG_R05_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL )
-#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR05
- */
-#define XDDR_XMPU1_CFG_R05    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL )
-#define XDDR_XMPU1_CFG_R05_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R05_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R05_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R05_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR06Strt
- */
-#define XDDR_XMPU1_CFG_R06_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL )
-#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR06End
- */
-#define XDDR_XMPU1_CFG_R06_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL )
-#define XDDR_XMPU1_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR06Mstr
- */
-#define XDDR_XMPU1_CFG_R06_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL )
-#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR06
- */
-#define XDDR_XMPU1_CFG_R06    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL )
-#define XDDR_XMPU1_CFG_R06_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R06_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R06_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R06_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR07Strt
- */
-#define XDDR_XMPU1_CFG_R07_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL )
-#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR07End
- */
-#define XDDR_XMPU1_CFG_R07_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL )
-#define XDDR_XMPU1_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR07Mstr
- */
-#define XDDR_XMPU1_CFG_R07_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL )
-#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR07
- */
-#define XDDR_XMPU1_CFG_R07    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL )
-#define XDDR_XMPU1_CFG_R07_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R07_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R07_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R07_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR08Strt
- */
-#define XDDR_XMPU1_CFG_R08_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL )
-#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR08End
- */
-#define XDDR_XMPU1_CFG_R08_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL )
-#define XDDR_XMPU1_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR08Mstr
- */
-#define XDDR_XMPU1_CFG_R08_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL )
-#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR08
- */
-#define XDDR_XMPU1_CFG_R08    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL )
-#define XDDR_XMPU1_CFG_R08_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R08_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R08_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R08_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR09Strt
- */
-#define XDDR_XMPU1_CFG_R09_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL )
-#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR09End
- */
-#define XDDR_XMPU1_CFG_R09_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL )
-#define XDDR_XMPU1_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR09Mstr
- */
-#define XDDR_XMPU1_CFG_R09_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL )
-#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR09
- */
-#define XDDR_XMPU1_CFG_R09    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL )
-#define XDDR_XMPU1_CFG_R09_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R09_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R09_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R09_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR10Strt
- */
-#define XDDR_XMPU1_CFG_R10_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL )
-#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR10End
- */
-#define XDDR_XMPU1_CFG_R10_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL )
-#define XDDR_XMPU1_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR10Mstr
- */
-#define XDDR_XMPU1_CFG_R10_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL )
-#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR10
- */
-#define XDDR_XMPU1_CFG_R10    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL )
-#define XDDR_XMPU1_CFG_R10_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R10_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R10_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R10_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR11Strt
- */
-#define XDDR_XMPU1_CFG_R11_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL )
-#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR11End
- */
-#define XDDR_XMPU1_CFG_R11_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL )
-#define XDDR_XMPU1_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR11Mstr
- */
-#define XDDR_XMPU1_CFG_R11_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL )
-#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR11
- */
-#define XDDR_XMPU1_CFG_R11    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL )
-#define XDDR_XMPU1_CFG_R11_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R11_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R11_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R11_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR12Strt
- */
-#define XDDR_XMPU1_CFG_R12_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL )
-#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR12End
- */
-#define XDDR_XMPU1_CFG_R12_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL )
-#define XDDR_XMPU1_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR12Mstr
- */
-#define XDDR_XMPU1_CFG_R12_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL )
-#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR12
- */
-#define XDDR_XMPU1_CFG_R12    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL )
-#define XDDR_XMPU1_CFG_R12_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R12_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R12_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R12_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR13Strt
- */
-#define XDDR_XMPU1_CFG_R13_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL )
-#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR13End
- */
-#define XDDR_XMPU1_CFG_R13_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL )
-#define XDDR_XMPU1_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR13Mstr
- */
-#define XDDR_XMPU1_CFG_R13_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL )
-#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR13
- */
-#define XDDR_XMPU1_CFG_R13    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL )
-#define XDDR_XMPU1_CFG_R13_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R13_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R13_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R13_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR14Strt
- */
-#define XDDR_XMPU1_CFG_R14_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL )
-#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR14End
- */
-#define XDDR_XMPU1_CFG_R14_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL )
-#define XDDR_XMPU1_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR14Mstr
- */
-#define XDDR_XMPU1_CFG_R14_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL )
-#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR14
- */
-#define XDDR_XMPU1_CFG_R14    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL )
-#define XDDR_XMPU1_CFG_R14_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R14_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R14_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R14_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR15Strt
- */
-#define XDDR_XMPU1_CFG_R15_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL )
-#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR15End
- */
-#define XDDR_XMPU1_CFG_R15_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL )
-#define XDDR_XMPU1_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR15Mstr
- */
-#define XDDR_XMPU1_CFG_R15_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL )
-#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu1CfgR15
- */
-#define XDDR_XMPU1_CFG_R15    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL )
-#define XDDR_XMPU1_CFG_R15_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT   3UL
-#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT   2UL
-#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT   1UL
-#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU1_CFG_R15_EN_SHIFT   0UL
-#define XDDR_XMPU1_CFG_R15_EN_WIDTH   1UL
-#define XDDR_XMPU1_CFG_R15_EN_MASK    0x00000001UL
-#define XDDR_XMPU1_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XDDR_XMPU1_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h
deleted file mode 100644
index 55ea2a7d3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XDDR_XMPU2_CFG_H__
-#define __XDDR_XMPU2_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XddrXmpu2Cfg Base Address
- */
-#define XDDR_XMPU2_CFG_BASEADDR      0xFD020000UL
-
-/**
- * Register: XddrXmpu2CfgCtrl
- */
-#define XDDR_XMPU2_CFG_CTRL    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL )
-#define XDDR_XMPU2_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu2CfgErrSts1
- */
-#define XDDR_XMPU2_CFG_ERR_STS1    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL )
-#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgErrSts2
- */
-#define XDDR_XMPU2_CFG_ERR_STS2    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL )
-#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgPoison
- */
-#define XDDR_XMPU2_CFG_POISON    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL )
-#define XDDR_XMPU2_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT   0UL
-#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH   20UL
-#define XDDR_XMPU2_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgIsr
- */
-#define XDDR_XMPU2_CFG_ISR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL )
-#define XDDR_XMPU2_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgImr
- */
-#define XDDR_XMPU2_CFG_IMR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL )
-#define XDDR_XMPU2_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu2CfgIen
- */
-#define XDDR_XMPU2_CFG_IEN    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL )
-#define XDDR_XMPU2_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT   0UL
-#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgIds
- */
-#define XDDR_XMPU2_CFG_IDS    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL )
-#define XDDR_XMPU2_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT   0UL
-#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH   1UL
-#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgLock
- */
-#define XDDR_XMPU2_CFG_LOCK    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL )
-#define XDDR_XMPU2_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR00Strt
- */
-#define XDDR_XMPU2_CFG_R00_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL )
-#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR00End
- */
-#define XDDR_XMPU2_CFG_R00_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL )
-#define XDDR_XMPU2_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR00Mstr
- */
-#define XDDR_XMPU2_CFG_R00_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL )
-#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR00
- */
-#define XDDR_XMPU2_CFG_R00    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL )
-#define XDDR_XMPU2_CFG_R00_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R00_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R00_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R00_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR01Strt
- */
-#define XDDR_XMPU2_CFG_R01_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL )
-#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR01End
- */
-#define XDDR_XMPU2_CFG_R01_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL )
-#define XDDR_XMPU2_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR01Mstr
- */
-#define XDDR_XMPU2_CFG_R01_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL )
-#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR01
- */
-#define XDDR_XMPU2_CFG_R01    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL )
-#define XDDR_XMPU2_CFG_R01_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R01_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R01_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R01_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR02Strt
- */
-#define XDDR_XMPU2_CFG_R02_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL )
-#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR02End
- */
-#define XDDR_XMPU2_CFG_R02_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL )
-#define XDDR_XMPU2_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR02Mstr
- */
-#define XDDR_XMPU2_CFG_R02_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL )
-#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR02
- */
-#define XDDR_XMPU2_CFG_R02    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL )
-#define XDDR_XMPU2_CFG_R02_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R02_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R02_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R02_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR03Strt
- */
-#define XDDR_XMPU2_CFG_R03_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL )
-#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR03End
- */
-#define XDDR_XMPU2_CFG_R03_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL )
-#define XDDR_XMPU2_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR03Mstr
- */
-#define XDDR_XMPU2_CFG_R03_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL )
-#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR03
- */
-#define XDDR_XMPU2_CFG_R03    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL )
-#define XDDR_XMPU2_CFG_R03_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R03_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R03_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R03_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR04Strt
- */
-#define XDDR_XMPU2_CFG_R04_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL )
-#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR04End
- */
-#define XDDR_XMPU2_CFG_R04_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL )
-#define XDDR_XMPU2_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR04Mstr
- */
-#define XDDR_XMPU2_CFG_R04_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL )
-#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR04
- */
-#define XDDR_XMPU2_CFG_R04    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL )
-#define XDDR_XMPU2_CFG_R04_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R04_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R04_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R04_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR05Strt
- */
-#define XDDR_XMPU2_CFG_R05_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL )
-#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR05End
- */
-#define XDDR_XMPU2_CFG_R05_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL )
-#define XDDR_XMPU2_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR05Mstr
- */
-#define XDDR_XMPU2_CFG_R05_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL )
-#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR05
- */
-#define XDDR_XMPU2_CFG_R05    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL )
-#define XDDR_XMPU2_CFG_R05_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R05_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R05_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R05_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR06Strt
- */
-#define XDDR_XMPU2_CFG_R06_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL )
-#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR06End
- */
-#define XDDR_XMPU2_CFG_R06_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL )
-#define XDDR_XMPU2_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR06Mstr
- */
-#define XDDR_XMPU2_CFG_R06_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL )
-#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR06
- */
-#define XDDR_XMPU2_CFG_R06    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL )
-#define XDDR_XMPU2_CFG_R06_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R06_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R06_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R06_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR07Strt
- */
-#define XDDR_XMPU2_CFG_R07_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL )
-#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR07End
- */
-#define XDDR_XMPU2_CFG_R07_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL )
-#define XDDR_XMPU2_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR07Mstr
- */
-#define XDDR_XMPU2_CFG_R07_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL )
-#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR07
- */
-#define XDDR_XMPU2_CFG_R07    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL )
-#define XDDR_XMPU2_CFG_R07_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R07_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R07_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R07_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR08Strt
- */
-#define XDDR_XMPU2_CFG_R08_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL )
-#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR08End
- */
-#define XDDR_XMPU2_CFG_R08_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL )
-#define XDDR_XMPU2_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR08Mstr
- */
-#define XDDR_XMPU2_CFG_R08_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL )
-#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR08
- */
-#define XDDR_XMPU2_CFG_R08    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL )
-#define XDDR_XMPU2_CFG_R08_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R08_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R08_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R08_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR09Strt
- */
-#define XDDR_XMPU2_CFG_R09_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL )
-#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR09End
- */
-#define XDDR_XMPU2_CFG_R09_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL )
-#define XDDR_XMPU2_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR09Mstr
- */
-#define XDDR_XMPU2_CFG_R09_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL )
-#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR09
- */
-#define XDDR_XMPU2_CFG_R09    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL )
-#define XDDR_XMPU2_CFG_R09_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R09_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R09_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R09_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR10Strt
- */
-#define XDDR_XMPU2_CFG_R10_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL )
-#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR10End
- */
-#define XDDR_XMPU2_CFG_R10_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL )
-#define XDDR_XMPU2_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR10Mstr
- */
-#define XDDR_XMPU2_CFG_R10_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL )
-#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR10
- */
-#define XDDR_XMPU2_CFG_R10    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL )
-#define XDDR_XMPU2_CFG_R10_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R10_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R10_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R10_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR11Strt
- */
-#define XDDR_XMPU2_CFG_R11_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL )
-#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR11End
- */
-#define XDDR_XMPU2_CFG_R11_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL )
-#define XDDR_XMPU2_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR11Mstr
- */
-#define XDDR_XMPU2_CFG_R11_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL )
-#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR11
- */
-#define XDDR_XMPU2_CFG_R11    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL )
-#define XDDR_XMPU2_CFG_R11_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R11_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R11_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R11_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR12Strt
- */
-#define XDDR_XMPU2_CFG_R12_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL )
-#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR12End
- */
-#define XDDR_XMPU2_CFG_R12_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL )
-#define XDDR_XMPU2_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR12Mstr
- */
-#define XDDR_XMPU2_CFG_R12_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL )
-#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR12
- */
-#define XDDR_XMPU2_CFG_R12    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL )
-#define XDDR_XMPU2_CFG_R12_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R12_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R12_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R12_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR13Strt
- */
-#define XDDR_XMPU2_CFG_R13_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL )
-#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR13End
- */
-#define XDDR_XMPU2_CFG_R13_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL )
-#define XDDR_XMPU2_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR13Mstr
- */
-#define XDDR_XMPU2_CFG_R13_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL )
-#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR13
- */
-#define XDDR_XMPU2_CFG_R13    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL )
-#define XDDR_XMPU2_CFG_R13_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R13_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R13_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R13_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR14Strt
- */
-#define XDDR_XMPU2_CFG_R14_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL )
-#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR14End
- */
-#define XDDR_XMPU2_CFG_R14_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL )
-#define XDDR_XMPU2_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR14Mstr
- */
-#define XDDR_XMPU2_CFG_R14_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL )
-#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR14
- */
-#define XDDR_XMPU2_CFG_R14    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL )
-#define XDDR_XMPU2_CFG_R14_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R14_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R14_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R14_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR15Strt
- */
-#define XDDR_XMPU2_CFG_R15_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL )
-#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR15End
- */
-#define XDDR_XMPU2_CFG_R15_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL )
-#define XDDR_XMPU2_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR15Mstr
- */
-#define XDDR_XMPU2_CFG_R15_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL )
-#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu2CfgR15
- */
-#define XDDR_XMPU2_CFG_R15    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL )
-#define XDDR_XMPU2_CFG_R15_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT   3UL
-#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT   2UL
-#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT   1UL
-#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU2_CFG_R15_EN_SHIFT   0UL
-#define XDDR_XMPU2_CFG_R15_EN_WIDTH   1UL
-#define XDDR_XMPU2_CFG_R15_EN_MASK    0x00000001UL
-#define XDDR_XMPU2_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XDDR_XMPU2_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h
deleted file mode 100644
index 416314967..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XDDR_XMPU3_CFG_H__
-#define __XDDR_XMPU3_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XddrXmpu3Cfg Base Address
- */
-#define XDDR_XMPU3_CFG_BASEADDR      0xFD030000UL
-
-/**
- * Register: XddrXmpu3CfgCtrl
- */
-#define XDDR_XMPU3_CFG_CTRL    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL )
-#define XDDR_XMPU3_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu3CfgErrSts1
- */
-#define XDDR_XMPU3_CFG_ERR_STS1    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL )
-#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgErrSts2
- */
-#define XDDR_XMPU3_CFG_ERR_STS2    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL )
-#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgPoison
- */
-#define XDDR_XMPU3_CFG_POISON    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL )
-#define XDDR_XMPU3_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT   0UL
-#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH   20UL
-#define XDDR_XMPU3_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgIsr
- */
-#define XDDR_XMPU3_CFG_ISR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL )
-#define XDDR_XMPU3_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgImr
- */
-#define XDDR_XMPU3_CFG_IMR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL )
-#define XDDR_XMPU3_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu3CfgIen
- */
-#define XDDR_XMPU3_CFG_IEN    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL )
-#define XDDR_XMPU3_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT   0UL
-#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgIds
- */
-#define XDDR_XMPU3_CFG_IDS    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL )
-#define XDDR_XMPU3_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT   0UL
-#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH   1UL
-#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgLock
- */
-#define XDDR_XMPU3_CFG_LOCK    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL )
-#define XDDR_XMPU3_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR00Strt
- */
-#define XDDR_XMPU3_CFG_R00_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL )
-#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR00End
- */
-#define XDDR_XMPU3_CFG_R00_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL )
-#define XDDR_XMPU3_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR00Mstr
- */
-#define XDDR_XMPU3_CFG_R00_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL )
-#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR00
- */
-#define XDDR_XMPU3_CFG_R00    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL )
-#define XDDR_XMPU3_CFG_R00_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R00_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R00_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R00_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR01Strt
- */
-#define XDDR_XMPU3_CFG_R01_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL )
-#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR01End
- */
-#define XDDR_XMPU3_CFG_R01_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL )
-#define XDDR_XMPU3_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR01Mstr
- */
-#define XDDR_XMPU3_CFG_R01_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL )
-#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR01
- */
-#define XDDR_XMPU3_CFG_R01    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL )
-#define XDDR_XMPU3_CFG_R01_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R01_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R01_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R01_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR02Strt
- */
-#define XDDR_XMPU3_CFG_R02_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL )
-#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR02End
- */
-#define XDDR_XMPU3_CFG_R02_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL )
-#define XDDR_XMPU3_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR02Mstr
- */
-#define XDDR_XMPU3_CFG_R02_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL )
-#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR02
- */
-#define XDDR_XMPU3_CFG_R02    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL )
-#define XDDR_XMPU3_CFG_R02_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R02_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R02_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R02_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR03Strt
- */
-#define XDDR_XMPU3_CFG_R03_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL )
-#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR03End
- */
-#define XDDR_XMPU3_CFG_R03_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL )
-#define XDDR_XMPU3_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR03Mstr
- */
-#define XDDR_XMPU3_CFG_R03_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL )
-#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR03
- */
-#define XDDR_XMPU3_CFG_R03    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL )
-#define XDDR_XMPU3_CFG_R03_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R03_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R03_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R03_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR04Strt
- */
-#define XDDR_XMPU3_CFG_R04_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL )
-#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR04End
- */
-#define XDDR_XMPU3_CFG_R04_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL )
-#define XDDR_XMPU3_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR04Mstr
- */
-#define XDDR_XMPU3_CFG_R04_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL )
-#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR04
- */
-#define XDDR_XMPU3_CFG_R04    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL )
-#define XDDR_XMPU3_CFG_R04_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R04_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R04_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R04_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR05Strt
- */
-#define XDDR_XMPU3_CFG_R05_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL )
-#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR05End
- */
-#define XDDR_XMPU3_CFG_R05_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL )
-#define XDDR_XMPU3_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR05Mstr
- */
-#define XDDR_XMPU3_CFG_R05_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL )
-#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR05
- */
-#define XDDR_XMPU3_CFG_R05    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL )
-#define XDDR_XMPU3_CFG_R05_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R05_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R05_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R05_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR06Strt
- */
-#define XDDR_XMPU3_CFG_R06_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL )
-#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR06End
- */
-#define XDDR_XMPU3_CFG_R06_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL )
-#define XDDR_XMPU3_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR06Mstr
- */
-#define XDDR_XMPU3_CFG_R06_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL )
-#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR06
- */
-#define XDDR_XMPU3_CFG_R06    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL )
-#define XDDR_XMPU3_CFG_R06_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R06_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R06_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R06_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR07Strt
- */
-#define XDDR_XMPU3_CFG_R07_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL )
-#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR07End
- */
-#define XDDR_XMPU3_CFG_R07_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL )
-#define XDDR_XMPU3_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR07Mstr
- */
-#define XDDR_XMPU3_CFG_R07_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL )
-#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR07
- */
-#define XDDR_XMPU3_CFG_R07    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL )
-#define XDDR_XMPU3_CFG_R07_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R07_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R07_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R07_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR08Strt
- */
-#define XDDR_XMPU3_CFG_R08_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL )
-#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR08End
- */
-#define XDDR_XMPU3_CFG_R08_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL )
-#define XDDR_XMPU3_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR08Mstr
- */
-#define XDDR_XMPU3_CFG_R08_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL )
-#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR08
- */
-#define XDDR_XMPU3_CFG_R08    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL )
-#define XDDR_XMPU3_CFG_R08_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R08_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R08_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R08_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR09Strt
- */
-#define XDDR_XMPU3_CFG_R09_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL )
-#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR09End
- */
-#define XDDR_XMPU3_CFG_R09_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL )
-#define XDDR_XMPU3_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR09Mstr
- */
-#define XDDR_XMPU3_CFG_R09_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL )
-#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR09
- */
-#define XDDR_XMPU3_CFG_R09    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL )
-#define XDDR_XMPU3_CFG_R09_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R09_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R09_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R09_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR10Strt
- */
-#define XDDR_XMPU3_CFG_R10_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL )
-#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR10End
- */
-#define XDDR_XMPU3_CFG_R10_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL )
-#define XDDR_XMPU3_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR10Mstr
- */
-#define XDDR_XMPU3_CFG_R10_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL )
-#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR10
- */
-#define XDDR_XMPU3_CFG_R10    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL )
-#define XDDR_XMPU3_CFG_R10_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R10_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R10_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R10_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR11Strt
- */
-#define XDDR_XMPU3_CFG_R11_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL )
-#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR11End
- */
-#define XDDR_XMPU3_CFG_R11_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL )
-#define XDDR_XMPU3_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR11Mstr
- */
-#define XDDR_XMPU3_CFG_R11_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL )
-#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR11
- */
-#define XDDR_XMPU3_CFG_R11    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL )
-#define XDDR_XMPU3_CFG_R11_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R11_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R11_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R11_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR12Strt
- */
-#define XDDR_XMPU3_CFG_R12_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL )
-#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR12End
- */
-#define XDDR_XMPU3_CFG_R12_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL )
-#define XDDR_XMPU3_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR12Mstr
- */
-#define XDDR_XMPU3_CFG_R12_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL )
-#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR12
- */
-#define XDDR_XMPU3_CFG_R12    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL )
-#define XDDR_XMPU3_CFG_R12_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R12_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R12_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R12_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR13Strt
- */
-#define XDDR_XMPU3_CFG_R13_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL )
-#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR13End
- */
-#define XDDR_XMPU3_CFG_R13_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL )
-#define XDDR_XMPU3_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR13Mstr
- */
-#define XDDR_XMPU3_CFG_R13_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL )
-#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR13
- */
-#define XDDR_XMPU3_CFG_R13    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL )
-#define XDDR_XMPU3_CFG_R13_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R13_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R13_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R13_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR14Strt
- */
-#define XDDR_XMPU3_CFG_R14_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL )
-#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR14End
- */
-#define XDDR_XMPU3_CFG_R14_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL )
-#define XDDR_XMPU3_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR14Mstr
- */
-#define XDDR_XMPU3_CFG_R14_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL )
-#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR14
- */
-#define XDDR_XMPU3_CFG_R14    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL )
-#define XDDR_XMPU3_CFG_R14_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R14_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R14_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R14_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR15Strt
- */
-#define XDDR_XMPU3_CFG_R15_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL )
-#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR15End
- */
-#define XDDR_XMPU3_CFG_R15_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL )
-#define XDDR_XMPU3_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR15Mstr
- */
-#define XDDR_XMPU3_CFG_R15_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL )
-#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu3CfgR15
- */
-#define XDDR_XMPU3_CFG_R15    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL )
-#define XDDR_XMPU3_CFG_R15_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT   3UL
-#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT   2UL
-#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT   1UL
-#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU3_CFG_R15_EN_SHIFT   0UL
-#define XDDR_XMPU3_CFG_R15_EN_WIDTH   1UL
-#define XDDR_XMPU3_CFG_R15_EN_MASK    0x00000001UL
-#define XDDR_XMPU3_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XDDR_XMPU3_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h
deleted file mode 100644
index 2df814419..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XDDR_XMPU4_CFG_H__
-#define __XDDR_XMPU4_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XddrXmpu4Cfg Base Address
- */
-#define XDDR_XMPU4_CFG_BASEADDR      0xFD040000UL
-
-/**
- * Register: XddrXmpu4CfgCtrl
- */
-#define XDDR_XMPU4_CFG_CTRL    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL )
-#define XDDR_XMPU4_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu4CfgErrSts1
- */
-#define XDDR_XMPU4_CFG_ERR_STS1    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL )
-#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgErrSts2
- */
-#define XDDR_XMPU4_CFG_ERR_STS2    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL )
-#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgPoison
- */
-#define XDDR_XMPU4_CFG_POISON    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL )
-#define XDDR_XMPU4_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT   0UL
-#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH   20UL
-#define XDDR_XMPU4_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgIsr
- */
-#define XDDR_XMPU4_CFG_ISR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL )
-#define XDDR_XMPU4_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgImr
- */
-#define XDDR_XMPU4_CFG_IMR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL )
-#define XDDR_XMPU4_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu4CfgIen
- */
-#define XDDR_XMPU4_CFG_IEN    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL )
-#define XDDR_XMPU4_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT   0UL
-#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgIds
- */
-#define XDDR_XMPU4_CFG_IDS    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL )
-#define XDDR_XMPU4_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT   0UL
-#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH   1UL
-#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgLock
- */
-#define XDDR_XMPU4_CFG_LOCK    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL )
-#define XDDR_XMPU4_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR00Strt
- */
-#define XDDR_XMPU4_CFG_R00_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL )
-#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR00End
- */
-#define XDDR_XMPU4_CFG_R00_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL )
-#define XDDR_XMPU4_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR00Mstr
- */
-#define XDDR_XMPU4_CFG_R00_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL )
-#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR00
- */
-#define XDDR_XMPU4_CFG_R00    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL )
-#define XDDR_XMPU4_CFG_R00_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R00_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R00_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R00_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR01Strt
- */
-#define XDDR_XMPU4_CFG_R01_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL )
-#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR01End
- */
-#define XDDR_XMPU4_CFG_R01_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL )
-#define XDDR_XMPU4_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR01Mstr
- */
-#define XDDR_XMPU4_CFG_R01_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL )
-#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR01
- */
-#define XDDR_XMPU4_CFG_R01    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL )
-#define XDDR_XMPU4_CFG_R01_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R01_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R01_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R01_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR02Strt
- */
-#define XDDR_XMPU4_CFG_R02_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL )
-#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR02End
- */
-#define XDDR_XMPU4_CFG_R02_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL )
-#define XDDR_XMPU4_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR02Mstr
- */
-#define XDDR_XMPU4_CFG_R02_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL )
-#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR02
- */
-#define XDDR_XMPU4_CFG_R02    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL )
-#define XDDR_XMPU4_CFG_R02_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R02_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R02_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R02_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR03Strt
- */
-#define XDDR_XMPU4_CFG_R03_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL )
-#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR03End
- */
-#define XDDR_XMPU4_CFG_R03_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL )
-#define XDDR_XMPU4_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR03Mstr
- */
-#define XDDR_XMPU4_CFG_R03_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL )
-#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR03
- */
-#define XDDR_XMPU4_CFG_R03    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL )
-#define XDDR_XMPU4_CFG_R03_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R03_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R03_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R03_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR04Strt
- */
-#define XDDR_XMPU4_CFG_R04_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL )
-#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR04End
- */
-#define XDDR_XMPU4_CFG_R04_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL )
-#define XDDR_XMPU4_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR04Mstr
- */
-#define XDDR_XMPU4_CFG_R04_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL )
-#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR04
- */
-#define XDDR_XMPU4_CFG_R04    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL )
-#define XDDR_XMPU4_CFG_R04_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R04_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R04_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R04_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR05Strt
- */
-#define XDDR_XMPU4_CFG_R05_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL )
-#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR05End
- */
-#define XDDR_XMPU4_CFG_R05_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL )
-#define XDDR_XMPU4_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR05Mstr
- */
-#define XDDR_XMPU4_CFG_R05_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL )
-#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR05
- */
-#define XDDR_XMPU4_CFG_R05    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL )
-#define XDDR_XMPU4_CFG_R05_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R05_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R05_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R05_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR06Strt
- */
-#define XDDR_XMPU4_CFG_R06_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL )
-#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR06End
- */
-#define XDDR_XMPU4_CFG_R06_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL )
-#define XDDR_XMPU4_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR06Mstr
- */
-#define XDDR_XMPU4_CFG_R06_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL )
-#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR06
- */
-#define XDDR_XMPU4_CFG_R06    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL )
-#define XDDR_XMPU4_CFG_R06_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R06_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R06_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R06_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR07Strt
- */
-#define XDDR_XMPU4_CFG_R07_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL )
-#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR07End
- */
-#define XDDR_XMPU4_CFG_R07_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL )
-#define XDDR_XMPU4_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR07Mstr
- */
-#define XDDR_XMPU4_CFG_R07_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL )
-#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR07
- */
-#define XDDR_XMPU4_CFG_R07    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL )
-#define XDDR_XMPU4_CFG_R07_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R07_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R07_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R07_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR08Strt
- */
-#define XDDR_XMPU4_CFG_R08_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL )
-#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR08End
- */
-#define XDDR_XMPU4_CFG_R08_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL )
-#define XDDR_XMPU4_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR08Mstr
- */
-#define XDDR_XMPU4_CFG_R08_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL )
-#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR08
- */
-#define XDDR_XMPU4_CFG_R08    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL )
-#define XDDR_XMPU4_CFG_R08_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R08_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R08_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R08_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR09Strt
- */
-#define XDDR_XMPU4_CFG_R09_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL )
-#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR09End
- */
-#define XDDR_XMPU4_CFG_R09_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL )
-#define XDDR_XMPU4_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR09Mstr
- */
-#define XDDR_XMPU4_CFG_R09_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL )
-#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR09
- */
-#define XDDR_XMPU4_CFG_R09    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL )
-#define XDDR_XMPU4_CFG_R09_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R09_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R09_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R09_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR10Strt
- */
-#define XDDR_XMPU4_CFG_R10_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL )
-#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR10End
- */
-#define XDDR_XMPU4_CFG_R10_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL )
-#define XDDR_XMPU4_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR10Mstr
- */
-#define XDDR_XMPU4_CFG_R10_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL )
-#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR10
- */
-#define XDDR_XMPU4_CFG_R10    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL )
-#define XDDR_XMPU4_CFG_R10_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R10_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R10_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R10_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR11Strt
- */
-#define XDDR_XMPU4_CFG_R11_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL )
-#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR11End
- */
-#define XDDR_XMPU4_CFG_R11_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL )
-#define XDDR_XMPU4_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR11Mstr
- */
-#define XDDR_XMPU4_CFG_R11_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL )
-#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR11
- */
-#define XDDR_XMPU4_CFG_R11    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL )
-#define XDDR_XMPU4_CFG_R11_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R11_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R11_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R11_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR12Strt
- */
-#define XDDR_XMPU4_CFG_R12_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL )
-#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR12End
- */
-#define XDDR_XMPU4_CFG_R12_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL )
-#define XDDR_XMPU4_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR12Mstr
- */
-#define XDDR_XMPU4_CFG_R12_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL )
-#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR12
- */
-#define XDDR_XMPU4_CFG_R12    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL )
-#define XDDR_XMPU4_CFG_R12_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R12_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R12_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R12_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR13Strt
- */
-#define XDDR_XMPU4_CFG_R13_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL )
-#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR13End
- */
-#define XDDR_XMPU4_CFG_R13_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL )
-#define XDDR_XMPU4_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR13Mstr
- */
-#define XDDR_XMPU4_CFG_R13_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL )
-#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR13
- */
-#define XDDR_XMPU4_CFG_R13    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL )
-#define XDDR_XMPU4_CFG_R13_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R13_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R13_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R13_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR14Strt
- */
-#define XDDR_XMPU4_CFG_R14_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL )
-#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR14End
- */
-#define XDDR_XMPU4_CFG_R14_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL )
-#define XDDR_XMPU4_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR14Mstr
- */
-#define XDDR_XMPU4_CFG_R14_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL )
-#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR14
- */
-#define XDDR_XMPU4_CFG_R14    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL )
-#define XDDR_XMPU4_CFG_R14_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R14_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R14_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R14_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR15Strt
- */
-#define XDDR_XMPU4_CFG_R15_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL )
-#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR15End
- */
-#define XDDR_XMPU4_CFG_R15_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL )
-#define XDDR_XMPU4_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR15Mstr
- */
-#define XDDR_XMPU4_CFG_R15_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL )
-#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu4CfgR15
- */
-#define XDDR_XMPU4_CFG_R15    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL )
-#define XDDR_XMPU4_CFG_R15_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT   3UL
-#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT   2UL
-#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT   1UL
-#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU4_CFG_R15_EN_SHIFT   0UL
-#define XDDR_XMPU4_CFG_R15_EN_WIDTH   1UL
-#define XDDR_XMPU4_CFG_R15_EN_MASK    0x00000001UL
-#define XDDR_XMPU4_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XDDR_XMPU4_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h
deleted file mode 100644
index 60811718d..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XDDR_XMPU5_CFG_H__
-#define __XDDR_XMPU5_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XddrXmpu5Cfg Base Address
- */
-#define XDDR_XMPU5_CFG_BASEADDR      0xFD050000UL
-
-/**
- * Register: XddrXmpu5CfgCtrl
- */
-#define XDDR_XMPU5_CFG_CTRL    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL )
-#define XDDR_XMPU5_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu5CfgErrSts1
- */
-#define XDDR_XMPU5_CFG_ERR_STS1    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL )
-#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgErrSts2
- */
-#define XDDR_XMPU5_CFG_ERR_STS2    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL )
-#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgPoison
- */
-#define XDDR_XMPU5_CFG_POISON    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL )
-#define XDDR_XMPU5_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT   0UL
-#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH   20UL
-#define XDDR_XMPU5_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgIsr
- */
-#define XDDR_XMPU5_CFG_ISR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL )
-#define XDDR_XMPU5_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgImr
- */
-#define XDDR_XMPU5_CFG_IMR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL )
-#define XDDR_XMPU5_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT   0UL
-#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XddrXmpu5CfgIen
- */
-#define XDDR_XMPU5_CFG_IEN    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL )
-#define XDDR_XMPU5_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT   0UL
-#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgIds
- */
-#define XDDR_XMPU5_CFG_IDS    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL )
-#define XDDR_XMPU5_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT   0UL
-#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH   1UL
-#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgLock
- */
-#define XDDR_XMPU5_CFG_LOCK    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL )
-#define XDDR_XMPU5_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR00Strt
- */
-#define XDDR_XMPU5_CFG_R00_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL )
-#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR00End
- */
-#define XDDR_XMPU5_CFG_R00_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL )
-#define XDDR_XMPU5_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR00Mstr
- */
-#define XDDR_XMPU5_CFG_R00_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL )
-#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR00
- */
-#define XDDR_XMPU5_CFG_R00    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL )
-#define XDDR_XMPU5_CFG_R00_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R00_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R00_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R00_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR01Strt
- */
-#define XDDR_XMPU5_CFG_R01_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL )
-#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR01End
- */
-#define XDDR_XMPU5_CFG_R01_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL )
-#define XDDR_XMPU5_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR01Mstr
- */
-#define XDDR_XMPU5_CFG_R01_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL )
-#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR01
- */
-#define XDDR_XMPU5_CFG_R01    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL )
-#define XDDR_XMPU5_CFG_R01_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R01_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R01_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R01_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR02Strt
- */
-#define XDDR_XMPU5_CFG_R02_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL )
-#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR02End
- */
-#define XDDR_XMPU5_CFG_R02_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL )
-#define XDDR_XMPU5_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR02Mstr
- */
-#define XDDR_XMPU5_CFG_R02_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL )
-#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR02
- */
-#define XDDR_XMPU5_CFG_R02    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL )
-#define XDDR_XMPU5_CFG_R02_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R02_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R02_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R02_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR03Strt
- */
-#define XDDR_XMPU5_CFG_R03_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL )
-#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR03End
- */
-#define XDDR_XMPU5_CFG_R03_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL )
-#define XDDR_XMPU5_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR03Mstr
- */
-#define XDDR_XMPU5_CFG_R03_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL )
-#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR03
- */
-#define XDDR_XMPU5_CFG_R03    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL )
-#define XDDR_XMPU5_CFG_R03_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R03_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R03_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R03_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR04Strt
- */
-#define XDDR_XMPU5_CFG_R04_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL )
-#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR04End
- */
-#define XDDR_XMPU5_CFG_R04_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL )
-#define XDDR_XMPU5_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR04Mstr
- */
-#define XDDR_XMPU5_CFG_R04_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL )
-#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR04
- */
-#define XDDR_XMPU5_CFG_R04    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL )
-#define XDDR_XMPU5_CFG_R04_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R04_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R04_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R04_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR05Strt
- */
-#define XDDR_XMPU5_CFG_R05_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL )
-#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR05End
- */
-#define XDDR_XMPU5_CFG_R05_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL )
-#define XDDR_XMPU5_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR05Mstr
- */
-#define XDDR_XMPU5_CFG_R05_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL )
-#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR05
- */
-#define XDDR_XMPU5_CFG_R05    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL )
-#define XDDR_XMPU5_CFG_R05_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R05_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R05_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R05_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR06Strt
- */
-#define XDDR_XMPU5_CFG_R06_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL )
-#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR06End
- */
-#define XDDR_XMPU5_CFG_R06_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL )
-#define XDDR_XMPU5_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR06Mstr
- */
-#define XDDR_XMPU5_CFG_R06_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL )
-#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR06
- */
-#define XDDR_XMPU5_CFG_R06    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL )
-#define XDDR_XMPU5_CFG_R06_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R06_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R06_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R06_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR07Strt
- */
-#define XDDR_XMPU5_CFG_R07_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL )
-#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR07End
- */
-#define XDDR_XMPU5_CFG_R07_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL )
-#define XDDR_XMPU5_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR07Mstr
- */
-#define XDDR_XMPU5_CFG_R07_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL )
-#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR07
- */
-#define XDDR_XMPU5_CFG_R07    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL )
-#define XDDR_XMPU5_CFG_R07_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R07_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R07_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R07_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR08Strt
- */
-#define XDDR_XMPU5_CFG_R08_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL )
-#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR08End
- */
-#define XDDR_XMPU5_CFG_R08_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL )
-#define XDDR_XMPU5_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR08Mstr
- */
-#define XDDR_XMPU5_CFG_R08_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL )
-#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR08
- */
-#define XDDR_XMPU5_CFG_R08    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL )
-#define XDDR_XMPU5_CFG_R08_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R08_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R08_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R08_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR09Strt
- */
-#define XDDR_XMPU5_CFG_R09_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL )
-#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR09End
- */
-#define XDDR_XMPU5_CFG_R09_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL )
-#define XDDR_XMPU5_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR09Mstr
- */
-#define XDDR_XMPU5_CFG_R09_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL )
-#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR09
- */
-#define XDDR_XMPU5_CFG_R09    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL )
-#define XDDR_XMPU5_CFG_R09_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R09_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R09_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R09_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR10Strt
- */
-#define XDDR_XMPU5_CFG_R10_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL )
-#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR10End
- */
-#define XDDR_XMPU5_CFG_R10_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL )
-#define XDDR_XMPU5_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR10Mstr
- */
-#define XDDR_XMPU5_CFG_R10_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL )
-#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR10
- */
-#define XDDR_XMPU5_CFG_R10    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL )
-#define XDDR_XMPU5_CFG_R10_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R10_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R10_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R10_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR11Strt
- */
-#define XDDR_XMPU5_CFG_R11_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL )
-#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR11End
- */
-#define XDDR_XMPU5_CFG_R11_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL )
-#define XDDR_XMPU5_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR11Mstr
- */
-#define XDDR_XMPU5_CFG_R11_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL )
-#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR11
- */
-#define XDDR_XMPU5_CFG_R11    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL )
-#define XDDR_XMPU5_CFG_R11_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R11_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R11_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R11_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR12Strt
- */
-#define XDDR_XMPU5_CFG_R12_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL )
-#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR12End
- */
-#define XDDR_XMPU5_CFG_R12_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL )
-#define XDDR_XMPU5_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR12Mstr
- */
-#define XDDR_XMPU5_CFG_R12_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL )
-#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR12
- */
-#define XDDR_XMPU5_CFG_R12    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL )
-#define XDDR_XMPU5_CFG_R12_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R12_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R12_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R12_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR13Strt
- */
-#define XDDR_XMPU5_CFG_R13_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL )
-#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR13End
- */
-#define XDDR_XMPU5_CFG_R13_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL )
-#define XDDR_XMPU5_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR13Mstr
- */
-#define XDDR_XMPU5_CFG_R13_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL )
-#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR13
- */
-#define XDDR_XMPU5_CFG_R13    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL )
-#define XDDR_XMPU5_CFG_R13_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R13_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R13_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R13_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR14Strt
- */
-#define XDDR_XMPU5_CFG_R14_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL )
-#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR14End
- */
-#define XDDR_XMPU5_CFG_R14_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL )
-#define XDDR_XMPU5_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR14Mstr
- */
-#define XDDR_XMPU5_CFG_R14_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL )
-#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR14
- */
-#define XDDR_XMPU5_CFG_R14    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL )
-#define XDDR_XMPU5_CFG_R14_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R14_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R14_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R14_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR15Strt
- */
-#define XDDR_XMPU5_CFG_R15_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL )
-#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR15End
- */
-#define XDDR_XMPU5_CFG_R15_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL )
-#define XDDR_XMPU5_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH   28UL
-#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR15Mstr
- */
-#define XDDR_XMPU5_CFG_R15_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL )
-#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XddrXmpu5CfgR15
- */
-#define XDDR_XMPU5_CFG_R15    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL )
-#define XDDR_XMPU5_CFG_R15_RSTVAL   0x00000008UL
-
-#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT   3UL
-#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT   2UL
-#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT   1UL
-#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XDDR_XMPU5_CFG_R15_EN_SHIFT   0UL
-#define XDDR_XMPU5_CFG_R15_EN_WIDTH   1UL
-#define XDDR_XMPU5_CFG_R15_EN_MASK    0x00000001UL
-#define XDDR_XMPU5_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XDDR_XMPU5_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h
deleted file mode 100644
index b565b958a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h
+++ /dev/null
@@ -1,382 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XFPD_SLCR_H__
-#define __XFPD_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XfpdSlcr Base Address
- */
-#define XFPD_SLCR_BASEADDR      0xFD610000UL
-
-/**
- * Register: XfpdSlcrWprot0
- */
-#define XFPD_SLCR_WPROT0    ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
-#define XFPD_SLCR_WPROT0_RSTVAL   0x00000001UL
-
-#define XFPD_SLCR_WPROT0_ACT_SHIFT   0UL
-#define XFPD_SLCR_WPROT0_ACT_WIDTH   1UL
-#define XFPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
-#define XFPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrCtrl
- */
-#define XFPD_SLCR_CTRL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
-#define XFPD_SLCR_CTRL_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
-#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
-#define XFPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
-#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrIsr
- */
-#define XFPD_SLCR_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
-#define XFPD_SLCR_ISR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrImr
- */
-#define XFPD_SLCR_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
-#define XFPD_SLCR_IMR_RSTVAL   0x00000001UL
-
-#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrIer
- */
-#define XFPD_SLCR_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
-#define XFPD_SLCR_IER_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrIdr
- */
-#define XFPD_SLCR_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
-#define XFPD_SLCR_IDR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrItr
- */
-#define XFPD_SLCR_ITR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
-#define XFPD_SLCR_ITR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrWdtClkSel
- */
-#define XFPD_SLCR_WDT_CLK_SEL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
-#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_WDT_CLK_SEL_SHIFT   0UL
-#define XFPD_SLCR_WDT_CLK_SEL_WIDTH   1UL
-#define XFPD_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
-#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrIntFpd
- */
-#define XFPD_SLCR_INT_FPD    ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
-#define XFPD_SLCR_INT_FPD_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT   0UL
-#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH   1UL
-#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK    0x00000001UL
-#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrGpu
- */
-#define XFPD_SLCR_GPU    ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
-#define XFPD_SLCR_GPU_RSTVAL   0x00000007UL
-
-#define XFPD_SLCR_GPU_ARCACHE_SHIFT   7UL
-#define XFPD_SLCR_GPU_ARCACHE_WIDTH   4UL
-#define XFPD_SLCR_GPU_ARCACHE_MASK    0x00000780UL
-#define XFPD_SLCR_GPU_ARCACHE_DEFVAL  0x0UL
-
-#define XFPD_SLCR_GPU_AWCACHE_SHIFT   3UL
-#define XFPD_SLCR_GPU_AWCACHE_WIDTH   4UL
-#define XFPD_SLCR_GPU_AWCACHE_MASK    0x00000078UL
-#define XFPD_SLCR_GPU_AWCACHE_DEFVAL  0x0UL
-
-#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT   2UL
-#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH   1UL
-#define XFPD_SLCR_GPU_PP1_IDLE_MASK    0x00000004UL
-#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL  0x1UL
-
-#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT   1UL
-#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH   1UL
-#define XFPD_SLCR_GPU_PP0_IDLE_MASK    0x00000002UL
-#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL  0x1UL
-
-#define XFPD_SLCR_GPU_IDLE_SHIFT   0UL
-#define XFPD_SLCR_GPU_IDLE_WIDTH   1UL
-#define XFPD_SLCR_GPU_IDLE_MASK    0x00000001UL
-#define XFPD_SLCR_GPU_IDLE_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrGdmaCfg
- */
-#define XFPD_SLCR_GDMA_CFG    ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
-#define XFPD_SLCR_GDMA_CFG_RSTVAL   0x00000048UL
-
-#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT   5UL
-#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH   2UL
-#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK    0x00000060UL
-#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL  0x2UL
-
-#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT   0UL
-#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH   5UL
-#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK    0x0000001fUL
-#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL  0x8UL
-
-/**
- * Register: XfpdSlcrGdma
- */
-#define XFPD_SLCR_GDMA    ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
-#define XFPD_SLCR_GDMA_RSTVAL   0x00003b3bUL
-
-#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT   12UL
-#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH   3UL
-#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK    0x00007000UL
-#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL  0x3UL
-
-#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT   11UL
-#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH   1UL
-#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK    0x00000800UL
-#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL  0x1UL
-
-#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT   8UL
-#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH   3UL
-#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK    0x00000700UL
-#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL  0x3UL
-
-#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT   4UL
-#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH   3UL
-#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK    0x00000070UL
-#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL  0x3UL
-
-#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT   3UL
-#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH   1UL
-#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK    0x00000008UL
-#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL  0x1UL
-
-#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT   0UL
-#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH   3UL
-#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK    0x00000007UL
-#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL  0x3UL
-
-/**
- * Register: XfpdSlcrAfiFs
- */
-#define XFPD_SLCR_AFI_FS    ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
-#define XFPD_SLCR_AFI_FS_RSTVAL   0x00000a00UL
-
-#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT   10UL
-#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH   2UL
-#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK    0x00000c00UL
-#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL  0x2UL
-
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT   8UL
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH   2UL
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK    0x00000300UL
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL  0x2UL
-
-/**
- * Register: XfpdSlcrErrAtbIsr
- */
-#define XFPD_SLCR_ERR_ATB_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
-#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT   2UL
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK    0x00000004UL
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT   1UL
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK    0x00000002UL
-#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT   0UL
-#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK    0x00000001UL
-#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrErrAtbImr
- */
-#define XFPD_SLCR_ERR_ATB_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
-#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000007UL
-
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT   2UL
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK    0x00000004UL
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL  0x1UL
-
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT   1UL
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK    0x00000002UL
-#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL  0x1UL
-
-#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT   0UL
-#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK    0x00000001UL
-#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrErrAtbIer
- */
-#define XFPD_SLCR_ERR_ATB_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
-#define XFPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT   2UL
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK    0x00000004UL
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT   1UL
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK    0x00000002UL
-#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT   0UL
-#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK    0x00000001UL
-#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrErrAtbIdr
- */
-#define XFPD_SLCR_ERR_ATB_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
-#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT   2UL
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK    0x00000004UL
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT   1UL
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK    0x00000002UL
-#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT   0UL
-#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH   1UL
-#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK    0x00000001UL
-#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrAtbCmdstore
- */
-#define XFPD_SLCR_ATB_CMDSTORE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
-#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL   0x00000007UL
-
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT   2UL
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH   1UL
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK    0x00000004UL
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL  0x1UL
-
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT   1UL
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH   1UL
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK    0x00000002UL
-#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL  0x1UL
-
-#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT   0UL
-#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH   1UL
-#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK    0x00000001UL
-#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrAtbRespEn
- */
-#define XFPD_SLCR_ATB_RESP_EN    ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
-#define XFPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT   2UL
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH   1UL
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK    0x00000004UL
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT   1UL
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH   1UL
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK    0x00000002UL
-#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT   0UL
-#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH   1UL
-#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK    0x00000001UL
-#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrAtbResptype
- */
-#define XFPD_SLCR_ATB_RESPTYPE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
-#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL   0x00000007UL
-
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT   2UL
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH   1UL
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK    0x00000004UL
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL  0x1UL
-
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT   1UL
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH   1UL
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK    0x00000002UL
-#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL  0x1UL
-
-#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT   0UL
-#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH   1UL
-#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK    0x00000001UL
-#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrAtbPrescale
- */
-#define XFPD_SLCR_ATB_PRESCALE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
-#define XFPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
-
-#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
-#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
-#define XFPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
-#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
-
-#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
-#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
-#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
-#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XFPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h
deleted file mode 100644
index 6541a4f1d..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XFPD_SLCR_SECURE_H__
-#define __XFPD_SLCR_SECURE_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XfpdSlcrSecure Base Address
- */
-#define XFPD_SLCR_SECURE_BASEADDR      0xFD690000UL
-
-/**
- * Register: XfpdSlcrSecCtrl
- */
-#define XFPD_SLCR_SEC_CTRL    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
-#define XFPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
-#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
-#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrSecIsr
- */
-#define XFPD_SLCR_SEC_ISR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
-#define XFPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrSecImr
- */
-#define XFPD_SLCR_SEC_IMR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
-#define XFPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
-
-#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrSecIer
- */
-#define XFPD_SLCR_SEC_IER    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
-#define XFPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrSecIdr
- */
-#define XFPD_SLCR_SEC_IDR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
-#define XFPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrSecItr
- */
-#define XFPD_SLCR_SEC_ITR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
-#define XFPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
-#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
-#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrSecSata
- */
-#define XFPD_SLCR_SEC_SATA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
-#define XFPD_SLCR_SEC_SATA_RSTVAL   0x0000000eUL
-
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT   3UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH   1UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK    0x00000008UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT   2UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH   1UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK    0x00000004UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT   1UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH   1UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK    0x00000002UL
-#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT   0UL
-#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH   1UL
-#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdSlcrSecPcie
- */
-#define XFPD_SLCR_SEC_PCIE    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
-#define XFPD_SLCR_SEC_PCIE_RSTVAL   0x01ffffffUL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT   24UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK    0x01000000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT   23UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK    0x00800000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT   22UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK    0x00400000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT   21UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK    0x00200000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT   20UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK    0x00100000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT   19UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK    0x00080000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT   18UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK    0x00040000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT   17UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK    0x00020000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT   16UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK    0x00010000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT   15UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK    0x00008000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT   14UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK    0x00004000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT   13UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK    0x00002000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT   12UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK    0x00001000UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT   11UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK    0x00000800UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT   10UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK    0x00000400UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT   9UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK    0x00000200UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT   8UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK    0x00000100UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT   7UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK    0x00000080UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT   6UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK    0x00000040UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT   5UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK    0x00000020UL
-#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT   4UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK    0x00000010UL
-#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT   3UL
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK    0x00000008UL
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT   2UL
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK    0x00000004UL
-#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK    0x00000002UL
-#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL  0x1UL
-
-#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT   0UL
-#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH   1UL
-#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrSecDpdma
- */
-#define XFPD_SLCR_SEC_DPDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
-#define XFPD_SLCR_SEC_DPDMA_RSTVAL   0x00000001UL
-
-#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT   0UL
-#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH   1UL
-#define XFPD_SLCR_SEC_DPDMA_TZ_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL  0x1UL
-
-/**
- * Register: XfpdSlcrSecGdma
- */
-#define XFPD_SLCR_SEC_GDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
-#define XFPD_SLCR_SEC_GDMA_RSTVAL   0x000000ffUL
-
-#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT   0UL
-#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH   8UL
-#define XFPD_SLCR_SEC_GDMA_TZ_MASK    0x000000ffUL
-#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL  0xffUL
-
-/**
- * Register: XfpdSlcrSecGic
- */
-#define XFPD_SLCR_SEC_GIC    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
-#define XFPD_SLCR_SEC_GIC_RSTVAL   0x00000000UL
-
-#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT   0UL
-#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH   1UL
-#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK    0x00000001UL
-#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XFPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h
deleted file mode 100644
index 75aef19f9..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XFPD_XMPU_CFG_H__
-#define __XFPD_XMPU_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XfpdXmpuCfg Base Address
- */
-#define XFPD_XMPU_CFG_BASEADDR      0xFD5D0000UL
-
-/**
- * Register: XfpdXmpuCfgCtrl
- */
-#define XFPD_XMPU_CFG_CTRL    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL )
-#define XFPD_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XfpdXmpuCfgErrSts1
- */
-#define XFPD_XMPU_CFG_ERR_STS1    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL )
-#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgErrSts2
- */
-#define XFPD_XMPU_CFG_ERR_STS2    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL )
-#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgPoison
- */
-#define XFPD_XMPU_CFG_POISON    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
-#define XFPD_XMPU_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_POISON_BASE_SHIFT   0UL
-#define XFPD_XMPU_CFG_POISON_BASE_WIDTH   20UL
-#define XFPD_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgIsr
- */
-#define XFPD_XMPU_CFG_ISR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL )
-#define XFPD_XMPU_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
-#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
-#define XFPD_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgImr
- */
-#define XFPD_XMPU_CFG_IMR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL )
-#define XFPD_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
-#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
-#define XFPD_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XfpdXmpuCfgIen
- */
-#define XFPD_XMPU_CFG_IEN    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL )
-#define XFPD_XMPU_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
-#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
-#define XFPD_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgIds
- */
-#define XFPD_XMPU_CFG_IDS    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
-#define XFPD_XMPU_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
-#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
-#define XFPD_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgLock
- */
-#define XFPD_XMPU_CFG_LOCK    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL )
-#define XFPD_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR00Strt
- */
-#define XFPD_XMPU_CFG_R00_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL )
-#define XFPD_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR00End
- */
-#define XFPD_XMPU_CFG_R00_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL )
-#define XFPD_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR00Mstr
- */
-#define XFPD_XMPU_CFG_R00_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL )
-#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR00
- */
-#define XFPD_XMPU_CFG_R00    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
-#define XFPD_XMPU_CFG_R00_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R00_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R00_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R00_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR01Strt
- */
-#define XFPD_XMPU_CFG_R01_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL )
-#define XFPD_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR01End
- */
-#define XFPD_XMPU_CFG_R01_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL )
-#define XFPD_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR01Mstr
- */
-#define XFPD_XMPU_CFG_R01_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL )
-#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR01
- */
-#define XFPD_XMPU_CFG_R01    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
-#define XFPD_XMPU_CFG_R01_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R01_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R01_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R01_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR02Strt
- */
-#define XFPD_XMPU_CFG_R02_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL )
-#define XFPD_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR02End
- */
-#define XFPD_XMPU_CFG_R02_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL )
-#define XFPD_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR02Mstr
- */
-#define XFPD_XMPU_CFG_R02_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL )
-#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR02
- */
-#define XFPD_XMPU_CFG_R02    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
-#define XFPD_XMPU_CFG_R02_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R02_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R02_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R02_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR03Strt
- */
-#define XFPD_XMPU_CFG_R03_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL )
-#define XFPD_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR03End
- */
-#define XFPD_XMPU_CFG_R03_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL )
-#define XFPD_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR03Mstr
- */
-#define XFPD_XMPU_CFG_R03_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL )
-#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR03
- */
-#define XFPD_XMPU_CFG_R03    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
-#define XFPD_XMPU_CFG_R03_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R03_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R03_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R03_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR04Strt
- */
-#define XFPD_XMPU_CFG_R04_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL )
-#define XFPD_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR04End
- */
-#define XFPD_XMPU_CFG_R04_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL )
-#define XFPD_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR04Mstr
- */
-#define XFPD_XMPU_CFG_R04_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL )
-#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR04
- */
-#define XFPD_XMPU_CFG_R04    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
-#define XFPD_XMPU_CFG_R04_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R04_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R04_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R04_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR05Strt
- */
-#define XFPD_XMPU_CFG_R05_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL )
-#define XFPD_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR05End
- */
-#define XFPD_XMPU_CFG_R05_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL )
-#define XFPD_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR05Mstr
- */
-#define XFPD_XMPU_CFG_R05_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL )
-#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR05
- */
-#define XFPD_XMPU_CFG_R05    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
-#define XFPD_XMPU_CFG_R05_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R05_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R05_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R05_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR06Strt
- */
-#define XFPD_XMPU_CFG_R06_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL )
-#define XFPD_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR06End
- */
-#define XFPD_XMPU_CFG_R06_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL )
-#define XFPD_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR06Mstr
- */
-#define XFPD_XMPU_CFG_R06_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL )
-#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR06
- */
-#define XFPD_XMPU_CFG_R06    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
-#define XFPD_XMPU_CFG_R06_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R06_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R06_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R06_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR07Strt
- */
-#define XFPD_XMPU_CFG_R07_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL )
-#define XFPD_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR07End
- */
-#define XFPD_XMPU_CFG_R07_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL )
-#define XFPD_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR07Mstr
- */
-#define XFPD_XMPU_CFG_R07_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL )
-#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR07
- */
-#define XFPD_XMPU_CFG_R07    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
-#define XFPD_XMPU_CFG_R07_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R07_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R07_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R07_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR08Strt
- */
-#define XFPD_XMPU_CFG_R08_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL )
-#define XFPD_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR08End
- */
-#define XFPD_XMPU_CFG_R08_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL )
-#define XFPD_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR08Mstr
- */
-#define XFPD_XMPU_CFG_R08_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL )
-#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR08
- */
-#define XFPD_XMPU_CFG_R08    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
-#define XFPD_XMPU_CFG_R08_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R08_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R08_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R08_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR09Strt
- */
-#define XFPD_XMPU_CFG_R09_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL )
-#define XFPD_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR09End
- */
-#define XFPD_XMPU_CFG_R09_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL )
-#define XFPD_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR09Mstr
- */
-#define XFPD_XMPU_CFG_R09_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL )
-#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR09
- */
-#define XFPD_XMPU_CFG_R09    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
-#define XFPD_XMPU_CFG_R09_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R09_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R09_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R09_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR10Strt
- */
-#define XFPD_XMPU_CFG_R10_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
-#define XFPD_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR10End
- */
-#define XFPD_XMPU_CFG_R10_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
-#define XFPD_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR10Mstr
- */
-#define XFPD_XMPU_CFG_R10_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
-#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR10
- */
-#define XFPD_XMPU_CFG_R10    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
-#define XFPD_XMPU_CFG_R10_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R10_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R10_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R10_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR11Strt
- */
-#define XFPD_XMPU_CFG_R11_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
-#define XFPD_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR11End
- */
-#define XFPD_XMPU_CFG_R11_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
-#define XFPD_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR11Mstr
- */
-#define XFPD_XMPU_CFG_R11_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
-#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR11
- */
-#define XFPD_XMPU_CFG_R11    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
-#define XFPD_XMPU_CFG_R11_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R11_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R11_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R11_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR12Strt
- */
-#define XFPD_XMPU_CFG_R12_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
-#define XFPD_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR12End
- */
-#define XFPD_XMPU_CFG_R12_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
-#define XFPD_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR12Mstr
- */
-#define XFPD_XMPU_CFG_R12_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
-#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR12
- */
-#define XFPD_XMPU_CFG_R12    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
-#define XFPD_XMPU_CFG_R12_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R12_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R12_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R12_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR13Strt
- */
-#define XFPD_XMPU_CFG_R13_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
-#define XFPD_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR13End
- */
-#define XFPD_XMPU_CFG_R13_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
-#define XFPD_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR13Mstr
- */
-#define XFPD_XMPU_CFG_R13_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
-#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR13
- */
-#define XFPD_XMPU_CFG_R13    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
-#define XFPD_XMPU_CFG_R13_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R13_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R13_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R13_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR14Strt
- */
-#define XFPD_XMPU_CFG_R14_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
-#define XFPD_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR14End
- */
-#define XFPD_XMPU_CFG_R14_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
-#define XFPD_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR14Mstr
- */
-#define XFPD_XMPU_CFG_R14_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
-#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR14
- */
-#define XFPD_XMPU_CFG_R14    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
-#define XFPD_XMPU_CFG_R14_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R14_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R14_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R14_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR15Strt
- */
-#define XFPD_XMPU_CFG_R15_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
-#define XFPD_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR15End
- */
-#define XFPD_XMPU_CFG_R15_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
-#define XFPD_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
-#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
-#define XFPD_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR15Mstr
- */
-#define XFPD_XMPU_CFG_R15_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
-#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuCfgR15
- */
-#define XFPD_XMPU_CFG_R15    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
-#define XFPD_XMPU_CFG_R15_RSTVAL   0x00000008UL
-
-#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT   3UL
-#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH   1UL
-#define XFPD_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT   2UL
-#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT   1UL
-#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH   1UL
-#define XFPD_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XFPD_XMPU_CFG_R15_EN_SHIFT   0UL
-#define XFPD_XMPU_CFG_R15_EN_WIDTH   1UL
-#define XFPD_XMPU_CFG_R15_EN_MASK    0x00000001UL
-#define XFPD_XMPU_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XFPD_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h
deleted file mode 100644
index 39172f1f4..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XFPD_XMPU_SINK_H__
-#define __XFPD_XMPU_SINK_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XfpdXmpuSink Base Address
- */
-#define XFPD_XMPU_SINK_BASEADDR      0xFD4F0000UL
-
-/**
- * Register: XfpdXmpuSinkErrSts
- */
-#define XFPD_XMPU_SINK_ERR_STS    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
-#define XFPD_XMPU_SINK_ERR_STS_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT   31UL
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH   1UL
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
-
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT   0UL
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH   12UL
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuSinkIsr
- */
-#define XFPD_XMPU_SINK_ISR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
-#define XFPD_XMPU_SINK_ISR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT   0UL
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH   1UL
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuSinkImr
- */
-#define XFPD_XMPU_SINK_IMR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
-#define XFPD_XMPU_SINK_IMR_RSTVAL   0x00000001UL
-
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT   0UL
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH   1UL
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
-
-/**
- * Register: XfpdXmpuSinkIer
- */
-#define XFPD_XMPU_SINK_IER    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
-#define XFPD_XMPU_SINK_IER_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT   0UL
-#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH   1UL
-#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
-#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
-
-/**
- * Register: XfpdXmpuSinkIdr
- */
-#define XFPD_XMPU_SINK_IDR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
-#define XFPD_XMPU_SINK_IDR_RSTVAL   0x00000000UL
-
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT   0UL
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH   1UL
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XFPD_XMPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h
deleted file mode 100644
index cb4ad4903..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XIOU_SECURE_SLCR_H__
-#define __XIOU_SECURE_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XiouSecureSlcr Base Address
- */
-#define XIOU_SECURE_SLCR_BASEADDR      0xFF240000UL
-
-/**
- * Register: XiouSecSlcrAxiWprtcn
- */
-#define XIOU_SEC_SLCR_AXI_WPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
-#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL   0x00000000UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT   25UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK    0x0e000000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT   22UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK    0x01c00000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   19UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00380000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   16UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00070000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   9UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000e00UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   6UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x000001c0UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000038UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   0UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000007UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
-
-/**
- * Register: XiouSecSlcrAxiRprtcn
- */
-#define XIOU_SEC_SLCR_AXI_RPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
-#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL   0x00000000UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT   22UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK    0x01c00000UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   19UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00380000UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   16UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00070000UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   9UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000e00UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   6UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x000001c0UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000038UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   0UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000007UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
-
-/**
- * Register: XiouSecSlcrCtrl
- */
-#define XIOU_SEC_SLCR_CTRL    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
-#define XIOU_SEC_SLCR_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
-
-/**
- * Register: XiouSecSlcrIsr
- */
-#define XIOU_SEC_SLCR_ISR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
-#define XIOU_SEC_SLCR_ISR_RSTVAL   0x00000000UL
-
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XiouSecSlcrImr
- */
-#define XIOU_SEC_SLCR_IMR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
-#define XIOU_SEC_SLCR_IMR_RSTVAL   0x00000001UL
-
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
-
-/**
- * Register: XiouSecSlcrIer
- */
-#define XIOU_SEC_SLCR_IER    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
-#define XIOU_SEC_SLCR_IER_RSTVAL   0x00000000UL
-
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XiouSecSlcrIdr
- */
-#define XIOU_SEC_SLCR_IDR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
-#define XIOU_SEC_SLCR_IDR_RSTVAL   0x00000000UL
-
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XiouSecSlcrItr
- */
-#define XIOU_SEC_SLCR_ITR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
-#define XIOU_SEC_SLCR_ITR_RSTVAL   0x00000000UL
-
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XIOU_SECURE_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h
deleted file mode 100644
index d81d178d3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h
+++ /dev/null
@@ -1,4029 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XIOU_SLCR_H__
-#define __XIOU_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XiouSlcr Base Address
- */
-#define XIOU_SLCR_BASEADDR      0xFF180000UL
-
-/**
- * Register: XiouSlcrMioPin0
- */
-#define XIOU_SLCR_MIO_PIN_0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL )
-#define XIOU_SLCR_MIO_PIN_0_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin1
- */
-#define XIOU_SLCR_MIO_PIN_1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL )
-#define XIOU_SLCR_MIO_PIN_1_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin2
- */
-#define XIOU_SLCR_MIO_PIN_2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL )
-#define XIOU_SLCR_MIO_PIN_2_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin3
- */
-#define XIOU_SLCR_MIO_PIN_3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL )
-#define XIOU_SLCR_MIO_PIN_3_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin4
- */
-#define XIOU_SLCR_MIO_PIN_4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL )
-#define XIOU_SLCR_MIO_PIN_4_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin5
- */
-#define XIOU_SLCR_MIO_PIN_5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL )
-#define XIOU_SLCR_MIO_PIN_5_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin6
- */
-#define XIOU_SLCR_MIO_PIN_6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL )
-#define XIOU_SLCR_MIO_PIN_6_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin7
- */
-#define XIOU_SLCR_MIO_PIN_7    ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL )
-#define XIOU_SLCR_MIO_PIN_7_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin8
- */
-#define XIOU_SLCR_MIO_PIN_8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL )
-#define XIOU_SLCR_MIO_PIN_8_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin9
- */
-#define XIOU_SLCR_MIO_PIN_9    ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL )
-#define XIOU_SLCR_MIO_PIN_9_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin10
- */
-#define XIOU_SLCR_MIO_PIN_10    ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL )
-#define XIOU_SLCR_MIO_PIN_10_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin11
- */
-#define XIOU_SLCR_MIO_PIN_11    ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL )
-#define XIOU_SLCR_MIO_PIN_11_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin12
- */
-#define XIOU_SLCR_MIO_PIN_12    ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL )
-#define XIOU_SLCR_MIO_PIN_12_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin13
- */
-#define XIOU_SLCR_MIO_PIN_13    ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL )
-#define XIOU_SLCR_MIO_PIN_13_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin14
- */
-#define XIOU_SLCR_MIO_PIN_14    ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL )
-#define XIOU_SLCR_MIO_PIN_14_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin15
- */
-#define XIOU_SLCR_MIO_PIN_15    ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL )
-#define XIOU_SLCR_MIO_PIN_15_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin16
- */
-#define XIOU_SLCR_MIO_PIN_16    ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL )
-#define XIOU_SLCR_MIO_PIN_16_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin17
- */
-#define XIOU_SLCR_MIO_PIN_17    ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL )
-#define XIOU_SLCR_MIO_PIN_17_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin18
- */
-#define XIOU_SLCR_MIO_PIN_18    ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL )
-#define XIOU_SLCR_MIO_PIN_18_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin19
- */
-#define XIOU_SLCR_MIO_PIN_19    ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL )
-#define XIOU_SLCR_MIO_PIN_19_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin20
- */
-#define XIOU_SLCR_MIO_PIN_20    ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL )
-#define XIOU_SLCR_MIO_PIN_20_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin21
- */
-#define XIOU_SLCR_MIO_PIN_21    ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL )
-#define XIOU_SLCR_MIO_PIN_21_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin22
- */
-#define XIOU_SLCR_MIO_PIN_22    ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL )
-#define XIOU_SLCR_MIO_PIN_22_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin23
- */
-#define XIOU_SLCR_MIO_PIN_23    ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL )
-#define XIOU_SLCR_MIO_PIN_23_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin24
- */
-#define XIOU_SLCR_MIO_PIN_24    ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL )
-#define XIOU_SLCR_MIO_PIN_24_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin25
- */
-#define XIOU_SLCR_MIO_PIN_25    ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL )
-#define XIOU_SLCR_MIO_PIN_25_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin26
- */
-#define XIOU_SLCR_MIO_PIN_26    ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL )
-#define XIOU_SLCR_MIO_PIN_26_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin27
- */
-#define XIOU_SLCR_MIO_PIN_27    ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL )
-#define XIOU_SLCR_MIO_PIN_27_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin28
- */
-#define XIOU_SLCR_MIO_PIN_28    ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL )
-#define XIOU_SLCR_MIO_PIN_28_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin29
- */
-#define XIOU_SLCR_MIO_PIN_29    ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL )
-#define XIOU_SLCR_MIO_PIN_29_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin30
- */
-#define XIOU_SLCR_MIO_PIN_30    ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL )
-#define XIOU_SLCR_MIO_PIN_30_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin31
- */
-#define XIOU_SLCR_MIO_PIN_31    ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL )
-#define XIOU_SLCR_MIO_PIN_31_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin32
- */
-#define XIOU_SLCR_MIO_PIN_32    ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL )
-#define XIOU_SLCR_MIO_PIN_32_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin33
- */
-#define XIOU_SLCR_MIO_PIN_33    ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL )
-#define XIOU_SLCR_MIO_PIN_33_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin34
- */
-#define XIOU_SLCR_MIO_PIN_34    ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL )
-#define XIOU_SLCR_MIO_PIN_34_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin35
- */
-#define XIOU_SLCR_MIO_PIN_35    ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL )
-#define XIOU_SLCR_MIO_PIN_35_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin36
- */
-#define XIOU_SLCR_MIO_PIN_36    ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL )
-#define XIOU_SLCR_MIO_PIN_36_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin37
- */
-#define XIOU_SLCR_MIO_PIN_37    ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL )
-#define XIOU_SLCR_MIO_PIN_37_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin38
- */
-#define XIOU_SLCR_MIO_PIN_38    ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL )
-#define XIOU_SLCR_MIO_PIN_38_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin39
- */
-#define XIOU_SLCR_MIO_PIN_39    ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL )
-#define XIOU_SLCR_MIO_PIN_39_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin40
- */
-#define XIOU_SLCR_MIO_PIN_40    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL )
-#define XIOU_SLCR_MIO_PIN_40_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin41
- */
-#define XIOU_SLCR_MIO_PIN_41    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL )
-#define XIOU_SLCR_MIO_PIN_41_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin42
- */
-#define XIOU_SLCR_MIO_PIN_42    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL )
-#define XIOU_SLCR_MIO_PIN_42_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin43
- */
-#define XIOU_SLCR_MIO_PIN_43    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL )
-#define XIOU_SLCR_MIO_PIN_43_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin44
- */
-#define XIOU_SLCR_MIO_PIN_44    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL )
-#define XIOU_SLCR_MIO_PIN_44_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin45
- */
-#define XIOU_SLCR_MIO_PIN_45    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL )
-#define XIOU_SLCR_MIO_PIN_45_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin46
- */
-#define XIOU_SLCR_MIO_PIN_46    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL )
-#define XIOU_SLCR_MIO_PIN_46_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin47
- */
-#define XIOU_SLCR_MIO_PIN_47    ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL )
-#define XIOU_SLCR_MIO_PIN_47_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin48
- */
-#define XIOU_SLCR_MIO_PIN_48    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL )
-#define XIOU_SLCR_MIO_PIN_48_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin49
- */
-#define XIOU_SLCR_MIO_PIN_49    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL )
-#define XIOU_SLCR_MIO_PIN_49_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin50
- */
-#define XIOU_SLCR_MIO_PIN_50    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL )
-#define XIOU_SLCR_MIO_PIN_50_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin51
- */
-#define XIOU_SLCR_MIO_PIN_51    ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL )
-#define XIOU_SLCR_MIO_PIN_51_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin52
- */
-#define XIOU_SLCR_MIO_PIN_52    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL )
-#define XIOU_SLCR_MIO_PIN_52_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin53
- */
-#define XIOU_SLCR_MIO_PIN_53    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL )
-#define XIOU_SLCR_MIO_PIN_53_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin54
- */
-#define XIOU_SLCR_MIO_PIN_54    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL )
-#define XIOU_SLCR_MIO_PIN_54_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin55
- */
-#define XIOU_SLCR_MIO_PIN_55    ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL )
-#define XIOU_SLCR_MIO_PIN_55_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin56
- */
-#define XIOU_SLCR_MIO_PIN_56    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL )
-#define XIOU_SLCR_MIO_PIN_56_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin57
- */
-#define XIOU_SLCR_MIO_PIN_57    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL )
-#define XIOU_SLCR_MIO_PIN_57_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin58
- */
-#define XIOU_SLCR_MIO_PIN_58    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL )
-#define XIOU_SLCR_MIO_PIN_58_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin59
- */
-#define XIOU_SLCR_MIO_PIN_59    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL )
-#define XIOU_SLCR_MIO_PIN_59_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin60
- */
-#define XIOU_SLCR_MIO_PIN_60    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL )
-#define XIOU_SLCR_MIO_PIN_60_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin61
- */
-#define XIOU_SLCR_MIO_PIN_61    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL )
-#define XIOU_SLCR_MIO_PIN_61_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin62
- */
-#define XIOU_SLCR_MIO_PIN_62    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL )
-#define XIOU_SLCR_MIO_PIN_62_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin63
- */
-#define XIOU_SLCR_MIO_PIN_63    ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL )
-#define XIOU_SLCR_MIO_PIN_63_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin64
- */
-#define XIOU_SLCR_MIO_PIN_64    ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL )
-#define XIOU_SLCR_MIO_PIN_64_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin65
- */
-#define XIOU_SLCR_MIO_PIN_65    ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL )
-#define XIOU_SLCR_MIO_PIN_65_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin66
- */
-#define XIOU_SLCR_MIO_PIN_66    ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL )
-#define XIOU_SLCR_MIO_PIN_66_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin67
- */
-#define XIOU_SLCR_MIO_PIN_67    ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL )
-#define XIOU_SLCR_MIO_PIN_67_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin68
- */
-#define XIOU_SLCR_MIO_PIN_68    ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL )
-#define XIOU_SLCR_MIO_PIN_68_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin69
- */
-#define XIOU_SLCR_MIO_PIN_69    ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL )
-#define XIOU_SLCR_MIO_PIN_69_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin70
- */
-#define XIOU_SLCR_MIO_PIN_70    ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL )
-#define XIOU_SLCR_MIO_PIN_70_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin71
- */
-#define XIOU_SLCR_MIO_PIN_71    ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL )
-#define XIOU_SLCR_MIO_PIN_71_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin72
- */
-#define XIOU_SLCR_MIO_PIN_72    ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL )
-#define XIOU_SLCR_MIO_PIN_72_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin73
- */
-#define XIOU_SLCR_MIO_PIN_73    ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL )
-#define XIOU_SLCR_MIO_PIN_73_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin74
- */
-#define XIOU_SLCR_MIO_PIN_74    ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL )
-#define XIOU_SLCR_MIO_PIN_74_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin75
- */
-#define XIOU_SLCR_MIO_PIN_75    ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL )
-#define XIOU_SLCR_MIO_PIN_75_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin76
- */
-#define XIOU_SLCR_MIO_PIN_76    ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL )
-#define XIOU_SLCR_MIO_PIN_76_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioPin77
- */
-#define XIOU_SLCR_MIO_PIN_77    ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL )
-#define XIOU_SLCR_MIO_PIN_77_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT   5UL
-#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH   3UL
-#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK    0x000000e0UL
-#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT   3UL
-#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH   2UL
-#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK    0x00000018UL
-#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT   2UL
-#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT   1UL
-#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH   1UL
-#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank0Ctrl0
- */
-#define XIOU_SLCR_BANK0_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL )
-#define XIOU_SLCR_BANK0_CTRL0_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT   0UL
-#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH   26UL
-#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank0Ctrl1
- */
-#define XIOU_SLCR_BANK0_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL )
-#define XIOU_SLCR_BANK0_CTRL1_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT   0UL
-#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH   26UL
-#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank0Ctrl3
- */
-#define XIOU_SLCR_BANK0_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL )
-#define XIOU_SLCR_BANK0_CTRL3_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
-#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
-#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank0Ctrl4
- */
-#define XIOU_SLCR_BANK0_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL )
-#define XIOU_SLCR_BANK0_CTRL4_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT   0UL
-#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH   26UL
-#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank0Ctrl5
- */
-#define XIOU_SLCR_BANK0_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL )
-#define XIOU_SLCR_BANK0_CTRL5_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT   0UL
-#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH   26UL
-#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank0Ctrl6
- */
-#define XIOU_SLCR_BANK0_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL )
-#define XIOU_SLCR_BANK0_CTRL6_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
-#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
-#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank0Sts
- */
-#define XIOU_SLCR_BANK0_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL )
-#define XIOU_SLCR_BANK0_STS_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT   0UL
-#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH   1UL
-#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK    0x00000001UL
-#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank1Ctrl0
- */
-#define XIOU_SLCR_BANK1_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL )
-#define XIOU_SLCR_BANK1_CTRL0_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT   0UL
-#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH   26UL
-#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank1Ctrl1
- */
-#define XIOU_SLCR_BANK1_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL )
-#define XIOU_SLCR_BANK1_CTRL1_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT   0UL
-#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH   26UL
-#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank1Ctrl3
- */
-#define XIOU_SLCR_BANK1_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL )
-#define XIOU_SLCR_BANK1_CTRL3_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
-#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
-#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank1Ctrl4
- */
-#define XIOU_SLCR_BANK1_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL )
-#define XIOU_SLCR_BANK1_CTRL4_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT   0UL
-#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH   26UL
-#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank1Ctrl5
- */
-#define XIOU_SLCR_BANK1_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL )
-#define XIOU_SLCR_BANK1_CTRL5_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT   0UL
-#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH   26UL
-#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank1Ctrl6
- */
-#define XIOU_SLCR_BANK1_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL )
-#define XIOU_SLCR_BANK1_CTRL6_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
-#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
-#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank1Sts
- */
-#define XIOU_SLCR_BANK1_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL )
-#define XIOU_SLCR_BANK1_STS_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT   0UL
-#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH   1UL
-#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK    0x00000001UL
-#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank2Ctrl0
- */
-#define XIOU_SLCR_BANK2_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL )
-#define XIOU_SLCR_BANK2_CTRL0_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT   0UL
-#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH   26UL
-#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank2Ctrl1
- */
-#define XIOU_SLCR_BANK2_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL )
-#define XIOU_SLCR_BANK2_CTRL1_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT   0UL
-#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH   26UL
-#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank2Ctrl3
- */
-#define XIOU_SLCR_BANK2_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL )
-#define XIOU_SLCR_BANK2_CTRL3_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
-#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
-#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank2Ctrl4
- */
-#define XIOU_SLCR_BANK2_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL )
-#define XIOU_SLCR_BANK2_CTRL4_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT   0UL
-#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH   26UL
-#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank2Ctrl5
- */
-#define XIOU_SLCR_BANK2_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL )
-#define XIOU_SLCR_BANK2_CTRL5_RSTVAL   0x03ffffffUL
-
-#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT   0UL
-#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH   26UL
-#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
-
-/**
- * Register: XiouSlcrBank2Ctrl6
- */
-#define XIOU_SLCR_BANK2_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL )
-#define XIOU_SLCR_BANK2_CTRL6_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
-#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
-#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
-#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrBank2Sts
- */
-#define XIOU_SLCR_BANK2_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL )
-#define XIOU_SLCR_BANK2_STS_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT   0UL
-#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH   1UL
-#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK    0x00000001UL
-#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioLpbck
- */
-#define XIOU_SLCR_MIO_LPBCK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL )
-#define XIOU_SLCR_MIO_LPBCK_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT   3UL
-#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH   1UL
-#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK    0x00000008UL
-#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT   2UL
-#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH   1UL
-#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT   1UL
-#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH   1UL
-#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL  0x0UL
-
-#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT   0UL
-#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH   1UL
-#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK    0x00000001UL
-#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrMioMstTri0
- */
-#define XIOU_SLCR_MIO_MST_TRI0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL )
-#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL   0xffffffffUL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT   31UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK    0x80000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT   30UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK    0x40000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT   29UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK    0x20000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT   28UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK    0x10000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT   27UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK    0x08000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT   26UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK    0x04000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT   25UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK    0x02000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT   24UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK    0x01000000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT   23UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK    0x00800000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT   22UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK    0x00400000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT   21UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK    0x00200000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT   20UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK    0x00100000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT   19UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK    0x00080000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT   18UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK    0x00040000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT   17UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK    0x00020000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT   16UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK    0x00010000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT   15UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK    0x00008000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT   14UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK    0x00004000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT   13UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK    0x00002000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT   12UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK    0x00001000UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT   11UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK    0x00000800UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT   10UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK    0x00000400UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT   9UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK    0x00000200UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT   8UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK    0x00000100UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT   7UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK    0x00000080UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT   6UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK    0x00000040UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT   5UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK    0x00000020UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT   4UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK    0x00000010UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT   3UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK    0x00000008UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT   2UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT   0UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK    0x00000001UL
-#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL  0x1UL
-
-/**
- * Register: XiouSlcrMioMstTri1
- */
-#define XIOU_SLCR_MIO_MST_TRI1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL )
-#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL   0xffffffffUL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT   31UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK    0x80000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT   30UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK    0x40000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT   29UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK    0x20000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT   28UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK    0x10000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT   27UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK    0x08000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT   26UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK    0x04000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT   25UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK    0x02000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT   24UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK    0x01000000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT   23UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK    0x00800000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT   22UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK    0x00400000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT   21UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK    0x00200000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT   20UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK    0x00100000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT   19UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK    0x00080000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT   18UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK    0x00040000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT   17UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK    0x00020000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT   16UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK    0x00010000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT   15UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK    0x00008000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT   14UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK    0x00004000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT   13UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK    0x00002000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT   12UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK    0x00001000UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT   11UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK    0x00000800UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT   10UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK    0x00000400UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT   9UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK    0x00000200UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT   8UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK    0x00000100UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT   7UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK    0x00000080UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT   6UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK    0x00000040UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT   5UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK    0x00000020UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT   4UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK    0x00000010UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT   3UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK    0x00000008UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT   2UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT   0UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK    0x00000001UL
-#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL  0x1UL
-
-/**
- * Register: XiouSlcrMioMstTri2
- */
-#define XIOU_SLCR_MIO_MST_TRI2    ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL )
-#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL   0x00003fffUL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT   13UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK    0x00002000UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT   12UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK    0x00001000UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT   11UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK    0x00000800UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT   10UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK    0x00000400UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT   9UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK    0x00000200UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT   8UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK    0x00000100UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT   7UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK    0x00000080UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT   6UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK    0x00000040UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT   5UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK    0x00000020UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT   4UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK    0x00000010UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT   3UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK    0x00000008UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT   2UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK    0x00000004UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK    0x00000002UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL  0x1UL
-
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT   0UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH   1UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK    0x00000001UL
-#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL  0x1UL
-
-/**
- * Register: XiouSlcrWdtClkSel
- */
-#define XIOU_SLCR_WDT_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL )
-#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_WDT_CLK_SEL_SHIFT   0UL
-#define XIOU_SLCR_WDT_CLK_SEL_WIDTH   1UL
-#define XIOU_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
-#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrCanMioCtrl
- */
-#define XIOU_SLCR_CAN_MIO_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL )
-#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT   23UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH   1UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK    0x00800000UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL  0x0UL
-
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT   22UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH   1UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK    0x00400000UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT   15UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH   7UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK    0x003f8000UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL  0x0UL
-
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT   8UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH   1UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK    0x00000100UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL  0x0UL
-
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT   7UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH   1UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK    0x00000080UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT   0UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH   7UL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK    0x0000007fUL
-#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrGemClkCtrl
- */
-#define XIOU_SLCR_GEM_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL )
-#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT   22UL
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK    0x00400000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT   20UL
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH   2UL
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK    0x00300000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   18UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00040000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   17UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00020000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   16UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00010000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   15UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00008000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   13UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00002000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   12UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00001000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   11UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000800UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   10UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000400UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   8UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000100UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   7UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000080UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   6UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000040UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   5UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000020UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   3UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000008UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   2UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000004UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   0UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000001UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdioClkCtrl
- */
-#define XIOU_SLCR_SDIO_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL )
-#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT   18UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH   1UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK    0x00040000UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT   17UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK    0x00020000UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT   2UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH   1UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK    0x00000004UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT   0UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH   2UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK    0x00000003UL
-#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrCtrlRegSd
- */
-#define XIOU_SLCR_CTRL_REG_SD    ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL )
-#define XIOU_SLCR_CTRL_REG_SD_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   15UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00008000UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   0UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00000001UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdItapdly
- */
-#define XIOU_SLCR_SD_ITAPDLY    ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL )
-#define XIOU_SLCR_SD_ITAPDLY_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   25UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x02000000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   24UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x01000000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   16UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   9UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x00000200UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x00000100UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdOtapdlysel
- */
-#define XIOU_SLCR_SD_OTAPDLYSEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL )
-#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   22UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00400000UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x003f0000UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00000040UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x0000003fUL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdCfgReg1
- */
-#define XIOU_SLCR_SD_CFG_REG1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL )
-#define XIOU_SLCR_SD_CFG_REG1_RSTVAL   0x32403240UL
-
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   23UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x7f800000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
-
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   17UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x007e0000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
-
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   16UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00010000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   7UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x00007f80UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
-
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x0000007eUL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
-
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   0UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00000001UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdCfgReg2
- */
-#define XIOU_SLCR_SD_CFG_REG2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL )
-#define XIOU_SLCR_SD_CFG_REG2_RSTVAL   0x0ffc0ffcUL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   28UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x30000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   27UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x08000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   26UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x04000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   25UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x02000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   24UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x01000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   23UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00800000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   22UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00400000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   21UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00200000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   20UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00100000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   19UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00080000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   18UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00040000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   16UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00030000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   12UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x00003000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   11UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x00000800UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   10UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x00000400UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   9UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x00000200UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   8UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x00000100UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   7UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00000080UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   6UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00000040UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   5UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00000020UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   4UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00000010UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   3UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00000008UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00000004UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   0UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00000003UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdCfgReg3
- */
-#define XIOU_SLCR_SD_CFG_REG3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL )
-#define XIOU_SLCR_SD_CFG_REG3_RSTVAL   0x06070607UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   26UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x04000000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   22UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x03c00000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   21UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00200000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   20UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00100000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   19UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00080000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   18UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00040000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   17UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00020000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   16UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00010000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   10UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x00000400UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   6UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x000003c0UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   5UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00000020UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00000010UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   3UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00000008UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   2UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00000004UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00000002UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   0UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00000001UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
-
-/**
- * Register: XiouSlcrSdInitpreset
- */
-#define XIOU_SLCR_SD_INITPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL )
-#define XIOU_SLCR_SD_INITPRESET_RSTVAL   0x01000100UL
-
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
-
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
-
-/**
- * Register: XiouSlcrSdDsppreset
- */
-#define XIOU_SLCR_SD_DSPPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
-#define XIOU_SLCR_SD_DSPPRESET_RSTVAL   0x00040004UL
-
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
-
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
-
-/**
- * Register: XiouSlcrSdHspdpreset
- */
-#define XIOU_SLCR_SD_HSPDPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL )
-#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL   0x00020002UL
-
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
-
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
-
-/**
- * Register: XiouSlcrSdSdr12preset
- */
-#define XIOU_SLCR_SD_SDR12PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL )
-#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL   0x00040004UL
-
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
-
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
-
-/**
- * Register: XiouSlcrSdSdr25preset
- */
-#define XIOU_SLCR_SD_SDR25PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL )
-#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL   0x00020002UL
-
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
-
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
-
-/**
- * Register: XiouSlcrSdSdr50prset
- */
-#define XIOU_SLCR_SD_SDR50PRSET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL )
-#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL   0x00010001UL
-
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
-
-/**
- * Register: XiouSlcrSdSdr104prst
- */
-#define XIOU_SLCR_SD_SDR104PRST    ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL )
-#define XIOU_SLCR_SD_SDR104PRST_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdDdr50preset
- */
-#define XIOU_SLCR_SD_DDR50PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL )
-#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL   0x00020002UL
-
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
-
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
-
-/**
- * Register: XiouSlcrSdMaxcur1p8
- */
-#define XIOU_SLCR_SD_MAXCUR1P8    ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
-#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdMaxcur3p0
- */
-#define XIOU_SLCR_SD_MAXCUR3P0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL )
-#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdMaxcur3p3
- */
-#define XIOU_SLCR_SD_MAXCUR3P3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL )
-#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdDllCtrl
- */
-#define XIOU_SLCR_SD_DLL_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL )
-#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   18UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00040000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   17UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00020000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   16UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00010000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   2UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00000004UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00000002UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00000001UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrSdCdnCtrl
- */
-#define XIOU_SLCR_SD_CDN_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL )
-#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00010000UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00000001UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrGemCtrl
- */
-#define XIOU_SLCR_GEM_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL )
-#define XIOU_SLCR_GEM_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   6UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x000000c0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   4UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000030UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x0000000cUL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000003UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrTtcApbClk
- */
-#define XIOU_SLCR_TTC_APB_CLK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL )
-#define XIOU_SLCR_TTC_APB_CLK_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT   6UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH   2UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK    0x000000c0UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT   4UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH   2UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK    0x00000030UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT   2UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH   2UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK    0x0000000cUL
-#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT   0UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH   2UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK    0x00000003UL
-#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrTapdlyBypass
- */
-#define XIOU_SLCR_TAPDLY_BYPASS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL )
-#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL   0x00000007UL
-
-#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT   2UL
-#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH   1UL
-#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK    0x00000004UL
-#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL  0x1UL
-
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT   1UL
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH   1UL
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK    0x00000002UL
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT   0UL
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH   1UL
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK    0x00000001UL
-#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL  0x1UL
-
-/**
- * Register: XiouSlcrCoherentCtrl
- */
-#define XIOU_SLCR_COHERENT_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL )
-#define XIOU_SLCR_COHERENT_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT   28UL
-#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK    0xf0000000UL
-#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL  0x0UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT   24UL
-#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK    0x0f000000UL
-#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL  0x0UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   20UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x00f00000UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   16UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x000f0000UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   12UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000f000UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   8UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x00000f00UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x000000f0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
-
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000000fUL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrVideoPssClkSel
- */
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL )
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT   1UL
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH   1UL
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK    0x00000002UL
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL  0x0UL
-
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT   0UL
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH   1UL
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK    0x00000001UL
-#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrInterconnectRoute
- */
-#define XIOU_SLCR_INTERCONNECT_ROUTE    ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL )
-#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT   7UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK    0x00000080UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL  0x0UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT   6UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK    0x00000040UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL  0x0UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   5UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000020UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   4UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000010UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   3UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000008UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   2UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000004UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000002UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
-
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000001UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrRamXemacps
- */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamXemacps
- */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamXemacps
- */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamXemacps
- */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamXsdps
- */
-#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
-#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
-
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamXsdps
- */
-#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
-#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
-
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamCan0
- */
-#define XIOU_SLCR_RAM_CAN0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL )
-#define XIOU_SLCR_RAM_CAN0_RSTVAL   0x005b5b5bUL
-
-#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT   22UL
-#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH   1UL
-#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK    0x00400000UL
-#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT   19UL
-#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK    0x00380000UL
-#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT   16UL
-#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK    0x00070000UL
-#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamCan1
- */
-#define XIOU_SLCR_RAM_CAN1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL )
-#define XIOU_SLCR_RAM_CAN1_RSTVAL   0x005b5b5bUL
-
-#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT   22UL
-#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH   1UL
-#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK    0x00400000UL
-#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT   19UL
-#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK    0x00380000UL
-#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT   16UL
-#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK    0x00070000UL
-#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamLqspi
- */
-#define XIOU_SLCR_RAM_LQSPI    ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL )
-#define XIOU_SLCR_RAM_LQSPI_RSTVAL   0x00002ddbUL
-
-#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT   13UL
-#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK    0x00002000UL
-#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT   10UL
-#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK    0x00001c00UL
-#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT   7UL
-#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK    0x00000380UL
-#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrRamXnandps8
- */
-#define XIOU_SLCR_RAM_XNANDPS8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL )
-#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL   0x0000005bUL
-
-#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL  0x1UL
-
-#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL  0x3UL
-
-#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL  0x3UL
-
-/**
- * Register: XiouSlcrCtrl
- */
-#define XIOU_SLCR_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL )
-#define XIOU_SLCR_CTRL_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
-#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
-#define XIOU_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
-#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrIsr
- */
-#define XIOU_SLCR_ISR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL )
-#define XIOU_SLCR_ISR_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrImr
- */
-#define XIOU_SLCR_IMR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL )
-#define XIOU_SLCR_IMR_RSTVAL   0x00000001UL
-
-#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
-
-/**
- * Register: XiouSlcrIer
- */
-#define XIOU_SLCR_IER    ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL )
-#define XIOU_SLCR_IER_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrIdr
- */
-#define XIOU_SLCR_IDR    ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL )
-#define XIOU_SLCR_IDR_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XiouSlcrItr
- */
-#define XIOU_SLCR_ITR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL )
-#define XIOU_SLCR_ITR_RSTVAL   0x00000000UL
-
-#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
-#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
-#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XIOU_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h
deleted file mode 100644
index cc05672e4..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h
+++ /dev/null
@@ -1,5667 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XLPD_SLCR_H__
-#define __XLPD_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XlpdSlcr Base Address
- */
-#define XLPD_SLCR_BASEADDR      0xFF410000UL
-
-/**
- * Register: XlpdSlcrWprot0
- */
-#define XLPD_SLCR_WPROT0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL )
-#define XLPD_SLCR_WPROT0_RSTVAL   0x00000001UL
-
-#define XLPD_SLCR_WPROT0_ACT_SHIFT   0UL
-#define XLPD_SLCR_WPROT0_ACT_WIDTH   1UL
-#define XLPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
-#define XLPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrCtrl
- */
-#define XLPD_SLCR_CTRL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL )
-#define XLPD_SLCR_CTRL_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
-#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
-#define XLPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
-#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrIsr
- */
-#define XLPD_SLCR_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL )
-#define XLPD_SLCR_ISR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrImr
- */
-#define XLPD_SLCR_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL )
-#define XLPD_SLCR_IMR_RSTVAL   0x00000001UL
-
-#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrIer
- */
-#define XLPD_SLCR_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL )
-#define XLPD_SLCR_IER_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrIdr
- */
-#define XLPD_SLCR_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL )
-#define XLPD_SLCR_IDR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrItr
- */
-#define XLPD_SLCR_ITR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL )
-#define XLPD_SLCR_ITR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSafetyChk0
- */
-#define XLPD_SLCR_SAFETY_CHK0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL )
-#define XLPD_SLCR_SAFETY_CHK0_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT   0UL
-#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH   32UL
-#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK    0xffffffffUL
-#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSafetyChk1
- */
-#define XLPD_SLCR_SAFETY_CHK1    ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL )
-#define XLPD_SLCR_SAFETY_CHK1_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT   0UL
-#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH   32UL
-#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK    0xffffffffUL
-#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSafetyChk2
- */
-#define XLPD_SLCR_SAFETY_CHK2    ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL )
-#define XLPD_SLCR_SAFETY_CHK2_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT   0UL
-#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH   32UL
-#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK    0xffffffffUL
-#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSafetyChk3
- */
-#define XLPD_SLCR_SAFETY_CHK3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL )
-#define XLPD_SLCR_SAFETY_CHK3_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT   0UL
-#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH   32UL
-#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK    0xffffffffUL
-#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrXcsupmuWdtClkSel
- */
-#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL )
-#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT   0UL
-#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH   1UL
-#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK    0x00000001UL
-#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrAdmaCfg
- */
-#define XLPD_SLCR_ADMA_CFG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL )
-#define XLPD_SLCR_ADMA_CFG_RSTVAL   0x00000028UL
-
-#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT   5UL
-#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH   2UL
-#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK    0x00000060UL
-#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT   0UL
-#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH   5UL
-#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK    0x0000001fUL
-#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL  0x8UL
-
-/**
- * Register: XlpdSlcrAdmaRam
- */
-#define XLPD_SLCR_ADMA_RAM    ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL )
-#define XLPD_SLCR_ADMA_RAM_RSTVAL   0x00003b3bUL
-
-#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT   12UL
-#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH   3UL
-#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK    0x00007000UL
-#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL  0x3UL
-
-#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT   11UL
-#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH   1UL
-#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK    0x00000800UL
-#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT   8UL
-#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH   3UL
-#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK    0x00000700UL
-#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL  0x3UL
-
-#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT   4UL
-#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH   3UL
-#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK    0x00000070UL
-#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL  0x3UL
-
-#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT   3UL
-#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH   1UL
-#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK    0x00000008UL
-#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT   0UL
-#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH   3UL
-#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK    0x00000007UL
-#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL  0x3UL
-
-/**
- * Register: XlpdSlcrErrAibaxiIsr
- */
-#define XLPD_SLCR_ERR_AIBAXI_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL )
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT   28UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK    0x10000000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT   27UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK    0x08000000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT   26UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK    0x04000000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT   24UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK    0x01000000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT   23UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK    0x00800000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT   22UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK    0x00400000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT   19UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK    0x00080000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT   18UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK    0x00040000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT   17UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK    0x00020000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT   16UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK    0x00010000UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT   3UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK    0x00000008UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT   2UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK    0x00000004UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAibaxiImr
- */
-#define XLPD_SLCR_ERR_AIBAXI_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL )
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL   0x1dcf000fUL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT   28UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK    0x10000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT   27UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK    0x08000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT   26UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK    0x04000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT   24UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK    0x01000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT   23UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK    0x00800000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT   22UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK    0x00400000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT   19UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK    0x00080000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT   18UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK    0x00040000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT   17UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK    0x00020000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT   16UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK    0x00010000UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT   3UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK    0x00000008UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT   2UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK    0x00000004UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrErrAibaxiIer
- */
-#define XLPD_SLCR_ERR_AIBAXI_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL )
-#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT   28UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK    0x10000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT   27UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK    0x08000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT   26UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK    0x04000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT   24UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK    0x01000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT   23UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK    0x00800000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT   22UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK    0x00400000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT   19UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK    0x00080000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT   18UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK    0x00040000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT   17UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK    0x00020000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT   16UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK    0x00010000UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT   3UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK    0x00000008UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT   2UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK    0x00000004UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAibaxiIdr
- */
-#define XLPD_SLCR_ERR_AIBAXI_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL )
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT   28UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK    0x10000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT   27UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK    0x08000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT   26UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK    0x04000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT   24UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK    0x01000000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT   23UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK    0x00800000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT   22UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK    0x00400000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT   19UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK    0x00080000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT   18UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK    0x00040000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT   17UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK    0x00020000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT   16UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK    0x00010000UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT   3UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK    0x00000008UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT   2UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK    0x00000004UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAibapbIsr
- */
-#define XLPD_SLCR_ERR_AIBAPB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL )
-#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAibapbImr
- */
-#define XLPD_SLCR_ERR_AIBAPB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL )
-#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL   0x00000001UL
-
-#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrErrAibapbIer
- */
-#define XLPD_SLCR_ERR_AIBAPB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL )
-#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAibapbIdr
- */
-#define XLPD_SLCR_ERR_AIBAPB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL )
-#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT   0UL
-#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH   1UL
-#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrIsoAibaxiReq
- */
-#define XLPD_SLCR_ISO_AIBAXI_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL )
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT   28UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK    0x10000000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT   27UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK    0x08000000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT   26UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK    0x04000000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT   24UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK    0x01000000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT   23UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK    0x00800000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT   22UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK    0x00400000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT   19UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK    0x00080000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT   18UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK    0x00040000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT   17UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK    0x00020000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT   16UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK    0x00010000UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT   3UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK    0x00000008UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT   2UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK    0x00000004UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK    0x00000002UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT   0UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK    0x00000001UL
-#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrIsoAibaxiType
- */
-#define XLPD_SLCR_ISO_AIBAXI_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL )
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL   0x19cf000fUL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT   28UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK    0x10000000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT   27UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK    0x08000000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT   26UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK    0x04000000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT   24UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK    0x01000000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT   23UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK    0x00800000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT   22UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK    0x00400000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT   19UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK    0x00080000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT   18UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK    0x00040000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT   17UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK    0x00020000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT   16UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK    0x00010000UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT   3UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK    0x00000008UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT   2UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK    0x00000004UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK    0x00000002UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT   0UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK    0x00000001UL
-#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrIsoAibaxiAck
- */
-#define XLPD_SLCR_ISO_AIBAXI_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL )
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT   28UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK    0x10000000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT   27UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK    0x08000000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT   26UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK    0x04000000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT   24UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK    0x01000000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT   23UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK    0x00800000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT   22UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK    0x00400000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT   19UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK    0x00080000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT   18UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK    0x00040000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT   17UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK    0x00020000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT   16UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK    0x00010000UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT   3UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK    0x00000008UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT   2UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK    0x00000004UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK    0x00000002UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT   0UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK    0x00000001UL
-#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrIsoAibapbReq
- */
-#define XLPD_SLCR_ISO_AIBAPB_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL )
-#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT   0UL
-#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK    0x00000001UL
-#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrIsoAibapbType
- */
-#define XLPD_SLCR_ISO_AIBAPB_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL )
-#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL   0x00000001UL
-
-#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT   0UL
-#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK    0x00000001UL
-#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrIsoAibapbAck
- */
-#define XLPD_SLCR_ISO_AIBAPB_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL )
-#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT   0UL
-#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH   1UL
-#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK    0x00000001UL
-#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAtbIsr
- */
-#define XLPD_SLCR_ERR_ATB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL )
-#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT   1UL
-#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT   0UL
-#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAtbImr
- */
-#define XLPD_SLCR_ERR_ATB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL )
-#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000003UL
-
-#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT   1UL
-#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT   0UL
-#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrErrAtbIer
- */
-#define XLPD_SLCR_ERR_ATB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL )
-#define XLPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT   1UL
-#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT   0UL
-#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrErrAtbIdr
- */
-#define XLPD_SLCR_ERR_ATB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL )
-#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT   1UL
-#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK    0x00000002UL
-#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT   0UL
-#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH   1UL
-#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK    0x00000001UL
-#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrAtbCmdStoreEn
- */
-#define XLPD_SLCR_ATB_CMD_STORE_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL )
-#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL   0x00000003UL
-
-#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT   1UL
-#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK    0x00000002UL
-#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT   0UL
-#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH   1UL
-#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK    0x00000001UL
-#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrAtbRespEn
- */
-#define XLPD_SLCR_ATB_RESP_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL )
-#define XLPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT   1UL
-#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK    0x00000002UL
-#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT   0UL
-#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH   1UL
-#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK    0x00000001UL
-#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrAtbRespType
- */
-#define XLPD_SLCR_ATB_RESP_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL )
-#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL   0x00000003UL
-
-#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT   1UL
-#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH   1UL
-#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK    0x00000002UL
-#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT   0UL
-#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH   1UL
-#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK    0x00000001UL
-#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrAtbPrescale
- */
-#define XLPD_SLCR_ATB_PRESCALE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL )
-#define XLPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
-
-#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
-#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
-#define XLPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
-#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
-
-#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
-#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
-#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
-#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
-
-/**
- * Register: XlpdSlcrMutex0
- */
-#define XLPD_SLCR_MUTEX0    ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL )
-#define XLPD_SLCR_MUTEX0_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_MUTEX0_ID_SHIFT   0UL
-#define XLPD_SLCR_MUTEX0_ID_WIDTH   32UL
-#define XLPD_SLCR_MUTEX0_ID_MASK    0xffffffffUL
-#define XLPD_SLCR_MUTEX0_ID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrMutex1
- */
-#define XLPD_SLCR_MUTEX1    ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL )
-#define XLPD_SLCR_MUTEX1_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_MUTEX1_ID_SHIFT   0UL
-#define XLPD_SLCR_MUTEX1_ID_WIDTH   32UL
-#define XLPD_SLCR_MUTEX1_ID_MASK    0xffffffffUL
-#define XLPD_SLCR_MUTEX1_ID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrMutex2
- */
-#define XLPD_SLCR_MUTEX2    ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL )
-#define XLPD_SLCR_MUTEX2_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_MUTEX2_ID_SHIFT   0UL
-#define XLPD_SLCR_MUTEX2_ID_WIDTH   32UL
-#define XLPD_SLCR_MUTEX2_ID_MASK    0xffffffffUL
-#define XLPD_SLCR_MUTEX2_ID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrMutex3
- */
-#define XLPD_SLCR_MUTEX3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL )
-#define XLPD_SLCR_MUTEX3_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_MUTEX3_ID_SHIFT   0UL
-#define XLPD_SLCR_MUTEX3_ID_WIDTH   32UL
-#define XLPD_SLCR_MUTEX3_ID_MASK    0xffffffffUL
-#define XLPD_SLCR_MUTEX3_ID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp0IrqSts
- */
-#define XLPD_SLCR_GICP0_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL )
-#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp0IrqMsk
- */
-#define XLPD_SLCR_GICP0_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL )
-#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL   0xffffffffUL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrGicp0IrqEn
- */
-#define XLPD_SLCR_GICP0_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL )
-#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp0IrqDis
- */
-#define XLPD_SLCR_GICP0_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL )
-#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp0IrqTrig
- */
-#define XLPD_SLCR_GICP0_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL )
-#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp1IrqSts
- */
-#define XLPD_SLCR_GICP1_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL )
-#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp1IrqMsk
- */
-#define XLPD_SLCR_GICP1_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL )
-#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL   0xffffffffUL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrGicp1IrqEn
- */
-#define XLPD_SLCR_GICP1_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL )
-#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp1IrqDis
- */
-#define XLPD_SLCR_GICP1_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL )
-#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp1IrqTrig
- */
-#define XLPD_SLCR_GICP1_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL )
-#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp2IrqSts
- */
-#define XLPD_SLCR_GICP2_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL )
-#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp2IrqMsk
- */
-#define XLPD_SLCR_GICP2_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL )
-#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL   0xffffffffUL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrGicp2IrqEn
- */
-#define XLPD_SLCR_GICP2_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL )
-#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp2IrqDis
- */
-#define XLPD_SLCR_GICP2_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL )
-#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp2IrqTrig
- */
-#define XLPD_SLCR_GICP2_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL )
-#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp3IrqSts
- */
-#define XLPD_SLCR_GICP3_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL )
-#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp3IrqMsk
- */
-#define XLPD_SLCR_GICP3_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL )
-#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL   0xffffffffUL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrGicp3IrqEn
- */
-#define XLPD_SLCR_GICP3_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL )
-#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp3IrqDis
- */
-#define XLPD_SLCR_GICP3_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL )
-#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp3IrqTrig
- */
-#define XLPD_SLCR_GICP3_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL )
-#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp4IrqSts
- */
-#define XLPD_SLCR_GICP4_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL )
-#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp4IrqMsk
- */
-#define XLPD_SLCR_GICP4_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL )
-#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL   0xffffffffUL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrGicp4IrqEn
- */
-#define XLPD_SLCR_GICP4_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL )
-#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp4IrqDis
- */
-#define XLPD_SLCR_GICP4_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL )
-#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicp4IrqTrig
- */
-#define XLPD_SLCR_GICP4_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL )
-#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT   31UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK    0x80000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT   30UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK    0x40000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT   29UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK    0x20000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT   28UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK    0x10000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT   27UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK    0x08000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT   26UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK    0x04000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT   25UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK    0x02000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT   24UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK    0x01000000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT   23UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK    0x00800000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT   22UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK    0x00400000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT   21UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK    0x00200000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT   20UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK    0x00100000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT   19UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK    0x00080000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT   18UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK    0x00040000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT   17UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK    0x00020000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT   16UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK    0x00010000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT   15UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK    0x00008000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT   14UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK    0x00004000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT   13UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK    0x00002000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT   12UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK    0x00001000UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT   11UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK    0x00000800UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT   10UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK    0x00000400UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT   9UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK    0x00000200UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT   8UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK    0x00000100UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicpPmuIrqSts
- */
-#define XLPD_SLCR_GICP_PMU_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL )
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicpPmuIrqMsk
- */
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL )
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL   0x000000ffUL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrGicpPmuIrqEn
- */
-#define XLPD_SLCR_GICP_PMU_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL )
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicpPmuIrqDis
- */
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL )
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrGicpPmuIrqTrig
- */
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL )
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT   7UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK    0x00000080UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT   6UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK    0x00000040UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT   5UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK    0x00000020UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT   4UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK    0x00000010UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT   3UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK    0x00000008UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT   2UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK    0x00000004UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK    0x00000002UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT   0UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH   1UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK    0x00000001UL
-#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrAfiFs
- */
-#define XLPD_SLCR_AFI_FS    ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL )
-#define XLPD_SLCR_AFI_FS_RSTVAL   0x00000200UL
-
-#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT   8UL
-#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH   2UL
-#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK    0x00000300UL
-#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL  0x2UL
-
-/**
- * Register: XlpdSlcrCci
- */
-#define XLPD_SLCR_CCI    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL )
-#define XLPD_SLCR_CCI_RSTVAL   0x03801c07UL
-
-#define XLPD_SLCR_CCI_SPR_SHIFT   28UL
-#define XLPD_SLCR_CCI_SPR_WIDTH   4UL
-#define XLPD_SLCR_CCI_SPR_MASK    0xf0000000UL
-#define XLPD_SLCR_CCI_SPR_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT   27UL
-#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH   1UL
-#define XLPD_SLCR_CCI_QVNVNETS4_MASK    0x08000000UL
-#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT   26UL
-#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH   1UL
-#define XLPD_SLCR_CCI_QVNVNETS3_MASK    0x04000000UL
-#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT   25UL
-#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH   1UL
-#define XLPD_SLCR_CCI_QVNVNETS2_MASK    0x02000000UL
-#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT   24UL
-#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH   1UL
-#define XLPD_SLCR_CCI_QVNVNETS1_MASK    0x01000000UL
-#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT   23UL
-#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH   1UL
-#define XLPD_SLCR_CCI_QVNVNETS0_MASK    0x00800000UL
-#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT   18UL
-#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH   5UL
-#define XLPD_SLCR_CCI_QOS_OVRRD_MASK    0x007c0000UL
-#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT   17UL
-#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH   1UL
-#define XLPD_SLCR_CCI_QVN_EN_M2_MASK    0x00020000UL
-#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT   16UL
-#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH   1UL
-#define XLPD_SLCR_CCI_QVN_EN_M1_MASK    0x00010000UL
-#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT   13UL
-#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH   3UL
-#define XLPD_SLCR_CCI_STRPG_GRAN_MASK    0x0000e000UL
-#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT   12UL
-#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH   1UL
-#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK    0x00001000UL
-#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT   11UL
-#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH   1UL
-#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK    0x00000800UL
-#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT   10UL
-#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH   1UL
-#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK    0x00000400UL
-#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT   6UL
-#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH   4UL
-#define XLPD_SLCR_CCI_ECOREVNUM_MASK    0x000003c0UL
-#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ASA2_SHIFT   5UL
-#define XLPD_SLCR_CCI_ASA2_WIDTH   1UL
-#define XLPD_SLCR_CCI_ASA2_MASK    0x00000020UL
-#define XLPD_SLCR_CCI_ASA2_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ASA1_SHIFT   4UL
-#define XLPD_SLCR_CCI_ASA1_WIDTH   1UL
-#define XLPD_SLCR_CCI_ASA1_MASK    0x00000010UL
-#define XLPD_SLCR_CCI_ASA1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ASA0_SHIFT   3UL
-#define XLPD_SLCR_CCI_ASA0_WIDTH   1UL
-#define XLPD_SLCR_CCI_ASA0_MASK    0x00000008UL
-#define XLPD_SLCR_CCI_ASA0_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_OWO2_SHIFT   2UL
-#define XLPD_SLCR_CCI_OWO2_WIDTH   1UL
-#define XLPD_SLCR_CCI_OWO2_MASK    0x00000004UL
-#define XLPD_SLCR_CCI_OWO2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_OWO1_SHIFT   1UL
-#define XLPD_SLCR_CCI_OWO1_WIDTH   1UL
-#define XLPD_SLCR_CCI_OWO1_MASK    0x00000002UL
-#define XLPD_SLCR_CCI_OWO1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_CCI_OWO0_SHIFT   0UL
-#define XLPD_SLCR_CCI_OWO0_WIDTH   1UL
-#define XLPD_SLCR_CCI_OWO0_MASK    0x00000001UL
-#define XLPD_SLCR_CCI_OWO0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrCciAddrmap
- */
-#define XLPD_SLCR_CCI_ADDRMAP    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL )
-#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL   0x00c000ffUL
-
-#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT   30UL
-#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_15_MASK    0xc0000000UL
-#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT   28UL
-#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_14_MASK    0x30000000UL
-#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT   26UL
-#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_13_MASK    0x0c000000UL
-#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT   24UL
-#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_12_MASK    0x03000000UL
-#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT   22UL
-#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_11_MASK    0x00c00000UL
-#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL  0x3UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT   20UL
-#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_10_MASK    0x00300000UL
-#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT   18UL
-#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_9_MASK    0x000c0000UL
-#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT   16UL
-#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_8_MASK    0x00030000UL
-#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT   14UL
-#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_7_MASK    0x0000c000UL
-#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT   12UL
-#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_6_MASK    0x00003000UL
-#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT   10UL
-#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_5_MASK    0x00000c00UL
-#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT   8UL
-#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_4_MASK    0x00000300UL
-#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL  0x0UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT   6UL
-#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_3_MASK    0x000000c0UL
-#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL  0x3UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT   4UL
-#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_2_MASK    0x00000030UL
-#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL  0x3UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_1_MASK    0x0000000cUL
-#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL  0x3UL
-
-#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT   0UL
-#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH   2UL
-#define XLPD_SLCR_CCI_ADDRMAP_0_MASK    0x00000003UL
-#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL  0x3UL
-
-/**
- * Register: XlpdSlcrCciQvnprealloc
- */
-#define XLPD_SLCR_CCI_QVNPREALLOC    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL )
-#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL   0x00330330UL
-
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT   20UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH   4UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK    0x00f00000UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL  0x3UL
-
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT   16UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH   4UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK    0x000f0000UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL  0x3UL
-
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT   8UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH   4UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK    0x00000f00UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL  0x3UL
-
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT   4UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH   4UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK    0x000000f0UL
-#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL  0x3UL
-
-/**
- * Register: XlpdSlcrSmmu
- */
-#define XLPD_SLCR_SMMU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL )
-#define XLPD_SLCR_SMMU_RSTVAL   0x0000003fUL
-
-#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT   7UL
-#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH   1UL
-#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK    0x00000080UL
-#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL  0x0UL
-
-#define XLPD_SLCR_SMMU_CTTW_SHIFT   6UL
-#define XLPD_SLCR_SMMU_CTTW_WIDTH   1UL
-#define XLPD_SLCR_SMMU_CTTW_MASK    0x00000040UL
-#define XLPD_SLCR_SMMU_CTTW_DEFVAL  0x0UL
-
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT   5UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH   1UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK    0x00000020UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL  0x1UL
-
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT   4UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH   1UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK    0x00000010UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL  0x1UL
-
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT   3UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH   1UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK    0x00000008UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL  0x1UL
-
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT   2UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH   1UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK    0x00000004UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL  0x1UL
-
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT   1UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH   1UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK    0x00000002UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT   0UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH   1UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK    0x00000001UL
-#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrApu
- */
-#define XLPD_SLCR_APU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL )
-#define XLPD_SLCR_APU_RSTVAL   0x00000001UL
-
-#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT   3UL
-#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH   1UL
-#define XLPD_SLCR_APU_BRDC_BARRIER_MASK    0x00000008UL
-#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL  0x0UL
-
-#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT   2UL
-#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH   1UL
-#define XLPD_SLCR_APU_BRDC_CMNT_MASK    0x00000004UL
-#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL  0x0UL
-
-#define XLPD_SLCR_APU_BRDC_INNER_SHIFT   1UL
-#define XLPD_SLCR_APU_BRDC_INNER_WIDTH   1UL
-#define XLPD_SLCR_APU_BRDC_INNER_MASK    0x00000002UL
-#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL  0x0UL
-
-#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT   0UL
-#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH   1UL
-#define XLPD_SLCR_APU_BRDC_OUTER_MASK    0x00000001UL
-#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL  0x1UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XLPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h
deleted file mode 100644
index aff3bf2fa..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XLPD_SLCR_SECURE_H__
-#define __XLPD_SLCR_SECURE_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XlpdSlcrSecure Base Address
- */
-#define XLPD_SLCR_SECURE_BASEADDR      0xFF4B0000UL
-
-/**
- * Register: XlpdSlcrSecCtrl
- */
-#define XLPD_SLCR_SEC_CTRL    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
-#define XLPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
-#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
-#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecIsr
- */
-#define XLPD_SLCR_SEC_ISR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
-#define XLPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecImr
- */
-#define XLPD_SLCR_SEC_IMR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
-#define XLPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
-
-#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
-
-/**
- * Register: XlpdSlcrSecIer
- */
-#define XLPD_SLCR_SEC_IER    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
-#define XLPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecIdr
- */
-#define XLPD_SLCR_SEC_IDR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
-#define XLPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecItr
- */
-#define XLPD_SLCR_SEC_ITR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
-#define XLPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
-#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
-#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecRpu
- */
-#define XLPD_SLCR_SEC_RPU    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
-#define XLPD_SLCR_SEC_RPU_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT   1UL
-#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH   1UL
-#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK    0x00000002UL
-#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL  0x0UL
-
-#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT   0UL
-#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH   1UL
-#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecAdma
- */
-#define XLPD_SLCR_SEC_ADMA    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
-#define XLPD_SLCR_SEC_ADMA_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT   0UL
-#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH   8UL
-#define XLPD_SLCR_SEC_ADMA_TZ_MASK    0x000000ffUL
-#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecSafetyChk
- */
-#define XLPD_SLCR_SEC_SAFETY_CHK    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
-#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL   0x00000000UL
-
-#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT   0UL
-#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH   32UL
-#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK    0xffffffffUL
-#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL  0x0UL
-
-/**
- * Register: XlpdSlcrSecUsb
- */
-#define XLPD_SLCR_SEC_USB    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
-#define XLPD_SLCR_SEC_USB_RSTVAL   0x00000003UL
-
-#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT   1UL
-#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH   1UL
-#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK    0x00000002UL
-#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL  0x1UL
-
-#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT   0UL
-#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH   1UL
-#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK    0x00000001UL
-#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL  0x1UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XLPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h
deleted file mode 100644
index a5145eac7..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h
+++ /dev/null
@@ -1,858 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XLPD_XPPU_H__
-#define __XLPD_XPPU_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XlpdXppu Base Address
- */
-#define XLPD_XPPU_BASEADDR      0xFF980000UL
-
-/**
- * Register: XlpdXppuCtrl
- */
-#define XLPD_XPPU_CTRL    ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
-#define XLPD_XPPU_CTRL_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT   2UL
-#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH   1UL
-#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK    0x00000004UL
-#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL  0x0UL
-
-#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT   1UL
-#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH   1UL
-#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK    0x00000002UL
-#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL  0x0UL
-
-#define XLPD_XPPU_CTRL_EN_SHIFT   0UL
-#define XLPD_XPPU_CTRL_EN_WIDTH   1UL
-#define XLPD_XPPU_CTRL_EN_MASK    0x00000001UL
-#define XLPD_XPPU_CTRL_EN_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuErrSts1
- */
-#define XLPD_XPPU_ERR_STS1    ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
-#define XLPD_XPPU_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuErrSts2
- */
-#define XLPD_XPPU_ERR_STS2    ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
-#define XLPD_XPPU_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuPoison
- */
-#define XLPD_XPPU_POISON    ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
-#define XLPD_XPPU_POISON_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_POISON_BASE_SHIFT   0UL
-#define XLPD_XPPU_POISON_BASE_WIDTH   20UL
-#define XLPD_XPPU_POISON_BASE_MASK    0x000fffffUL
-#define XLPD_XPPU_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuIsr
- */
-#define XLPD_XPPU_ISR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
-#define XLPD_XPPU_ISR_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_ISR_APER_PARITY_SHIFT   7UL
-#define XLPD_XPPU_ISR_APER_PARITY_WIDTH   1UL
-#define XLPD_XPPU_ISR_APER_PARITY_MASK    0x00000080UL
-#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL  0x0UL
-
-#define XLPD_XPPU_ISR_APER_TZ_SHIFT   6UL
-#define XLPD_XPPU_ISR_APER_TZ_WIDTH   1UL
-#define XLPD_XPPU_ISR_APER_TZ_MASK    0x00000040UL
-#define XLPD_XPPU_ISR_APER_TZ_DEFVAL  0x0UL
-
-#define XLPD_XPPU_ISR_APER_PERM_SHIFT   5UL
-#define XLPD_XPPU_ISR_APER_PERM_WIDTH   1UL
-#define XLPD_XPPU_ISR_APER_PERM_MASK    0x00000020UL
-#define XLPD_XPPU_ISR_APER_PERM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_ISR_MID_PARITY_SHIFT   3UL
-#define XLPD_XPPU_ISR_MID_PARITY_WIDTH   1UL
-#define XLPD_XPPU_ISR_MID_PARITY_MASK    0x00000008UL
-#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL  0x0UL
-
-#define XLPD_XPPU_ISR_MID_RO_SHIFT   2UL
-#define XLPD_XPPU_ISR_MID_RO_WIDTH   1UL
-#define XLPD_XPPU_ISR_MID_RO_MASK    0x00000004UL
-#define XLPD_XPPU_ISR_MID_RO_DEFVAL  0x0UL
-
-#define XLPD_XPPU_ISR_MID_MISS_SHIFT   1UL
-#define XLPD_XPPU_ISR_MID_MISS_WIDTH   1UL
-#define XLPD_XPPU_ISR_MID_MISS_MASK    0x00000002UL
-#define XLPD_XPPU_ISR_MID_MISS_DEFVAL  0x0UL
-
-#define XLPD_XPPU_ISR_INV_APB_SHIFT   0UL
-#define XLPD_XPPU_ISR_INV_APB_WIDTH   1UL
-#define XLPD_XPPU_ISR_INV_APB_MASK    0x00000001UL
-#define XLPD_XPPU_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuImr
- */
-#define XLPD_XPPU_IMR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
-#define XLPD_XPPU_IMR_RSTVAL   0x000000efUL
-
-#define XLPD_XPPU_IMR_APER_PARITY_SHIFT   7UL
-#define XLPD_XPPU_IMR_APER_PARITY_WIDTH   1UL
-#define XLPD_XPPU_IMR_APER_PARITY_MASK    0x00000080UL
-#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL  0x1UL
-
-#define XLPD_XPPU_IMR_APER_TZ_SHIFT   6UL
-#define XLPD_XPPU_IMR_APER_TZ_WIDTH   1UL
-#define XLPD_XPPU_IMR_APER_TZ_MASK    0x00000040UL
-#define XLPD_XPPU_IMR_APER_TZ_DEFVAL  0x1UL
-
-#define XLPD_XPPU_IMR_APER_PERM_SHIFT   5UL
-#define XLPD_XPPU_IMR_APER_PERM_WIDTH   1UL
-#define XLPD_XPPU_IMR_APER_PERM_MASK    0x00000020UL
-#define XLPD_XPPU_IMR_APER_PERM_DEFVAL  0x1UL
-
-#define XLPD_XPPU_IMR_MID_PARITY_SHIFT   3UL
-#define XLPD_XPPU_IMR_MID_PARITY_WIDTH   1UL
-#define XLPD_XPPU_IMR_MID_PARITY_MASK    0x00000008UL
-#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL  0x1UL
-
-#define XLPD_XPPU_IMR_MID_RO_SHIFT   2UL
-#define XLPD_XPPU_IMR_MID_RO_WIDTH   1UL
-#define XLPD_XPPU_IMR_MID_RO_MASK    0x00000004UL
-#define XLPD_XPPU_IMR_MID_RO_DEFVAL  0x1UL
-
-#define XLPD_XPPU_IMR_MID_MISS_SHIFT   1UL
-#define XLPD_XPPU_IMR_MID_MISS_WIDTH   1UL
-#define XLPD_XPPU_IMR_MID_MISS_MASK    0x00000002UL
-#define XLPD_XPPU_IMR_MID_MISS_DEFVAL  0x1UL
-
-#define XLPD_XPPU_IMR_INV_APB_SHIFT   0UL
-#define XLPD_XPPU_IMR_INV_APB_WIDTH   1UL
-#define XLPD_XPPU_IMR_INV_APB_MASK    0x00000001UL
-#define XLPD_XPPU_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XlpdXppuIen
- */
-#define XLPD_XPPU_IEN    ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
-#define XLPD_XPPU_IEN_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_IEN_APER_PARITY_SHIFT   7UL
-#define XLPD_XPPU_IEN_APER_PARITY_WIDTH   1UL
-#define XLPD_XPPU_IEN_APER_PARITY_MASK    0x00000080UL
-#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IEN_APER_TZ_SHIFT   6UL
-#define XLPD_XPPU_IEN_APER_TZ_WIDTH   1UL
-#define XLPD_XPPU_IEN_APER_TZ_MASK    0x00000040UL
-#define XLPD_XPPU_IEN_APER_TZ_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IEN_APER_PERM_SHIFT   5UL
-#define XLPD_XPPU_IEN_APER_PERM_WIDTH   1UL
-#define XLPD_XPPU_IEN_APER_PERM_MASK    0x00000020UL
-#define XLPD_XPPU_IEN_APER_PERM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IEN_MID_PARITY_SHIFT   3UL
-#define XLPD_XPPU_IEN_MID_PARITY_WIDTH   1UL
-#define XLPD_XPPU_IEN_MID_PARITY_MASK    0x00000008UL
-#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IEN_MID_RO_SHIFT   2UL
-#define XLPD_XPPU_IEN_MID_RO_WIDTH   1UL
-#define XLPD_XPPU_IEN_MID_RO_MASK    0x00000004UL
-#define XLPD_XPPU_IEN_MID_RO_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IEN_MID_MISS_SHIFT   1UL
-#define XLPD_XPPU_IEN_MID_MISS_WIDTH   1UL
-#define XLPD_XPPU_IEN_MID_MISS_MASK    0x00000002UL
-#define XLPD_XPPU_IEN_MID_MISS_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IEN_INV_APB_SHIFT   0UL
-#define XLPD_XPPU_IEN_INV_APB_WIDTH   1UL
-#define XLPD_XPPU_IEN_INV_APB_MASK    0x00000001UL
-#define XLPD_XPPU_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuIds
- */
-#define XLPD_XPPU_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
-#define XLPD_XPPU_IDS_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_IDS_APER_PARITY_SHIFT   7UL
-#define XLPD_XPPU_IDS_APER_PARITY_WIDTH   1UL
-#define XLPD_XPPU_IDS_APER_PARITY_MASK    0x00000080UL
-#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IDS_APER_TZ_SHIFT   6UL
-#define XLPD_XPPU_IDS_APER_TZ_WIDTH   1UL
-#define XLPD_XPPU_IDS_APER_TZ_MASK    0x00000040UL
-#define XLPD_XPPU_IDS_APER_TZ_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IDS_APER_PERM_SHIFT   5UL
-#define XLPD_XPPU_IDS_APER_PERM_WIDTH   1UL
-#define XLPD_XPPU_IDS_APER_PERM_MASK    0x00000020UL
-#define XLPD_XPPU_IDS_APER_PERM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IDS_MID_PARITY_SHIFT   3UL
-#define XLPD_XPPU_IDS_MID_PARITY_WIDTH   1UL
-#define XLPD_XPPU_IDS_MID_PARITY_MASK    0x00000008UL
-#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IDS_MID_RO_SHIFT   2UL
-#define XLPD_XPPU_IDS_MID_RO_WIDTH   1UL
-#define XLPD_XPPU_IDS_MID_RO_MASK    0x00000004UL
-#define XLPD_XPPU_IDS_MID_RO_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IDS_MID_MISS_SHIFT   1UL
-#define XLPD_XPPU_IDS_MID_MISS_WIDTH   1UL
-#define XLPD_XPPU_IDS_MID_MISS_MASK    0x00000002UL
-#define XLPD_XPPU_IDS_MID_MISS_DEFVAL  0x0UL
-
-#define XLPD_XPPU_IDS_INV_APB_SHIFT   0UL
-#define XLPD_XPPU_IDS_INV_APB_WIDTH   1UL
-#define XLPD_XPPU_IDS_INV_APB_MASK    0x00000001UL
-#define XLPD_XPPU_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMMstrIds
- */
-#define XLPD_XPPU_M_MSTR_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
-#define XLPD_XPPU_M_MSTR_IDS_RSTVAL   0x00000014UL
-
-#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT   0UL
-#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH   32UL
-#define XLPD_XPPU_M_MSTR_IDS_NO_MASK    0xffffffffUL
-#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL  0x14UL
-
-/**
- * Register: XlpdXppuMAperture32b
- */
-#define XLPD_XPPU_M_APERTURE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
-#define XLPD_XPPU_M_APERTURE_32B_RSTVAL   0x00000080UL
-
-#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT   0UL
-#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH   32UL
-#define XLPD_XPPU_M_APERTURE_32B_NO_MASK    0xffffffffUL
-#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL  0x80UL
-
-/**
- * Register: XlpdXppuMAperture64kb
- */
-#define XLPD_XPPU_M_APERTURE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
-#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL   0x00000100UL
-
-#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT   0UL
-#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH   32UL
-#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK    0xffffffffUL
-#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL  0x100UL
-
-/**
- * Register: XlpdXppuMAperture1mb
- */
-#define XLPD_XPPU_M_APERTURE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
-#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL   0x00000010UL
-
-#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT   0UL
-#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH   32UL
-#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK    0xffffffffUL
-#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL  0x10UL
-
-/**
- * Register: XlpdXppuMAperture512mb
- */
-#define XLPD_XPPU_M_APERTURE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
-#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL   0x00000001UL
-
-#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT   0UL
-#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH   32UL
-#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK    0xffffffffUL
-#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL  0x1UL
-
-/**
- * Register: XlpdXppuBase32b
- */
-#define XLPD_XPPU_BASE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
-#define XLPD_XPPU_BASE_32B_RSTVAL   0xff990000UL
-
-#define XLPD_XPPU_BASE_32B_ADDR_SHIFT   0UL
-#define XLPD_XPPU_BASE_32B_ADDR_WIDTH   32UL
-#define XLPD_XPPU_BASE_32B_ADDR_MASK    0xffffffffUL
-#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL  0xff990000UL
-
-/**
- * Register: XlpdXppuBase64kb
- */
-#define XLPD_XPPU_BASE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
-#define XLPD_XPPU_BASE_64KB_RSTVAL   0xff000000UL
-
-#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT   0UL
-#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH   32UL
-#define XLPD_XPPU_BASE_64KB_ADDR_MASK    0xffffffffUL
-#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL  0xff000000UL
-
-/**
- * Register: XlpdXppuBase1mb
- */
-#define XLPD_XPPU_BASE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
-#define XLPD_XPPU_BASE_1MB_RSTVAL   0xfe000000UL
-
-#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT   0UL
-#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH   32UL
-#define XLPD_XPPU_BASE_1MB_ADDR_MASK    0xffffffffUL
-#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL  0xfe000000UL
-
-/**
- * Register: XlpdXppuBase512mb
- */
-#define XLPD_XPPU_BASE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
-#define XLPD_XPPU_BASE_512MB_RSTVAL   0xc0000000UL
-
-#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT   0UL
-#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH   32UL
-#define XLPD_XPPU_BASE_512MB_ADDR_MASK    0xffffffffUL
-#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL  0xc0000000UL
-
-/**
- * Register: XlpdXppuMstrId00
- */
-#define XLPD_XPPU_MSTR_ID00    ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
-#define XLPD_XPPU_MSTR_ID00_RSTVAL   0x83ff0040UL
-
-#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID00_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL  0x1UL
-
-#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID00_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID00_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL  0x3ffUL
-
-#define XLPD_XPPU_MSTR_ID00_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID00_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID00_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL  0x40UL
-
-/**
- * Register: XlpdXppuMstrId01
- */
-#define XLPD_XPPU_MSTR_ID01    ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
-#define XLPD_XPPU_MSTR_ID01_RSTVAL   0x03f00000UL
-
-#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID01_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID01_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID01_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL  0x3f0UL
-
-#define XLPD_XPPU_MSTR_ID01_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID01_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID01_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId02
- */
-#define XLPD_XPPU_MSTR_ID02    ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
-#define XLPD_XPPU_MSTR_ID02_RSTVAL   0x83f00010UL
-
-#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID02_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL  0x1UL
-
-#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID02_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID02_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL  0x3f0UL
-
-#define XLPD_XPPU_MSTR_ID02_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID02_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID02_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL  0x10UL
-
-/**
- * Register: XlpdXppuMstrId03
- */
-#define XLPD_XPPU_MSTR_ID03    ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
-#define XLPD_XPPU_MSTR_ID03_RSTVAL   0x83c00080UL
-
-#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID03_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL  0x1UL
-
-#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID03_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID03_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL  0x3c0UL
-
-#define XLPD_XPPU_MSTR_ID03_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID03_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID03_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL  0x80UL
-
-/**
- * Register: XlpdXppuMstrId04
- */
-#define XLPD_XPPU_MSTR_ID04    ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
-#define XLPD_XPPU_MSTR_ID04_RSTVAL   0x83c30080UL
-
-#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID04_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL  0x1UL
-
-#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID04_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID04_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL  0x3c3UL
-
-#define XLPD_XPPU_MSTR_ID04_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID04_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID04_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL  0x80UL
-
-/**
- * Register: XlpdXppuMstrId05
- */
-#define XLPD_XPPU_MSTR_ID05    ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
-#define XLPD_XPPU_MSTR_ID05_RSTVAL   0x03c30081UL
-
-#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID05_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID05_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID05_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL  0x3c3UL
-
-#define XLPD_XPPU_MSTR_ID05_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID05_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID05_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL  0x81UL
-
-/**
- * Register: XlpdXppuMstrId06
- */
-#define XLPD_XPPU_MSTR_ID06    ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
-#define XLPD_XPPU_MSTR_ID06_RSTVAL   0x03c30082UL
-
-#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID06_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID06_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID06_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL  0x3c3UL
-
-#define XLPD_XPPU_MSTR_ID06_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID06_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID06_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL  0x82UL
-
-/**
- * Register: XlpdXppuMstrId07
- */
-#define XLPD_XPPU_MSTR_ID07    ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
-#define XLPD_XPPU_MSTR_ID07_RSTVAL   0x83c30083UL
-
-#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID07_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL  0x1UL
-
-#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID07_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID07_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL  0x3c3UL
-
-#define XLPD_XPPU_MSTR_ID07_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID07_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID07_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL  0x83UL
-
-/**
- * Register: XlpdXppuMstrId08
- */
-#define XLPD_XPPU_MSTR_ID08    ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
-#define XLPD_XPPU_MSTR_ID08_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID08_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID08_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID08_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID08_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID08_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID08_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId09
- */
-#define XLPD_XPPU_MSTR_ID09    ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
-#define XLPD_XPPU_MSTR_ID09_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID09_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID09_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID09_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID09_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID09_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID09_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId10
- */
-#define XLPD_XPPU_MSTR_ID10    ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
-#define XLPD_XPPU_MSTR_ID10_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID10_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID10_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID10_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID10_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID10_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID10_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId11
- */
-#define XLPD_XPPU_MSTR_ID11    ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
-#define XLPD_XPPU_MSTR_ID11_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID11_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID11_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID11_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID11_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID11_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID11_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId12
- */
-#define XLPD_XPPU_MSTR_ID12    ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
-#define XLPD_XPPU_MSTR_ID12_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID12_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID12_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID12_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID12_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID12_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID12_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId13
- */
-#define XLPD_XPPU_MSTR_ID13    ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
-#define XLPD_XPPU_MSTR_ID13_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID13_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID13_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID13_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID13_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID13_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID13_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId14
- */
-#define XLPD_XPPU_MSTR_ID14    ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
-#define XLPD_XPPU_MSTR_ID14_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID14_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID14_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID14_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID14_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID14_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID14_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId15
- */
-#define XLPD_XPPU_MSTR_ID15    ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
-#define XLPD_XPPU_MSTR_ID15_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID15_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID15_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID15_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID15_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID15_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID15_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId16
- */
-#define XLPD_XPPU_MSTR_ID16    ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
-#define XLPD_XPPU_MSTR_ID16_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID16_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID16_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID16_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID16_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID16_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID16_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId17
- */
-#define XLPD_XPPU_MSTR_ID17    ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
-#define XLPD_XPPU_MSTR_ID17_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID17_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID17_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID17_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID17_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID17_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID17_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId18
- */
-#define XLPD_XPPU_MSTR_ID18    ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
-#define XLPD_XPPU_MSTR_ID18_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID18_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID18_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID18_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID18_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID18_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID18_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuMstrId19
- */
-#define XLPD_XPPU_MSTR_ID19    ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
-#define XLPD_XPPU_MSTR_ID19_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT   31UL
-#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID19_MIDP_MASK    0x80000000UL
-#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT   30UL
-#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH   1UL
-#define XLPD_XPPU_MSTR_ID19_MIDR_MASK    0x40000000UL
-#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT   16UL
-#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID19_MIDM_MASK    0x03ff0000UL
-#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL  0x0UL
-
-#define XLPD_XPPU_MSTR_ID19_MID_SHIFT   0UL
-#define XLPD_XPPU_MSTR_ID19_MID_WIDTH   10UL
-#define XLPD_XPPU_MSTR_ID19_MID_MASK    0x000003ffUL
-#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XLPD_XPPU_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h
deleted file mode 100644
index 95f7e20a2..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XLPD_XPPU_SINK_H__
-#define __XLPD_XPPU_SINK_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XlpdXppuSink Base Address
- */
-#define XLPD_XPPU_SINK_BASEADDR      0xFF9C0000UL
-
-/**
- * Register: XlpdXppuSinkErrSts
- */
-#define XLPD_XPPU_SINK_ERR_STS    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
-#define XLPD_XPPU_SINK_ERR_STS_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT   31UL
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH   1UL
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
-
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT   0UL
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH   12UL
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuSinkIsr
- */
-#define XLPD_XPPU_SINK_ISR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
-#define XLPD_XPPU_SINK_ISR_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT   0UL
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH   1UL
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuSinkImr
- */
-#define XLPD_XPPU_SINK_IMR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
-#define XLPD_XPPU_SINK_IMR_RSTVAL   0x00000001UL
-
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT   0UL
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH   1UL
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
-
-/**
- * Register: XlpdXppuSinkIer
- */
-#define XLPD_XPPU_SINK_IER    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
-#define XLPD_XPPU_SINK_IER_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT   0UL
-#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH   1UL
-#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
-#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
-
-/**
- * Register: XlpdXppuSinkIdr
- */
-#define XLPD_XPPU_SINK_IDR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
-#define XLPD_XPPU_SINK_IDR_RSTVAL   0x00000000UL
-
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT   0UL
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH   1UL
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XLPD_XPPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h
deleted file mode 100644
index 5e3631f3e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/* ### HEADER ### */
-
-#ifndef __XOCM_XMPU_CFG_H__
-#define __XOCM_XMPU_CFG_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * XocmXmpuCfg Base Address
- */
-#define XOCM_XMPU_CFG_BASEADDR      0xFFA70000UL
-
-/**
- * Register: XocmXmpuCfgCtrl
- */
-#define XOCM_XMPU_CFG_CTRL    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL )
-#define XOCM_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
-
-#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
-#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
-#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
-#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
-#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
-#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
-
-/**
- * Register: XocmXmpuCfgErrSts1
- */
-#define XOCM_XMPU_CFG_ERR_STS1    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL )
-#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
-#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
-#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgErrSts2
- */
-#define XOCM_XMPU_CFG_ERR_STS2    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL )
-#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgPoison
- */
-#define XOCM_XMPU_CFG_POISON    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
-#define XOCM_XMPU_CFG_POISON_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
-#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
-#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
-#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_POISON_BASE_SHIFT   0UL
-#define XOCM_XMPU_CFG_POISON_BASE_WIDTH   20UL
-#define XOCM_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
-#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgIsr
- */
-#define XOCM_XMPU_CFG_ISR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL )
-#define XOCM_XMPU_CFG_ISR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
-#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
-#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
-#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
-#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
-#define XOCM_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgImr
- */
-#define XOCM_XMPU_CFG_IMR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL )
-#define XOCM_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
-
-#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
-#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
-#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
-#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
-#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
-#define XOCM_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
-
-/**
- * Register: XocmXmpuCfgIen
- */
-#define XOCM_XMPU_CFG_IEN    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL )
-#define XOCM_XMPU_CFG_IEN_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
-#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
-#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
-#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
-#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
-#define XOCM_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgIds
- */
-#define XOCM_XMPU_CFG_IDS    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
-#define XOCM_XMPU_CFG_IDS_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
-#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
-#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
-#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
-#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
-#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
-#define XOCM_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgLock
- */
-#define XOCM_XMPU_CFG_LOCK    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL )
-#define XOCM_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
-#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
-#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR00Strt
- */
-#define XOCM_XMPU_CFG_R00_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL )
-#define XOCM_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR00End
- */
-#define XOCM_XMPU_CFG_R00_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL )
-#define XOCM_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR00Mstr
- */
-#define XOCM_XMPU_CFG_R00_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL )
-#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR00
- */
-#define XOCM_XMPU_CFG_R00    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
-#define XOCM_XMPU_CFG_R00_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R00_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R00_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R00_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R00_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR01Strt
- */
-#define XOCM_XMPU_CFG_R01_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL )
-#define XOCM_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR01End
- */
-#define XOCM_XMPU_CFG_R01_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL )
-#define XOCM_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR01Mstr
- */
-#define XOCM_XMPU_CFG_R01_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL )
-#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR01
- */
-#define XOCM_XMPU_CFG_R01    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
-#define XOCM_XMPU_CFG_R01_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R01_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R01_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R01_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R01_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR02Strt
- */
-#define XOCM_XMPU_CFG_R02_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL )
-#define XOCM_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR02End
- */
-#define XOCM_XMPU_CFG_R02_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL )
-#define XOCM_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR02Mstr
- */
-#define XOCM_XMPU_CFG_R02_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL )
-#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR02
- */
-#define XOCM_XMPU_CFG_R02    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
-#define XOCM_XMPU_CFG_R02_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R02_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R02_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R02_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R02_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR03Strt
- */
-#define XOCM_XMPU_CFG_R03_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL )
-#define XOCM_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR03End
- */
-#define XOCM_XMPU_CFG_R03_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL )
-#define XOCM_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR03Mstr
- */
-#define XOCM_XMPU_CFG_R03_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL )
-#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR03
- */
-#define XOCM_XMPU_CFG_R03    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
-#define XOCM_XMPU_CFG_R03_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R03_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R03_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R03_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R03_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR04Strt
- */
-#define XOCM_XMPU_CFG_R04_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL )
-#define XOCM_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR04End
- */
-#define XOCM_XMPU_CFG_R04_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL )
-#define XOCM_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR04Mstr
- */
-#define XOCM_XMPU_CFG_R04_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL )
-#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR04
- */
-#define XOCM_XMPU_CFG_R04    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
-#define XOCM_XMPU_CFG_R04_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R04_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R04_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R04_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R04_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR05Strt
- */
-#define XOCM_XMPU_CFG_R05_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL )
-#define XOCM_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR05End
- */
-#define XOCM_XMPU_CFG_R05_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL )
-#define XOCM_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR05Mstr
- */
-#define XOCM_XMPU_CFG_R05_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL )
-#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR05
- */
-#define XOCM_XMPU_CFG_R05    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
-#define XOCM_XMPU_CFG_R05_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R05_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R05_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R05_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R05_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR06Strt
- */
-#define XOCM_XMPU_CFG_R06_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL )
-#define XOCM_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR06End
- */
-#define XOCM_XMPU_CFG_R06_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL )
-#define XOCM_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR06Mstr
- */
-#define XOCM_XMPU_CFG_R06_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL )
-#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR06
- */
-#define XOCM_XMPU_CFG_R06    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
-#define XOCM_XMPU_CFG_R06_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R06_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R06_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R06_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R06_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR07Strt
- */
-#define XOCM_XMPU_CFG_R07_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL )
-#define XOCM_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR07End
- */
-#define XOCM_XMPU_CFG_R07_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL )
-#define XOCM_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR07Mstr
- */
-#define XOCM_XMPU_CFG_R07_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL )
-#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR07
- */
-#define XOCM_XMPU_CFG_R07    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
-#define XOCM_XMPU_CFG_R07_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R07_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R07_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R07_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R07_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR08Strt
- */
-#define XOCM_XMPU_CFG_R08_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL )
-#define XOCM_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR08End
- */
-#define XOCM_XMPU_CFG_R08_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL )
-#define XOCM_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR08Mstr
- */
-#define XOCM_XMPU_CFG_R08_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL )
-#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR08
- */
-#define XOCM_XMPU_CFG_R08    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
-#define XOCM_XMPU_CFG_R08_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R08_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R08_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R08_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R08_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR09Strt
- */
-#define XOCM_XMPU_CFG_R09_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL )
-#define XOCM_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR09End
- */
-#define XOCM_XMPU_CFG_R09_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL )
-#define XOCM_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR09Mstr
- */
-#define XOCM_XMPU_CFG_R09_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL )
-#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR09
- */
-#define XOCM_XMPU_CFG_R09    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
-#define XOCM_XMPU_CFG_R09_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R09_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R09_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R09_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R09_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR10Strt
- */
-#define XOCM_XMPU_CFG_R10_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
-#define XOCM_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR10End
- */
-#define XOCM_XMPU_CFG_R10_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
-#define XOCM_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR10Mstr
- */
-#define XOCM_XMPU_CFG_R10_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
-#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR10
- */
-#define XOCM_XMPU_CFG_R10    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
-#define XOCM_XMPU_CFG_R10_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R10_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R10_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R10_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R10_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR11Strt
- */
-#define XOCM_XMPU_CFG_R11_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
-#define XOCM_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR11End
- */
-#define XOCM_XMPU_CFG_R11_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
-#define XOCM_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR11Mstr
- */
-#define XOCM_XMPU_CFG_R11_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
-#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR11
- */
-#define XOCM_XMPU_CFG_R11    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
-#define XOCM_XMPU_CFG_R11_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R11_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R11_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R11_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R11_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR12Strt
- */
-#define XOCM_XMPU_CFG_R12_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
-#define XOCM_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR12End
- */
-#define XOCM_XMPU_CFG_R12_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
-#define XOCM_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR12Mstr
- */
-#define XOCM_XMPU_CFG_R12_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
-#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR12
- */
-#define XOCM_XMPU_CFG_R12    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
-#define XOCM_XMPU_CFG_R12_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R12_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R12_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R12_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R12_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR13Strt
- */
-#define XOCM_XMPU_CFG_R13_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
-#define XOCM_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR13End
- */
-#define XOCM_XMPU_CFG_R13_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
-#define XOCM_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR13Mstr
- */
-#define XOCM_XMPU_CFG_R13_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
-#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR13
- */
-#define XOCM_XMPU_CFG_R13    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
-#define XOCM_XMPU_CFG_R13_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R13_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R13_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R13_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R13_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR14Strt
- */
-#define XOCM_XMPU_CFG_R14_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
-#define XOCM_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR14End
- */
-#define XOCM_XMPU_CFG_R14_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
-#define XOCM_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR14Mstr
- */
-#define XOCM_XMPU_CFG_R14_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
-#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR14
- */
-#define XOCM_XMPU_CFG_R14    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
-#define XOCM_XMPU_CFG_R14_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R14_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R14_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R14_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R14_EN_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR15Strt
- */
-#define XOCM_XMPU_CFG_R15_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
-#define XOCM_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR15End
- */
-#define XOCM_XMPU_CFG_R15_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
-#define XOCM_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
-#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
-#define XOCM_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
-#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR15Mstr
- */
-#define XOCM_XMPU_CFG_R15_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
-#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
-
-#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
-#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
-#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
-#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
-#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
-#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
-#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
-
-/**
- * Register: XocmXmpuCfgR15
- */
-#define XOCM_XMPU_CFG_R15    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
-#define XOCM_XMPU_CFG_R15_RSTVAL   0x00000008UL
-
-#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
-#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
-#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
-#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT   3UL
-#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH   1UL
-#define XOCM_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
-#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
-
-#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT   2UL
-#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
-#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT   1UL
-#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH   1UL
-#define XOCM_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
-#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
-
-#define XOCM_XMPU_CFG_R15_EN_SHIFT   0UL
-#define XOCM_XMPU_CFG_R15_EN_WIDTH   1UL
-#define XOCM_XMPU_CFG_R15_EN_MASK    0x00000001UL
-#define XOCM_XMPU_CFG_R15_EN_DEFVAL  0x0UL
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XOCM_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c
deleted file mode 100644
index 242d8faf3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#include <unistd.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) sint32 _isatty(sint32 fd);
-}
-#endif
-
-/*
- * isatty -- returns 1 if connected to a terminal device,
- *           returns 0 if not. Since we're hooked up to a
- *           serial port, we'll say yes _AND return a 1.
- */
-__attribute__((weak)) sint32 isatty(sint32 fd)
-{
-  (void)fd;
-  return (1);
-}
-
-__attribute__((weak)) sint32 _isatty(sint32 fd)
-{
-  (void)fd;
-  return (1);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c
deleted file mode 100644
index 1c67ace57..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#include <signal.h>
-#include <unistd.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
-}
-#endif
-
-/*
- * kill -- go out via exit...
- */
-
-__attribute__((weak)) s32 kill(s32 pid, s32 sig)
-{
-  if(pid == 1) {
-    _exit(sig);
-  }
-  return 0;
-}
-
-__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
-{
-  if(pid == 1) {
-    _exit(sig);
-  }
-  return 0;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c
deleted file mode 100644
index 5cd5a2dd1..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <sys/types.h>
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
-}
-#endif
-/*
- * lseek --  Since a serial port is non-seekable, we return an error.
- */
-__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
-{
-  (void)fd;
-  (void)offset;
-  (void)whence;
-  errno = ESPIPE;
-  return ((off_t)-1);
-}
-
-__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
-{
-  (void)fd;
-  (void)offset;
-  (void)whence;
-  errno = ESPIPE;
-  return ((off_t)-1);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c
deleted file mode 100644
index bf5ddeefe..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file mpu.c
-*
-* This file contains initial configuration of the MPU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 	pkp  02/20/14 First release
-* 5.04	pkp  12/18/15 Updated MPU initialization as per the proper address map
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xreg_cortexr5.h"
-#include "xil_mpu.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-static const struct {
-	u64 size;
-	unsigned int encoding;
-}region_size[] = {
-	{ 0x20, REGION_32B },
-	{ 0x40, REGION_64B },
-	{ 0x80, REGION_128B },
-	{ 0x100, REGION_256B },
-	{ 0x200, REGION_512B },
-	{ 0x400, REGION_1K },
-	{ 0x800, REGION_2K },
-	{ 0x1000, REGION_4K },
-	{ 0x2000, REGION_8K },
-	{ 0x4000, REGION_16K },
-	{ 0x8000, REGION_32K },
-	{ 0x10000, REGION_64K },
-	{ 0x20000, REGION_128K },
-	{ 0x40000, REGION_256K },
-	{ 0x80000, REGION_512K },
-	{ 0x100000, REGION_1M },
-	{ 0x200000, REGION_2M },
-	{ 0x400000, REGION_4M },
-	{ 0x800000, REGION_8M },
-	{ 0x1000000, REGION_16M },
-	{ 0x2000000, REGION_32M },
-	{ 0x4000000, REGION_64M },
-	{ 0x8000000, REGION_128M },
-	{ 0x10000000, REGION_256M },
-	{ 0x20000000, REGION_512M },
-	{ 0x40000000, REGION_1G },
-	{ 0x80000000, REGION_2G },
-	{ 0x100000000, REGION_4G },
-};
-
-/************************** Function Prototypes ******************************/
-void Init_MPU(void);
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
-static void Xil_DisableMPURegions(void);
-
-/*****************************************************************************
-*
-* Initialize MPU for a given address map and Enabled the background Region in
-* MPU with default memory attributes for rest of address range for Cortex R5
-* processor.
-*
-* @param	None.
-*
-* @return	None.
-*
-*
-******************************************************************************/
-
-void Init_MPU(void)
-{
-	u32 Addr;
-	u32 RegSize;
-	u32 Attrib;
-	u32 RegNum = 0, i;
-	u64 size;
-
-	Xil_DisableMPURegions();
-
-	Addr = 0x00000000U;
-#ifdef	XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
-	/* If the DDR is present, configure region as per DDR size */
-	size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
-	if (size < 0x80000000) {
-		/* Lookup the size.  */
-		for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
-			if (size <= region_size[i].size) {
-				RegSize = region_size[i].encoding;
-				break;
-			}
-		}
-	} else {
-		/* if the DDR size is > 2GB, truncate it to 2GB */
-		RegSize = REGION_2G;
-	}
-#else
-	/* For DDRless system, configure region for TCM */
-	RegSize = REGION_256K;
-#endif
-	Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/*
-	 * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
-	 * 512 MB - LPD-PL interface
-	 * 256 MB - FPD-PL (HPM0) interface
-	 * 256 MB - FPD-PL (HPM1) interface
-	 */
-	Addr = 0x80000000;
-	RegSize = REGION_1G;
-	Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
-	Addr = 0xC0000000U;
-	RegSize = REGION_512M;
-	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
-	Addr = 0xE0000000U;
-	RegSize = REGION_256M;
-	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
-	Addr = 0xF8000000U;
-	RegSize = REGION_16M;
-	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
-	Addr = 0xF9000000U;
-	RegSize = REGION_1M;
-	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
-	Addr = 0xFD000000U;
-	RegSize = REGION_16M;
-	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
-	Addr = 0xFE000000U;
-	RegSize = REGION_16M;
-	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/*
-	 * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
-	 * CSU, PMU, TCM, OCM
-	 */
-	Addr = 0xFF000000U;
-	RegSize = REGION_16M;
-	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-	RegNum++;
-
-	/* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
-	Addr = 0xFFFC0000U;
-	RegSize = REGION_256K;
-	Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW  ;
-	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
-
-	/* A total of 10 MPU regions are allocated with another 6 being free for users */
-
-}
-
-/*****************************************************************************
-*
-* Set the memory attributes for a section of memory with starting address addr
-* of the region size defined by reg_size having attributes attrib of region number
-* reg_num
-*
-* @param	addr is the address for which attributes are to be set.
-* @param	attrib specifies the attributes for that memory region.
-* @param	reg_size specifies the size for that memory region.
-* @param	reg_num specifies the number for that memory region.
-* @return	None.
-*
-*
-******************************************************************************/
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
-{
-	u32 Local_reg_size = reg_size;
-
-	Local_reg_size = Local_reg_size<<1U;
-	Local_reg_size |= REGION_EN;
-	dsb();
-	mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
-	isb();
-	mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); 		/* Set base address of a region */
-	mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); 	/* Set the control attribute */
-	mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size);	/* set the region size and enable it*/
-	dsb();
-	isb();						/* synchronize context on this processor */
-}
-
-
-/*****************************************************************************
-*
-* Disable all the MPU regions if any of them is enabled
-*
-* @param	None.
-*
-* @return	None.
-*
-*
-******************************************************************************/
-static void Xil_DisableMPURegions(void)
-{
-	u32 Temp;
-	u32 Index;
-	for (Index = 0; Index <= 15; Index++) {
-		mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
-		Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
-		Temp &= (~REGION_EN);
-		dsb();
-		mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
-		dsb();
-		isb();
-	}
-
-}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c
deleted file mode 100644
index c32530bab..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/* Use toolchain function for openamp applications*/
-
-#ifndef UNDEFINE_FILE_OPS
-
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
-}
-#endif
-/*
- * open -- open a file descriptor. We don't have a filesystem, so
- *         we return an error.
- */
-__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
-{
-  (void *)buf;
-  (void)flags;
-  (void)mode;
-  errno = EIO;
-  return (-1);
-}
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c
deleted file mode 100644
index 3c6430886..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c
+++ /dev/null
@@ -1,15 +0,0 @@
-#include "xparameters.h"
-#include "xuartps_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-void outbyte(char c); 
-
-#ifdef __cplusplus
-}
-#endif 
-
-void outbyte(char c) {
-	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c
deleted file mode 100644
index 31d7b1989..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* print.c -- print a string on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- *
- */
-
-/*
- * print -- do a raw print of a string
- */
-#include "xil_printf.h"
-
-void print(const char8 *ptr)
-{
-#ifdef STDOUT_BASEADDRESS
-  while (*ptr != (char8)0) {
-    outbyte (*ptr);
-	*ptr++;
-  }
-#else
-(void)ptr;
-#endif
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c
deleted file mode 100644
index 86d3a74e8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* putnum.c -- put a hex number on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
- * putnum -- print a 32 bit number in hex
- */
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Function Prototypes ******************************/
-extern void print (const char8 *ptr);
-void putnum(u32 num);
-
-void putnum(u32 num)
-{
-  char8  buf[9];
-  u32   cnt;
-  s32 i;
-  char8  *ptr;
-  u32  digit;
-  for(i = 0; i<9; i++) {
-	buf[i] = '0';
-  }
-
-  ptr = buf;
-  for (cnt = 7U ; cnt >= 0U ; cnt--) {
-    digit = (num >> (cnt * 4U)) & 0x0000000fU;
-
-    if ((digit <= 9U) && (ptr != NULL)) {
-		digit += (u32)'0';
-		*ptr = ((char8) digit);
-		ptr += 1;
-	} else if (ptr != NULL) {
-		digit += ((u32)'a' - (u32)10);
-		*ptr = ((char8)digit);
-		ptr += 1;
-	} else {
-		/*Made for MisraC Compliance*/;
-	}
-  }
-
-  if(ptr != NULL) {
-	  *ptr = (char8) 0;
-  }
-  print (buf);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c
deleted file mode 100644
index 90fb25029..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/* Use toolchain function for openamp applications*/
-
-#ifndef UNDEFINE_FILE_OPS
-
-/* read.c -- read bytes from a input device.
- */
-
-#include "xparameters.h"
-#include "xil_printf.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
-}
-#endif
-
-/*
- * read  -- read bytes from the serial port. Ignore fd, since
- *          we only have stdin.
- */
-__attribute__((weak)) s32
-read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
-  s32 i;
-  char8* LocalBuf = buf;
-
-  (void)fd;
-  for (i = 0; i < nbytes; i++) {
-	if(LocalBuf != NULL) {
-		LocalBuf += i;
-	}
-	if(LocalBuf != NULL) {
-	    *LocalBuf = inbyte();
-	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
-	        break;
-		}
-	}
-	if(LocalBuf != NULL) {
-	LocalBuf -= i;
-	}
-  }
-
-  return (i + 1);
-#else
-  (void)fd;
-  (void)buf;
-  (void)nbytes;
-  return 0;
-#endif
-}
-
-__attribute__((weak)) s32
-_read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
-  s32 i;
-  char8* LocalBuf = buf;
-
-  (void)fd;
-  for (i = 0; i < nbytes; i++) {
-	if(LocalBuf != NULL) {
-		LocalBuf += i;
-	}
-	if(LocalBuf != NULL) {
-	    *LocalBuf = inbyte();
-	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
-	        break;
-		}
-	}
-	if(LocalBuf != NULL) {
-	LocalBuf -= i;
-	}
-  }
-
-  return (i + 1);
-#else
-  (void)fd;
-  (void)buf;
-  (void)nbytes;
-  return 0;
-#endif
-}
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c
deleted file mode 100644
index 7f94fabb4..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <errno.h>
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) char8 *sbrk (s32 nbytes);
-}
-#endif
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-extern char8 HeapBase[];
-extern char8 HeapLimit[];
-
-
-
-__attribute__((weak)) char8 *sbrk (s32 nbytes)
-{
-  char8 *base;
-  static char8 *heap_ptr = HeapBase;
-
-  base = heap_ptr;
-  if(heap_ptr != NULL) {
-	heap_ptr += nbytes;
-  }
-
-/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
-  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
-    return base;
-  }	else {
-    errno = ENOMEM;
-    return ((char8 *)-1);
-  }
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
deleted file mode 100644
index 508b30f61..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Global Timer register in
-* the ARM Cortex R5 MP core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
-* 5.04  pkp		 02/19/16 sleep routine is modified to use TTC3 if present
-*						  else it will use set of assembly instructions to
-*						  provide the required delay
-* 5.04	pkp		 03/09/16 Assembly routine for sleep is modified to avoid
-*						  disabling the interrupt
-* 5.04	pkp		 03/11/16 Compare the counter value to previously read value
-*						  to detect the overflow for TTC3
-* </pre>
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds.
-*
-* @param	seconds requested
-*
-* @return	0 always
-*
-* @note		The sleep API is implemented using TTC3 counter 0 timer if present.
-*			When TTC3 is absent, sleep is implemented using assembly
-*			instructions which is tested with instruction and data caches
-*			enabled and it gives proper delay. It may give more delay than
-*			exepcted when caches are disabled. If interrupt comes when sleep
-*			using assembly instruction is being executed, the delay may be
-*			greater than what is expected since once the interrupt is served
-*			count resumes from where it was interrupted unlike the case of TTC3
-*			where counter keeps running while interrupt is being served.
-*
-****************************************************************************/
-
-s32 sleep(u32 seconds)
-{
-#ifdef SLEEP_TIMER_BASEADDR
-	u64 tEnd;
-	u64 tCur;
-	u32 TimeHighVal;
-	XTime TimeLowVal1;
-	XTime TimeLowVal2;
-
-	TimeHighVal = 0;
-
-	XTime_GetTime(&TimeLowVal1);
-	tEnd  = (u64)TimeLowVal1 + (((u64) seconds) * COUNTS_PER_SECOND);
-
-	do
-	{
-
-	    XTime_GetTime(&TimeLowVal2);
-	    if (TimeLowVal2 < TimeLowVal1) {
-				TimeHighVal++;
-		}
-
-		TimeLowVal1 = TimeLowVal2;
-	    tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
-
-	} while (tCur < tEnd);
-
-	return 0;
-#else
-	__asm__ __volatile__ (
-			" push {r0,r1}		\n\t"
-			" mov r0, %[sec]	\n\t"
-			" 1: \n\t"
-			" mov r1, %[iter] 	\n\t"
-			" 2:				\n\t"
-			" subs r1, r1, #0x1 \n\t"
-			" bne   2b    		\n\t"
-			" subs r0,r0,#0x1 	\n\t"
-			"  bne 1b 			\n\t"
-			" pop {r0,r1} 		\n\t"
-			:: [iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds)
-	);
-#endif
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h
deleted file mode 100644
index 9b49173c6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-s32 usleep(u32 useconds);
-s32 sleep(u32 seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c
deleted file mode 100644
index bff3ed24f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file uart.c
-*
-* This file contains APIs for configuring the UART.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 	pkp  02/20/14 First release
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/* Register offsets */
-#define UART_CR_OFFSET		0x00000000U
-#define UART_MR_OFFSET		0x00000004U
-#define UART_BAUDGEN_OFFSET	0x00000018U
-#define UART_BAUDDIV_OFFSET	0x00000034U
-
-#define MAX_BAUD_ERROR_RATE	0x00000003U	/* max % error allowed */
-#define UART_BAUDRATE	115200U
-#define CSU_VERSION_REG     0xFFCA0044U
-
-void Init_Uart(void);
-
-void Init_Uart(void)
-{
-#ifdef STDOUT_BASEADDRESS
-	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
-	u32 BRGR_Value;		/* Calculated value for baud rate generator */
-	u32 CalcBaudRate;	/* Calculated baud rate */
-	u32 BaudError;		/* Diff between calculated and requested baud rate */
-	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
-	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
-	u32 Best_Error = 0xFFFFFFFFU;
-	u32 PercentError;
-	u32 InputClk;
-   u32 BaudRate = UART_BAUDRATE;
-
-#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
-	InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
-#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
-	InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
-#else
-	/* STDIO is not set or axi_uart is being used for STDIO */
-	return;
-#endif
-InputClk = 25000000U;
-	/*
-	 * Determine the Baud divider. It can be 4to 254.
-	 * Loop through all possible combinations
-	 */
-	for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
-
-		/*
-		 * Calculate the value for BRGR register
-		 */
-		BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 0x00000001U));
-
-		/*
-		 * Calculate the baud rate from the BRGR value
-		 */
-		CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 0x00000001U));
-
-		/*
-		 * Avoid unsigned integer underflow
-		 */
-		if (BaudRate > CalcBaudRate) {
-			BaudError = BaudRate - CalcBaudRate;
-		} else {
-			BaudError = CalcBaudRate - BaudRate;
-		}
-
-		/*
-		 * Find the calculated baud rate closest to requested baud rate.
-		 */
-		if (Best_Error > BaudError) {
-
-			Best_BRGR = BRGR_Value;
-			Best_BAUDDIV = IterBAUDDIV;
-			Best_Error = BaudError;
-
-		}
-	}
-
-	/*
-	 * Make sure the best error is not too large.
-	 */
-	PercentError = (Best_Error * 100U) / BaudRate;
-	if (MAX_BAUD_ERROR_RATE < PercentError) {
-		return;
-	}
-
-	/* set CD and BDIV */
-	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
-	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
-
-    /*
-     * Veloce specific code
-     */
-    if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
-	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 0x00000002U);
-	    Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 0x00000004U);
-    }
-
-	/*
-	 * 8 data, 1 stop, 0 parity bits
-	 * sel_clk=uart_clk=APB clock
-	 */
-	Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
-
-	/* enable Tx/Rx and reset Tx/Rx data path */
-	Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
-
-	return;
-#endif
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c
deleted file mode 100644
index 0c9f0f78e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) sint32 unlink(char8 *path);
-}
-#endif
-/*
- * unlink -- since we have no file system,
- *           we just return an error.
- */
-__attribute__((weak)) sint32 unlink(char8 *path)
-{
-  (void *)path;
-  errno = EIO;
-  return (-1);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c
deleted file mode 100644
index afc9414bb..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Global Timer register in
-* the ARM Cortex R5 MP core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
-* 5.04  pkp		 02/19/16 usleep routine is modified to use TTC3 if present
-*						  else it will use set of assembly instructions to
-*						  provide the required delay
-* 5.04	pkp		 03/09/16 Assembly routine for usleep is modified to avoid
-*						  disabling the interrupt
-* 5.04	pkp		 03/11/16 Compare the counter value to previously read value
-*						  to detect the overflow for TTC3
-* </pre>
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexr5.h"
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param	useconds requested
-*
-* @return	0 always
-*
-* @note		The usleep API is implemented using TTC3 counter 0 timer if present
-*			When TTC3 is absent, usleep is implemented using assembly
-*			instructions which is tested with instruction and data caches
-*			enabled and it gives proper delay. It may give more delay than
-*			exepcted when caches are disabled. If interrupt comes when usleep
-*			using assembly instruction is being executed, the delay may be
-*			greater than what is expected since once the interrupt is served
-*			count resumes from where it was interrupted unlike the case of TTC3
-*			where counter keeps running while interrupt is being served.
-*
-****************************************************************************/
-
-s32 usleep(u32 useconds)
-{
-
-#ifdef SLEEP_TIMER_BASEADDR
-	u64 tEnd;
-	u64 tCur;
-	u32 TimeHighVal;
-	XTime TimeLowVal1;
-	XTime TimeLowVal2;
-
-	TimeHighVal = 0;
-
-	XTime_GetTime(&TimeLowVal1);
-	tEnd  = (u64)TimeLowVal1 + (((u64) useconds) * COUNTS_PER_USECOND);
-
-	do
-	{
-		XTime_GetTime(&TimeLowVal2);
-	    if (TimeLowVal2 < TimeLowVal1) {
-				TimeHighVal++;
-		}
-		TimeLowVal1 = TimeLowVal2;
-		tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
-	} while (tCur < tEnd);
-
-	return 0;
-#else
-	__asm__ __volatile__ (
-			" push {r0,r1}		\n\t"
-			" mov r0, %[usec]	\n\t"
-			" 1: \n\t"
-			" mov r1, %[iter] 	\n\t"
-			" 2:				\n\t"
-			" subs r1, r1, #0x1 \n\t"
-			" bne   2b    		\n\t"
-			" subs r0,r0,#0x1 	\n\t"
-			"  bne 1b 			\n\t"
-			" pop {r0,r1} 		\n\t"
-			:: [iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds)
-	);
-#endif
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c
deleted file mode 100644
index 73162672f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file vectors.c
-*
-* This file contains the C level vectors for the ARM Cortex R5 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 	pkp  02/20/14 First release
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_exception.h"
-#include "vectors.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-typedef struct {
-	Xil_ExceptionHandler Handler;
-	void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-extern XExc_VectorTableEntry XExc_VectorTable[];
-
-/************************** Function Prototypes ******************************/
-
-
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the FIQ interrupt called from the vectors.s
-* file.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void FIQInterrupt(void)
-{
-	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
-					XIL_EXCEPTION_ID_FIQ_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the IRQ interrupt called from the vectors.s
-* file.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void IRQInterrupt(void)
-{
-	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
-					XIL_EXCEPTION_ID_IRQ_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SW Interrupt called from the vectors.s
-* file.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void SWInterrupt(void)
-{
-	XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
-					XIL_EXCEPTION_ID_SWI_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the DataAbort Interrupt called from the
-* vectors.s file.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void DataAbortInterrupt(void)
-{
-	XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
-		XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the PrefetchAbort Interrupt called from the
-* vectors.s file.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void PrefetchAbortInterrupt(void)
-{
-	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
-		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h
deleted file mode 100644
index ad4d8ece3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex R5 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 	pkp  02/20/14 First release
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef VECTORS_H_
-#define VECTORS_H_
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-void FIQInterrupt(void);
-void IRQInterrupt(void);
-void SWInterrupt(void);
-void DataAbortInterrupt(void);
-void PrefetchAbortInterrupt(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c
deleted file mode 100644
index 4ae96c29f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/* Use toolchain function for openamp applications*/
-
-#ifndef UNDEFINE_FILE_OPS
-
-/* write.c -- write bytes to an output device.
- */
-
-#include "xparameters.h"
-#include "xil_printf.h"
-
-#ifdef __cplusplus
-extern "C" {
-	__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
-}
-#endif
-
-/*
- * write -- write bytes to the serial port. Ignore fd, since
- *          stdout and stderr are the same. Since we have no filesystem,
- *          open will only return an error.
- */
-__attribute__((weak)) s32
-write (s32 fd, char8* buf, s32 nbytes)
-
-{
-#ifdef STDOUT_BASEADDRESS
-  s32 i;
-  char8* LocalBuf = buf;
-
-  (void)fd;
-  for (i = 0; i < nbytes; i++) {
-	if(LocalBuf != NULL) {
-		LocalBuf += i;
-	}
-	if(LocalBuf != NULL) {
-	    if (*LocalBuf == '\n') {
-	      outbyte ('\r');
-	    }
-	    outbyte (*LocalBuf);
-	}
-	if(LocalBuf != NULL) {
-		LocalBuf -= i;
-	}
-  }
-  return (nbytes);
-#else
-  (void)fd;
-  (void)buf;
-  (void)nbytes;
-  return 0;
-#endif
-}
-
-__attribute__((weak)) s32
-_write (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDOUT_BASEADDRESS
-  s32 i;
-  char8* LocalBuf = buf;
-
-  (void)fd;
-  for (i = 0; i < nbytes; i++) {
-	if(LocalBuf != NULL) {
-		LocalBuf += i;
-	}
-	if(LocalBuf != NULL) {
-	    if (*LocalBuf == '\n') {
-	      outbyte ('\r');
-	    }
-	    outbyte (*LocalBuf);
-	}
-	if(LocalBuf != NULL) {
-		LocalBuf -= i;
-	}
-  }
-  return (nbytes);
-#else
-  (void)fd;
-  (void)buf;
-  (void)nbytes;
-  return 0;
-#endif
-}
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h
deleted file mode 100644
index 787212ca7..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note  Dummy File for backwards compatibility
-*
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
-#define XBASIC_TYPES_H	/* by using protection macros */
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
-typedef char		Xint8;		/**< signed 8-bit */
-typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
-typedef short		Xint16;		/**< signed 16-bit */
-typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
-typedef long		Xint32;		/**< signed 32-bit */
-typedef float		Xfloat32;	/**< 32-bit floating point */
-typedef double		Xfloat64;	/**< 64-bit double precision FP */
-typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
-	Xuint32 Upper;
-	Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32         u32;
-typedef Xuint16         u16;
-typedef Xuint8          u8;
-#endif
-#else
-#include <linux/types.h>
-#endif
-
-#ifndef TRUE
-#  define TRUE		1U
-#endif
-
-#ifndef FALSE
-#  define FALSE		0U
-#endif
-
-#ifndef NULL
-#define NULL		0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL		NULL
-#define XTRUE		TRUE
-#define XFALSE		FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning  Please refer the Standalone BSP UG647 for further details
-
-
-#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h
deleted file mode 100644
index 650946bd0..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef XDEBUG  /* prevent circular inclusions */
-#define XDEBUG  /* by using protection macros */
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
-#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
-#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL)
-
-#define xdbg_stmnt(x)  x
-
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-#define xdbg_printf(...)
-
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#endif /* XDEBUG */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h
deleted file mode 100644
index 3d97bebd4..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch   10/24/02 Added XENV_LINUX
-* 1.00a rmm  04/17/02 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param   DestPtr is the destination address to copy data to.
- * @param   SrcPtr is the source address to copy data from.
- * @param   Bytes is the number of bytes to copy.
- *
- * @return  None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param   DestPtr is the destination address to set.
- * @param   Data contains the value to set.
- * @param   Bytes is the number of bytes to set.
- *
- * @return  None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param   StampPtr is the storage for the retrieved time stamp.
- *
- * @return  None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param   Stamp1Ptr - First sampled time stamp.
- * @param   Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return  An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param   Stamp1Ptr - First sampled time stamp.
- * @param   Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return  An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param   delay is the number of microseconds to delay.
- *
- * @return  None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif            /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h
deleted file mode 100644
index f18601874..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* 	This file is not intended to be included directly by driver code.
-* 	Instead, the generic xenv.h file is intended to be included by driver
-* 	code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr  02/28/07 Added cache handling macros.
-* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-*                     used under Xilinx standalone BSP.
-* 1.00a xd   11/03/04 Improved support for doxygen.
-* 1.00a rmm  03/21/02 First release
-* 1.00a wgr  03/22/07 Converted to new coding style.
-* 1.00a rpm  06/29/07 Added udelay macro for standalone
-* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
-*                     to in MICROBLAZE section
-* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include <string.h>
-
-#if defined __MICROBLAZE__
-#  include "mb_interface.h"
-#  include "xparameters.h"   /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-#  include "sleep.h"
-#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param	DestPtr
- *		Destination address to copy data to.
- *
- * @param	SrcPtr
- * 		Source address to copy data from.
- *
- * @param	Bytes
- * 		Number of bytes to copy.
- *
- * @return	None.
- *
- * @note
- * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * 		This implemention MAY BREAK work if source and target memory
- * 		area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
-	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param	DestPtr
- *		Destination address to copy data to.
- *
- * @param	Data
- * 		Value to set.
- *
- * @param	Bytes
- * 		Number of bytes to copy.
- *
- * @return	None.
- *
- * @note
- * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
-	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param   StampPtr is the storage for the retrieved time stamp.
- *
- * @return  None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- * <br><br>
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param   Stamp1Ptr is the first sampled time stamp.
- * @param   Stamp2Ptr is the second sampled time stamp.
- *
- * @return  0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param   Stamp1Ptr is the first sampled time stamp.
- * @param   Stamp2Ptr is the second sampled time stamp.
- *
- * @return  0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param	delay
- * 		Number of microseconds to delay.
- *
- * @return	None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay)	usleep(delay)
-#define udelay(delay)	usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE()	\
-		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE()	\
-		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
-#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
-#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
-
-#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
-			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
-#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
-			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
-#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
-			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-#  define XCACHE_ENABLE_DCACHE()
-#  define XCACHE_DISABLE_DCACHE()
-#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
-#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
-
-#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
-
-#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
-			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-#  define XCACHE_ENABLE_ICACHE()
-#  define XCACHE_DISABLE_ICACHE()
-#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- *   specific memory region (0x80000001). Each bit (0-30) in the regions
- *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- *   range.
- *
- *   regions    --> cached address range
- *   ------------|--------------------------------------------------
- *   0x80000000  | [0, 0x7FFFFFF]
- *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
- *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
-		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
-		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S
deleted file mode 100644
index cca2f0d69..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 	pkp  02/10/14 First release
-* 5.04  pkp  12/18/15 Initialized global constructor for C++ applications
-* 5.04  pkp  02/19/16 Added timer configuration using XTime_StartTimer API when
-*		      TTC3 is present
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xparameters.h"
-	.file	"xil-crt0.S"
-	.section ".got2","aw"
-	.align	2
-
-	.text
-.Lsbss_start:
-	.long	__sbss_start
-
-.Lsbss_end:
-	.long	__sbss_end
-
-.Lbss_start:
-	.long	__bss_start__
-
-.Lbss_end:
-	.long	__bss_end__
-
-.Lstack:
-	.long	__stack
-
-
-	.globl	_startup
-
-_startup:
-	bl      __cpu_init		/* Initialize the CPU first (BSP provides this) */
-
-	mov	r0, #0
-
-	/* clear sbss */
-	ldr 	r1,.Lsbss_start		/* calculate beginning of the SBSS */
-	ldr	r2,.Lsbss_end		/* calculate end of the SBSS */
-
-.Lloop_sbss:
-	cmp	r1,r2
-	bge	.Lenclsbss		/* If no SBSS, no clearing required */
-	str	r0, [r1], #4
-	b	.Lloop_sbss
-
-.Lenclsbss:
-	/* clear bss */
-	ldr	r1,.Lbss_start		/* calculate beginning of the BSS */
-	ldr	r2,.Lbss_end		/* calculate end of the BSS */
-
-.Lloop_bss:
-	cmp	r1,r2
-	bge	.Lenclbss		/* If no BSS, no clearing required */
-	str	r0, [r1], #4
-	b	.Lloop_bss
-
-.Lenclbss:
-
-	/* set stack pointer */
-	ldr	r13,.Lstack		/* stack address */
-
-	/* configure the timer if TTC3 is present */
-#ifdef SLEEP_TIMER_BASEADDR
-	bl XTime_StartTimer
-#endif
-
-	/* run global constructors */
-	bl __libc_init_array
-
-	/* make sure argc and argv are valid */
-	mov	r0, #0
-	mov	r1, #0
-
-	bl	main			/* Jump to main C code */
-
-	/* Cleanup global constructors */
-	bl __libc_fini_array
-
-	bl	exit
-
-.Lexit:	/* should never get here */
-	b .Lexit
-
-.Lstart:
-	.size	_startup,.Lstart-_startup
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c
deleted file mode 100644
index 42db07deb..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.c
-*
-* This file contains basic assert related functions for Xilinx software IP.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/14/09 Initial release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-u32 Xil_AssertStatus;
-
-/**
- * This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-/*s32 Xil_AssertWait = 1*/
-
-/* The callback function to be invoked when an assert is taken */
-static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Implement assert. Currently, it calls a user-defined callback function
-* if one has been set.  Then, it potentially enters an infinite loop depending
-* on the value of the Xil_AssertWait variable.
-*
-* @param    file is the name of the filename of the source
-* @param    line is the linenumber within File
-*
-* @return   None.
-*
-* @note     None.
-*
-******************************************************************************/
-void Xil_Assert(const char8 *File, s32 Line)
-{
-	s32 Xil_AssertWait = 1;
-	/* if the callback has been set then invoke it */
-	if (Xil_AssertCallbackRoutine != 0) {
-		(*Xil_AssertCallbackRoutine)(File, Line);
-	}
-
-	/* if specified, wait indefinitely such that the assert will show up
-	 * in testing
-	 */
-	while (Xil_AssertWait != 0) {
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* Set up a callback function to be invoked when an assert occurs. If there
-* was already a callback installed, then it is replaced.
-*
-* @param    routine is the callback to be invoked when an assert is taken
-*
-* @return   None.
-*
-* @note     This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void Xil_AssertSetCallback(Xil_AssertCallback Routine)
-{
-	Xil_AssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* Null handler function. This follows the XInterruptHandler signature for
-* interrupt handlers. It can be used to assign a null handler (a stub) to an
-* interrupt controller vector table.
-*
-* @param    NullParameter is an arbitrary void pointer and not used.
-*
-* @return   None.
-*
-* @note     None.
-*
-******************************************************************************/
-void XNullHandler(void *NullParameter)
-{
- (void *) NullParameter;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h
deleted file mode 100644
index 7034bc9ad..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* This file contains assert related functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/14/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
-#define XIL_ASSERT_H	/* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE     0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern void Xil_Assert(const char8 *File, s32 Line);
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the Xil_AssertWait boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
-*
-* @param    Expression is the expression to evaluate. If it evaluates to
-*           false, the assert occurs.
-*
-* @return   Returns void unless the Xil_AssertWait variable is true, in which
-*           case no return is made and an infinite loop is entered.
-*
-* @note     None.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression)                \
-{                                                  \
-    if (Expression) {                              \
-        Xil_AssertStatus = XIL_ASSERT_NONE;       \
-    } else {                                       \
-        Xil_Assert(__FILE__, __LINE__);            \
-        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
-        return;                                    \
-    }                                              \
-}
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
-* so that asserts which fail allow execution to continue.
-*
-* @param    Expression is the expression to evaluate. If it evaluates to false,
-*           the assert occurs.
-*
-* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
-* 	    case no return is made and an infinite loop is entered.
-*
-* @note     None.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression)             \
-{                                                  \
-    if (Expression) {                              \
-        Xil_AssertStatus = XIL_ASSERT_NONE;       \
-    } else {                                       \
-        Xil_Assert(__FILE__, __LINE__);            \
-        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
-        return 0;                                  \
-    }                                              \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-*	  case no return is made and an infinite loop is entered.
-*
-* @note   None.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways()                   \
-{                                                  \
-   Xil_Assert(__FILE__, __LINE__);                 \
-   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
-   return;                                         \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-*	  case no return is made and an infinite loop is entered.
-*
-* @note   None.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways()                \
-{                                                  \
-   Xil_Assert(__FILE__, __LINE__);                 \
-   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
-   return 0;                                       \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c
deleted file mode 100644
index 2ba080dff..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c
+++ /dev/null
@@ -1,580 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* Contains required functions for the ARM cache functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver    Who Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 	pkp  02/20/14 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexr5.h"
-#include "xil_exception.h"
-
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
-
-
-extern s32  _stack_end;
-extern s32  __undef_stack;
-
-/****************************************************************************/
-/************************** Function Prototypes ******************************/
-
-/****************************************************************************
-*
-* Enable the Data cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
-	register u32 CtrlReg;
-
-	/* enable caches only if they are disabled */
-	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-
-	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
-		/* invalidate the Data cache */
-		Xil_DCacheInvalidate();
-
-		/* enable the Data cache */
-		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
-		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	}
-}
-
-/****************************************************************************
-*
-* Disable the Data cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
-	register u32 CtrlReg;
-
-	/* clean and invalidate the Data cache */
-	Xil_DCacheFlush();
-
-	/* disable the Data cache */
-	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-
-	CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
-	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************
-*
-* Invalidate the entire Data cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
-	u32 currmask;
-	u32 stack_start,stack_end,stack_size;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-
-	stack_end = (u32 )&_stack_end;
-	stack_start = (u32 )&__undef_stack;
-	stack_size = stack_start-stack_end;
-
-	/* Flush stack memory to save return address */
-	Xil_DCacheFlushRange(stack_end, stack_size);
-
-	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-	/*invalidate all D cache*/
-	mtcp(XREG_CP15_INVAL_DC_ALL, 0);
-
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-*
-* Invalidate a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated.	If the cacheline is modified (dirty), the modified contents
-* are lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param	Address to be flushed.
-*
-* @return	None.
-*
-* @note		The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(INTPTR adr)
-{
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
-		/* Wait for invalidate to complete */
-	dsb();
-
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-*
-* Invalidate the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the Data cache,
-* the cacheline containing that byte is invalidated.	If the cacheline
-* is modified (dirty), the modified contents are lost and are NOT
-* written to system memory before the line is invalidated.
-*
-* @param	Start address of range to be invalidated.
-* @param	Length of range to be invalidated in bytes.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
-	const u32 cacheline = 32U;
-	u32 end;
-	u32 tempadr = adr;
-	u32 tempend;
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	if (len != 0U) {
-		end = tempadr + len;
-		tempend = end;
-		/* Select L1 Data cache in CSSR */
-		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
-		if ((tempadr & (cacheline-1U)) != 0U) {
-			tempadr &= (~(cacheline - 1U));
-
-			Xil_DCacheFlushLine(tempadr);
-		}
-		if ((tempend & (cacheline-1U)) != 0U) {
-			tempend &= (~(cacheline - 1U));
-
-			Xil_DCacheFlushLine(tempend);
-		}
-
-		while (tempadr < tempend) {
-
-		/* Invalidate Data cache line */
-		asm_inval_dc_line_mva_poc(tempadr);
-
-		tempadr += cacheline;
-		}
-	}
-
-	dsb();
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-*
-* Flush the entire Data cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
-	register u32 CsidReg, C7Reg;
-	u32 CacheSize, LineSize, NumWays;
-	u32 Way, WayIndex, Set, SetIndex, NumSet;
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	/* Select cache level 0 and D cache in CSSR */
-	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-
-	/* Determine Cache Size */
-
-	CacheSize = (CsidReg >> 13U) & 0x000001FFU;
-	CacheSize += 0x00000001U;
-	CacheSize *= (u32)128;    /* to get number of bytes */
-
-	/* Number of Ways */
-	NumWays = (CsidReg & 0x000003ffU) >> 3U;
-	NumWays += 0x00000001U;
-
-	/* Get the cacheline size, way size, index size from csidr */
-	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
-	NumSet = CacheSize/NumWays;
-	NumSet /= (0x00000001U << LineSize);
-
-	Way = 0U;
-	Set = 0U;
-
-	/* Invalidate all the cachelines */
-	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
-		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
-			C7Reg = Way | Set;
-			/* Flush by Set/Way */
-			asm_clean_inval_dc_line_sw(C7Reg);
-
-			Set += (0x00000001U << LineSize);
-		}
-		Set = 0U;
-		Way += 0x40000000U;
-	}
-
-	/* Wait for flush to complete */
-	dsb();
-	mtcpsr(currmask);
-
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-*
-* Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated.	If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param	Address to be flushed.
-*
-* @return	None.
-*
-* @note		The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(INTPTR adr)
-{
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
-		/* Wait for flush to complete */
-	dsb();
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-* Flush the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the Data cache,
-* the cacheline containing that byte is invalidated.	If the cacheline
-* is modified (dirty), the written to system memory first before the
-* before the line is invalidated.
-*
-* @param	Start address of range to be flushed.
-* @param	Length of range to be flushed in bytes.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
-	u32 LocalAddr = adr;
-	const u32 cacheline = 32U;
-	u32 end;
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	if (len != 0x00000000U) {
-		/* Back the starting address up to the start of a cache line
-		 * perform cache operations until adr+len
-		 */
-		end = LocalAddr + len;
-		LocalAddr &= ~(cacheline - 1U);
-
-		while (LocalAddr < end) {
-			/* Flush Data cache line */
-			asm_clean_inval_dc_line_mva_poc(LocalAddr);
-
-			LocalAddr += cacheline;
-		}
-	}
-	dsb();
-	mtcpsr(currmask);
-}
-/****************************************************************************
-*
-* Store a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache and the cacheline is modified (dirty),
-* the entire contents of the cacheline are written to system memory.
-* After the store completes, the cacheline is marked as unmodified
-* (not dirty).
-*
-* @param	Address to be stored.
-*
-* @return	None.
-*
-* @note		The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(INTPTR adr)
-{
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-	mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
-	/* Wait for store to complete */
-	dsb();
-	isb();
-
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-*
-* Enable the instruction cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
-	register u32 CtrlReg;
-
-	/* enable caches only if they are disabled */
-
-	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-
-	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
-		/* invalidate the instruction cache */
-		mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
-		/* enable the instruction cache */
-		CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
-		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	}
-}
-
-/****************************************************************************
-*
-* Disable the instruction cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
-	register u32 CtrlReg;
-
-	dsb();
-
-	/* invalidate the instruction cache */
-	mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
-		/* disable the instruction cache */
-
-	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-
-	CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
-	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************
-*
-* Invalidate the entire instruction cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
-
-	/* invalidate the instruction cache */
-	mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
-	/* Wait for invalidate to complete */
-	dsb();
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-*
-* Invalidate an instruction cache line.	If the instruction specified by the
-* parameter adr is cached by the instruction cache, the cacheline containing
-* that instruction is invalidated.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(INTPTR adr)
-{
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-
-	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
-	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
-
-		/* Wait for invalidate to complete */
-	dsb();
-	mtcpsr(currmask);
-}
-
-/****************************************************************************
-*
-* Invalidate the instruction cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the Data cache,
-* the cacheline containing that byte is invalidated. If the cacheline
-* is modified (dirty), the modified contents are lost and are NOT
-* written to system memory before the line is invalidated.
-*
-* @param	Start address of range to be invalidated.
-* @param	Length of range to be invalidated in bytes.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
-	u32 LocalAddr = adr;
-	const u32 cacheline = 32U;
-	u32 end;
-	u32 currmask;
-
-	currmask = mfcpsr();
-	mtcpsr(currmask | IRQ_FIQ_MASK);
-	if (len != 0x00000000U) {
-		/* Back the starting address up to the start of a cache line
-		 * perform cache operations until adr+len
-		 */
-		end = LocalAddr + len;
-		LocalAddr = LocalAddr & ~(cacheline - 1U);
-
-		/* Select cache L0 I-cache in CSSR */
-		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
-		while (LocalAddr < end) {
-
-			/* Invalidate L1 I-cache line */
-			asm_inval_ic_line_mva_pou(LocalAddr);
-
-			LocalAddr += cacheline;
-		}
-	}
-
-	/* Wait for invalidate to complete */
-	dsb();
-	mtcpsr(currmask);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h
deleted file mode 100644
index 581db3f16..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* Contains required functions for the ARM cache functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 	pkp  02/20/14 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
-		XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
-
-#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
-		XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
-
-#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
-		XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
-
-#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
-		XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-void Xil_DCacheInvalidateLine(INTPTR adr);
-void Xil_DCacheFlushLine(INTPTR adr);
-void Xil_DCacheStoreLine(INTPTR adr);
-
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_ICacheInvalidateLine(INTPTR adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
deleted file mode 100644
index 6e8cfa75f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date	 Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  12/11/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
-		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
-		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
-		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c
deleted file mode 100644
index f41976eec..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xil_exception.c
-*
-* This file contains low-level driver functions for the Cortex R5 exception
-* Handler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
-*
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xpseudo_asm.h"
-#include "xdebug.h"
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef struct {
-	Xil_ExceptionHandler Handler;
-	void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-static void Xil_ExceptionNullHandler(void *Data);
-/************************** Variable Definitions *****************************/
-/*
- * Exception vector table to store handlers for each exception vector.
- */
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
-	{Xil_ExceptionNullHandler, NULL},
-	{Xil_ExceptionNullHandler, NULL},
-	{Xil_ExceptionNullHandler, NULL},
-	{Xil_PrefetchAbortHandler, NULL},
-	{Xil_DataAbortHandler, NULL},
-	{Xil_ExceptionNullHandler, NULL},
-	{Xil_ExceptionNullHandler, NULL},
-};
-
-/*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* This function is a stub Handler that is the default Handler that gets called
-* if the application has not setup a Handler for a specific  exception. The
-* function interface has to match the interface specified for a Handler even
-* though none of the arguments are used.
-*
-* @param	Data is unused by this function.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
-	(void *)Data;
-DieLoop: goto DieLoop;
-}
-
-/****************************************************************************/
-/**
-* The function is a common API used to initialize exception handlers across all
-* processors supported. For ARM CortexR5, the exception handlers are being
-* initialized statically and hence this function does not do anything.
-*
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
-	return;
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Id of the exception source and the
-* associated Handler that is to run when the exception is recognized. The
-* argument provided in this call as the Data is used as the argument
-* for the Handler when it is called.
-*
-* @param	exception_id contains the ID of the exception source and should
-*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-		See xil_exception_l.h for further information.
-* @param	Handler to the Handler for that exception.
-* @param	Data is a reference to Data that will be passed to the
-*		Handler when it gets called.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Exception_id,
-				    Xil_ExceptionHandler Handler,
-				    void *Data)
-{
-	XExc_VectorTable[Exception_id].Handler = Handler;
-	XExc_VectorTable[Exception_id].Data = Data;
-}
-
-/*****************************************************************************/
-/**
-*
-* Removes the Handler for a specific exception Id. The stub Handler is then
-* registered for this exception Id.
-*
-* @param	exception_id contains the ID of the exception source and should
-*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-*		See xil_exception_l.h for further information.
-
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Exception_id)
-{
-	Xil_ExceptionRegisterHandler(Exception_id,
-				       Xil_ExceptionNullHandler,
-				       NULL);
-}
-/*****************************************************************************/
-/**
-*
-* Default Data abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @param	None
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-
-void Xil_DataAbortHandler(void *CallBackRef){
-
-	xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
-	while(1) {
-		;
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* Default Prefetch abort handler which printsa debug message on console if
-* Debug flag is enabled
-*
-* @param	None
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void Xil_PrefetchAbortHandler(void *CallBackRef){
-
-	xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
-	while(1) {
-		;
-	}
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h
deleted file mode 100644
index 9d903175c..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  02/20/14 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST			0U
-#define XIL_EXCEPTION_ID_RESET			0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
-#define XIL_EXCEPTION_ID_SWI_INT		2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
-#define XIL_EXCEPTION_ID_IRQ_INT		5U
-#define XIL_EXCEPTION_ID_FIQ_INT		6U
-#define XIL_EXCEPTION_ID_LAST			6U
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Enable Exceptions.
-*
-* @param	Mask for exceptions to be enabled.
-*
-* @return	None.
-*
-* @note		If bit is 0, exception is enabled.
-*		C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#define Xil_ExceptionEnableMask(Mask)	\
-		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-
-
-/****************************************************************************/
-/**
-* Enable the IRQ exception.
-*
-* @return   None.
-*
-* @note     None.
-*
-******************************************************************************/
-#define Xil_ExceptionEnable() \
-		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-
-/****************************************************************************/
-/**
-* Disable Exceptions.
-*
-* @param	Mask for exceptions to be enabled.
-*
-* @return	None.
-*
-* @note		If bit is 1, exception is disabled.
-*		C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#define Xil_ExceptionDisableMask(Mask)	\
-		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return   None.
-*
-* @note     None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
-		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-/****************************************************************************/
-/**
-* Enable nested interrupts by clearing the I and F bits it CPSR
-*
-* @return   None.
-*
-* @note     This macro is supposed to be used from interrupt handlers. In the
-*			interrupt handler the interrupts are disabled by default (I and F
-*			are 1). To allow nesting of interrupts, this macro should be
-*			used. It clears the I and F bits by changing the ARM mode to
-*			system mode. Once these bits are cleared and provided the
-*			preemption of interrupt conditions are met in the GIC, nesting of
-*			interrupts will start happening.
-*			Caution: This macro must be used with caution. Before calling this
-*			macro, the user must ensure that the source of the current IRQ
-*			is appropriately cleared. Otherwise, as soon as we clear the I and
-*			F bits, there can be an infinite loop of interrupts with an
-*			eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
-		__asm__ __volatile__ ("mrs     lr, spsr");  \
-		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
-		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
-		__asm__ __volatile__ ("stmfd   sp!, {lr}");
-
-/****************************************************************************/
-/**
-* Disable the nested interrupts by setting the I and F bits.
-*
-* @return   None.
-*
-* @note     This macro is meant to be called in the interrupt service routines.
-*			This macro cannot be used independently. It can only be used when
-*			nesting of interrupts have been enabled by using the macro
-*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
-*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-*			point. The user then must call this macro before exiting the interrupt
-*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
-*			hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
-		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
-		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
-		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
-		__asm__ __volatile__ ("msr     spsr_cxsf, lr");
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
-					 Xil_ExceptionHandler Handler,
-					 void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-
-extern void Xil_ExceptionInit(void);
-
-extern void Xil_DataAbortHandler(void *CallBackRef);
-
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h
deleted file mode 100644
index d4434d07f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date	 Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/28/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c
deleted file mode 100644
index 90fd22559..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.c
-*
-* Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures.  These functions encapsulate Cortex R5 architecture-specific
-* I/O requirements.
-*
-* @note
-*
-* This file contains architecture-dependent code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
-* </pre>
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexr5.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for an 8-bit memory location by reading from the
-* specified address and returning the Value read from that address.
-*
-* @param	Addr contains the address to perform the input operation
-*		at.
-*
-* @return	The Value read from the specified input address.
-*
-* @note		None.
-*
-******************************************************************************/
-u8 Xil_In8(INTPTR Addr)
-{
-	return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the Value read from that address.
-*
-* @param	Addr contains the address to perform the input operation
-*		at.
-*
-* @return	The Value read from the specified input address.
-*
-* @note		None.
-*
-******************************************************************************/
-u16 Xil_In16(INTPTR Addr)
-{
-	return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the Value read from that address.
-*
-* @param	Addr contains the address to perform the input operation
-*		at.
-*
-* @return	The Value read from the specified input address.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 Xil_In32(INTPTR Addr)
-{
-	return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for an 8-bit memory location by writing the
-* specified Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out8(INTPTR Addr, u8 Value)
-{
-	volatile u8 *LocalAddr = (u8 *)Addr;
-	*LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 16-bit memory location by writing the
-* specified Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out16(INTPTR Addr, u16 Value)
-{
-	volatile u16 *LocalAddr = (u16 *)Addr;
-	*LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 32-bit memory location by writing the
-* specified Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out32(INTPTR Addr, u32 Value)
-{
-	volatile u32 *LocalAddr = (u32 *)Addr;
-	*LocalAddr = Value;
-}
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 64-bit memory location by writing the
-* specified Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out64(INTPTR Addr, u64 Value)
-{
-	volatile u64 *LocalAddr = (u64 *)Addr;
-	*LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 64-bit memory location by reading the
-* specified Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-u64 Xil_In64(INTPTR Addr)
-{
-	return *(volatile u64 *) Addr;
-}
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param	Addr contains the address to perform the input operation
-*		at.
-*
-* @return	The byte-swapped Value read from the specified input address.
-*
-* @note		None.
-*
-******************************************************************************/
-u16 Xil_In16BE(INTPTR Addr)
-{
-	u16 temp;
-	u16 result;
-
-	temp = Xil_In16(Addr);
-
-	result = Xil_EndianSwap16(temp);
-
-	return result;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param	Addr contains the address to perform the input operation
-*		at.
-*
-* @return	The byte-swapped Value read from the specified input address.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 Xil_In32BE(INTPTR Addr)
-{
-	u32 temp;
-	u32 result;
-
-	temp = Xil_In32(Addr);
-
-	result = Xil_EndianSwap32(temp);
-
-	return result;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 16-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param	OutAddress contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out16BE(INTPTR Addr, u16 Value)
-{
-	u16 temp;
-
-	temp = Xil_EndianSwap16(Value);
-
-    Xil_Out16(Addr, temp);
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 32-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param	OutAddress contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out32BE(INTPTR Addr, u32 Value)
-{
-	u32 temp;
-
-	temp = Xil_EndianSwap32(Value);
-
-    Xil_Out32(Addr, temp);
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a 16-bit endian converion.
-*
-* @param	Data contains the value to be converted.
-*
-* @return	converted value.
-*
-* @note		None.
-*
-******************************************************************************/
-u16 Xil_EndianSwap16(u16 Data)
-{
-	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a 32-bit endian converion.
-*
-* @param	Data contains the value to be converted.
-*
-* @return	converted value.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 Xil_EndianSwap32(u32 Data)
-{
-	u16 LoWord;
-	u16 HiWord;
-
-	/* get each of the half words from the 32 bit word */
-
-	LoWord = (u16) (Data & 0x0000FFFFU);
-	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
-	/* byte swap each of the 16 bit half words */
-
-	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
-	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
-	/* swap the half words before returning the value */
-
-	return ((((u32)LoWord) << 16U) | (u32)HiWord);
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h
deleted file mode 100644
index 18cdebf7a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* This file contains the interface for the general IO component, which
-* encapsulates the Input/Output functions for processors that do not
-* require any special I/O handling.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
-* </pre>
-******************************************************************************/
-
-#ifndef XIL_IO_H           /* prevent circular inclusions */
-#define XIL_IO_H           /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xil_printf.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#if defined __GNUC__
-#  define SYNCHRONIZE_IO	dmb()
-#  define INST_SYNC		isb()
-#  define DATA_SYNC		dsb()
-#else
-#  define SYNCHRONIZE_IO
-#  define INST_SYNC
-#  define DATA_SYNC
-#endif /* __GNUC__ */
-
-/*****************************************************************************/
-/**
-*
-* Perform an big-endian input operation for a 16-bit memory location
-* by reading from the specified address and returning the Value read from
-* that address.
-*
-* @param	Addr contains the address to perform the input operation at.
-*
-* @return	The Value read from the specified input address with the
-*		proper endianness. The return Value has the same endianness
-*		as that of the processor, i.e. if the processor is
-*		little-engian, the return Value is the byte-swapped Value read
-*		from the address.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_In16LE(Addr) Xil_In16((Addr))
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian input operation for a 32-bit memory location
-* by reading from the specified address and returning the Value read from
-* that address.
-*
-* @param	Addr contains the address to perform the input operation at.
-*
-* @return	The Value read from the specified input address with the
-*		proper endianness. The return Value has the same endianness
-*		as that of the processor, i.e. if the processor is
-*		little-engian, the return Value is the byte-swapped Value read
-*		from the address.
-*
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_In32LE(Addr) Xil_In32((Addr))
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian output operation for a 16-bit memory location
-* by writing the specified Value to the specified address.
-*
-* @param	Addr contains the address to perform the output operation at.
-* @param	Value contains the Value to be output at the specified address.
-*		The Value has the same endianness as that of the processor.
-*		If the processor is little-endian, the byte-swapped Value is
-*		written to the address.
-*
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian output operation for a 32-bit memory location
-* by writing the specified Value to the specified address.
-*
-* @param	Addr contains the address to perform the output operation at.
-* @param	Value contains the Value to be output at the specified address.
-*		The Value has the same endianness as that of the processor.
-*		If the processor is little-endian, the byte-swapped Value is
-*		written to the address.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 32-bit number from host byte order to network byte order.
-*
-* @param	Data the 32-bit number to be converted.
-*
-* @return	The converted 32-bit number in network byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 16-bit number from host byte order to network byte order.
-*
-* @param	Data the 16-bit number to be converted.
-*
-* @return	The converted 16-bit number in network byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Htons(Data) Xil_EndianSwap16((Data))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 32-bit number from network byte order to host byte order.
-*
-* @param	Data the 32-bit number to be converted.
-*
-* @return	The converted 32-bit number in host byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 16-bit number from network byte order to host byte order.
-*
-* @param	Data the 16-bit number to be converted.
-*
-* @return	The converted 16-bit number in host byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
-
-/************************** Function Prototypes ******************************/
-
-/* The following functions allow the software to be transportable across
- * processors which may use memory mapped I/O or I/O which is mapped into a
- * seperate address space.
- */
-u8 Xil_In8(INTPTR Addr);
-u16 Xil_In16(INTPTR Addr);
-u32 Xil_In32(INTPTR Addr);
-u64 Xil_In64(INTPTR Addr);
-
-void Xil_Out8(INTPTR Addr, u8 Value);
-void Xil_Out16(INTPTR Addr, u16 Value);
-void Xil_Out32(INTPTR Addr, u32 Value);
-void Xil_Out64(INTPTR Addr, u64 Value);
-
-u16 Xil_In16BE(INTPTR Addr);
-u32 Xil_In32BE(INTPTR Addr);
-void Xil_Out16BE(INTPTR Addr, u16 Value);
-void Xil_Out32BE(INTPTR Addr, u32 Value);
-
-u16 Xil_EndianSwap16(u16 Data);
-u32 Xil_EndianSwap32(u32 Data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h
deleted file mode 100644
index ebafde87d..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h
+++ /dev/null
@@ -1,1052 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*********************************************************************/
-/**
- * @file xil_macroback.h
- *
- * This header file is meant to bring back the removed _m macros.
- * This header file must be included last.
- * The following macros are not defined here due to the driver change:
- *   XGpio_mSetDataDirection
- *   XGpio_mGetDataReg
- *   XGpio_mSetDataReg
- *   XIIC_RESET
- *   XIIC_CLEAR_STATS
- *   XSpi_mReset
- *   XSysAce_mSetCfgAddr
- *   XSysAce_mIsCfgDone
- *   XTft_mSetPixel
- *   XTft_mGetPixel
- *   XWdtTb_mEnableWdt
- *   XWdtTb_mDisbleWdt
- *   XWdtTb_mRestartWdt
- *   XWdtTb_mGetTimebaseReg
- *   XWdtTb_mHasReset
- *
- * Please refer the corresonding driver document for replacement.
- *
- *********************************************************************/
-
-#ifndef XIL_MACROBACK_H
-#define XIL_MACROBACK_H
-
-/*********************************************************************/
-/**
- * Macros for Driver XCan
- *
- *********************************************************************/
-#ifndef XCan_mReadReg
-#define XCan_mReadReg XCan_ReadReg
-#endif
-
-#ifndef XCan_mWriteReg
-#define XCan_mWriteReg XCan_WriteReg
-#endif
-
-#ifndef XCan_mIsTxDone
-#define XCan_mIsTxDone XCan_IsTxDone
-#endif
-
-#ifndef XCan_mIsTxFifoFull
-#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
-#endif
-
-#ifndef XCan_mIsHighPriorityBufFull
-#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
-#endif
-
-#ifndef XCan_mIsRxEmpty
-#define XCan_mIsRxEmpty XCan_IsRxEmpty
-#endif
-
-#ifndef XCan_mIsAcceptFilterBusy
-#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
-#endif
-
-#ifndef XCan_mCreateIdValue
-#define XCan_mCreateIdValue XCan_CreateIdValue
-#endif
-
-#ifndef XCan_mCreateDlcValue
-#define XCan_mCreateDlcValue XCan_CreateDlcValue
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDmaCentral
- *
- *********************************************************************/
-#ifndef XDmaCentral_mWriteReg
-#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
-#endif
-
-#ifndef XDmaCentral_mReadReg
-#define XDmaCentral_mReadReg XDmaCentral_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsAdc
- *
- *********************************************************************/
-#ifndef XDsAdc_mWriteReg
-#define XDsAdc_mWriteReg XDsAdc_WriteReg
-#endif
-
-#ifndef XDsAdc_mReadReg
-#define XDsAdc_mReadReg XDsAdc_ReadReg
-#endif
-
-#ifndef XDsAdc_mIsEmpty
-#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
-#endif
-
-#ifndef XDsAdc_mSetFstmReg
-#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
-#endif
-
-#ifndef XDsAdc_mGetFstmReg
-#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
-#endif
-
-#ifndef XDsAdc_mEnableConversion
-#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
-#endif
-
-#ifndef XDsAdc_mDisableConversion
-#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
-#endif
-
-#ifndef XDsAdc_mGetFifoOccyReg
-#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsDac
- *
- *********************************************************************/
-#ifndef XDsDac_mWriteReg
-#define XDsDac_mWriteReg XDsDac_WriteReg
-#endif
-
-#ifndef XDsDac_mReadReg
-#define XDsDac_mReadReg XDsDac_ReadReg
-#endif
-
-#ifndef XDsDac_mIsEmpty
-#define XDsDac_mIsEmpty XDsDac_IsEmpty
-#endif
-
-#ifndef XDsDac_mFifoIsFull
-#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
-#endif
-
-#ifndef XDsDac_mGetVacancy
-#define XDsDac_mGetVacancy XDsDac_GetVacancy
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XEmacLite
- *
- *********************************************************************/
-#ifndef XEmacLite_mReadReg
-#define XEmacLite_mReadReg XEmacLite_ReadReg
-#endif
-
-#ifndef XEmacLite_mWriteReg
-#define XEmacLite_mWriteReg XEmacLite_WriteReg
-#endif
-
-#ifndef XEmacLite_mGetTxStatus
-#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
-#endif
-
-#ifndef XEmacLite_mSetTxStatus
-#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
-#endif
-
-#ifndef XEmacLite_mGetRxStatus
-#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
-#endif
-
-#ifndef XEmacLite_mSetRxStatus
-#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
-#endif
-
-#ifndef XEmacLite_mIsTxDone
-#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
-#endif
-
-#ifndef XEmacLite_mIsRxEmpty
-#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
-#endif
-
-#ifndef XEmacLite_mNextTransmitAddr
-#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
-#endif
-
-#ifndef XEmacLite_mNextReceiveAddr
-#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
-#endif
-
-#ifndef XEmacLite_mIsMdioConfigured
-#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
-#endif
-
-#ifndef XEmacLite_mIsLoopbackConfigured
-#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
-#endif
-
-#ifndef XEmacLite_mGetReceiveDataLength
-#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
-#endif
-
-#ifndef XEmacLite_mGetTxActive
-#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
-#endif
-
-#ifndef XEmacLite_mSetTxActive
-#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XGpio
- *
- *********************************************************************/
-#ifndef XGpio_mWriteReg
-#define XGpio_mWriteReg XGpio_WriteReg
-#endif
-
-#ifndef XGpio_mReadReg
-#define XGpio_mReadReg XGpio_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XHwIcap
- *
- *********************************************************************/
-#ifndef XHwIcap_mFifoWrite
-#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
-#endif
-
-#ifndef XHwIcap_mFifoRead
-#define XHwIcap_mFifoRead XHwIcap_FifoRead
-#endif
-
-#ifndef XHwIcap_mSetSizeReg
-#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
-#endif
-
-#ifndef XHwIcap_mGetControlReg
-#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
-#endif
-
-#ifndef XHwIcap_mStartConfig
-#define XHwIcap_mStartConfig XHwIcap_StartConfig
-#endif
-
-#ifndef XHwIcap_mStartReadBack
-#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
-#endif
-
-#ifndef XHwIcap_mGetStatusReg
-#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
-#endif
-
-#ifndef XHwIcap_mIsTransferDone
-#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
-#endif
-
-#ifndef XHwIcap_mIsDeviceBusy
-#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
-#endif
-
-#ifndef XHwIcap_mIntrGlobalEnable
-#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
-#endif
-
-#ifndef XHwIcap_mIntrGlobalDisable
-#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
-#endif
-
-#ifndef XHwIcap_mIntrGetStatus
-#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
-#endif
-
-#ifndef XHwIcap_mIntrDisable
-#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
-#endif
-
-#ifndef XHwIcap_mIntrEnable
-#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
-#endif
-
-#ifndef XHwIcap_mIntrGetEnabled
-#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
-#endif
-
-#ifndef XHwIcap_mIntrClear
-#define XHwIcap_mIntrClear XHwIcap_IntrClear
-#endif
-
-#ifndef XHwIcap_mGetWrFifoVacancy
-#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
-#endif
-
-#ifndef XHwIcap_mGetRdFifoOccupancy
-#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
-#endif
-
-#ifndef XHwIcap_mSliceX2Col
-#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
-#endif
-
-#ifndef XHwIcap_mSliceY2Row
-#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
-#endif
-
-#ifndef XHwIcap_mSliceXY2Slice
-#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
-#endif
-
-#ifndef XHwIcap_mReadReg
-#define XHwIcap_mReadReg XHwIcap_ReadReg
-#endif
-
-#ifndef XHwIcap_mWriteReg
-#define XHwIcap_mWriteReg XHwIcap_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIic
- *
- *********************************************************************/
-#ifndef XIic_mReadReg
-#define XIic_mReadReg XIic_ReadReg
-#endif
-
-#ifndef XIic_mWriteReg
-#define XIic_mWriteReg XIic_WriteReg
-#endif
-
-#ifndef XIic_mEnterCriticalRegion
-#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIic_mExitCriticalRegion
-#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_GINTR_DISABLE
-#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIIC_GINTR_ENABLE
-#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_IS_GINTR_ENABLED
-#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
-#endif
-
-#ifndef XIIC_WRITE_IISR
-#define XIIC_WRITE_IISR XIic_WriteIisr
-#endif
-
-#ifndef XIIC_READ_IISR
-#define XIIC_READ_IISR XIic_ReadIisr
-#endif
-
-#ifndef XIIC_WRITE_IIER
-#define XIIC_WRITE_IIER XIic_WriteIier
-#endif
-
-#ifndef XIic_mClearIisr
-#define XIic_mClearIisr XIic_ClearIisr
-#endif
-
-#ifndef XIic_mSend7BitAddress
-#define XIic_mSend7BitAddress XIic_Send7BitAddress
-#endif
-
-#ifndef XIic_mDynSend7BitAddress
-#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
-#endif
-
-#ifndef XIic_mDynSendStartStopAddress
-#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
-#endif
-
-#ifndef XIic_mDynSendStop
-#define XIic_mDynSendStop XIic_DynSendStop
-#endif
-
-#ifndef XIic_mSend10BitAddrByte1
-#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
-#endif
-
-#ifndef XIic_mSend10BitAddrByte2
-#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
-#endif
-
-#ifndef XIic_mSend7BitAddr
-#define XIic_mSend7BitAddr XIic_Send7BitAddr
-#endif
-
-#ifndef XIic_mDisableIntr
-#define XIic_mDisableIntr XIic_DisableIntr
-#endif
-
-#ifndef XIic_mEnableIntr
-#define XIic_mEnableIntr XIic_EnableIntr
-#endif
-
-#ifndef XIic_mClearIntr
-#define XIic_mClearIntr XIic_ClearIntr
-#endif
-
-#ifndef XIic_mClearEnableIntr
-#define XIic_mClearEnableIntr XIic_ClearEnableIntr
-#endif
-
-#ifndef XIic_mFlushRxFifo
-#define XIic_mFlushRxFifo XIic_FlushRxFifo
-#endif
-
-#ifndef XIic_mFlushTxFifo
-#define XIic_mFlushTxFifo XIic_FlushTxFifo
-#endif
-
-#ifndef XIic_mReadRecvByte
-#define XIic_mReadRecvByte XIic_ReadRecvByte
-#endif
-
-#ifndef XIic_mWriteSendByte
-#define XIic_mWriteSendByte XIic_WriteSendByte
-#endif
-
-#ifndef XIic_mSetControlRegister
-#define XIic_mSetControlRegister XIic_SetControlRegister
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIntc
- *
- *********************************************************************/
-#ifndef XIntc_mMasterEnable
-#define XIntc_mMasterEnable XIntc_MasterEnable
-#endif
-
-#ifndef XIntc_mMasterDisable
-#define XIntc_mMasterDisable XIntc_MasterDisable
-#endif
-
-#ifndef XIntc_mEnableIntr
-#define XIntc_mEnableIntr XIntc_EnableIntr
-#endif
-
-#ifndef XIntc_mDisableIntr
-#define XIntc_mDisableIntr XIntc_DisableIntr
-#endif
-
-#ifndef XIntc_mAckIntr
-#define XIntc_mAckIntr XIntc_AckIntr
-#endif
-
-#ifndef XIntc_mGetIntrStatus
-#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XLlDma
- *
- *********************************************************************/
-#ifndef XLlDma_mBdRead
-#define XLlDma_mBdRead XLlDma_BdRead
-#endif
-
-#ifndef XLlDma_mBdWrite
-#define XLlDma_mBdWrite XLlDma_BdWrite
-#endif
-
-#ifndef XLlDma_mWriteReg
-#define XLlDma_mWriteReg XLlDma_WriteReg
-#endif
-
-#ifndef XLlDma_mReadReg
-#define XLlDma_mReadReg XLlDma_ReadReg
-#endif
-
-#ifndef XLlDma_mBdClear
-#define XLlDma_mBdClear XLlDma_BdClear
-#endif
-
-#ifndef XLlDma_mBdSetStsCtrl
-#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdGetStsCtrl
-#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdSetLength
-#define XLlDma_mBdSetLength XLlDma_BdSetLength
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mBdSetId
-#define XLlDma_mBdSetId XLlDma_BdSetId
-#endif
-
-#ifndef XLlDma_mBdGetId
-#define XLlDma_mBdGetId XLlDma_BdGetId
-#endif
-
-#ifndef XLlDma_mBdSetBufAddr
-#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetBufAddr
-#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mGetTxRing
-#define XLlDma_mGetTxRing XLlDma_GetTxRing
-#endif
-
-#ifndef XLlDma_mGetRxRing
-#define XLlDma_mGetRxRing XLlDma_GetRxRing
-#endif
-
-#ifndef XLlDma_mGetCr
-#define XLlDma_mGetCr XLlDma_GetCr
-#endif
-
-#ifndef XLlDma_mSetCr
-#define XLlDma_mSetCr XLlDma_SetCr
-#endif
-
-#ifndef XLlDma_mBdRingCntCalc
-#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
-#endif
-
-#ifndef XLlDma_mBdRingMemCalc
-#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
-#endif
-
-#ifndef XLlDma_mBdRingGetCnt
-#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
-#endif
-
-#ifndef XLlDma_mBdRingGetFreeCnt
-#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
-#endif
-
-#ifndef XLlDma_mBdRingSnapShotCurrBd
-#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
-#endif
-
-#ifndef XLlDma_mBdRingNext
-#define XLlDma_mBdRingNext XLlDma_BdRingNext
-#endif
-
-#ifndef XLlDma_mBdRingPrev
-#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
-#endif
-
-#ifndef XLlDma_mBdRingGetSr
-#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
-#endif
-
-#ifndef XLlDma_mBdRingSetSr
-#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
-#endif
-
-#ifndef XLlDma_mBdRingGetCr
-#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
-#endif
-
-#ifndef XLlDma_mBdRingSetCr
-#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
-#endif
-
-#ifndef XLlDma_mBdRingBusy
-#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
-#endif
-
-#ifndef XLlDma_mBdRingIntEnable
-#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
-#endif
-
-#ifndef XLlDma_mBdRingIntDisable
-#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
-#endif
-
-#ifndef XLlDma_mBdRingIntGetEnabled
-#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
-#endif
-
-#ifndef XLlDma_mBdRingGetIrq
-#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
-#endif
-
-#ifndef XLlDma_mBdRingAckIrq
-#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMbox
- *
- *********************************************************************/
-#ifndef XMbox_mWriteReg
-#define XMbox_mWriteReg XMbox_WriteReg
-#endif
-
-#ifndef XMbox_mReadReg
-#define XMbox_mReadReg XMbox_ReadReg
-#endif
-
-#ifndef XMbox_mWriteMBox
-#define XMbox_mWriteMBox XMbox_WriteMBox
-#endif
-
-#ifndef XMbox_mReadMBox
-#define XMbox_mReadMBox XMbox_ReadMBox
-#endif
-
-#ifndef XMbox_mFSLReadMBox
-#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
-#endif
-
-#ifndef XMbox_mFSLWriteMBox
-#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
-#endif
-
-#ifndef XMbox_mFSLIsEmpty
-#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
-#endif
-
-#ifndef XMbox_mFSLIsFull
-#define XMbox_mFSLIsFull XMbox_FSLIsFull
-#endif
-
-#ifndef XMbox_mIsEmpty
-#define XMbox_mIsEmpty XMbox_IsEmptyHw
-#endif
-
-#ifndef XMbox_mIsFull
-#define XMbox_mIsFull XMbox_IsFullHw
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMpmc
- *
- *********************************************************************/
-#ifndef XMpmc_mReadReg
-#define XMpmc_mReadReg XMpmc_ReadReg
-#endif
-
-#ifndef XMpmc_mWriteReg
-#define XMpmc_mWriteReg XMpmc_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMutex
- *
- *********************************************************************/
-#ifndef XMutex_mWriteReg
-#define XMutex_mWriteReg XMutex_WriteReg
-#endif
-
-#ifndef XMutex_mReadReg
-#define XMutex_mReadReg XMutex_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XPcie
- *
- *********************************************************************/
-#ifndef XPcie_mReadReg
-#define XPcie_mReadReg XPcie_ReadReg
-#endif
-
-#ifndef XPcie_mWriteReg
-#define XPcie_mWriteReg XPcie_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSpi
- *
- *********************************************************************/
-#ifndef XSpi_mIntrGlobalEnable
-#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
-#endif
-
-#ifndef XSpi_mIntrGlobalDisable
-#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
-#endif
-
-#ifndef XSpi_mIsIntrGlobalEnabled
-#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
-#endif
-
-#ifndef XSpi_mIntrGetStatus
-#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
-#endif
-
-#ifndef XSpi_mIntrClear
-#define XSpi_mIntrClear XSpi_IntrClear
-#endif
-
-#ifndef XSpi_mIntrEnable
-#define XSpi_mIntrEnable XSpi_IntrEnable
-#endif
-
-#ifndef XSpi_mIntrDisable
-#define XSpi_mIntrDisable XSpi_IntrDisable
-#endif
-
-#ifndef XSpi_mIntrGetEnabled
-#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
-#endif
-
-#ifndef XSpi_mSetControlReg
-#define XSpi_mSetControlReg XSpi_SetControlReg
-#endif
-
-#ifndef XSpi_mGetControlReg
-#define XSpi_mGetControlReg XSpi_GetControlReg
-#endif
-
-#ifndef XSpi_mGetStatusReg
-#define XSpi_mGetStatusReg XSpi_GetStatusReg
-#endif
-
-#ifndef XSpi_mSetSlaveSelectReg
-#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mGetSlaveSelectReg
-#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mEnable
-#define XSpi_mEnable XSpi_Enable
-#endif
-
-#ifndef XSpi_mDisable
-#define XSpi_mDisable XSpi_Disable
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysAce
- *
- *********************************************************************/
-#ifndef XSysAce_mGetControlReg
-#define XSysAce_mGetControlReg XSysAce_GetControlReg
-#endif
-
-#ifndef XSysAce_mSetControlReg
-#define XSysAce_mSetControlReg XSysAce_SetControlReg
-#endif
-
-#ifndef XSysAce_mOrControlReg
-#define XSysAce_mOrControlReg XSysAce_OrControlReg
-#endif
-
-#ifndef XSysAce_mAndControlReg
-#define XSysAce_mAndControlReg XSysAce_AndControlReg
-#endif
-
-#ifndef XSysAce_mGetErrorReg
-#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
-#endif
-
-#ifndef XSysAce_mGetStatusReg
-#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
-#endif
-
-#ifndef XSysAce_mWaitForLock
-#define XSysAce_mWaitForLock XSysAce_WaitForLock
-#endif
-
-#ifndef XSysAce_mEnableIntr
-#define XSysAce_mEnableIntr XSysAce_EnableIntr
-#endif
-
-#ifndef XSysAce_mDisableIntr
-#define XSysAce_mDisableIntr XSysAce_DisableIntr
-#endif
-
-#ifndef XSysAce_mIsReadyForCmd
-#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
-#endif
-
-#ifndef XSysAce_mIsMpuLocked
-#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
-#endif
-
-#ifndef XSysAce_mIsIntrEnabled
-#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysMon
- *
- *********************************************************************/
-#ifndef XSysMon_mIsEventSamplingModeSet
-#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
-#endif
-
-#ifndef XSysMon_mIsDrpBusy
-#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
-#endif
-
-#ifndef XSysMon_mIsDrpLocked
-#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
-#endif
-
-#ifndef XSysMon_mRawToTemperature
-#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
-#endif
-
-#ifndef XSysMon_mRawToVoltage
-#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
-#endif
-
-#ifndef XSysMon_mTemperatureToRaw
-#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
-#endif
-
-#ifndef XSysMon_mVoltageToRaw
-#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
-#endif
-
-#ifndef XSysMon_mReadReg
-#define XSysMon_mReadReg XSysMon_ReadReg
-#endif
-
-#ifndef XSysMon_mWriteReg
-#define XSysMon_mWriteReg XSysMon_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XTmrCtr
- *
- *********************************************************************/
-#ifndef XTimerCtr_mReadReg
-#define XTimerCtr_mReadReg XTimerCtr_ReadReg
-#endif
-
-#ifndef XTmrCtr_mWriteReg
-#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
-#endif
-
-#ifndef XTmrCtr_mSetControlStatusReg
-#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetControlStatusReg
-#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetTimerCounterReg
-#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mSetLoadReg
-#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
-#endif
-
-#ifndef XTmrCtr_mGetLoadReg
-#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
-#endif
-
-#ifndef XTmrCtr_mEnable
-#define XTmrCtr_mEnable XTmrCtr_Enable
-#endif
-
-#ifndef XTmrCtr_mDisable
-#define XTmrCtr_mDisable XTmrCtr_Disable
-#endif
-
-#ifndef XTmrCtr_mEnableIntr
-#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
-#endif
-
-#ifndef XTmrCtr_mDisableIntr
-#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
-#endif
-
-#ifndef XTmrCtr_mLoadTimerCounterReg
-#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mHasEventOccurred
-#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartLite
- *
- *********************************************************************/
-#ifndef XUartLite_mUpdateStats
-#define XUartLite_mUpdateStats XUartLite_UpdateStats
-#endif
-
-#ifndef XUartLite_mWriteReg
-#define XUartLite_mWriteReg XUartLite_WriteReg
-#endif
-
-#ifndef XUartLite_mReadReg
-#define XUartLite_mReadReg XUartLite_ReadReg
-#endif
-
-#ifndef XUartLite_mClearStats
-#define XUartLite_mClearStats XUartLite_ClearStats
-#endif
-
-#ifndef XUartLite_mSetControlReg
-#define XUartLite_mSetControlReg XUartLite_SetControlReg
-#endif
-
-#ifndef XUartLite_mGetStatusReg
-#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
-#endif
-
-#ifndef XUartLite_mIsReceiveEmpty
-#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
-#endif
-
-#ifndef XUartLite_mIsTransmitFull
-#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
-#endif
-
-#ifndef XUartLite_mIsIntrEnabled
-#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
-#endif
-
-#ifndef XUartLite_mEnableIntr
-#define XUartLite_mEnableIntr XUartLite_EnableIntr
-#endif
-
-#ifndef XUartLite_mDisableIntr
-#define XUartLite_mDisableIntr XUartLite_DisableIntr
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartNs550
- *
- *********************************************************************/
-#ifndef XUartNs550_mUpdateStats
-#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
-#endif
-
-#ifndef XUartNs550_mReadReg
-#define XUartNs550_mReadReg XUartNs550_ReadReg
-#endif
-
-#ifndef XUartNs550_mWriteReg
-#define XUartNs550_mWriteReg XUartNs550_WriteReg
-#endif
-
-#ifndef XUartNs550_mClearStats
-#define XUartNs550_mClearStats XUartNs550_ClearStats
-#endif
-
-#ifndef XUartNs550_mGetLineStatusReg
-#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
-#endif
-
-#ifndef XUartNs550_mGetLineControlReg
-#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
-#endif
-
-#ifndef XUartNs550_mSetLineControlReg
-#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
-#endif
-
-#ifndef XUartNs550_mEnableIntr
-#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
-#endif
-
-#ifndef XUartNs550_mDisableIntr
-#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
-#endif
-
-#ifndef XUartNs550_mIsReceiveData
-#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
-#endif
-
-#ifndef XUartNs550_mIsTransmitEmpty
-#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUsb
- *
- *********************************************************************/
-#ifndef XUsb_mReadReg
-#define XUsb_mReadReg XUsb_ReadReg
-#endif
-
-#ifndef XUsb_mWriteReg
-#define XUsb_mWriteReg XUsb_WriteReg
-#endif
-
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h
deleted file mode 100644
index 8e43e8227..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API
-* defined for MPU in R5. R5 does not have mmu and for usage of similiar API
-* the file has been created.
-*
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.0	pkp  2/12/15 Initial version
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_mpu.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c
deleted file mode 100644
index 7c028c515..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_mpu.c
-*
-* This file provides APIs for enabling/disabling MPU and setting the memory
-* attributes for sections, in the MPU translation table.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mpu.h"
-#include "xdebug.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-static const struct {
-	u64 size;
-	unsigned int encoding;
-}region_size[] = {
-	{ 0x20, REGION_32B },
-	{ 0x40, REGION_64B },
-	{ 0x80, REGION_128B },
-	{ 0x100, REGION_256B },
-	{ 0x200, REGION_512B },
-	{ 0x400, REGION_1K },
-	{ 0x800, REGION_2K },
-	{ 0x1000, REGION_4K },
-	{ 0x2000, REGION_8K },
-	{ 0x4000, REGION_16K },
-	{ 0x8000, REGION_32K },
-	{ 0x10000, REGION_64K },
-	{ 0x20000, REGION_128K },
-	{ 0x40000, REGION_256K },
-	{ 0x80000, REGION_512K },
-	{ 0x100000, REGION_1M },
-	{ 0x200000, REGION_2M },
-	{ 0x400000, REGION_4M },
-	{ 0x800000, REGION_8M },
-	{ 0x1000000, REGION_16M },
-	{ 0x2000000, REGION_32M },
-	{ 0x4000000, REGION_64M },
-	{ 0x8000000, REGION_128M },
-	{ 0x10000000, REGION_256M },
-	{ 0x20000000, REGION_512M },
-	{ 0x40000000, REGION_1G },
-	{ 0x80000000, REGION_2G },
-	{ 0x100000000, REGION_4G },
-};
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************
-*
-* Set the memory attributes for a section of memory with starting address addr
-* of the region size 1MB having attributes attrib
-*
-* @param	addr is the address for which attributes are to be set.
-* @param	attrib specifies the attributes for that memory region.
-* @return	None.
-*
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
-{
-	INTPTR Localaddr = addr;
-	Localaddr &= (~(0xFFFFFU));
-	/* Setting the MPU region with given attribute with 1MB size */
-	Xil_SetMPURegion(Localaddr, 0x100000, attrib);
-}
-
-/*****************************************************************************
-*
-* Set the memory attributes for a section of memory with starting address addr
-* of the region size size and having attributes attrib
-*
-* @param	addr is the address for which attributes are to be set.
-* @param	size is the size of the region.
-* @param	attrib specifies the attributes for that memory region.
-* @return	None.
-*
-*
-******************************************************************************/
-void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
-{
-	u32 Regionsize = 0;
-	INTPTR Localaddr = addr;
-	u32 NextAvailableMemRegion;
-	unsigned int i;
-
-	Xil_DCacheFlush();
-	Xil_ICacheInvalidate();
-	NextAvailableMemRegion = mfcp(XREG_CP15_MPU_MEMORY_REG_NUMBER);
-	NextAvailableMemRegion++;
-	if (NextAvailableMemRegion > 16) {
-		xdbg_printf(DEBUG, "No regions available\r\n");
-		return;
-	}
-	mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
-	isb();
-
-	/* Lookup the size.  */
-	for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
-		if (size <= region_size[i].size) {
-			Regionsize = region_size[i].encoding;
-			break;
-		}
-	}
-
-	Localaddr &= ~(region_size[i].size - 1);
-
-	Regionsize <<= 1;
-	Regionsize |= REGION_EN;
-	dsb();
-	mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);	/* Set base address of a region */
-	mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);	/* Set the control attribute */
-	mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);	/* set the region size and enable it*/
-	dsb();
-	isb();
-}
-/*****************************************************************************
-*
-* Enable MPU for Cortex R5 processor. This function invalidates I cache and
-* flush the D Caches before enabling the MPU.
-*
-*
-* @param	None.
-* @return	None.
-*
-******************************************************************************/
-void Xil_EnableMPU(void)
-{
-	u32 CtrlReg, Reg;
-	s32 DCacheStatus=0, ICacheStatus=0;
-	/* enable caches only if they are disabled */
-	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
-		DCacheStatus=1;
-	}
-	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
-		ICacheStatus=1;
-	}
-
-	if(DCacheStatus != 0) {
-		Xil_DCacheDisable();
-	}
-	if(ICacheStatus != 0){
-		Xil_ICacheDisable();
-	}
-	Reg = mfcp(XREG_CP15_SYS_CONTROL);
-	Reg |= 0x00000001U;
-	dsb();
-	mtcp(XREG_CP15_SYS_CONTROL, Reg);
-	isb();
-	/* enable caches only if they are disabled in routine*/
-	if(DCacheStatus != 0) {
-		Xil_DCacheEnable();
-	}
-	if(ICacheStatus != 0) {
-		Xil_ICacheEnable();
-	}
-}
-
-/*****************************************************************************
-*
-* Disable MPU for Cortex R5 processors. This function invalidates I cache and
-* flush the D Caches before disabling the MPU.
-*
-* @param	None.
-*
-* @return	None.
-*
-******************************************************************************/
-void Xil_DisableMPU(void)
-{
-	u32 CtrlReg, Reg;
-	s32 DCacheStatus=0, ICacheStatus=0;
-	/* enable caches only if they are disabled */
-	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
-		DCacheStatus=1;
-	}
-	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
-		ICacheStatus=1;
-	}
-
-	if(DCacheStatus != 0) {
-		Xil_DCacheDisable();
-	}
-	if(ICacheStatus != 0){
-		Xil_ICacheDisable();
-	}
-
-	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
-	Reg = mfcp(XREG_CP15_SYS_CONTROL);
-	Reg &= ~(0x00000001U);
-	dsb();
-	mtcp(XREG_CP15_SYS_CONTROL, Reg);
-	isb();
-	/* enable caches only if they are disabled in routine*/
-	if(DCacheStatus != 0) {
-		Xil_DCacheEnable();
-	}
-	if(ICacheStatus != 0) {
-		Xil_ICacheEnable();
-	}
-}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h
deleted file mode 100644
index a55be916e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_MPU_H
-#define XIL_MPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#include "xil_types.h"
-/***************************** Include Files *********************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMPU(void);
-void Xil_DisableMPU(void);
-void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MPU_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c
deleted file mode 100644
index 0f0db4fc9..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/*---------------------------------------------------*/
-/* Modified from :                                   */
-/* Public Domain version of printf                   */
-/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
-/* For Embedded Systems Programming, 1991            */
-/*                                                   */
-/*---------------------------------------------------*/
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include <ctype.h>
-#include <string.h>
-#include <stdarg.h>
-
-static void padding( const s32 l_flag,const struct params_s *par);
-static void outs(const charptr lp, struct params_s *par);
-static s32 getnum( charptr* linep);
-
-typedef struct params_s {
-    s32 len;
-    s32 num1;
-    s32 num2;
-    char8 pad_character;
-    s32 do_padding;
-    s32 left_flag;
-    s32 unsigned_flag;
-} params_t;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the  */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and   */
-/* that is unacceptable in most embedded systems.    */
-/*---------------------------------------------------*/
-
-
-/*---------------------------------------------------*/
-/*                                                   */
-/* This routine puts pad characters into the output  */
-/* buffer.                                           */
-/*                                                   */
-static void padding( const s32 l_flag, const struct params_s *par)
-{
-    s32 i;
-
-    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
-		i=(par->len);
-        for (; i<(par->num1); i++) {
-#ifdef STDOUT_BASEADDRESS
-            outbyte( par->pad_character);
-#endif
-		}
-    }
-}
-
-/*---------------------------------------------------*/
-/*                                                   */
-/* This routine moves a string to the output buffer  */
-/* as directed by the padding and positioning flags. */
-/*                                                   */
-static void outs(const charptr lp, struct params_s *par)
-{
-    charptr LocalPtr;
-	LocalPtr = lp;
-    /* pad on left if needed                         */
-	if(LocalPtr != NULL) {
-		par->len = (s32)strlen( LocalPtr);
-	}
-    padding( !(par->left_flag), par);
-
-    /* Move string to the buffer                     */
-    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
-		(par->num2)--;
-#ifdef STDOUT_BASEADDRESS
-        outbyte(*LocalPtr);
-		LocalPtr += 1;
-#endif
-}
-
-    /* Pad on right if needed                        */
-    /* CR 439175 - elided next stmt. Seemed bogus.   */
-    /* par->len = strlen( lp)                      */
-    padding( par->left_flag, par);
-}
-
-/*---------------------------------------------------*/
-/*                                                   */
-/* This routine moves a number to the output buffer  */
-/* as directed by the padding and positioning flags. */
-/*                                                   */
-
-static void outnum( const s32 n, const s32 base, struct params_s *par)
-{
-    charptr cp;
-    s32 negative;
-	s32 i;
-    char8 outbuf[32];
-    const char8 digits[] = "0123456789ABCDEF";
-    u32 num;
-    for(i = 0; i<32; i++) {
-	outbuf[i] = '0';
-    }
-
-    /* Check if number is negative                   */
-    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
-        negative = 1;
-		num =(-(n));
-    }
-    else{
-        num = n;
-        negative = 0;
-    }
-
-    /* Build number (backwards) in outbuf            */
-    i = 0;
-    do {
-		outbuf[i] = digits[(num % base)];
-		i++;
-		num /= base;
-    } while (num > 0);
-
-    if (negative != 0) {
-		outbuf[i] = '-';
-		i++;
-	}
-
-    outbuf[i] = 0;
-    i--;
-
-    /* Move the converted number to the buffer and   */
-    /* add in the padding where needed.              */
-    par->len = (s32)strlen(outbuf);
-    padding( !(par->left_flag), par);
-    while (&outbuf[i] >= outbuf) {
-#ifdef STDOUT_BASEADDRESS
-	outbyte( outbuf[i] );
-		i--;
-#endif
-}
-    padding( par->left_flag, par);
-}
-
-/*---------------------------------------------------*/
-/*                                                   */
-/* This routine gets a number from the format        */
-/* string.                                           */
-/*                                                   */
-static s32 getnum( charptr* linep)
-{
-    s32 n;
-    s32 ResultIsDigit = 0;
-    charptr cptr;
-    n = 0;
-    cptr = *linep;
-	if(cptr != NULL){
-		ResultIsDigit = isdigit(((s32)*cptr));
-	}
-    while (ResultIsDigit != 0) {
-		if(cptr != NULL){
-			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
-			cptr += 1;
-			if(cptr != NULL){
-				ResultIsDigit = isdigit(((s32)*cptr));
-			}
-		}
-		ResultIsDigit = isdigit(((s32)*cptr));
-	}
-    *linep = ((charptr )(cptr));
-    return(n);
-}
-
-/*---------------------------------------------------*/
-/*                                                   */
-/* This routine operates just like a printf/sprintf  */
-/* routine. It outputs a set of data under the       */
-/* control of a formatting string. Not all of the    */
-/* standard C format control are supported. The ones */
-/* provided are primarily those needed for embedded  */
-/* systems work. Primarily the floating point        */
-/* routines are omitted. Other formats could be      */
-/* added easily by following the examples shown for  */
-/* the supported formats.                            */
-/*                                                   */
-
-/* void esp_printf( const func_ptr f_ptr,
-   const charptr ctrl1, ...) */
-void xil_printf( const char8 *ctrl1, ...)
-{
-	s32 Check;
-    s32 long_flag;
-    s32 dot_flag;
-
-    params_t par;
-
-    char8 ch;
-    va_list argp;
-    char8 *ctrl = (char8 *)ctrl1;
-
-    va_start( argp, ctrl1);
-
-    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
-
-        /* move format string chars to buffer until a  */
-        /* format control is found.                    */
-        if (*ctrl != '%') {
-#ifdef STDOUT_BASEADDRESS
-            outbyte(*ctrl);
-			ctrl += 1;
-#endif
-            continue;
-        }
-
-        /* initialize all the flags for this format.   */
-        dot_flag = 0;
-		long_flag = 0;
-        par.unsigned_flag = 0;
-		par.left_flag = 0;
-		par.do_padding = 0;
-        par.pad_character = ' ';
-        par.num2=32767;
-		par.num1=0;
-		par.len=0;
-
- try_next:
-		if(ctrl != NULL) {
-			ctrl += 1;
-		}
-		if(ctrl != NULL) {
-			ch = *ctrl;
-		}
-		else {
-			ch = *ctrl;
-		}
-
-        if (isdigit((s32)ch) != 0) {
-            if (dot_flag != 0) {
-                par.num2 = getnum(&ctrl);
-			}
-            else {
-                if (ch == '0') {
-                    par.pad_character = '0';
-				}
-				if(ctrl != NULL) {
-			par.num1 = getnum(&ctrl);
-				}
-                par.do_padding = 1;
-            }
-            if(ctrl != NULL) {
-			ctrl -= 1;
-			}
-            goto try_next;
-        }
-
-        switch (tolower((s32)ch)) {
-            case '%':
-#ifdef STDOUT_BASEADDRESS
-                outbyte( '%');
-#endif
-                Check = 1;
-                break;
-
-            case '-':
-                par.left_flag = 1;
-                Check = 0;
-                break;
-
-            case '.':
-                dot_flag = 1;
-                Check = 0;
-                break;
-
-            case 'l':
-                long_flag = 1;
-                Check = 0;
-                break;
-
-            case 'u':
-                par.unsigned_flag = 1;
-                /* fall through */
-            case 'i':
-            case 'd':
-                if ((long_flag != 0) || (ch == 'D')) {
-                    outnum( va_arg(argp, s32), 10L, &par);
-                }
-                else {
-                    outnum( va_arg(argp, s32), 10L, &par);
-                }
-				Check = 1;
-                break;
-            case 'p':
-            case 'X':
-            case 'x':
-                par.unsigned_flag = 1;
-                outnum((s32)va_arg(argp, s32), 16L, &par);
-                Check = 1;
-                break;
-
-            case 's':
-                outs( va_arg( argp, char *), &par);
-                Check = 1;
-                break;
-
-            case 'c':
-#ifdef STDOUT_BASEADDRESS
-                outbyte( va_arg( argp, s32));
-#endif
-                Check = 1;
-                break;
-
-            case '\\':
-                switch (*ctrl) {
-                    case 'a':
-#ifdef STDOUT_BASEADDRESS
-                        outbyte( ((char8)0x07));
-#endif
-                        break;
-                    case 'h':
-#ifdef STDOUT_BASEADDRESS
-                        outbyte( ((char8)0x08));
-#endif
-                        break;
-                    case 'r':
-#ifdef STDOUT_BASEADDRESS
-                        outbyte( ((char8)0x0D));
-#endif
-                        break;
-                    case 'n':
-#ifdef STDOUT_BASEADDRESS
-                        outbyte( ((char8)0x0D));
-                        outbyte( ((char8)0x0A));
-#endif
-                        break;
-                    default:
-#ifdef STDOUT_BASEADDRESS
-                        outbyte( *ctrl);
-#endif
-                        break;
-                }
-                ctrl += 1;
-                Check = 0;
-                break;
-
-            default:
-		Check = 1;
-		break;
-        }
-        if(Check == 1) {
-			if(ctrl != NULL) {
-				ctrl += 1;
-			}
-                continue;
-        }
-        goto try_next;
-    }
-    va_end( argp);
-}
-
-/*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h
deleted file mode 100644
index 2be5c5734..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h
+++ /dev/null
@@ -1,44 +0,0 @@
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <ctype.h>
-#include <string.h>
-#include <stdarg.h>
-#include "xil_types.h"
-#include "xparameters.h"
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to   */
-/* make xil_printf re-entrant.                        */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the  */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and   */
-/* that is unacceptable in most embedded systems.    */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/*                                                   */
-
-void xil_printf( const char8 *ctrl1, ...);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c
deleted file mode 100644
index a2c4b0bbf..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.c
-*
-* Contains utility functions to test cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date	 Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/28/09 Initial release
-* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
-*				      cache line.
-* </pre>
-*
-* @note
-*
-* This file contain functions that all operate on HAL.
-*
-******************************************************************************/
-#ifdef __ARM__
-#include "xil_cache.h"
-#include "xil_testcache.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#ifdef __aarch64__
-#include "xreg_cortexa53.h"
-#else
-#include "xreg_cortexr5.h"
-#endif
-
-#include "xil_types.h"
-
-extern void xil_printf(const char8 *ctrl1, ...);
-
-#define DATA_LENGTH 128
-
-#ifdef __aarch64__
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
-#else
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
-#endif
-
-/**
-* Perform DCache range related API test such as Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange. This test function writes a constant value
-* to the Data array, flushes the range, writes a new value, then invalidates
-* the corresponding range.
-*
-* @return
-*
-*     - 0 is returned for a pass
-*     - -1 is returned for a failure
-*/
-s32 Xil_TestDCacheRange(void)
-{
-	s32 Index;
-	s32 Status = 0;
-	u32 CtrlReg;
-	INTPTR Value;
-
-	xil_printf("-- Cache Range Test --\n\r");
-
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = 0xA0A00505;
-
-	xil_printf("    initialize Data done:\r\n");
-
-	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
-	xil_printf("    flush range done\r\n");
-
-	dsb();
-	#ifdef __aarch64__
-			CtrlReg = mfcp(SCTLR_EL3);
-			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
-			mtcp(SCTLR_EL3,CtrlReg);
-	#else
-			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	#endif
-	dsb();
-
-	Status = 0;
-
-	for (Index = 0; Index < DATA_LENGTH; Index++) {
-		Value = Data[Index];
-		if (Value != 0xA0A00505) {
-			Status = -1;
-			xil_printf("Data[%d] = %x\r\n", Index, Value);
-			break;
-		}
-	}
-
-	if (!Status) {
-		xil_printf("	Flush worked\r\n");
-	}
-	else {
-		xil_printf("Error: flush dcache range not working\r\n");
-	}
-	dsb();
-	#ifdef __aarch64__
-			CtrlReg = mfcp(SCTLR_EL3);
-			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
-			mtcp(SCTLR_EL3,CtrlReg);
-		#else
-			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-		#endif
-	dsb();
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = 0xA0A0C505;
-
-
-
-	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = Index + 3;
-
-	Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
-	xil_printf("    invalidate dcache range done\r\n");
-	dsb();
-	#ifdef __aarch64__
-			CtrlReg = mfcp(SCTLR_EL3);
-			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
-			mtcp(SCTLR_EL3,CtrlReg);
-	#else
-			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	#endif
-	dsb();
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = 0xA0A0A05;
-	dsb();
-	#ifdef __aarch64__
-			CtrlReg = mfcp(SCTLR_EL3);
-			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
-			mtcp(SCTLR_EL3,CtrlReg);
-	#else
-			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	#endif
-	dsb();
-
-	Status = 0;
-
-	for (Index = 0; Index < DATA_LENGTH; Index++) {
-		Value = Data[Index];
-		if (Value != 0xA0A0A05) {
-			Status = -1;
-			xil_printf("Data[%d] = %x\r\n", Index, Value);
-			break;
-		}
-	}
-
-
-	if (!Status) {
-		xil_printf("    Invalidate worked\r\n");
-	}
-	else {
-		xil_printf("Error: Invalidate dcache range not working\r\n");
-	}
-	xil_printf("-- Cache Range Test Complete --\r\n");
-	return Status;
-
-}
-
-/**
-* Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value, then invalidates
-* the DCache.
-*
-* @return
-*     - 0 is returned for a pass
-*     - -1 is returned for a failure
-*/
-s32 Xil_TestDCacheAll(void)
-{
-	s32 Index;
-	s32 Status;
-	INTPTR Value;
-	u32 CtrlReg;
-
-	xil_printf("-- Cache All Test --\n\r");
-
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = 0x50500A0A;
-	xil_printf("    initialize Data done:\r\n");
-
-	Xil_DCacheFlush();
-	xil_printf("    flush all done\r\n");
-	dsb();
-	#ifdef __aarch64__
-		CtrlReg = mfcp(SCTLR_EL3);
-		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
-		mtcp(SCTLR_EL3,CtrlReg);
-	#else
-		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	#endif
-	dsb();
-	Status = 0;
-
-	for (Index = 0; Index < DATA_LENGTH; Index++) {
-		Value = Data[Index];
-
-		if (Value != 0x50500A0A) {
-			Status = -1;
-			xil_printf("Data[%d] = %x\r\n", Index, Value);
-			break;
-		}
-	}
-
-	if (!Status) {
-		xil_printf("    Flush all worked\r\n");
-	}
-	else {
-		xil_printf("Error: Flush dcache all not working\r\n");
-	}
-	dsb();
-	#ifdef __aarch64__
-		CtrlReg = mfcp(SCTLR_EL3);
-		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
-		mtcp(SCTLR_EL3,CtrlReg);
-	#else
-		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	#endif
-	dsb();
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = 0x505FFA0A;
-
-	Xil_DCacheFlush();
-
-
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = Index + 3;
-
-	Xil_DCacheInvalidate();
-
-	xil_printf("    invalidate all done\r\n");
-	dsb();
-	#ifdef __aarch64__
-		CtrlReg = mfcp(SCTLR_EL3);
-		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
-		mtcp(SCTLR_EL3,CtrlReg);
-	#else
-		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	#endif
-	dsb();
-	for (Index = 0; Index < DATA_LENGTH; Index++)
-		Data[Index] = 0x50CFA0A;
-	dsb();
-	#ifdef __aarch64__
-		CtrlReg = mfcp(SCTLR_EL3);
-		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
-		mtcp(SCTLR_EL3,CtrlReg);
-	#else
-		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-	#endif
-	dsb();
-	Status = 0;
-
-	for (Index = 0; Index < DATA_LENGTH; Index++) {
-		Value = Data[Index];
-		if (Value != 0x50CFA0A) {
-			Status = -1;
-			xil_printf("Data[%d] = %x\r\n", Index, Value);
-			break;
-		}
-	}
-
-	if (!Status) {
-		xil_printf("    Invalidate all worked\r\n");
-	}
-	else {
-			xil_printf("Error: Invalidate dcache all not working\r\n");
-	}
-
-	xil_printf("-- DCache all Test Complete --\n\r");
-
-	return Status;
-}
-
-
-/**
-* Perform Xil_ICacheInvalidateRange() on a few function pointers.
-*
-* @return
-*
-*     - 0 is returned for a pass
-*     The function will hang if it fails.
-*/
-s32 Xil_TestICacheRange(void)
-{
-
-	Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
-	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
-	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
-
-	xil_printf("-- Invalidate icache range done --\r\n");
-
-	return 0;
-}
-
-/**
-* Perform Xil_ICacheInvalidate().
-*
-* @return
-*
-*     - 0 is returned for a pass
-*     The function will hang if it fails.
-*/
-s32 Xil_TestICacheAll(void)
-{
-	Xil_ICacheInvalidate();
-	xil_printf("-- Invalidate icache all done --\r\n");
-	return 0;
-}
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h
deleted file mode 100644
index b3c416cd0..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* This file contains utility functions to test cache.
-*
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm  07/29/09 First release
-*
-******************************************************************************/
-
-#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
-#define XIL_TESTCACHE_H	/* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c
deleted file mode 100644
index a68d7652f..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmemend.c
-*
-* Contains the memory test utility functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm  08/25/09 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testio.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- *
- * Endian swap a 16-bit word.
- * @param	Data is the 16-bit word to be swapped.
- * @return	The endian swapped value.
- *
- */
-static u16 Swap16(u16 Data)
-{
-	return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
-}
-
-/**
- *
- * Endian swap a 32-bit word.
- * @param	Data is the 32-bit word to be swapped.
- * @return	The endian swapped value.
- *
- */
-static u32 Swap32(u32 Data)
-{
-	u16 Lo16;
-	u16 Hi16;
-
-	u16 Swap16Lo;
-	u16 Swap16Hi;
-
-	Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
-	Lo16 = (u16)(Data & 0x0000FFFFU);
-
-	Swap16Lo = Swap16(Lo16);
-	Swap16Hi = Swap16(Hi16);
-
-	return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 8-bit wide register IO test where the register is
-* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
-* values.
-*
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
-{
-	u8 ValueIn;
-	s32 Index;
-	s32 Status = 0;
-
-	for (Index = 0; Index < Length; Index++) {
-		Xil_Out8((INTPTR)Addr, Value);
-
-		ValueIn = Xil_In8((INTPTR)Addr);
-
-		if ((Value != ValueIn) && (Status == 0)) {
-			Status = -1;
-			break;
-		}
-	}
-	return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 16-bit wide register IO test. Each location is tested
-* by sequentially writing a 16-bit wide register, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function performs the following
-* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
-* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
-* read-in value before comparing is controlled by the 5th argument.
-*
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
-* @param	Kind is the test kind. Acceptable values are:
-*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param	Swap indicates whether to byte swap the read-in value.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
-{
-	u16 *TempAddr16;
-	u16 ValueIn = 0U;
-	s32 Index;
-	TempAddr16 = Addr;
-	Xil_AssertNonvoid(TempAddr16 != NULL);
-
-	for (Index = 0; Index < Length; Index++) {
-		switch (Kind) {
-		case XIL_TESTIO_LE:
-			Xil_Out16LE((INTPTR)TempAddr16, Value);
-			break;
-		case XIL_TESTIO_BE:
-			Xil_Out16BE((INTPTR)TempAddr16, Value);
-			break;
-		default:
-			Xil_Out16((INTPTR)TempAddr16, Value);
-			break;
-		}
-
-		ValueIn = Xil_In16((INTPTR)TempAddr16);
-
-		if ((Kind != 0) && (Swap != 0)) {
-			ValueIn = Swap16(ValueIn);
-		}
-
-		if (Value != ValueIn) {
-			return -1;
-		}
-
-		/* second round */
-		Xil_Out16((INTPTR)TempAddr16, Value);
-
-		switch (Kind) {
-		case XIL_TESTIO_LE:
-			ValueIn = Xil_In16LE((INTPTR)TempAddr16);
-			break;
-		case XIL_TESTIO_BE:
-			ValueIn = Xil_In16BE((INTPTR)TempAddr16);
-			break;
-		default:
-			ValueIn = Xil_In16((INTPTR)TempAddr16);
-			break;
-		}
-
-
-		if ((Kind != 0) && (Swap != 0)) {
-			ValueIn = Swap16(ValueIn);
-		}
-
-		if (Value != ValueIn) {
-			return -1;
-		}
-		TempAddr16 += sizeof(u16);
-	}
-	return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 32-bit wide register IO test. Each location is tested
-* by sequentially writing a 32-bit wide regsiter, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function perform the following
-* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
-* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
-* before comparing is controlled by the 5th argument.
-*
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
-* @param	Kind is the test kind. Acceptable values are:
-*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param	Swap indicates whether to byte swap the read-in value.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
-{
-	u32 *TempAddr;
-	u32 ValueIn = 0U;
-	s32 Index;
-	TempAddr = Addr;
-	Xil_AssertNonvoid(TempAddr != NULL);
-
-	for (Index = 0; Index < Length; Index++) {
-		switch (Kind) {
-		case XIL_TESTIO_LE:
-			Xil_Out32LE((INTPTR)TempAddr, Value);
-			break;
-		case XIL_TESTIO_BE:
-			Xil_Out32BE((INTPTR)TempAddr, Value);
-			break;
-		default:
-			Xil_Out32((INTPTR)TempAddr, Value);
-			break;
-		}
-
-		ValueIn = Xil_In32((INTPTR)TempAddr);
-
-		if ((Kind != 0) && (Swap != 0)) {
-			ValueIn = Swap32(ValueIn);
-		}
-
-		if (Value != ValueIn) {
-			return -1;
-		}
-
-		/* second round */
-		Xil_Out32((INTPTR)TempAddr, Value);
-
-
-		switch (Kind) {
-		case XIL_TESTIO_LE:
-			ValueIn = Xil_In32LE((INTPTR)TempAddr);
-			break;
-		case XIL_TESTIO_BE:
-			ValueIn = Xil_In32BE((INTPTR)TempAddr);
-			break;
-		default:
-			ValueIn = Xil_In32((INTPTR)TempAddr);
-			break;
-		}
-
-		if ((Kind != 0) && (Swap != 0)) {
-			ValueIn = Swap32(ValueIn);
-		}
-
-		if (Value != ValueIn) {
-			return -1;
-		}
-		TempAddr += sizeof(u32);
-	}
-	return 0;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h
deleted file mode 100644
index fba0c1060..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmemend.h
-*
-* This file contains utility functions to teach endian related memory
-* IO functions.
-*
-* <b>Memory test description</b>
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm  08/05/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
-#define XIL_TESTIO_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 	0
-#define XIL_TESTIO_LE		1
-#define XIL_TESTIO_BE		2
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
-extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
-extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c
deleted file mode 100644
index 19a3b6608..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c
+++ /dev/null
@@ -1,882 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.c
-*
-* Contains the memory test utility functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm  08/25/09 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testmem.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static u32 RotateLeft(u32 Input, u8 Width);
-
-/* define ROTATE_RIGHT to give access to this functionality */
-/* #define ROTATE_RIGHT */
-#ifdef ROTATE_RIGHT
-static u32 RotateRight(u32 Input, u8 Width);
-#endif /* ROTATE_RIGHT */
-
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 32-bit wide memory test.
-*
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
-*           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
-*
-* @return
-*
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
-{
-	u32 I;
-	u32 j;
-	u32 Val;
-	u32 FirtVal;
-	u32 WordMem32;
-	s32 Status = 0;
-
-	Xil_AssertNonvoid(Words != (u32)0);
-	Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-	Xil_AssertNonvoid(Addr != NULL);
-
-	/*
-	 * variable initialization
-	 */
-	Val = XIL_TESTMEM_INIT_VALUE;
-	FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
-		/*
-		 * Fill the memory with incrementing
-		 * values starting from 'FirtVal'
-		 */
-		for (I = 0U; I < Words; I++) {
-			*(Addr+I) = Val;
-			Val++;
-		}
-
-		/*
-		 * Restore the reference 'Val' to the
-		 * initial value
-		 */
-		Val = FirtVal;
-
-		/*
-		 * Check every word within the words
-		 * of tested memory and compare it
-		 * with the incrementing reference
-		 * Val
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			WordMem32 = *(Addr+I);
-
-			if (WordMem32 != Val) {
-				Status = -1;
-				goto End_Label;
-			}
-
-			Val++;
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
-		/*
-		 * set up to cycle through all possible initial
-		 * test Patterns for walking ones test
-		 */
-
-		for (j = 0U; j < (u32)32; j++) {
-			/*
-			 * Generate an initial value for walking ones test
-			 * to test for bad data bits
-			 */
-
-			Val = (1U << j);
-
-			/*
-			 * START walking ones test
-			 * Write a one to each data bit indifferent locations
-			 */
-
-			for (I = 0U; I < (u32)32; I++) {
-				/* write memory location */
-				*(Addr+I) = Val;
-				Val = (u32) RotateLeft(Val, 32U);
-			}
-
-			/*
-			 * Restore the reference 'val' to the
-			 * initial value
-			 */
-			Val = 1U << j;
-
-			/* Read the values from each location that was
-			 * written */
-			for (I = 0U; I < (u32)32; I++) {
-				/* read memory location */
-
-				WordMem32 = *(Addr+I);
-
-				if (WordMem32 != Val) {
-					Status = -1;
-					goto End_Label;
-				}
-
-				Val = (u32)RotateLeft(Val, 32U);
-			}
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
-		/*
-		 * set up to cycle through all possible
-		 * initial test Patterns for walking zeros test
-		 */
-
-		for (j = 0U; j < (u32)32; j++) {
-
-			/*
-			 * Generate an initial value for walking ones test
-			 * to test for bad data bits
-			 */
-
-			Val = ~(1U << j);
-
-			/*
-			 * START walking zeros test
-			 * Write a one to each data bit indifferent locations
-			 */
-
-			for (I = 0U; I < (u32)32; I++) {
-				/* write memory location */
-				*(Addr+I) = Val;
-				Val = ~((u32)RotateLeft(~Val, 32U));
-			}
-
-			/*
-			 * Restore the reference 'Val' to the
-			 * initial value
-			 */
-
-			Val = ~(1U << j);
-
-			/* Read the values from each location that was
-			 * written */
-			for (I = 0U; I < (u32)32; I++) {
-				/* read memory location */
-				WordMem32 = *(Addr+I);
-				if (WordMem32 != Val) {
-					Status = -1;
-					goto End_Label;
-				}
-				Val = ~((u32)RotateLeft(~Val, 32U));
-			}
-
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
-		/* Fill the memory with inverse of address */
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			Val = (u32) (~((INTPTR) (&Addr[I])));
-			*(Addr+I) = Val;
-		}
-
-		/*
-		 * Check every word within the words
-		 * of tested memory
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* Read the location */
-			WordMem32 = *(Addr+I);
-			Val = (u32) (~((INTPTR) (&Addr[I])));
-
-			if ((WordMem32 ^ Val) != 0x00000000U) {
-				Status = -1;
-				goto End_Label;
-			}
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
-		/*
-		 * Generate an initial value for
-		 * memory testing
-		 */
-
-		if (Pattern == (u32)0) {
-			Val = 0xDEADBEEFU;
-		}
-		else {
-			Val = Pattern;
-		}
-
-		/*
-		 * Fill the memory with fixed Pattern
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			*(Addr+I) = Val;
-		}
-
-		/*
-		 * Check every word within the words
-		 * of tested memory and compare it
-		 * with the fixed Pattern
-		 */
-
-		for (I = 0U; I < Words; I++) {
-
-			/* read memory location */
-
-			WordMem32 = *(Addr+I);
-			if (WordMem32 != Val) {
-				Status = -1;
-				goto End_Label;
-			}
-		}
-	}
-
-End_Label:
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 16-bit wide memory test.
-*
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant Pattern test, if 0,
-*           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
-{
-	u32 I;
-	u32 j;
-	u16 Val;
-	u16 FirtVal;
-	u16 WordMem16;
-	s32 Status = 0;
-
-	Xil_AssertNonvoid(Words != (u32)0);
-	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-	Xil_AssertNonvoid(Addr != NULL);
-
-	/*
-	 * variable initialization
-	 */
-	Val = XIL_TESTMEM_INIT_VALUE;
-	FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-	/*
-	 * selectthe proper Subtest(s)
-	 */
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
-		/*
-		 * Fill the memory with incrementing
-		 * values starting from 'FirtVal'
-		 */
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			*(Addr+I) = Val;
-			Val++;
-		}
-		/*
-		 * Restore the reference 'Val' to the
-		 * initial value
-		 */
-		Val = FirtVal;
-
-		/*
-		 * Check every word within the words
-		 * of tested memory and compare it
-		 * with the incrementing reference val
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* read memory location */
-			WordMem16 = *(Addr+I);
-			if (WordMem16 != Val) {
-				Status = -1;
-				goto End_Label;
-			}
-			Val++;
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
-		/*
-		 * set up to cycle through all possible initial test
-		 * Patterns for walking ones test
-		 */
-
-		for (j = 0U; j < (u32)16; j++) {
-			/*
-			 * Generate an initial value for walking ones test
-			 * to test for bad data bits
-			 */
-
-			Val = (u16)((u32)1 << j);
-			/*
-			 * START walking ones test
-			 * Write a one to each data bit indifferent locations
-			 */
-
-			for (I = 0U; I < (u32)16; I++) {
-				/* write memory location */
-				*(Addr+I) = Val;
-				Val = (u16)RotateLeft(Val, 16U);
-			}
-			/*
-			 * Restore the reference 'Val' to the
-			 * initial value
-			 */
-			Val = (u16)((u32)1 << j);
-			/* Read the values from each location that was written */
-			for (I = 0U; I < (u32)16; I++) {
-				/* read memory location */
-				WordMem16 = *(Addr+I);
-				if (WordMem16 != Val) {
-					Status = -1;
-					goto End_Label;
-				}
-				Val = (u16)RotateLeft(Val, 16U);
-			}
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
-		/*
-		 * set up to cycle through all possible initial
-		 * test Patterns for walking zeros test
-		 */
-
-		for (j = 0U; j < (u32)16; j++) {
-			/*
-			 * Generate an initial value for walking ones
-			 * test to test for bad
-			 * data bits
-			 */
-
-			Val = ~(1U << j);
-			/*
-			 * START walking zeros test
-			 * Write a one to each data bit indifferent locations
-			 */
-
-			for (I = 0U; I < (u32)16; I++) {
-				/* write memory location */
-				*(Addr+I) = Val;
-				Val = ~((u16)RotateLeft(~Val, 16U));
-			}
-			/*
-			 * Restore the reference 'Val' to the
-			 * initial value
-			 */
-			Val = ~(1U << j);
-			/* Read the values from each location that was written */
-			for (I = 0U; I < (u32)16; I++) {
-				/* read memory location */
-				WordMem16 = *(Addr+I);
-				if (WordMem16 != Val) {
-					Status = -1;
-					goto End_Label;
-				}
-				Val = ~((u16)RotateLeft(~Val, 16U));
-			}
-
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
-		/* Fill the memory with inverse of address */
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			Val = (u16) (~((INTPTR)(&Addr[I])));
-			*(Addr+I) = Val;
-		}
-		/*
-		 * Check every word within the words
-		 * of tested memory
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* read memory location */
-			WordMem16 = *(Addr+I);
-			Val = (u16) (~((INTPTR) (&Addr[I])));
-			if ((WordMem16 ^ Val) != 0x0000U) {
-				Status = -1;
-				goto End_Label;
-			}
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
-		/*
-		 * Generate an initial value for
-		 * memory testing
-		 */
-		if (Pattern == (u16)0) {
-			Val = 0xDEADU;
-		}
-		else {
-			Val = Pattern;
-		}
-
-		/*
-		 * Fill the memory with fixed pattern
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			*(Addr+I) = Val;
-		}
-
-		/*
-		 * Check every word within the words
-		 * of tested memory and compare it
-		 * with the fixed pattern
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* read memory location */
-			WordMem16 = *(Addr+I);
-			if (WordMem16 != Val) {
-				Status = -1;
-				goto End_Label;
-			}
-		}
-	}
-
-End_Label:
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 8-bit wide memory test.
-*
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
-*           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
-{
-	u32 I;
-	u32 j;
-	u8 Val;
-	u8 FirtVal;
-	u8 WordMem8;
-	s32 Status = 0;
-
-	Xil_AssertNonvoid(Words != (u32)0);
-	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-	Xil_AssertNonvoid(Addr != NULL);
-
-	/*
-	 * variable initialization
-	 */
-	Val = XIL_TESTMEM_INIT_VALUE;
-	FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-	/*
-	 * select the proper Subtest(s)
-	 */
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
-		/*
-		 * Fill the memory with incrementing
-		 * values starting from 'FirtVal'
-		 */
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			*(Addr+I) = Val;
-			Val++;
-		}
-		/*
-		 * Restore the reference 'Val' to the
-		 * initial value
-		 */
-		Val = FirtVal;
-		/*
-		 * Check every word within the words
-		 * of tested memory and compare it
-		 * with the incrementing reference
-		 * Val
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* read memory location */
-			WordMem8 = *(Addr+I);
-			if (WordMem8 != Val) {
-				Status = -1;
-				goto End_Label;
-			}
-			Val++;
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
-		/*
-		 * set up to cycle through all possible initial
-		 * test Patterns for walking ones test
-		 */
-
-		for (j = 0U; j < (u32)8; j++) {
-			/*
-			 * Generate an initial value for walking ones test
-			 * to test for bad data bits
-			 */
-			Val = (u8)((u32)1 << j);
-			/*
-			 * START walking ones test
-			 * Write a one to each data bit indifferent locations
-			 */
-			for (I = 0U; I < (u32)8; I++) {
-				/* write memory location */
-				*(Addr+I) = Val;
-				Val = (u8)RotateLeft(Val, 8U);
-			}
-			/*
-			 * Restore the reference 'Val' to the
-			 * initial value
-			 */
-			Val = (u8)((u32)1 << j);
-			/* Read the values from each location that was written */
-			for (I = 0U; I < (u32)8; I++) {
-				/* read memory location */
-				WordMem8 = *(Addr+I);
-				if (WordMem8 != Val) {
-					Status = -1;
-					goto End_Label;
-				}
-				Val = (u8)RotateLeft(Val, 8U);
-			}
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
-		/*
-		 * set up to cycle through all possible initial test
-		 * Patterns for walking zeros test
-		 */
-
-		for (j = 0U; j < (u32)8; j++) {
-			/*
-			 * Generate an initial value for walking ones test to test
-			 * for bad data bits
-			 */
-			Val = ~(1U << j);
-			/*
-			 * START walking zeros test
-			 * Write a one to each data bit indifferent locations
-			 */
-			for (I = 0U; I < (u32)8; I++) {
-				/* write memory location */
-				*(Addr+I) = Val;
-				Val = ~((u8)RotateLeft(~Val, 8U));
-			}
-			/*
-			 * Restore the reference 'Val' to the
-			 * initial value
-			 */
-			Val = ~(1U << j);
-			/* Read the values from each location that was written */
-			for (I = 0U; I < (u32)8; I++) {
-				/* read memory location */
-				WordMem8 = *(Addr+I);
-				if (WordMem8 != Val) {
-					Status = -1;
-					goto End_Label;
-				}
-
-				Val = ~((u8)RotateLeft(~Val, 8U));
-			}
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
-		/* Fill the memory with inverse of address */
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			Val = (u8) (~((INTPTR) (&Addr[I])));
-			*(Addr+I) = Val;
-		}
-
-		/*
-		 * Check every word within the words
-		 * of tested memory
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* read memory location */
-			WordMem8 = *(Addr+I);
-			Val = (u8) (~((INTPTR) (&Addr[I])));
-			if ((WordMem8 ^ Val) != 0x00U) {
-				Status = -1;
-				goto End_Label;
-			}
-		}
-	}
-
-	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
-		/*
-		 * Generate an initial value for
-		 * memory testing
-		 */
-
-		if (Pattern == (u8)0) {
-			Val = 0xA5U;
-		}
-		else {
-			Val = Pattern;
-		}
-		/*
-		 * Fill the memory with fixed Pattern
-		 */
-		for (I = 0U; I < Words; I++) {
-			/* write memory location */
-			*(Addr+I) = Val;
-		}
-		/*
-		 * Check every word within the words
-		 * of tested memory and compare it
-		 * with the fixed Pattern
-		 */
-
-		for (I = 0U; I < Words; I++) {
-			/* read memory location */
-			WordMem8 = *(Addr+I);
-			if (WordMem8 != Val) {
-				Status = -1;
-				goto End_Label;
-			}
-		}
-	}
-
-End_Label:
-	return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Rotates the provided value to the left one bit position
-*
-* @param    Input is value to be rotated to the left
-* @param    Width is the number of bits in the input data
-*
-* @return
-*
-* The resulting unsigned long value of the rotate left
-*
-* @note
-*
-* None.
-*
-*****************************************************************************/
-static u32 RotateLeft(u32 Input, u8 Width)
-{
-	u32 Msb;
-	u32 ReturnVal;
-	u32 WidthMask;
-	u32 MsbMask;
-	u32 LocalInput = Input;
-
-	/*
-	 * set up the WidthMask and the MsbMask
-	 */
-
-	MsbMask = 1U << (Width - 1U);
-
-	WidthMask = (MsbMask << (u32)1) - (u32)1;
-
-	/*
-	 * set the Width of the Input to the correct width
-	 */
-
-	LocalInput = LocalInput & WidthMask;
-
-	Msb = LocalInput & MsbMask;
-
-	ReturnVal = LocalInput << 1U;
-
-	if (Msb != 0x00000000U) {
-		ReturnVal = ReturnVal | (u32)0x00000001;
-	}
-
-	ReturnVal = ReturnVal & WidthMask;
-
-	return ReturnVal;
-
-}
-
-#ifdef ROTATE_RIGHT
-/*****************************************************************************/
-/**
-*
-* Rotates the provided value to the right one bit position
-*
-* @param    Input is value to be rotated to the right
-* @param    Width is the number of bits in the input data
-*
-* @return
-*
-* The resulting u32 value of the rotate right
-*
-* @note
-*
-* None.
-*
-*****************************************************************************/
-static u32 RotateRight(u32 Input, u8 Width)
-{
-	u32 Lsb;
-	u32 ReturnVal;
-	u32 WidthMask;
-	u32 MsbMask;
-	u32 LocalInput = Input;
-	/*
-	 * set up the WidthMask and the MsbMask
-	 */
-
-	MsbMask = 1U << (Width - 1U);
-
-	WidthMask = (MsbMask << 1U) - 1U;
-
-	/*
-	 * set the width of the input to the correct width
-	 */
-
-	LocalInput = LocalInput & WidthMask;
-
-	ReturnVal = LocalInput >> 1U;
-
-	Lsb = LocalInput & 0x00000001U;
-
-	if (Lsb != 0x00000000U) {
-		ReturnVal = ReturnVal | MsbMask;
-	}
-
-	ReturnVal = ReturnVal & WidthMask;
-
-	return ReturnVal;
-
-}
-#endif /* ROTATE_RIGHT */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h
deleted file mode 100644
index 4cbfd878b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-*
-* This file contains utility functions to test memory.
-*
-* <b>Memory test description</b>
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* Subtest descriptions:
-* <pre>
-* XIL_TESTMEM_ALLMEMTESTS:
-*       Runs all of the following tests
-*
-* XIL_TESTMEM_INCREMENT:
-*       Incrementing Value Test.
-*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
-*	incrementing value as the test value for memory.
-*
-* XIL_TESTMEM_WALKONES:
-*       Walking Ones Test.
-*       This test uses a walking '1' as the test value for memory.
-*       location 1 = 0x00000001
-*       location 2 = 0x00000002
-*       ...
-*
-* XIL_TESTMEM_WALKZEROS:
-*       Walking Zero's Test.
-*       This test uses the inverse value of the walking ones test
-*       as the test value for memory.
-*       location 1 = 0xFFFFFFFE
-*       location 2 = 0xFFFFFFFD
-*       ...
-*
-* XIL_TESTMEM_INVERSEADDR:
-*       Inverse Address Test.
-*       This test uses the inverse of the address of the location under test
-*       as the test value for memory.
-*
-* XIL_TESTMEM_FIXEDPATTERN:
-*       Fixed Pattern Test.
-*       This test uses the provided patters as the test value for memory.
-*       If zero is provided as the pattern the test uses '0xDEADBEEF".
-* </pre>
-*
-* <i>WARNING</i>
-*
-* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
-* have been set up.
-*
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm  08/25/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
-#define XIL_TESTMEM_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* xutil_memtest defines */
-
-#define XIL_TESTMEM_INIT_VALUE	1U
-
-/** @name Memory subtests
- * @{
- */
-/**
- * See the detailed description of the subtests in the file description.
- */
-#define XIL_TESTMEM_ALLMEMTESTS     0x00U
-#define XIL_TESTMEM_INCREMENT       0x01U
-#define XIL_TESTMEM_WALKONES        0x02U
-#define XIL_TESTMEM_WALKZEROS       0x03U
-#define XIL_TESTMEM_INVERSEADDR     0x04U
-#define XIL_TESTMEM_FIXEDPATTERN    0x05U
-#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/* xutil_testmem prototypes */
-
-extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h
deleted file mode 100644
index e8b78b7c6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* This file contains basic types for Xilinx software IP.
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/14/09 First release
-* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
-*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
-*		      Define LONG and ULONG datatypes and mask values
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TYPES_H	/* prevent circular inclusions */
-#define XIL_TYPES_H	/* by using protection macros */
-
-#include <stdint.h>
-#include <stddef.h>
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#  define TRUE		1U
-#endif
-
-#ifndef FALSE
-#  define FALSE		0U
-#endif
-
-#ifndef NULL
-#define NULL		0U
-#endif
-
-#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
-#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/**
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-
-#define __XUINT64__
-typedef struct
-{
-	u32 Upper;
-	u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* Return the most significant half of the 64 bit data type.
-*
-* @param    x is the 64 bit word.
-*
-* @return   The upper 32 bits of the 64 bit word.
-*
-* @note     None.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* Return the least significant half of the 64 bit data type.
-*
-* @param    x is the 64 bit word.
-*
-* @return   The lower 32 bits of the 64 bit word.
-*
-* @note     None.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/**
- * xbasic_types.h does not typedef s* or u64
- */
-
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK	~ULONG64_HI_MASK
-
-#else
-#include <linux/types.h>
-#endif
-
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * UPPER_32_BITS - return bits 32-63 of a number
- * @n: the number we're accessing
- *
- * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
- * the "right shift count >= width of type" warning when that quantity is
- * 32-bits.
- */
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-
-/**
- * LOWER_32_BITS - return bits 0-31 of a number
- * @n: the number we're accessing
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-/*@}*/
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE		1U
-#endif
-
-#ifndef FALSE
-#define FALSE		0U
-#endif
-
-#ifndef NULL
-#define NULL		0U
-#endif
-
-#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h
deleted file mode 100644
index 91d6b6408..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex R5 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00  pkp  	02/29/14 Initial version
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XPARAMETERS_PS_H_
-#define XPARAMETERS_PS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock
- */
-
-/* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR		0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
-
-/* Canonical definitions for Interrupts  */
-#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
-#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
-#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
-#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
-#define XPAR_XEMACPS_2_INTR		XPS_GEM2_INT_ID
-#define XPAR_XEMACPS_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
-#define XPAR_XEMACPS_3_INTR		XPS_GEM3_INT_ID
-#define XPAR_XEMACPS_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
-#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
-#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
-#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
-#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
-#define XPAR_XTTCPS_6_INTR		XPS_TTC2_0_INT_ID
-#define XPAR_XTTCPS_7_INTR		XPS_TTC2_1_INT_ID
-#define XPAR_XTTCPS_8_INTR		XPS_TTC2_2_INT_ID
-#define XPAR_XTTCPS_9_INTR		XPS_TTC3_0_INT_ID
-#define XPAR_XTTCPS_10_INTR		XPS_TTC3_1_INT_ID
-#define XPAR_XTTCPS_11_INTR		XPS_TTC3_2_INT_ID
-#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
-#define XPAR_XNANDPS8_0_INTR        	XPS_NAND_INT_ID
-#define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
-#define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
-#define XPAR_XADMAPS_2_INTR		XPS_ADMA_CH2_INT_ID
-#define XPAR_XADMAPS_3_INTR 		XPS_ADMA_CH3_INT_ID
-#define XPAR_XADMAPS_4_INTR		XPS_ADMA_CH4_INT_ID
-#define XPAR_XADMAPS_5_INTR 		XPS_ADMA_CH5_INT_ID
-#define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
-#define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
-#define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
-#define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
-#define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
-#define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
-#define XPAR_XZDMAPS_2_INTR 		XPS_ZDMA_CH2_INT_ID
-#define XPAR_XZDMAPS_3_INTR 		XPS_ZDMA_CH3_INT_ID
-#define XPAR_XZDMAPS_4_INTR		XPS_ZDMA_CH4_INT_ID
-#define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
-#define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
-#define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
-#define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
-#define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
-#define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
-#define XPAR_XUSBPS_0_INTR		XPS_USB3_0_ENDPT_INT_ID
-#define XPAR_XUSBPS_1_INTR		XPS_USB3_1_ENDPT_INT_ID
-#define	XPAR_XRTCPSU_ALARM_INTR 	XPS_RTC_ALARM_INT_ID
-#define	XPAR_XRTCPSU_SECONDS_INTR	XPS_RTC_SEC_INT_ID
-#define XPAR_XAPMPS_0_INTR		XPS_APM0_INT_ID
-#define XPAR_XAPMPS_1_INTR		XPS_APM1_INT_ID
-#define XPAR_XAPMPS_2_INTR		XPS_APM2_INT_ID
-#define XPAR_XAPMPS_5_INTR		XPS_APM5_INT_ID
-#define XPAR_XSYSMONPSU_INTR		XPS_AMS_INT_ID
-
-/* Canonical definitions for SCU GIC */
-#define XPAR_SCUGIC_NUM_INSTANCES	1U
-#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
-#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
-#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00002000U)
-#define XPAR_SCUGIC_ACK_BEFORE		0U
-
-#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
-
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock. These have been put for bacwards compatibilty
- */
-
-#define XPS_SYS_CTRL_BASEADDR	0xFF180000U
-#define XPS_SCU_PERIPH_BASE		0xF9000000U
-
-
-/* Shared Peripheral Interrupts (SPI) */
-
-/* FIXME */
-/*#define XPS_FPGA0_INT_ID		100U */
-#define XPS_FPGA1_INT_ID		62U
-#define XPS_FPGA2_INT_ID		63U
-#define XPS_FPGA3_INT_ID		64U
-#define XPS_FPGA4_INT_ID		65U
-#define XPS_FPGA5_INT_ID		66U
-#define XPS_FPGA6_INT_ID		67U
-#define XPS_FPGA7_INT_ID		68U
-#define XPS_DMA4_INT_ID			72U
-#define XPS_DMA5_INT_ID			73U
-#define XPS_DMA6_INT_ID			74U
-#define XPS_DMA7_INT_ID			75U
-#define XPS_FPGA8_INT_ID		84U
-#define XPS_FPGA9_INT_ID		85U
-#define XPS_FPGA10_INT_ID		86U
-#define XPS_FPGA11_INT_ID		87U
-#define XPS_FPGA12_INT_ID		88U
-#define XPS_FPGA13_INT_ID		89U
-#define XPS_FPGA14_INT_ID		90U
-#define XPS_FPGA15_INT_ID		91U
-
-/* Updated Interrupt-IDs */
-#define XPS_OCMINTR_INT_ID		(10U + 32U)
-#define XPS_NAND_INT_ID        		(14U + 32U)
-#define XPS_QSPI_INT_ID			(15U + 32U)
-#define XPS_GPIO_INT_ID			(16U + 32U)
-#define XPS_I2C0_INT_ID			(17U + 32U)
-#define XPS_I2C1_INT_ID			(18U + 32U)
-#define XPS_SPI0_INT_ID			(19U + 32U)
-#define XPS_SPI1_INT_ID			(20U + 32U)
-#define XPS_UART0_INT_ID		(21U + 32U)
-#define XPS_UART1_INT_ID		(22U + 32U)
-#define XPS_CAN0_INT_ID			(23U + 32U)
-#define XPS_CAN1_INT_ID			(24U + 32U)
-#define	XPS_RTC_ALARM_INT_ID 	(26U + 32U)
-#define	XPS_RTC_SEC_INT_ID	 	(27U + 32U)
-#define XPS_WDT_INT_ID			(52U + 32U)
-#define XPS_TTC0_0_INT_ID		(36U + 32U)
-#define XPS_TTC0_1_INT_ID		(37U + 32U)
-#define XPS_TTC0_2_INT_ID 		(38U + 32U)
-#define XPS_TTC1_0_INT_ID		(39U + 32U)
-#define XPS_TTC1_1_INT_ID		(40U + 32U)
-#define XPS_TTC1_2_INT_ID		(41U + 32U)
-#define XPS_TTC2_0_INT_ID		(42U + 32U)
-#define XPS_TTC2_1_INT_ID		(43U + 32U)
-#define XPS_TTC2_2_INT_ID		(44U + 32U)
-#define XPS_TTC3_0_INT_ID		(45U + 32U)
-#define XPS_TTC3_1_INT_ID		(46U + 32U)
-#define XPS_TTC3_2_INT_ID		(47U + 32U)
-#define XPS_SDIO0_INT_ID		(48U + 32U)
-#define XPS_SDIO1_INT_ID		(49U + 32U)
-#define XPS_AMS_INT_ID			(56U + 32U)
-#define XPS_GEM0_INT_ID			(57U + 32U)
-#define XPS_GEM0_WAKE_INT_ID		(58U + 32U)
-#define XPS_GEM1_INT_ID			(59U + 32U)
-#define XPS_GEM1_WAKE_INT_ID		(60U + 32U)
-#define XPS_GEM2_INT_ID			(61U + 32U)
-#define XPS_GEM2_WAKE_INT_ID		(62U + 32U)
-#define XPS_GEM3_INT_ID			(63U + 32U)
-#define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
-#define XPS_USB3_0_ENDPT_INT_ID		(65U + 32U)
-#define XPS_USB3_1_ENDPT_INT_ID		(70U + 32U)
-#define XPS_ADMA_CH0_INT_ID		(77U + 32U)
-#define XPS_ADMA_CH1_INT_ID		(78U + 32U)
-#define XPS_ADMA_CH2_INT_ID		(79U + 32U)
-#define XPS_ADMA_CH3_INT_ID		(80U + 32U)
-#define XPS_ADMA_CH4_INT_ID		(81U + 32U)
-#define XPS_ADMA_CH5_INT_ID		(82U + 32U)
-#define XPS_ADMA_CH6_INT_ID		(83U + 32U)
-#define XPS_ADMA_CH7_INT_ID		(84U + 32U)
-#define XPS_CSU_DMA_INT_ID		(86U + 32U)
-#define XPS_XMPU_LPD_INT_ID		(88U + 32U)
-#define XPS_ZDMA_CH0_INT_ID		(124U + 32U)
-#define XPS_ZDMA_CH1_INT_ID		(125U + 32U)
-#define XPS_ZDMA_CH2_INT_ID		(126U + 32U)
-#define XPS_ZDMA_CH3_INT_ID		(127U + 32U)
-#define XPS_ZDMA_CH4_INT_ID		(128U + 32U)
-#define XPS_ZDMA_CH5_INT_ID		(129U + 32U)
-#define XPS_ZDMA_CH6_INT_ID		(130U + 32U)
-#define XPS_ZDMA_CH7_INT_ID		(131U + 32U)
-#define XPS_XMPU_FPD_INT_ID		(134U + 32U)
-#define XPS_FPD_CCI_INT_ID		(154U + 32U)
-#define XPS_FPD_SMMU_INT_ID		(155U + 32U)
-#define XPS_APM0_INT_ID		(123U + 32U)
-#define XPS_APM1_INT_ID		(25U + 32U)
-#define XPS_APM2_INT_ID		(25U + 32U)
-#define XPS_APM5_INT_ID		(123U + 32U)
-
-/* REDEFINES for TEST APP */
-/* Definitions for UART */
-#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
-#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
-#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
-#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
-#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
-#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
-#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
-#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
-#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
-#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
-#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
-#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
-#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
-#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_2_INTR	XPS_GEM2_INT_ID
-#define XPAR_PS7_ETHERNET_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_3_INTR	XPS_GEM3_INT_ID
-#define XPAR_PS7_ETHERNET_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
-
-#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
-#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
-#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
-#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
-#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
-
-#define XPAR_PSU_UART_0_INTR        XPS_UART0_INT_ID
-#define XPAR_PSU_UART_1_INTR        XPS_UART1_INT_ID
-#define XPAR_PSU_USB_0_INTR     XPS_USB0_INT_ID
-#define XPAR_PSU_USB_1_INTR     XPS_USB1_INT_ID
-#define XPAR_PSU_I2C_0_INTR     XPS_I2C0_INT_ID
-#define XPAR_PSU_I2C_1_INTR     XPS_I2C1_INT_ID
-#define XPAR_PSU_SPI_0_INTR     XPS_SPI0_INT_ID
-#define XPAR_PSU_SPI_1_INTR     XPS_SPI1_INT_ID
-#define XPAR_PSU_CAN_0_INTR     XPS_CAN0_INT_ID
-#define XPAR_PSU_CAN_1_INTR     XPS_CAN1_INT_ID
-#define XPAR_PSU_GPIO_0_INTR        XPS_GPIO_INT_ID
-#define XPAR_PSU_ETHERNET_0_INTR    XPS_GEM0_INT_ID
-#define XPAR_PSU_ETHERNET_0_WAKE_INTR   XPS_GEM0_WAKE_INT_ID
-#define XPAR_PSU_ETHERNET_1_INTR    XPS_GEM1_INT_ID
-#define XPAR_PSU_ETHERNET_1_WAKE_INTR   XPS_GEM1_WAKE_INT_ID
-#define XPAR_PSU_ETHERNET_2_INTR    XPS_GEM2_INT_ID
-#define XPAR_PSU_ETHERNET_2_WAKE_INTR   XPS_GEM2_WAKE_INT_ID
-#define XPAR_PSU_ETHERNET_3_INTR    XPS_GEM3_INT_ID
-#define XPAR_PSU_ETHERNET_3_WAKE_INTR   XPS_GEM3_WAKE_INT_ID
-#define XPAR_PSU_QSPI_0_INTR        XPS_QSPI_INT_ID
-#define XPAR_PSU_WDT_0_INTR     XPS_WDT_INT_ID
-#define XPAR_PSU_SCUWDT_0_INTR      XPS_SCU_WDT_INT_ID
-#define XPAR_PSU_SCUTIMER_0_INTR    XPS_SCU_TMR_INT_ID
-#define XPAR_PSU_XADC_0_INTR        XPS_SYSMON_INT_ID
-#define XPAR_PSU_TTC_0_INTR         XPS_TTC0_0_INT_ID
-#define XPAR_PSU_TTC_1_INTR         XPS_TTC0_1_INT_ID
-#define XPAR_PSU_TTC_2_INTR         XPS_TTC0_2_INT_ID
-#define XPAR_PSU_TTC_3_INTR         XPS_TTC1_0_INT_ID
-#define XPAR_PSU_TTC_4_INTR         XPS_TTC1_1_INT_ID
-#define XPAR_PSU_TTC_5_INTR         XPS_TTC1_2_INT_ID
-#define XPAR_PSU_TTC_6_INTR			XPS_TTC2_0_INT_ID
-#define XPAR_PSU_TTC_7_INTR			XPS_TTC2_1_INT_ID
-#define XPAR_PSU_TTC_8_INTR			XPS_TTC2_2_INT_ID
-#define XPAR_PSU_TTC_9_INTR			XPS_TTC3_0_INT_ID
-#define XPAR_PSU_TTC_10_INTR		XPS_TTC3_1_INT_ID
-#define XPAR_PSU_TTC_11_INTR		XPS_TTC3_2_INT_ID
-
-#define XPAR_XADCPS_NUM_INSTANCES 1U
-#define XPAR_XADCPS_0_DEVICE_ID   0U
-#define XPAR_XADCPS_0_BASEADDR	  (0xF8007000U)
-#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
-
-/* For backwards compatibilty */
-#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
-
-#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
-
-#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
-#endif
-
-#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
-#endif
-
-#define XPAR_SCUWDT_DEVICE_ID		0U
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c
deleted file mode 100644
index fea992e40..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.c
-*
-* This file contains information about hardware for which the code is built
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00  pkp  12/15/14 Initial release
-* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
-*					  mode
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* This API is used to provide information about platform
-*
-* @param    None.
-*
-* @return   The information about platform defined in xplatform_info.h
-*
-* @note     None.
-*
-******************************************************************************/
-u32 XGetPlatform_Info()
-{
-	u32 reg;
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-	return XPLAT_ZYNQ_ULTRA_MP;
-#elif (__microblaze__)
-	return XPLAT_MICROBLAZE;
-#else
-	return XPLAT_ZYNQ;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* This API is used to provide information about zynq ultrascale MP platform
-*
-* @param    None.
-*
-* @return   The information about zynq ultrascale MP platform defined in
-*			xplatform_info.h
-*
-* @note     None.
-*
-******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info()
-{
-	u32 reg;
-	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
-	return reg;
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API is used to provide information about PS Silicon version
-*
-* @param    None.
-*
-* @return   The information about PS Silicon version.
-*
-* @note     None.
-*
-******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGetPSVersion_Info()
-{
-	u32 reg;
-	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
-			& XPS_VERSION_INFO_MASK);
-	return reg;
-}
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h
deleted file mode 100644
index 7028a83af..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-* This file contains definitions for various platforms available
-*
-******************************************************************************/
-
-#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
-#define XPLATFORM_INFO_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define	XPAR_CSU_VER_OFFSET 0x00000044U
-
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-
-#define XPLAT_INFO_MASK (0xF)
-#define XPS_VERSION_INFO_MASK (0xF)
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info();
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGetPSVersion_Info();
-#endif
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info();
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c
deleted file mode 100644
index 0851408cc..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.c
-*
-* This file contains APIs for configuring and controlling the Cortex-R5
-* Performance Monitor Events. For more information about the event counters,
-* see xpm_counter.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xpm_counter.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-
-
-/************************** Function Prototypes ******************************/
-
-void Xpm_DisableEventCounters(void);
-void Xpm_EnableEventCounters (void);
-void Xpm_ResetEventCounters (void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* This function disables the Cortex R5 event counters.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void Xpm_DisableEventCounters(void)
-{
-	/* Disable the event counters */
-	mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the Cortex R5 event counters.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void Xpm_EnableEventCounters(void)
-{
-	/* Enable the event counters */
-	mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* This function resets the Cortex R5 event counters.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void Xpm_ResetEventCounters(void)
-{
-	u32 Reg;
-
-#ifdef __GNUC__
-	Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
-#else
-	{ register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
-	  Reg = C15Reg; }
-#endif
-	Reg |= (1U << 2U); /* reset event counters */
-	mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function configures the Cortex R5 event counters controller, with the
-* event codes, in a configuration selected by the user and enables the counters.
-*
-* @param	PmcrCfg is configuration value based on which the event counters
-*		are configured.
-*		Use XPM_CNTRCFG* values defined in xpm_counter.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void Xpm_SetEvents(s32 PmcrCfg)
-{
-	u32 Counter;
-	static PmcrEventCfg32 PmcrEvents[] = {
-		{
-			XPM_EVENT_SOFTINCR,
-			XPM_EVENT_INSRFETCH_CACHEREFILL,
-			XPM_EVENT_INSTRFECT_TLBREFILL,
-			XPM_EVENT_DATA_CACHEREFILL,
-			XPM_EVENT_DATA_CACHEACCESS,
-			XPM_EVENT_DATA_TLBREFILL
-		},
-		{
-			XPM_EVENT_DATA_READS,
-			XPM_EVENT_DATA_WRITE,
-			XPM_EVENT_EXCEPTION,
-			XPM_EVENT_EXCEPRETURN,
-			XPM_EVENT_CHANGECONTEXT,
-			XPM_EVENT_SW_CHANGEPC
-		},
-		{
-			XPM_EVENT_IMMEDBRANCH,
-			XPM_EVENT_UNALIGNEDACCESS,
-			XPM_EVENT_BRANCHMISS,
-			XPM_EVENT_CLOCKCYCLES,
-			XPM_EVENT_BRANCHPREDICT,
-			XPM_EVENT_JAVABYTECODE
-		},
-		{
-			XPM_EVENT_SWJAVABYTECODE,
-			XPM_EVENT_JAVABACKBRANCH,
-			XPM_EVENT_COHERLINEMISS,
-			XPM_EVENT_COHERLINEHIT,
-			XPM_EVENT_INSTRSTALL,
-			XPM_EVENT_DATASTALL
-		},
-		{
-			XPM_EVENT_MAINTLBSTALL,
-			XPM_EVENT_STREXPASS,
-			XPM_EVENT_STREXFAIL,
-			XPM_EVENT_DATAEVICT,
-			XPM_EVENT_NODISPATCH,
-			XPM_EVENT_ISSUEEMPTY
-		},
-		{
-			XPM_EVENT_INSTRRENAME,
-			XPM_EVENT_PREDICTFUNCRET,
-			XPM_EVENT_MAINEXEC,
-			XPM_EVENT_SECEXEC,
-			XPM_EVENT_LDRSTR,
-			XPM_EVENT_FLOATRENAME
-		},
-		{
-			XPM_EVENT_NEONRENAME,
-			XPM_EVENT_PLDSTALL,
-			XPM_EVENT_WRITESTALL,
-			XPM_EVENT_INSTRTLBSTALL,
-			XPM_EVENT_DATATLBSTALL,
-			XPM_EVENT_INSTR_uTLBSTALL
-		},
-		{
-			XPM_EVENT_DATA_uTLBSTALL,
-			XPM_EVENT_DMB_STALL,
-			XPM_EVENT_INT_CLKEN,
-			XPM_EVENT_DE_CLKEN,
-			XPM_EVENT_INSTRISB,
-			XPM_EVENT_INSTRDSB
-		},
-		{
-			XPM_EVENT_INSTRDMB,
-			XPM_EVENT_EXTINT,
-			XPM_EVENT_PLE_LRC,
-			XPM_EVENT_PLE_LRS,
-			XPM_EVENT_PLE_FLUSH,
-			XPM_EVENT_PLE_CMPL
-		},
-		{
-			XPM_EVENT_PLE_OVFL,
-			XPM_EVENT_PLE_PROG,
-			XPM_EVENT_PLE_LRC,
-			XPM_EVENT_PLE_LRS,
-			XPM_EVENT_PLE_FLUSH,
-			XPM_EVENT_PLE_CMPL
-		},
-		{
-			XPM_EVENT_DATASTALL,
-			XPM_EVENT_INSRFETCH_CACHEREFILL,
-			XPM_EVENT_INSTRFECT_TLBREFILL,
-			XPM_EVENT_DATA_CACHEREFILL,
-			XPM_EVENT_DATA_CACHEACCESS,
-			XPM_EVENT_DATA_TLBREFILL
-		},
-	};
-	const u32 *ptr = PmcrEvents[PmcrCfg];
-
-	Xpm_DisableEventCounters();
-
-	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
-		/* Selecet event counter */
-		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-
-		/* Set the event */
-		mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
-	}
-
-	Xpm_ResetEventCounters();
-	Xpm_EnableEventCounters();
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the event counters and returns the counter values.
-*
-* @param	PmCtrValue is a pointer to an array of type u32 PmCtrValue[6].
-*		It is an output parameter which is used to return the PM
-*		counter values.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void Xpm_GetEventCounters(u32 *PmCtrValue)
-{
-	u32 Counter;
-
-	Xpm_DisableEventCounters();
-
-	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
-		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-#ifdef __GNUC__
-		PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#else
-		{ register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
-		  PmCtrValue[Counter] = Cp15Reg; }
-#endif
-	}
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h
deleted file mode 100644
index 5679d4bb5..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* This header file contains APIs for configuring and controlling the Cortex-R5
-* Performance Monitor Events.
-* Cortex-R5 Performance Monitor has 6 event counters which can be used to
-* count a variety of events described in Coretx-R5 TRM. This file defines
-* configurations, where value configures the event counters to count a
-* set of events.
-*
-* Xpm_SetEvents can be used to set the event counters to count a set of events
-* and Xpm_GetEventCounters can be used to read the counter values.
-*
-* @note
-*
-* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include <stdint.h>
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-R5 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-R5 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-R5 processor which also miss in all the other
- * Cortex-R5 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-R5 processor which hit in another Cortex-R5
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-R5 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- *    - b00 no instructions renamed
- *    - b01 one instruction renamed
- *    - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-R5 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config		PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
- *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
- *			  XPM_EVENT_INSTRFECT_TLBREFILL,
- *			  XPM_EVENT_DATA_CACHEREFILL,
- *			  XPM_EVENT_DATA_CACHEACCESS,
- *			  XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
- *			  XPM_EVENT_DATA_WRITE,
- *			  XPM_EVENT_EXCEPTION,
- *			  XPM_EVENT_EXCEPRETURN,
- *			  XPM_EVENT_CHANGECONTEXT,
- *			  XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
- *			  XPM_EVENT_UNALIGNEDACCESS,
- *			  XPM_EVENT_BRANCHMISS,
- *			  XPM_EVENT_CLOCKCYCLES,
- *			  XPM_EVENT_BRANCHPREDICT,
- *			  XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
- *			  XPM_EVENT_JAVABACKBRANCH,
- *			  XPM_EVENT_COHERLINEMISS,
- *			  XPM_EVENT_COHERLINEHIT,
- *			  XPM_EVENT_INSTRSTALL,
- *			  XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
- *			  XPM_EVENT_STREXPASS,
- *			  XPM_EVENT_STREXFAIL,
- *			  XPM_EVENT_DATAEVICT,
- *			  XPM_EVENT_NODISPATCH,
- *			  XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
- *			  XPM_EVENT_PREDICTFUNCRET,
- *			  XPM_EVENT_MAINEXEC,
- *			  XPM_EVENT_SECEXEC,
- *			  XPM_EVENT_LDRSTR,
- *			  XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
- *			  XPM_EVENT_PLDSTALL,
- *			  XPM_EVENT_WRITESTALL,
- *			  XPM_EVENT_INSTRTLBSTALL,
- *			  XPM_EVENT_DATATLBSTALL,
- *			  XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
- *			  XPM_EVENT_DMB_STALL,
- *			  XPM_EVENT_INT_CLKEN,
- *			  XPM_EVENT_DE_CLKEN,
- *			  XPM_EVENT_INSTRISB,
- *			  XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
- *			  XPM_EVENT_EXTINT,
- *			  XPM_EVENT_PLE_LRC,
- *			  XPM_EVENT_PLE_LRS,
- *			  XPM_EVENT_PLE_FLUSH,
- *			  XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
- *			  XPM_EVENT_PLE_PROG,
- *			  XPM_EVENT_PLE_LRC,
- *			  XPM_EVENT_PLE_LRS,
- *			  XPM_EVENT_PLE_FLUSH,
- *			  XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
- *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
- *			  XPM_EVENT_INSTRFECT_TLBREFILL,
- *			  XPM_EVENT_DATA_CACHEREFILL,
- *			  XPM_EVENT_DATA_CACHEACCESS,
- *			  XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1	0
-#define XPM_CNTRCFG2	1
-#define XPM_CNTRCFG3	2
-#define XPM_CNTRCFG4	3
-#define XPM_CNTRCFG5	4
-#define XPM_CNTRCFG6	5
-#define XPM_CNTRCFG7	6
-#define XPM_CNTRCFG8	7
-#define XPM_CNTRCFG9	8
-#define XPM_CNTRCFG10	9
-#define XPM_CNTRCFG11	10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface fuctions to access perfromance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
deleted file mode 100644
index aff19d5a9..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* This header file contains macros for using inline assembler code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* </pre>
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */
-#define XPSEUDO_ASM_H /* by using protection macros */
-
-#include "xreg_cortexr5.h"
-#include "xpseudo_asm_gcc.h"
-
-#endif /* XPSEUDO_ASM_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
deleted file mode 100644
index 2b382acb8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 05/29/14 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
-#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/* necessary for pre-processor */
-#define stringify(s)	tostring(s)
-#define tostring(s)	#s
-
-/* pseudo assembler instructions */
-#define mfcpsr()	({u32 rval; \
-			  __asm__ __volatile__(\
-			    "mrs	%0, cpsr\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })
-
-#define mtcpsr(v)	__asm__ __volatile__(\
-			  "msr	cpsr,%0\n"\
-			  : : "r" (v)\
-			)
-
-#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
-#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
-
-#define cpsief()	__asm__ __volatile__("cpsie	f\n")
-#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
-
-
-
-#define mtgpr(rn, v)	__asm__ __volatile__(\
-			  "mov r" stringify(rn) ", %0 \n"\
-			  : : "r" (v)\
-			)
-
-#define mfgpr(rn)	({u32 rval; \
-			  __asm__ __volatile__(\
-			    "mov %0,r" stringify(rn) "\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-
-/* Data Synchronization Barrier */
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-
-/* Data Memory Barrier */
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
-
-
-/* Memory Operations */
-#define ldr(adr)	({u32 rval; \
-			  __asm__ __volatile__(\
-			    "ldr	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
-
-#define ldrb(adr)	({u8 rval; \
-			  __asm__ __volatile__(\
-			    "ldrb	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
-
-#define str(adr, val)	__asm__ __volatile__(\
-			  "str	%0,[%1]\n"\
-			  : : "r" (val), "r" (adr)\
-			)
-
-#define strb(adr, val)	__asm__ __volatile__(\
-			  "strb	%0,[%1]\n"\
-			  : : "r" (val), "r" (adr)\
-			)
-
-/* Count leading zeroes (clz) */
-#define clz(arg)	({u8 rval; \
-			  __asm__ __volatile__(\
-			    "clz	%0,%1"\
-			    : "=r" (rval) : "r" (arg)\
-			  );\
-			  rval;\
-			 })
-
-/* CP15 operations */
-#define mtcp(rn, v)	__asm__ __volatile__(\
-			 "mcr " rn "\n"\
-			 : : "r" (v)\
-			);
-
-#define mfcp(rn)	({u32 rval; \
-			 __asm__ __volatile__(\
-			   "mrc " rn "\n"\
-			   : "=r" (rval)\
-			 );\
-			 rval;\
-			 })
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h
deleted file mode 100644
index 9d28c0acb..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h
+++ /dev/null
@@ -1,445 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexr5.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, IAR, ARMCC compiler.
-*
-* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* </pre>
-*
-******************************************************************************/
-#ifndef XREG_CORTEXR5_H	/* prevent circular inclusions */
-#define XREG_CORTEXR5_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* GPRs */
-#define XREG_GPR0				r0
-#define XREG_GPR1				r1
-#define XREG_GPR2				r2
-#define XREG_GPR3				r3
-#define XREG_GPR4				r4
-#define XREG_GPR5				r5
-#define XREG_GPR6				r6
-#define XREG_GPR7				r7
-#define XREG_GPR8				r8
-#define XREG_GPR9				r9
-#define XREG_GPR10				r10
-#define XREG_GPR11				r11
-#define XREG_GPR12				r12
-#define XREG_GPR13				r13
-#define XREG_GPR14				r14
-#define XREG_GPR15				r15
-#define XREG_CPSR				cpsr
-
-/* Coprocessor number defines */
-#define XREG_CP0				0
-#define XREG_CP1				1
-#define XREG_CP2				2
-#define XREG_CP3				3
-#define XREG_CP4				4
-#define XREG_CP5				5
-#define XREG_CP6				6
-#define XREG_CP7				7
-#define XREG_CP8				8
-#define XREG_CP9				9
-#define XREG_CP10				10
-#define XREG_CP11				11
-#define XREG_CP12				12
-#define XREG_CP13				13
-#define XREG_CP14				14
-#define XREG_CP15				15
-
-/* Coprocessor control register defines */
-#define XREG_CR0				cr0
-#define XREG_CR1				cr1
-#define XREG_CR2				cr2
-#define XREG_CR3				cr3
-#define XREG_CR4				cr4
-#define XREG_CR5				cr5
-#define XREG_CR6				cr6
-#define XREG_CR7				cr7
-#define XREG_CR8				cr8
-#define XREG_CR9				cr9
-#define XREG_CR10				cr10
-#define XREG_CR11				cr11
-#define XREG_CR12				cr12
-#define XREG_CR13				cr13
-#define XREG_CR14				cr14
-#define XREG_CR15				cr15
-
-/* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE			0x20U
-#define XREG_CPSR_MODE_BITS			0x1FU
-#define XREG_CPSR_SYSTEM_MODE			0x1FU
-#define XREG_CPSR_UNDEFINED_MODE		0x1BU
-#define XREG_CPSR_DATA_ABORT_MODE		0x17U
-#define XREG_CPSR_SVC_MODE			0x13U
-#define XREG_CPSR_IRQ_MODE			0x12U
-#define XREG_CPSR_FIQ_MODE			0x11U
-#define XREG_CPSR_USER_MODE			0x10U
-
-#define XREG_CPSR_IRQ_ENABLE			0x80U
-#define XREG_CPSR_FIQ_ENABLE			0x40U
-
-#define XREG_CPSR_N_BIT				0x80000000U
-#define XREG_CPSR_Z_BIT				0x40000000U
-#define XREG_CPSR_C_BIT				0x20000000U
-#define XREG_CPSR_V_BIT				0x10000000U
-
-/*MPU region definitions*/
-#define REGION_32B     0x00000004U
-#define REGION_64B     0x00000005U
-#define REGION_128B    0x00000006U
-#define REGION_256B    0x00000007U
-#define REGION_512B    0x00000008U
-#define REGION_1K      0x00000009U
-#define REGION_2K      0x0000000AU
-#define REGION_4K      0x0000000BU
-#define REGION_8K      0x0000000CU
-#define REGION_16K     0x0000000DU
-#define REGION_32K     0x0000000EU
-#define REGION_64K     0x0000000FU
-#define REGION_128K    0x00000010U
-#define REGION_256K    0x00000011U
-#define REGION_512K    0x00000012U
-#define REGION_1M      0x00000013U
-#define REGION_2M      0x00000014U
-#define REGION_4M      0x00000015U
-#define REGION_8M      0x00000016U
-#define REGION_16M     0x00000017U
-#define REGION_32M     0x00000018U
-#define REGION_64M     0x00000019U
-#define REGION_128M    0x0000001AU
-#define REGION_256M    0x0000001BU
-#define REGION_512M    0x0000001CU
-#define REGION_1G      0x0000001DU
-#define REGION_2G      0x0000001EU
-#define REGION_4G      0x0000001FU
-
-#define REGION_EN  0x00000001U
-
-
-
-#define SHAREABLE				0x00000004U 	/*shareable */
-#define STRONG_ORDERD_SHARED	0x00000000U	/*strongly ordered, always shareable*/
-
-#define DEVICE_SHARED			0x00000001U	/*device, shareable*/
-#define DEVICE_NONSHARED		0x00000010U	/*device, non shareable*/
-
-#define NORM_NSHARED_WT_NWA		0x00000002U 	/*Outer and Inner write-through, no write-allocate non-shareable*/
-#define NORM_SHARED_WT_NWA		0x00000006U 	/*Outer and Inner write-through, no write-allocate shareable*/
-
-#define NORM_NSHARED_WB_NWA 	0x00000003U 	/*Outer and Inner write-back, no write-allocate non shareable*/
-#define NORM_SHARED_WB_NWA 		0x00000007U 	/*Outer and Inner write-back, no write-allocate shareable*/
-
-#define NORM_NSHARED_NCACHE 	0x00000008U 	/*Outer and Inner Non cacheable  non shareable*/
-#define NORM_SHARED_NCACHE 		0x0000000CU 	/*Outer and Inner Non cacheable shareable*/
-
-#define NORM_NSHARED_WB_WA 		0x0000000BU 	/*Outer and Inner write-back non shared*/
-#define NORM_SHARED_WB_WA 		0x0000000FU 	/*Outer and Inner write-back shared*/
-
-/* inner and outer cache policies can be combined for different combinations */
-
-#define NORM_IN_POLICY_NCACHE	0x00000020U	/*inner non cacheable*/
-#define NORM_IN_POLICY_WB_WA	0x00000021U	/*inner write back write allocate*/
-#define NORM_IN_POLICY_WT_NWA	0x00000022U	/*inner write through no write allocate*/
-#define NORM_IN_POLICY_WB_NWA	0x00000023U	/*inner write back no write allocate*/
-
-#define NORM_OUT_POLICY_NCACHE	0x00000020U	/*outer non cacheable*/
-#define NORM_OUT_POLICY_WB_WA	0x00000028U	/*outer write back write allocate*/
-#define NORM_OUT_POLICY_WT_NWA	0x00000030U	/*outer write through no write allocate*/
-#define NORM_OUT_POLICY_WB_NWA	0x00000038U	/*outer write back no write allocate*/
-
-#define NO_ACCESS				(0x00000000U<<8U)	/*No access*/
-#define PRIV_RW_USER_NA			(0x00000001U<<8U) /*Privileged access only*/
-#define PRIV_RW_USER_RO			(0x00000002U<<8U) /*Writes in User mode generate permission faults*/
-#define	PRIV_RW_USER_RW			(0x00000003U<<8U)	/*Full Access*/
-#define PRIV_RO_USER_NA			(0x00000005U<<8U) /*Privileged eead only*/
-#define PRIV_RO_USER_RO			(0x00000006U<<8U) /*Privileged/User read-only*/
-
-#define EXECUTE_NEVER  			(0x00000001U<<12U)  /* Bit 12*/
-
-
-/* CP15 defines */
-
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
-#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
-#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
-#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
-#define XREG_CP15_MPU_TYPE			"p15, 0, %0,  c0,  c0, 4"
-#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
-
-#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
-#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
-#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
-#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
-#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
-#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
-#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
-
-#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
-#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
-#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
-#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
-#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
-#define XREG_CP15_INST_FEATURE_5		"p15, 0, %0,  c0,  c2, 5"
-
-#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
-#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
-#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
-
-#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
-#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
-#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
-
-
-/* XREG_CP15_CONTROL bit defines */
-#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
-#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
-#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
-#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
-#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
-#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
-#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
-#define XREG_CP15_CONTROL_V_BIT			0x00002000U
-#define XREG_CP15_CONTROL_I_BIT			0x00001000U
-#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
-#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
-#define XREG_CP15_CONTROL_B_BIT			0x00000080U
-#define XREG_CP15_CONTROL_C_BIT			0x00000004U
-#define XREG_CP15_CONTROL_A_BIT			0x00000002U
-#define XREG_CP15_CONTROL_M_BIT			0x00000001U
-/* C2 Register Defines */
-/* Not Used */
-
-/* C3 Register Defines */
-/* Not Used */
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
-#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
-#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
-
-#define XREG_CP15_MPU_REG_BASEADDR			"p15, 0, %0,  c6,  c1, 0"
-#define XREG_CP15_MPU_REG_SIZE_EN			"p15, 0, %0,  c6,  c1, 2"
-#define XREG_CP15_MPU_REG_ACCESS_CTRL		"p15, 0, %0,  c6,  c1, 4"
-
-#define XREG_CP15_MPU_MEMORY_REG_NUMBER			"p15, 0, %0,  c6,  c2, 0"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
-
-#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex R5.
- */
-#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE		"p15, 0, %0,  c7,  c5, 7"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
-#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
-
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
-#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
-
-#define XREG_CP15_INVAL_DC_ALL		"p15, 0, %0,  c15, c5, 0"
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex R5.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
-#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
-
-#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
-
-/* C8 Register Defines */
-/* Not Used */
-
-
-/* C9 Register Defines */
-
-#define XREG_CP15_ATCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 1"
-#define XREG_CP15_BTCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 0"
-#define XREG_CP15_TCM_SELECTION				"p15, 0, %0,  c9, c2, 0"
-
-#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
-#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
-#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
-#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
-#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
-#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
-#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
-#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
-
-#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
-#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
-#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
-
-/* C10 Register Defines */
-/* Not used */
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-/* Not used */
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
-#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
-#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
-#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_SEC_AUX_CTRL			"p15, 0, %0, c15,  c0, 0"
-
-
-
-
-/* MPE register definitions */
-#define XREG_FPSID				c0
-#define XREG_FPSCR				c1
-#define XREG_MVFR1				c6
-#define XREG_MVFR0				c7
-#define XREG_FPEXC				c8
-#define XREG_FPINST				c9
-#define XREG_FPINST2			c10
-
-/* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT	(24U)
-#define XREG_FPSID_IMPLEMENTER_MASK	(0x000000FFU << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE		(0X00000001U << 23U)
-#define XREG_FPSID_ARCH_BIT		(16U)
-#define XREG_FPSID_ARCH_MASK		(0x0000000FU  << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT		(8U)
-#define XREG_FPSID_PART_MASK		(0x000000FFU << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT		(4U)
-#define XREG_FPSID_VARIANT_MASK		(0x0000000FU  << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT		(0U)
-#define XREG_FPSID_REV_MASK		(0x0000000FU  << FPSID_REV_BIT)
-
-/* FPSCR bits */
-#define XREG_FPSCR_N_BIT		(0X00000001U << 31U)
-#define XREG_FPSCR_Z_BIT		(0X00000001U << 30U)
-#define XREG_FPSCR_C_BIT		(0X00000001U << 29U)
-#define XREG_FPSCR_V_BIT		(0X00000001U << 28U)
-#define XREG_FPSCR_QC			(0X00000001U << 27U)
-#define XREG_FPSCR_AHP			(0X00000001U << 26U)
-#define XREG_FPSCR_DEFAULT_NAN		(0X00000001U << 25U)
-#define XREG_FPSCR_FLUSHTOZERO		(0X00000001U << 24U)
-#define XREG_FPSCR_ROUND_NEAREST	(0X00000000U << 22U)
-#define XREG_FPSCR_ROUND_PLUSINF	(0X00000001U << 22U)
-#define XREG_FPSCR_ROUND_MINUSINF	(0X00000002U << 22U)
-#define XREG_FPSCR_ROUND_TOZERO		(0X00000003U << 22U)
-#define XREG_FPSCR_RMODE_BIT		(22U)
-#define XREG_FPSCR_RMODE_MASK		(0X00000003U << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT		(20U)
-#define XREG_FPSCR_STRIDE_MASK		(0X00000003U << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT		(16U)
-#define XREG_FPSCR_LENGTH_MASK		(0X00000007U << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC			(0X00000001U << 7U)
-#define XREG_FPSCR_IXC			(0X00000001U << 4U)
-#define XREG_FPSCR_UFC			(0X00000001U << 3U)
-#define XREG_FPSCR_OFC			(0X00000001U << 2U)
-#define XREG_FPSCR_DZC			(0X00000001U << 1U)
-#define XREG_FPSCR_IOC			(0X00000001U << 0U)
-
-/* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT		(28U)
-#define XREG_MVFR0_RMODE_MASK		(0x0000000FU << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT	(24U)
-#define XREG_MVFR0_SHORT_VEC_MASK	(0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT		(20U)
-#define XREG_MVFR0_SQRT_MASK		(0x0000000FU << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT		(16U)
-#define XREG_MVFR0_DIVIDE_MASK		(0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT	(12U)
-#define XREG_MVFR0_EXEC_TRAP_MASK	(0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT		(8U)
-#define XREG_MVFR0_DP_MASK		(0x0000000FU << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT		(4U)
-#define XREG_MVFR0_SP_MASK		(0x0000000FU << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT		(0U)
-#define XREG_MVFR0_A_SIMD_MASK		(0x0000000FU << MVFR0_A_SIMD_BIT)
-
-/* FPEXC bits */
-#define XREG_FPEXC_EX			(0X00000001U << 31U)
-#define XREG_FPEXC_EN			(0X00000001U << 30U)
-#define XREG_FPEXC_DEX			(0X00000001U << 29U)
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XREG_CORTEXR5_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h
deleted file mode 100644
index ba5f96b20..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* This file contains Xilinx software status codes.  Status codes have their
-* own data type called int.  These codes are used throughout the Xilinx
-* device drivers.
-*
-******************************************************************************/
-
-#ifndef XSTATUS_H		/* prevent circular inclusions */
-#define XSTATUS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-
-#define XST_SUCCESS                     0L
-#define XST_FAILURE                     1L
-#define XST_DEVICE_NOT_FOUND            2L
-#define XST_DEVICE_BLOCK_NOT_FOUND      3L
-#define XST_INVALID_VERSION             4L
-#define XST_DEVICE_IS_STARTED           5L
-#define XST_DEVICE_IS_STOPPED           6L
-#define XST_FIFO_ERROR                  7L	/* an error occurred during an
-						   operation with a FIFO such as
-						   an underrun or overrun, this
-						   error requires the device to
-						   be reset */
-#define XST_RESET_ERROR                 8L	/* an error occurred which requires
-						   the device to be reset */
-#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
-						   typically requires the device
-						   using the DMA to be reset */
-#define XST_NOT_POLLED                  10L	/* the device is not configured for
-						   polled mode operation */
-#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
-						   the specified data into */
-#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
-						   to hold the expected data */
-#define XST_NO_DATA                     13L	/* there was no data available */
-#define XST_REGISTER_ERROR              14L	/* a register did not contain the
-						   expected value */
-#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
-						   into the function */
-#define XST_NOT_SGDMA                   16L	/* the device is not configured for
-						   scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
-#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
-						   registered */
-#define XST_NO_FEATURE                  19L	/* device is not configured with
-						   the requested feature */
-#define XST_NOT_INTERRUPT               20L	/* device is not configured for
-						   interrupt mode operation */
-#define XST_DEVICE_BUSY                 21L	/* device is busy */
-#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
-						   have maxed out */
-#define XST_IS_STARTED                  23L	/* used when part of device is
-						   already started i.e.
-						   sub channel */
-#define XST_IS_STOPPED                  24L	/* used when part of device is
-						   already stopped i.e.
-						   sub channel */
-#define XST_DATA_LOST                   26L	/* driver defined error */
-#define XST_RECV_ERROR                  27L	/* generic receive error */
-#define XST_SEND_ERROR                  28L	/* generic transmit error */
-#define XST_NOT_ENABLED                 29L	/* a requested service is not
-						   available because it has not
-						   been enabled */
-
-/***************** Utility Component statuses 401 - 500  *********************/
-
-#define XST_MEMTEST_FAILED              401L	/* memory test failed */
-
-
-/***************** Common Components statuses 501 - 1000 *********************/
-
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
-#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
-#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
-						   was invalid after reset */
-#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
-						 * empty and full simultaneously
-						 */
-
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
-						   failed */
-#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
-						   was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
-						   no buffer descriptors ready
-						   to be processed */
-#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
-#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
-						   the scatter gather list are
-						   being used */
-#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
-						   descriptor which is to be
-						   copied over in the scatter
-						   list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
-						   put into the scatter gather
-						   list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
-						   specified was larger than the
-						   total # of buffer descriptors
-						   in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
-						   already been created */
-#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
-						   been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
-						   being started was not committed
-						   to the list */
-#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
-						   has already been used by the
-						   hardware so it can't be reused
-						 */
-#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
-						   error */
-#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
-						   error */
-
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
-						   was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
-						   reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
-						   register did not reset when
-						   acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
-						   register was not updated when
-						   other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
-						   did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
-						   not updated correctly when other
-						   registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
-						   register did not indicate the
-						   expected value */
-#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
-						   did not indicate the expected
-						   value */
-#define XST_IPIF_ERROR                  541L	/* generic ipif error */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
-						 * to hold the minimum number of
-						 * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
-#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
-						 * collision on polled send */
-
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR         1051L
-#define XST_UART_START_ERROR        1052L
-#define XST_UART_CONFIG_ERROR       1053L
-#define XST_UART_TEST_FAIL          1054L
-#define XST_UART_BAUD_ERROR         1055L
-#define XST_UART_BAUD_RANGE         1056L
-
-
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
-#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
-#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
-					     /* general call address        */
-#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
-					     /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
-					     /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
-					     /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
-					     /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
-					     /* didn't return written value */
-#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
-
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
-						   controller hit the max value
-						   which requires the statistics
-						   to be cleared */
-
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
-						 */
-#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
-#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
-						   error. Use XFlash_DeviceControl
-						   to retrieve device specific codes
-						 */
-#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
-						 */
-#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
-						 */
-#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
-						   driver */
-#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
-						   aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
-						   addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
-						   write/erase function with
-						   XFL_NON_BLOCKING_WRITE/ERASE
-						   option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
-
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
-#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
-#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
-						 * selected */
-#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
-						 */
-#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
-
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
-						 * one master assigned to two or more
-						 * priorities, or one master not
-						 * assigned to any priority
-						 */
-#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
-						 * priority levels without first
-						 * suspending the use of priority
-						 * levels
-						 */
-#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
-						 * bus parking was not enabled
-						 */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
-						 * priority mode to allow the
-						 * priorities to be changed
-						 */
-
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
-#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
-
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
-
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED      1251L
-
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST    1276L
-
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST   1301L
-
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST   1326L
-
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
-
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS     1361L
-
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR			1400
-#define XST_FR_TX_BUSY			1401
-#define XST_FR_BUF_LOCKED		1402
-#define XST_FR_NO_BUF			1403
-
-/****************** USB constants 1410 - 1420  *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED	1410
-#define XST_USB_BUF_ALIGN_ERROR		1411
-#define XST_USB_NO_DESC_AVAILABLE	1412
-#define XST_USB_BUF_TOO_BIG		1413
-#define XST_USB_NO_BUF			1414
-
-/****************** HWICAP constants 1421 - 1429  *****************************/
-
-#define XST_HWICAP_WRITE_DONE		1421
-
-
-/****************** AXI VDMA constants 1430 - 1440  *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR		1430
-
-/*********************** NAND Flash statuses 1441 - 1459  *********************/
-
-#define XST_NAND_BUSY			1441L	/* Flash is erasing or
-						 * programming
-						 */
-#define XST_NAND_READY			1442L	/* Flash is ready for commands
-						 */
-#define XST_NAND_ERROR			1443L	/* Flash had detected an
-						 * internal error.
-						 */
-#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
-						 * driver
-						 */
-#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
-						 */
-#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
-						 * operation aborted due to a
-						 * timeout
-						 */
-#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
-						 * addressible range
-						 */
-#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
-						 */
-#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
-						 * page of the device
-						 */
-#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
-						 */
-
-#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
-						 */
-
-/**************************** Type Definitions *******************************/
-
-typedef int XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c
deleted file mode 100644
index a17ee404b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex R5 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 	pkp    08/29/14 First release
-* 5.04  pkp	   02/19/16 XTime_StartTimer API is added to configure TTC3 timer
-*						when present. XTime_GetTime is modified to give 64bit
-*						output using timer overflow when TTC3 present.
-*						XTime_SetTime is modified to configure TTC3 counter
-*						value when present.
-* 5.04	pkp	   03/11/16 XTime_StartTimer is modified to avoid enabling the
-*						overflow interrupt and XTime_GetTime & XTime_SetTime
-*						are modified to read and write TTC counter value
-*						respectively
-* 5.04	pkp
-* </pre>
-*
-* @note		None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-#define RST_LPD_IOU2 					0xFF5E0238U
-#define RST_LPD_IOU2_TTC3_RESET_MASK	0x00004000U
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/* Function definitions are applicable only when TTC3 is present*/
-#ifdef SLEEP_TIMER_BASEADDR
-/****************************************************************************
-*
-* Start the TTC timer.
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note		In multiprocessor environment reference time will reset/lost for
-*		all processors, when this function called by any one processor.
-*
-****************************************************************************/
-void XTime_StartTimer(void)
-{
-	u32 LpdRst;
-	u32 TimerPrescalar;
-	u32 TimerCntrl;
-
-	LpdRst = Xil_In32(RST_LPD_IOU2);
-	if ((LpdRst & RST_LPD_IOU2_TTC3_RESET_MASK) != 0 ) {
-			LpdRst = LpdRst & (~RST_LPD_IOU2_TTC3_RESET_MASK);
-			Xil_Out32(RST_LPD_IOU2, LpdRst);
-
-	} else {
-		TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
-								SLEEP_TIMER_CNTR_CNTRL_OFFSET);
-		/* check if Timer is disabled */
-		if ((TimerCntrl & SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK) == 0) {
-			TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR +
-									SLEEP_TIMER_CLK_CNTRL_OFFSET);
-
-		/* check if Timer is configured with proper functionalty for sleep */
-			if ((TimerPrescalar & SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK) == 0)
-						return;
-		}
-	}
-	/* Disable the timer to configure */
-	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
-							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
-	TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK;
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
-				TimerCntrl);
-
-	/* Disable the prescalar */
-	TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR +
-								SLEEP_TIMER_CLK_CNTRL_OFFSET);
-	TimerPrescalar = TimerPrescalar & (~SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK);
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CLK_CNTRL_OFFSET,
-				TimerPrescalar);
-
-	/* Enable the Timer */
-	TimerCntrl = SLEEP_TIMER_COUNTER_CONTROL_RST_MASK &
-					(~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK);
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
-				TimerCntrl);
-
-}
-/****************************************************************************
-*
-* Set the time in the Timer Counter Register.
-*
-* @param	Value to be written to the Timer Counter Register.
-*
-* @return	None.
-*
-* @note		In multiprocessor environment reference time will reset/lost for
-*		all processors, when this function called by any one processor.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
-	u32 TimerCntrl;
-	/* Disable the timer to configure */
-	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
-							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
-	TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK;
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
-				TimerCntrl);
-
-	/* Write the lower 32bit value to timer counter register */
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_VAL_OFFSET,
-				Xtime_Global);
-
-	/* Enable the Timer */
-	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
-							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
-	TimerCntrl = TimerCntrl & (~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK);
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
-				TimerCntrl);
-}
-
-/****************************************************************************
-*
-* Get the time from the Timer Counter Register.
-*
-* @param	Pointer to the location to be updated with the time.
-*
-* @return	None.
-*
-* @note		None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
-	*Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +
-								SLEEP_TIMER_CNTR_VAL_OFFSET);
-}
-#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h
deleted file mode 100644
index 36c416d5a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 	pkp	   05/29/14 First release
-* 5.04  pkp	   02/19/16 Added timer configuration register offset definitions
-* 5.04	pkp	   03/11/16 Removed definitions for overflow interrupt register
-*						and mask
-* </pre>
-*
-* @note		None.
-*
-******************************************************************************/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xparameters.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Constant Definitions *****************************/
-
-#ifdef SLEEP_TIMER_BASEADDR
-
-#define COUNTS_PER_SECOND				SLEEP_TIMER_FREQUENCY
-#define COUNTS_PER_USECOND 				COUNTS_PER_SECOND/1000000
-
-/* Timer Register Offset*/
-#define SLEEP_TIMER_CLK_CNTRL_OFFSET 		0x00000000U
-#define SLEEP_TIMER_CNTR_CNTRL_OFFSET		0x0000000CU
-#define SLEEP_TIMER_CNTR_VAL_OFFSET			0x00000018U
-
-/*Timer register values*/
-#define SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK    0x00000001U
-#define SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK    0x00000001U
-#define SLEEP_TIMER_COUNTER_CONTROL_RST_MASK    0x00000010U
-#else
-#define ITERS_PER_SEC  (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4)
-#define ITERS_PER_USEC  (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000)
-#define IRQ_FIQ_MASK 	0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/* The following definitions are applicable only when TTC3 is present*/
-#ifdef SLEEP_TIMER_BASEADDR
-typedef u32 XTime;
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile
new file mode 100644
index 000000000..ca8621a76
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile
@@ -0,0 +1,74 @@
+###############################################################################
+#
+# Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+include config.make
+CC=$(COMPILER)
+AR=$(ARCHIVER)
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq ($(notdir $(CC)), armr5-none-eabi-gcc)
+ECC_FLAGS	+= -nostartfiles\
+		  -mfloat-abi=soft\
+		  -mfpu=vfpv3-d16
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+INCLUDEFILES=*.h
+INCLUDEFILES+=includes_ps/*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+	echo "Compiling standalone R5"
+	$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+	$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+.PHONY: include
+include: standalone_includes
+
+standalone_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OUTS}
+	$(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c
new file mode 100644
index 000000000..cf598882b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <unistd.h>
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+  (void)status;
+  while (1) {
+	;
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c
new file mode 100644
index 000000000..9b5a23adf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void *)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c
new file mode 100644
index 000000000..2a069ec06
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <sys/types.h>
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+  static u8 *heap = NULL;
+  u8 *prev_heap;
+  static u8 *HeapEndPtr = (u8 *)&_heap_end;
+  caddr_t Status;
+
+  if (heap == NULL) {
+    heap = (u8 *)&_heap_start;
+  }
+  prev_heap = heap;
+
+  heap += incr;
+
+  if (heap > HeapEndPtr){
+	  Status = (caddr_t) -1;
+  }
+  else if (prev_heap != NULL) {
+	  Status = (caddr_t) ((void *)prev_heap);
+  }
+  else {
+	  Status = (caddr_t) -1;
+  }
+
+  return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c
new file mode 100644
index 000000000..e8988c048
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <stdlib.h>
+#include <unistd.h>
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+  _exit(1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S
new file mode 100644
index 000000000..2c6f117eb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex R5 processor
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+* 6.0   mus     27/07/16 Added UndefinedException handler
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+.org 0
+.text
+
+.globl _boot
+.globl _vector_table
+
+.globl FIQInterrupt
+.globl IRQInterrupt
+.globl SWInterrupt
+.globl DataAbortInterrupt
+.globl PrefetchAbortInterrupt
+
+.globl IRQHandler
+.globl prof_pc
+
+.section .vectors, "a"
+_vector_table:
+	ldr	pc,=_boot
+	ldr	pc,=Undefined
+	ldr	pc,=SVCHandler
+	ldr	pc,=PrefetchAbortHandler
+	ldr	pc,=DataAbortHandler
+	NOP	/* Placeholder for address exception vector*/
+	ldr	pc,=IRQHandler
+	ldr	pc,=FIQHandler
+
+.text
+IRQHandler:					/* IRQ vector handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code*/
+	bl	IRQInterrupt			/* IRQ vector */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+FIQHandler:					/* FIQ vector handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+FIQLoop:
+	bl	FIQInterrupt			/* FIQ vector */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+Undefined:					/* Undefined handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =UndefinedExceptionAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Store address of instruction causing undefined exception */
+
+	bl	UndefinedException		/* UndefinedException: call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	movs	pc, lr
+
+SVCHandler:					/* SWI handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	tst	r0, #0x20			/* check the T bit */
+	ldrneh	r0, [lr,#-2]			/* Thumb mode */
+	bicne	r0, r0, #0xff00			/* Thumb mode */
+	ldreq	r0, [lr,#-4]			/* ARM mode */
+	biceq	r0, r0, #0xff000000		/* ARM mode */
+	bl	SWInterrupt			/* SWInterrupt: call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	movs	pc, lr				/* adjust return */
+
+DataAbortHandler:				/* Data Abort handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =DataAbortAddr
+	sub     r1, lr, #8
+	str     r1, [r0]            		/* Stores instruction causing data abort */
+	bl	DataAbortInterrupt		/*DataAbortInterrupt :call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #8			/* adjust return */
+
+PrefetchAbortHandler:				/* Prefetch Abort handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =PrefetchAbortAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Stores instruction causing prefetch abort */
+	bl	PrefetchAbortInterrupt		/* PrefetchAbortInterrupt: call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S
new file mode 100644
index 000000000..30b97cbfa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S
@@ -0,0 +1,308 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* This file contains the initial startup code for the Cortex R5 processor
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 5.04	pkp  09/11/15 Disabled ACTLR.DBWR bit to avoid potential R5 deadlock
+*		      for errata 780125
+* 5.04 pkp   02/04/16 Enabled the fault log for lock-step mode
+* 5.04 pkp   02/25/16 Initialized the banked registers for various modes,
+*		      initialized floating point registers and enabled the
+*		      cache ECC check before enabling the fault log for
+*		      lock step mode
+* 5.04 pkp   03/24/16 Reset the dbg_lpd_reset before enabling the fault log
+*		      to avoid intervention for lock-step mode
+* 5.05 pkp   04/11/16 Enable the comparators for non-JTAG boot mode for
+*		      lock-step to avoid putting debug logic to reset
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack,	__undef_stack
+.set FIQ_stack,		__fiq_stack
+.set Abort_stack,	__abort_stack
+.set SPV_stack,		__supervisor_stack
+.set IRQ_stack,		__irq_stack
+.set SYS_stack,		__stack
+
+.set vector_base,	_vector_table
+
+.set RPU_GLBL_CNTL,	0xFF9A0000
+.set RPU_ERR_INJ,	0xFF9A0020
+.set RST_LPD_DBG,	0xFF5E0240
+.set BOOT_MODE_USER,	0xFF5E0200
+.set fault_log_enable,	0x101
+
+.section .boot,"axS"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+OKToRun:
+
+/* Initialize processor registers to 0 */
+	mov	r0,#0
+	mov	r1,#0
+	mov	r2,#0
+	mov	r3,#0
+	mov	r4,#0
+	mov	r5,#0
+	mov	r6,#0
+	mov	r7,#0
+	mov	r8,#0
+	mov	r9,#0
+	mov	r10,#0
+	mov	r11,#0
+	mov	r12,#0
+
+/* Initialize stack pointer and banked registers for various mode */
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the irq stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x12			/* IRQ mode */
+	msr	cpsr, r2
+	ldr	r13,=IRQ_stack			/* IRQ stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the supervisor stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x13			/* supervisor mode */
+	msr	cpsr, r2
+	ldr	r13,=SPV_stack			/* Supervisor stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Abort  stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x17			/* Abort mode */
+	msr	cpsr, r2
+	ldr	r13,=Abort_stack		/* Abort stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the FIQ stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x11			/* FIQ mode */
+	msr	cpsr, r2
+	mov 	r8, #0
+	mov 	r9, #0
+	mov 	r10, #0
+	mov 	r11, #0
+	mov 	r12, #0
+	ldr	r13,=FIQ_stack			/* FIQ stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Undefine stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1b			/* Undefine mode */
+	msr	cpsr, r2
+	ldr	r13,=Undef_stack		/* Undefine stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the system stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1F			/* SYS mode */
+	msr	cpsr, r2
+	ldr	r13,=SYS_stack			/* SYS stack pointer */
+	mov 	r14,#0
+
+/*
+ * Enable access to VFP by enabling access to Coprocessors 10 and 11.
+ * Enables Full Access i.e. in both privileged and non privileged modes
+ */
+	mrc     p15, 0, r0, c1, c0, 2      	/* Read Coprocessor Access Control Register (CPACR) */
+        orr     r0, r0, #(0xF << 20)       	/* Enable access to CP 10 & 11 */
+        mcr     p15, 0, r0, c1, c0, 2      	/* Write Coprocessor Access Control Register (CPACR) */
+        isb
+
+/* enable fpu access  */
+	vmrs	r3, FPEXC
+	orr	r1, r3, #(1<<30)
+	vmsr	FPEXC, r1
+
+/* clear the floating point register*/
+	mov	r1,#0
+	vmov	d0,r1,r1
+	vmov	d1,r1,r1
+	vmov	d2,r1,r1
+	vmov	d3,r1,r1
+	vmov	d4,r1,r1
+	vmov	d5,r1,r1
+	vmov	d6,r1,r1
+	vmov	d7,r1,r1
+	vmov	d8,r1,r1
+	vmov	d9,r1,r1
+	vmov	d10,r1,r1
+	vmov	d11,r1,r1
+	vmov	d12,r1,r1
+	vmov	d13,r1,r1
+	vmov	d14,r1,r1
+	vmov	d15,r1,r1
+
+/* restore previous value for fpu access */
+	vmsr	FPEXC,r3
+
+/* Disable MPU and caches */
+        mrc     p15, 0, r0, c1, c0, 0       	/* Read CP15 Control Register*/
+        bic     r0, r0, #0x05               	/* Disable MPU (M bit) and data cache (C bit) */
+        bic     r0, r0, #0x1000             	/* Disable instruction cache (I bit) */
+        dsb                                 	/* Ensure all previous loads/stores have completed */
+        mcr     p15, 0, r0, c1, c0, 0       	/* Write CP15 Control Register */
+        isb                                 	/* Ensure subsequent insts execute wrt new MPU settings */
+
+/* Disable Branch prediction, TCM ECC checks */
+        mrc     p15, 0, r0, c1, c0, 1       	/* Read ACTLR */
+        orr     r0, r0, #(0x1 << 17)        	/* Enable RSDIS bit 17 to disable the return stack */
+        orr     r0, r0, #(0x1 << 16)        	/* Clear BP bit 15 and set BP bit 16:*/
+        bic     r0, r0, #(0x1 << 15)        	/* Branch always not taken and history table updates disabled*/
+        bic     r0, r0, #(0x1 << 27)		/* Disable B1TCM ECC check */
+        bic     r0, r0, #(0x1 << 26)		/* Disable B0TCM ECC check */
+        bic     r0, r0, #(0x1 << 25)		/* Disable ATCM ECC check */
+	orr	r0, r0, #(0x1 << 5)		/* Enable ECC with no forced write through with [5:3]=b'101*/
+	bic 	r0, r0, #(0x1 << 4)
+	orr	r0, r0, #(0x1 << 3)
+        mcr     p15, 0, r0, c1, c0, 1       	/* Write ACTLR*/
+	dsb				    	/* Complete all outstanding explicit memory operations*/
+
+/* Invalidate caches */
+	mov	r0,#0				/* r0 = 0  */
+	dsb
+	mcr	p15, 0, r0, c7, c5, 0		/* invalidate icache */
+	mcr 	p15, 0, r0, c15, c5, 0      	/* Invalidate entire data cache*/
+	isb
+
+/* enable fault log for lock step */
+	ldr	r0,=RPU_GLBL_CNTL
+	ldr	r1, [r0]
+	ands	r1, r1, #0x8
+/* branch to initialization if split mode*/
+	bne 	init
+/* check for boot mode if in lock step, branch to init if JTAG boot mode*/
+	ldr	r0,=BOOT_MODE_USER
+	ldr 	r1, [r0]
+	ands	r1, r1, #0xF
+	beq 	init
+/* reset the debug logic */
+	ldr	r0,=RST_LPD_DBG
+	ldr	r1, [r0]
+	orr	r1, r1, #(0x1 << 1)
+	orr	r1, r1, #(0x1 << 4)
+	orr	r1, r1, #(0x1 << 5)
+	str	r1, [r0]
+/* enable fault log */
+	ldr	r0,=RPU_ERR_INJ
+	ldr	r1,=fault_log_enable
+	ldr	r2, [r0]
+	orr	r2, r2, r1
+	str	r2, [r0]
+	nop
+	nop
+
+init:
+	bl 	Init_MPU		/* Initialize MPU */
+
+/* Enable Branch prediction */
+	mrc     p15, 0, r0, c1, c0, 1       /* Read ACTLR*/
+        bic     r0, r0, #(0x1 << 17)        /* Clear RSDIS bit 17 to enable return stack*/
+        bic     r0, r0, #(0x1 << 16)        /* Clear BP bit 15 and BP bit 16:*/
+        bic     r0, r0, #(0x1 << 15)        /* Normal operation, BP is taken from the global history table.*/
+        orr	r0, r0, #(0x1 << 14)	    /* Disable DBWR for errata 780125 */
+	mcr     p15, 0, r0, c1, c0, 1       /* Write ACTLR*/
+
+/* Enable icahce and dcache */
+	mrc 	p15,0,r1,c1,c0,0
+	ldr	r0, =0x1005
+	orr 	r1,r1,r0
+	dsb
+	mcr	p15,0,r1,c1,c0,0		/* Enable cache  */
+	isb					/* isb	flush prefetch buffer */
+
+/* Warning message to be removed after 2016.1 */
+/* USEAMP was introduced in 2015.4 with ZynqMP and caused confusion with USE_AMP */
+#ifdef USEAMP
+#warning "-DUSEAMP=1 is deprecated, use -DVEC_TABLE_IN_OCM instead to set vector table in OCM"
+#endif
+
+/* Set vector table in TCM/LOVEC */
+#ifndef VEC_TABLE_IN_OCM
+	mrc	p15, 0, r0, c1, c0, 0
+	mvn	r1, #0x2000
+	and	r0, r0, r1
+	mcr	p15, 0, r0, c1, c0, 0
+#endif
+
+/* enable asynchronous abort exception */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x100
+	msr	cpsr_xsf, r0
+
+        b 	_startup                       /* jump to C startup code */
+
+
+.Ldone:	b	.Ldone				/* Paranoia: we should never get here */
+
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h
new file mode 100644
index 000000000..8671e3fbe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt
new file mode 100644
index 000000000..f663af134
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt
@@ -0,0 +1,402 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ---------------------------------------------------
+  * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ *                     cacheable regions
+ *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ *                     generated by the cpu driver, for enabling caches
+ * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
+ *                     write-thru caches
+ * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
+ *		       Updated the MMU table to mark OCM in high address space
+ *		       as inner cacheable and reserved space as Invalid
+ * 3.03a sdm  08/20/11 Changes to support FreeRTOS
+ *		       Updated the MMU table to mark upper half of the DDR as
+ *		       non-cacheable
+ *		       Setup supervisor and abort mode stacks
+ *		       Do not initialize/enable L2CC in case of AMP
+ *		       Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ *		       in case of AMP
+ * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
+ *		       counters
+ * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
+ *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
+ *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ *		       for MicroBlaze will invalidate data in the cache instead
+ *		       of flushing it for writeback caches
+ * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
+ *		       Remove redundant dsb/dmb instructions in cache maintenance
+ *		       APIs
+ *		       Remove redundant dsb in mcr instruction
+ * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
+ *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
+ *                     for the QSPI complete address range - DT644567
+ *                     Removed profile directory for armcc compiler and changed
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
+ *                     Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ *		       invalidate the caches before enabling back the MMU and
+ *		       D cache.
+ * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
+ *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ *		       array, flush the D-cache before changing the attributes
+ *		       in translation table. The user need not call Xil_DisableMMU
+ *		       before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ *	 sgd	       initialization is present. Changes for this were done in
+ *		       uart.c and xil-crt0.s.
+ *		       Made changes in xil_io.c to use volatile pointers.
+ *		       Made changes in xil_mmu.c to correct the function
+ *		       Xil_SetTlbAttributes.
+ *		       Changes are made xil-crt0.s to initialize the static
+ *		       C++ constructors.
+ *		       Changes are made in boot.s, to fix the TTBR settings,
+ *		       correct the L2 Cache Auxiliary register settings, L2 cache
+ *		       latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ *	 sgd	       usleep.c to use global timer intstead of CP15.
+ *		       Made changes in cortexa9/gcc/translation_table.s to map
+ *		       the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/boot.S to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/translation_table.s to
+ *		       map the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/boot.S to optimize the
+ *		       L2 cache settings. Changes the section properties for
+ *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ *			and cortexa9/gcc/translation_table.S.
+ *		       Made changes in cortexa9/xil_cache.c to change the
+ *		       cache invalidation order.
+ * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
+ *		       compilation/linking issues for C++ compiler.
+ *		       Made changes in mb_interface.h to remove compilation/
+ *		       linking issues for C++ compiler.
+ *		       Added macros for swapb and swaph microblaze instructions
+ *		       mb_interface.h
+ *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ *		       for CortexA9.
+ * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa  08/31/12 Added xil_printf.h include
+ * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
+ *				Corrected L2 cache sequence disable sequence
+ * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
+ *		       irq/fiq handling.
+ *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ *		       fixes the CR #692094.
+ * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt  04/18/13 Implemented ARM Erratas.
+ *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
+ *		       L2Cache PL310 Errata - 588369, 727915, 759370
+ *		       Please refer to file 'xil_errata.h' for errata
+ *		       description.
+ * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ *		       cache APIs were corresponding to only Layer 1 cache
+ *		       memories. New APIs were now added and the existing cache
+ *		       related APIs were changed to provide a uniform interface
+ *		       to flush/invalidate/enable/disable the complete cache
+ *		       system which includes both L1 and L2 caches. The changes
+ *		       for these were done in:
+ *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ *		       files.
+ *		       Four new files were added for supporting L2 cache. They are:
+ *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
+ *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
+ *		       memory in L2 cache.
+ *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ *		       microblaze_invalidate_cache_ext_range -> Invalidates a
+ *		       range of memory in L2 cache.
+ *		       These changes are done to implement PR #697214.
+ * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ *		       fix the CR #706464. L2 cache disabling happens independent
+ *		       of L1 data cache disable operation. Changes are done in the
+ *		       same file in cache handling APIs to do a L2 cache sync
+ *		       (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested
+ *		       interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ *		       sync operation. This fixes the CR# 716781.
+ * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
+ *		       for armcc toolchain.
+ *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ *		       fix issues related to NEON context saving. The assembly
+ *		       routines for IRQ and FIQ handling are modified.
+ *		       Deprecated the older BSP (3.10a).
+ * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ *		       various potential issues. Made changes in the function
+ *		       Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ *		       in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ *		       L2 cache sync operation and to fix issues around complete
+ *		       L2 cache flush/invalidation by ways.
+ * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ *		       to fix linking issues with armcc/DS-5. Modified the armcc
+ *		       makefile to fix issues.
+ * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ *		       src\cortexa9\armcc\) to fix CR#767251
+ * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ *		       Few cache lines were missed to invalidate when unaligned address
+ *		       invalidation was accommodated in Xil_DCacheInvalidateRange.
+ *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ *		       stack memory (which contains return address) was invalidated. So
+ *		       stack memory is flushed first and then L1D cache is invalidated.
+ *		       This is done to fix CR #763829
+ * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ *			mblaze_nt_types.h file and replace uint32_t with u32 in the
+ *			profile_hist.c to fix the above CR.
+ * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * 		       instead of libxil.a and added prototypes for
+ *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ *		       mb_interface.h
+ * 4.1 hk    04/18/14  Add sleep function.
+ * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ *		       some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
+ *			CR#794205
+ * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ *		       common/xil_testcache.c
+ *	               Fix for CR#764881.
+ * 4.1 srt   06/27/14  Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ *                     output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp   06/27/14  Added support for IAR compiler in src/cortexa9/iccarm.
+ *		       Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp   06/19/14  Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ *		       cortexa9/armcc/boot.s. Added default exception handlers for data
+ *		       abort and prefetch abort using handlers called
+ *		       DataAbortHandler and PrefetchAbortHandler respectively in
+ *		       cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp   06/30/14  MakeFile for cortexa9/armcc has been changed to fixes the
+ *		       issue of improper linking of translation_table.s
+ * 4.2 pkp   07/04/14  added weak attribute for the function in BSP which are also present
+ *		       in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp   07/21/14  Corrected reset value of event counter in function
+ *		       Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp   07/21/14  Included xil_types.h file in xil_mmu.h which had contained a function
+ * 		       containing type def u32 defined in xil_types.g to resolve issue of
+ *		       CR#805869
+ * 4.2 pkp   08/04/14  Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ *		       it is not possible to generate timer in nanosecond due to limited
+ *		       cpu frequency
+ * 4.2 pkp   08/04/14  Removed PEEP board related code which contained initialization of
+ *		       uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ *		       and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ *		       removed function definition of XSmc_NorInit and XSmc_NorInit from
+ *		       cortexa9/smc.h
+ * 4.2 bss   08/11/14  Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ *		       cache_ext_range declarations in mb_interface.h CR#783821.
+ *		       Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp   08/21/14  modified makefile of iccarm for proper linking of objectfiles in
+ *		       cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp   09/02/14  modified translation table entries in cortexa9/gcc/translation_table.s,
+ *		       armcc/translation_table.s and iccarm/translation_table.s
+ *		       to properly defined reserved entries according to address map for
+ *		       fixing CR#820146
+ * 4.2 pkp   09/11/14  modified translation table entries in cortexa9/iccarm/translation_table.s
+ *		       and  cortexa9/armcc/translation_table.s to resolve compilation
+ *		       error for solving CR#822897
+ * 5.0 kvn   12/9/14   Support for Zync Ultrascale Mp.Also modified code for
+ *                     MISRA-C:2012 compliance.
+ * 5.0 pkp   12/15/14  Added APIs to get information about the platforms running the code by
+ *		       adding src/common/xplatform_info.*s
+ * 5.0 pkp   16/12/14  Modified boot code to enable scu after MMU is enabled and
+ *		       removed incorrect initialization of TLB lockdown register to fix
+ *		       CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ *		       and iccarm/boot.s
+ * 5.0 pkp   25/02/15  Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ *		       for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp   05/13/15  Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ *		       and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ *		       caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ *		       of L2Cache is done later.
+ * 5.1 pkp   12/05/15  Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ *		       Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ *		       taking long time to fix CR#853097. L2CacheSync is added into
+ *		       Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ *		       Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ *		       instead of just System Stack
+ * 5.1 pkp   14/05/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS and also take the compiler and archiver as specified
+ *		       in settings instead of hardcoding it.
+ * 5.2 pkp   06/08/15  Modified cortexa9/gcc/translation_table.S to put a check for
+ *		       XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ *		       accordingly generate the	translation table
+ * 5.2 pkp   23/07/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS to fix a bug introduced during new version creation
+ *		       of BSP.
+ * 5.3 pkp   10/07/15  Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ *		       functionalities are avoided for the OpenAMP slave application(when
+ *		       USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ *		       cache for its operation. Also file operations such as read, write,
+ *		       close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ *		       defined for BSP) because XilOpenAMP library contains own file operation.
+ *		       The xil-crt0.S file is modified for not initializing global timer for
+ *		       OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp   10/09/15  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ *		       definition for dsb, isb and dmb to fix the compilation error when used
+ *     kvn   16/10/15  Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp   09/11/15  Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ *		       R5 deadlock for errata 780125
+ * 5.4 pkp   09/11/15  Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ *		       32 bit BSP in the initialization
+ * 5.4 pkp   09/11/15  Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ * 5.4 pkp   16/11/15  Modified microblaze/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ *     kvn   21/11/15  Added volatile keyword for ADDR varibles in Xil_Out API
+ *     kvn   21/11/15  Changed ADDR variable type from u32 to UINTPTR. This is
+ *                     required for MISRA-C:2012 Compliance.
+ * 5.4 pkp   23/11/15  Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ *		       in cortexa9/xil_mmu.h
+ * 5.4 pkp   23/11/15  Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp   11/12/15  Modified common/xplatform_info.h to add #defines for silicon for
+ *		       checking the current executing platform
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ *		       to initialize global constructor for C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ *		       C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ *		       translation_table.S to update the translation table according to proper
+ *		       address map
+ * 5.4 pkp   18/12/15  Modified cortexar5/mpu.c to initialize the MPU according to proper
+ *		       address map
+ * 5.4	pkp  05/01/16  Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ *		       equivalent to vector table base address
+ * 5.4 pkp   08/01/16  Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ *		       as per the toolchain update
+ * 5.4 pkp   12/01/16  Changed common/xplatform_info.* to add platform information support
+ *		       for Cortex-A53 32bit mode
+ * 5.4 pkp   28/01/16  Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ *		       and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ *		       instead take it from xparameters.h to properly configure the timestamp
+ *		       clock frequency
+ * 5.4 asa   29/01/16  Modified microblaze/mb_interface.h to add macros that support the
+ *		       new instructions for MB address extension feature
+ * 5.4 kvn   30/01/16  Modified xparameters_ps.h file to add interrupt ID number for
+ *		       system monitor.
+ * 5.4 pkp   04/02/16  Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp   19/02/16  Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ *		       cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ *		       cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ *		       use set of assembly instructions to provide required delay to fix
+ *		       CR#913249.
+ * 5.4 asa   25/02/16  Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ *		       _exit with exit. We should not be directly calling _exit and should
+ *		       always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp   25/02/16  Made change to cortexr5/gcc/boot.S to initialize the floating point
+ *		       registers, banked registers for various modes and enabled
+ *		       the cache ECC check before enabling the fault log for lock step mode
+ *		       Also modified the cortexr5/gcc/Makefile to support floating point
+ *		       registers initialization in boot code.
+ * 5.4 pkp   03/01/16  Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ *		       logic in case of lock-step mode when fault log is enabled to fix
+ *		       CR#938281
+ * 5.4 pkp   03/02/16  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ *		       header file instrinsics.h which contains assembly instructions
+ *		       definitions which can be used by C
+ * 5.4 asa   03/02/16  Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ *                     proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp   03/09/16  Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ *		       interrupts when sleep/usleep is being executed using assembly
+ *		       instructions to fix CR#913249.
+ * 5.4 pkp   03/11/16  Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ *		       instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ *		       value and compare it with previous value to detect the overflow
+ *		       to fix CR#940209.
+ * 5.4 pkp   03/24/16  Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ *		       the fault log to avoid intervention for lock-step mode and cortexr5/
+ *		       _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ *		       to fix CR#947335
+ * 5.5 pkp   04/11/16  Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ *		       in lock-step to avoid resetting the debug logic which restricts the
+ *		       access for debugger and removed enabling back of debug modules in
+ *		       cortexr5/_exit.c
+ * 5.5 pkp   04/13/16  Modified cortexa9/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ *		       to return correct number of bytes when read buffer is filled and
+ *		       removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexr5/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ *		       instruction macros to disable certain optimizations which may move
+ *		       code out of loops if optimizers believe that the code will always
+ *		       return the same result or discard asm statements if optimizers
+ *		       determine there is no need for the output variables
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ *		       sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ *		       sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ *		       to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * 		       Xil_DCacheInvalidateRange functions description for proper
+ *		       explaination to fix CR#949801
+ * 5.5 asa   04/20/16  Added missing macros for hibernate and suspend in Microblaze BSP
+ *                     file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa   04/29/16  Fix for CR#951080. Updated cache APIs for HW designs where cache
+ *                     memory is not included for MicroBlaze.
+ * 5.5 pkp   05/06/16  Modified the cortexa9/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp   05/06/16  Modified the cortexr5/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn   05/31/16  Make Xil_AsserWait a global variable
+ * 6.0 pkp   06/27/16  Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ *		       section since it is part of boot process to fix CR#949555
+ *     hk    07/12/16  Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp   07/25/16  Program the counter frequency in boot code for CortexA53
+ * 6.0 asa   08/03/16  Updated sleep_common function in microblaze_sleep.c to improve the
+ *                     the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus   08/03/16  Restructured the BSP to avoid code duplication across all BSPs.
+ *                     Source code directories specific to ARM processor's are moved to src/arm
+ *                     directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ *                     src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ *                     print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ *                     consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ *                     xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ *                     into common file each and consolidated files are kept at src/arm/common directory.
+ *                     GCC source files related to file  operations are consolidated and kept
+ *                     at src/arm/common/gcc directory.
+ *                     All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ *                     are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ *                     xil_io.h must be included as a header file to access io interfacing functions.
+ *                     Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus   08/11/16  Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ *                     TTC counter value register is read only.
+ * 6.0 asa   08/15/16  Modified the signatures for functions sleep and usleep. This fixes
+ *                     the CR#956899.
+ * 6.0 mus   08/18/16  Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ *                     in cortexr5/xparameters_ps.h
+ * 6.0 mus   08/18/16  Added support for the the Zynq 7000s devices
+ * 6.0 mus   08/18/16  Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus   08/19/16  Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus   11/03/16  Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ *                     ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ *                     these APIs and modifications are done on top of it to handle stdout/stdin
+ *                     parameters for design which doesnt have UART.It fixes CR#953681
+ *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c
new file mode 100644
index 000000000..dbbe0d4fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c
@@ -0,0 +1,49 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make
new file mode 100644
index 000000000..2b7dbb6f7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make
@@ -0,0 +1,2 @@
+LIBSOURCES = *.c *.S
+LIBS = standalone_libs
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S
new file mode 100644
index 000000000..40bbc2c7a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S
@@ -0,0 +1,79 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.text
+	.global __cpu_init
+	.align 2
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+	mov	r0, #0x0
+	mcr	p15, 0, r0, c5, c0, 0	/* DFSR */
+	mcr	p15, 0, r0, c5, c0, 1	/* IFSR */
+	mcr	p15, 0, r0, c6, c0, 0	/* DFAR */
+	mcr	p15, 0, r0, c6, c0, 2	/* IFAR */
+	mcr	p15, 0, r0, c9, c13, 2	/* PMXEVCNTR */
+	mcr	p15, 0, r0, c13, c0, 2	/* TPIDRURW */
+	mcr	p15, 0, r0, c13, c0, 3	/* TPIDRURO */
+
+
+/* Reset and start Cycle Counter */
+	mov	r2, #0x80000000		/* clear overflow */
+	mcr	p15, 0, r2, c9, c12, 3
+	mov	r2, #0xd		/* D, C, E */
+	mcr	p15, 0, r2, c9, c12, 0
+	mov	r2, #0x80000000		/* enable cycle counter */
+	mcr	p15, 0, r2, c9, c12, 1
+
+	bx	lr
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c
new file mode 100644
index 000000000..df0218e86
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include <errno.h>
+#include <reent.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c
new file mode 100644
index 000000000..e58221a14
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <stdio.h>
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c
new file mode 100644
index 000000000..c5a31f31b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <sys/stat.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c
new file mode 100644
index 000000000..d02df5ce2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c
new file mode 100644
index 000000000..a5a6448d4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif 
+
+char inbyte(void) {
+	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h
new file mode 100644
index 000000000..9029bead8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU0_CFG_H__
+#define __XDDR_XMPU0_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu0Cfg Base Address
+ */
+#define XDDR_XMPU0_CFG_BASEADDR      0xFD000000UL
+
+/**
+ * Register: XddrXmpu0CfgCtrl
+ */
+#define XDDR_XMPU0_CFG_CTRL    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU0_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu0CfgErrSts1
+ */
+#define XDDR_XMPU0_CFG_ERR_STS1    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgErrSts2
+ */
+#define XDDR_XMPU0_CFG_ERR_STS2    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgPoison
+ */
+#define XDDR_XMPU0_CFG_POISON    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU0_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU0_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgIsr
+ */
+#define XDDR_XMPU0_CFG_ISR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU0_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgImr
+ */
+#define XDDR_XMPU0_CFG_IMR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU0_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu0CfgIen
+ */
+#define XDDR_XMPU0_CFG_IEN    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU0_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgIds
+ */
+#define XDDR_XMPU0_CFG_IDS    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU0_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgLock
+ */
+#define XDDR_XMPU0_CFG_LOCK    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU0_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00Strt
+ */
+#define XDDR_XMPU0_CFG_R00_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00End
+ */
+#define XDDR_XMPU0_CFG_R00_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU0_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00Mstr
+ */
+#define XDDR_XMPU0_CFG_R00_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00
+ */
+#define XDDR_XMPU0_CFG_R00    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU0_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01Strt
+ */
+#define XDDR_XMPU0_CFG_R01_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01End
+ */
+#define XDDR_XMPU0_CFG_R01_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU0_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01Mstr
+ */
+#define XDDR_XMPU0_CFG_R01_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01
+ */
+#define XDDR_XMPU0_CFG_R01    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU0_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02Strt
+ */
+#define XDDR_XMPU0_CFG_R02_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02End
+ */
+#define XDDR_XMPU0_CFG_R02_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU0_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02Mstr
+ */
+#define XDDR_XMPU0_CFG_R02_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02
+ */
+#define XDDR_XMPU0_CFG_R02    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU0_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03Strt
+ */
+#define XDDR_XMPU0_CFG_R03_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03End
+ */
+#define XDDR_XMPU0_CFG_R03_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU0_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03Mstr
+ */
+#define XDDR_XMPU0_CFG_R03_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03
+ */
+#define XDDR_XMPU0_CFG_R03    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU0_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04Strt
+ */
+#define XDDR_XMPU0_CFG_R04_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04End
+ */
+#define XDDR_XMPU0_CFG_R04_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU0_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04Mstr
+ */
+#define XDDR_XMPU0_CFG_R04_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04
+ */
+#define XDDR_XMPU0_CFG_R04    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU0_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05Strt
+ */
+#define XDDR_XMPU0_CFG_R05_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05End
+ */
+#define XDDR_XMPU0_CFG_R05_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU0_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05Mstr
+ */
+#define XDDR_XMPU0_CFG_R05_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05
+ */
+#define XDDR_XMPU0_CFG_R05    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU0_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06Strt
+ */
+#define XDDR_XMPU0_CFG_R06_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06End
+ */
+#define XDDR_XMPU0_CFG_R06_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU0_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06Mstr
+ */
+#define XDDR_XMPU0_CFG_R06_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06
+ */
+#define XDDR_XMPU0_CFG_R06    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU0_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07Strt
+ */
+#define XDDR_XMPU0_CFG_R07_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07End
+ */
+#define XDDR_XMPU0_CFG_R07_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU0_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07Mstr
+ */
+#define XDDR_XMPU0_CFG_R07_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07
+ */
+#define XDDR_XMPU0_CFG_R07    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU0_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08Strt
+ */
+#define XDDR_XMPU0_CFG_R08_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08End
+ */
+#define XDDR_XMPU0_CFG_R08_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU0_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08Mstr
+ */
+#define XDDR_XMPU0_CFG_R08_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08
+ */
+#define XDDR_XMPU0_CFG_R08    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU0_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09Strt
+ */
+#define XDDR_XMPU0_CFG_R09_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09End
+ */
+#define XDDR_XMPU0_CFG_R09_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU0_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09Mstr
+ */
+#define XDDR_XMPU0_CFG_R09_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09
+ */
+#define XDDR_XMPU0_CFG_R09    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU0_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10Strt
+ */
+#define XDDR_XMPU0_CFG_R10_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10End
+ */
+#define XDDR_XMPU0_CFG_R10_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU0_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10Mstr
+ */
+#define XDDR_XMPU0_CFG_R10_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10
+ */
+#define XDDR_XMPU0_CFG_R10    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU0_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11Strt
+ */
+#define XDDR_XMPU0_CFG_R11_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11End
+ */
+#define XDDR_XMPU0_CFG_R11_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU0_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11Mstr
+ */
+#define XDDR_XMPU0_CFG_R11_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11
+ */
+#define XDDR_XMPU0_CFG_R11    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU0_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12Strt
+ */
+#define XDDR_XMPU0_CFG_R12_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12End
+ */
+#define XDDR_XMPU0_CFG_R12_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU0_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12Mstr
+ */
+#define XDDR_XMPU0_CFG_R12_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12
+ */
+#define XDDR_XMPU0_CFG_R12    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU0_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13Strt
+ */
+#define XDDR_XMPU0_CFG_R13_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13End
+ */
+#define XDDR_XMPU0_CFG_R13_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU0_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13Mstr
+ */
+#define XDDR_XMPU0_CFG_R13_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13
+ */
+#define XDDR_XMPU0_CFG_R13    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU0_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14Strt
+ */
+#define XDDR_XMPU0_CFG_R14_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14End
+ */
+#define XDDR_XMPU0_CFG_R14_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU0_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14Mstr
+ */
+#define XDDR_XMPU0_CFG_R14_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14
+ */
+#define XDDR_XMPU0_CFG_R14    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU0_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15Strt
+ */
+#define XDDR_XMPU0_CFG_R15_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15End
+ */
+#define XDDR_XMPU0_CFG_R15_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU0_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15Mstr
+ */
+#define XDDR_XMPU0_CFG_R15_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15
+ */
+#define XDDR_XMPU0_CFG_R15    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU0_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU0_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h
new file mode 100644
index 000000000..e2fa6d4aa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU1_CFG_H__
+#define __XDDR_XMPU1_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu1Cfg Base Address
+ */
+#define XDDR_XMPU1_CFG_BASEADDR      0xFD010000UL
+
+/**
+ * Register: XddrXmpu1CfgCtrl
+ */
+#define XDDR_XMPU1_CFG_CTRL    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU1_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu1CfgErrSts1
+ */
+#define XDDR_XMPU1_CFG_ERR_STS1    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgErrSts2
+ */
+#define XDDR_XMPU1_CFG_ERR_STS2    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgPoison
+ */
+#define XDDR_XMPU1_CFG_POISON    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU1_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU1_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgIsr
+ */
+#define XDDR_XMPU1_CFG_ISR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU1_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgImr
+ */
+#define XDDR_XMPU1_CFG_IMR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU1_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu1CfgIen
+ */
+#define XDDR_XMPU1_CFG_IEN    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU1_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgIds
+ */
+#define XDDR_XMPU1_CFG_IDS    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU1_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgLock
+ */
+#define XDDR_XMPU1_CFG_LOCK    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU1_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00Strt
+ */
+#define XDDR_XMPU1_CFG_R00_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00End
+ */
+#define XDDR_XMPU1_CFG_R00_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU1_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00Mstr
+ */
+#define XDDR_XMPU1_CFG_R00_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00
+ */
+#define XDDR_XMPU1_CFG_R00    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU1_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01Strt
+ */
+#define XDDR_XMPU1_CFG_R01_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01End
+ */
+#define XDDR_XMPU1_CFG_R01_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU1_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01Mstr
+ */
+#define XDDR_XMPU1_CFG_R01_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01
+ */
+#define XDDR_XMPU1_CFG_R01    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU1_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02Strt
+ */
+#define XDDR_XMPU1_CFG_R02_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02End
+ */
+#define XDDR_XMPU1_CFG_R02_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU1_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02Mstr
+ */
+#define XDDR_XMPU1_CFG_R02_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02
+ */
+#define XDDR_XMPU1_CFG_R02    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU1_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03Strt
+ */
+#define XDDR_XMPU1_CFG_R03_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03End
+ */
+#define XDDR_XMPU1_CFG_R03_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU1_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03Mstr
+ */
+#define XDDR_XMPU1_CFG_R03_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03
+ */
+#define XDDR_XMPU1_CFG_R03    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU1_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04Strt
+ */
+#define XDDR_XMPU1_CFG_R04_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04End
+ */
+#define XDDR_XMPU1_CFG_R04_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU1_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04Mstr
+ */
+#define XDDR_XMPU1_CFG_R04_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04
+ */
+#define XDDR_XMPU1_CFG_R04    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU1_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05Strt
+ */
+#define XDDR_XMPU1_CFG_R05_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05End
+ */
+#define XDDR_XMPU1_CFG_R05_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU1_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05Mstr
+ */
+#define XDDR_XMPU1_CFG_R05_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05
+ */
+#define XDDR_XMPU1_CFG_R05    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU1_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06Strt
+ */
+#define XDDR_XMPU1_CFG_R06_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06End
+ */
+#define XDDR_XMPU1_CFG_R06_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU1_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06Mstr
+ */
+#define XDDR_XMPU1_CFG_R06_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06
+ */
+#define XDDR_XMPU1_CFG_R06    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU1_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07Strt
+ */
+#define XDDR_XMPU1_CFG_R07_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07End
+ */
+#define XDDR_XMPU1_CFG_R07_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU1_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07Mstr
+ */
+#define XDDR_XMPU1_CFG_R07_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07
+ */
+#define XDDR_XMPU1_CFG_R07    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU1_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08Strt
+ */
+#define XDDR_XMPU1_CFG_R08_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08End
+ */
+#define XDDR_XMPU1_CFG_R08_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU1_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08Mstr
+ */
+#define XDDR_XMPU1_CFG_R08_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08
+ */
+#define XDDR_XMPU1_CFG_R08    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU1_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09Strt
+ */
+#define XDDR_XMPU1_CFG_R09_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09End
+ */
+#define XDDR_XMPU1_CFG_R09_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU1_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09Mstr
+ */
+#define XDDR_XMPU1_CFG_R09_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09
+ */
+#define XDDR_XMPU1_CFG_R09    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU1_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10Strt
+ */
+#define XDDR_XMPU1_CFG_R10_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10End
+ */
+#define XDDR_XMPU1_CFG_R10_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU1_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10Mstr
+ */
+#define XDDR_XMPU1_CFG_R10_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10
+ */
+#define XDDR_XMPU1_CFG_R10    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU1_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11Strt
+ */
+#define XDDR_XMPU1_CFG_R11_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11End
+ */
+#define XDDR_XMPU1_CFG_R11_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU1_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11Mstr
+ */
+#define XDDR_XMPU1_CFG_R11_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11
+ */
+#define XDDR_XMPU1_CFG_R11    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU1_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12Strt
+ */
+#define XDDR_XMPU1_CFG_R12_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12End
+ */
+#define XDDR_XMPU1_CFG_R12_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU1_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12Mstr
+ */
+#define XDDR_XMPU1_CFG_R12_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12
+ */
+#define XDDR_XMPU1_CFG_R12    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU1_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13Strt
+ */
+#define XDDR_XMPU1_CFG_R13_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13End
+ */
+#define XDDR_XMPU1_CFG_R13_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU1_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13Mstr
+ */
+#define XDDR_XMPU1_CFG_R13_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13
+ */
+#define XDDR_XMPU1_CFG_R13    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU1_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14Strt
+ */
+#define XDDR_XMPU1_CFG_R14_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14End
+ */
+#define XDDR_XMPU1_CFG_R14_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU1_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14Mstr
+ */
+#define XDDR_XMPU1_CFG_R14_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14
+ */
+#define XDDR_XMPU1_CFG_R14    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU1_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15Strt
+ */
+#define XDDR_XMPU1_CFG_R15_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15End
+ */
+#define XDDR_XMPU1_CFG_R15_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU1_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15Mstr
+ */
+#define XDDR_XMPU1_CFG_R15_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15
+ */
+#define XDDR_XMPU1_CFG_R15    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU1_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU1_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h
new file mode 100644
index 000000000..55ea2a7d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU2_CFG_H__
+#define __XDDR_XMPU2_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu2Cfg Base Address
+ */
+#define XDDR_XMPU2_CFG_BASEADDR      0xFD020000UL
+
+/**
+ * Register: XddrXmpu2CfgCtrl
+ */
+#define XDDR_XMPU2_CFG_CTRL    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU2_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu2CfgErrSts1
+ */
+#define XDDR_XMPU2_CFG_ERR_STS1    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgErrSts2
+ */
+#define XDDR_XMPU2_CFG_ERR_STS2    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgPoison
+ */
+#define XDDR_XMPU2_CFG_POISON    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU2_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU2_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgIsr
+ */
+#define XDDR_XMPU2_CFG_ISR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU2_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgImr
+ */
+#define XDDR_XMPU2_CFG_IMR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU2_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu2CfgIen
+ */
+#define XDDR_XMPU2_CFG_IEN    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU2_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgIds
+ */
+#define XDDR_XMPU2_CFG_IDS    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU2_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgLock
+ */
+#define XDDR_XMPU2_CFG_LOCK    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU2_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00Strt
+ */
+#define XDDR_XMPU2_CFG_R00_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00End
+ */
+#define XDDR_XMPU2_CFG_R00_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU2_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00Mstr
+ */
+#define XDDR_XMPU2_CFG_R00_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00
+ */
+#define XDDR_XMPU2_CFG_R00    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU2_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01Strt
+ */
+#define XDDR_XMPU2_CFG_R01_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01End
+ */
+#define XDDR_XMPU2_CFG_R01_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU2_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01Mstr
+ */
+#define XDDR_XMPU2_CFG_R01_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01
+ */
+#define XDDR_XMPU2_CFG_R01    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU2_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02Strt
+ */
+#define XDDR_XMPU2_CFG_R02_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02End
+ */
+#define XDDR_XMPU2_CFG_R02_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU2_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02Mstr
+ */
+#define XDDR_XMPU2_CFG_R02_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02
+ */
+#define XDDR_XMPU2_CFG_R02    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU2_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03Strt
+ */
+#define XDDR_XMPU2_CFG_R03_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03End
+ */
+#define XDDR_XMPU2_CFG_R03_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU2_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03Mstr
+ */
+#define XDDR_XMPU2_CFG_R03_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03
+ */
+#define XDDR_XMPU2_CFG_R03    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU2_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04Strt
+ */
+#define XDDR_XMPU2_CFG_R04_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04End
+ */
+#define XDDR_XMPU2_CFG_R04_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU2_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04Mstr
+ */
+#define XDDR_XMPU2_CFG_R04_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04
+ */
+#define XDDR_XMPU2_CFG_R04    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU2_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05Strt
+ */
+#define XDDR_XMPU2_CFG_R05_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05End
+ */
+#define XDDR_XMPU2_CFG_R05_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU2_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05Mstr
+ */
+#define XDDR_XMPU2_CFG_R05_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05
+ */
+#define XDDR_XMPU2_CFG_R05    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU2_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06Strt
+ */
+#define XDDR_XMPU2_CFG_R06_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06End
+ */
+#define XDDR_XMPU2_CFG_R06_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU2_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06Mstr
+ */
+#define XDDR_XMPU2_CFG_R06_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06
+ */
+#define XDDR_XMPU2_CFG_R06    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU2_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07Strt
+ */
+#define XDDR_XMPU2_CFG_R07_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07End
+ */
+#define XDDR_XMPU2_CFG_R07_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU2_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07Mstr
+ */
+#define XDDR_XMPU2_CFG_R07_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07
+ */
+#define XDDR_XMPU2_CFG_R07    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU2_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08Strt
+ */
+#define XDDR_XMPU2_CFG_R08_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08End
+ */
+#define XDDR_XMPU2_CFG_R08_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU2_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08Mstr
+ */
+#define XDDR_XMPU2_CFG_R08_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08
+ */
+#define XDDR_XMPU2_CFG_R08    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU2_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09Strt
+ */
+#define XDDR_XMPU2_CFG_R09_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09End
+ */
+#define XDDR_XMPU2_CFG_R09_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU2_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09Mstr
+ */
+#define XDDR_XMPU2_CFG_R09_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09
+ */
+#define XDDR_XMPU2_CFG_R09    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU2_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10Strt
+ */
+#define XDDR_XMPU2_CFG_R10_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10End
+ */
+#define XDDR_XMPU2_CFG_R10_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU2_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10Mstr
+ */
+#define XDDR_XMPU2_CFG_R10_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10
+ */
+#define XDDR_XMPU2_CFG_R10    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU2_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11Strt
+ */
+#define XDDR_XMPU2_CFG_R11_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11End
+ */
+#define XDDR_XMPU2_CFG_R11_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU2_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11Mstr
+ */
+#define XDDR_XMPU2_CFG_R11_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11
+ */
+#define XDDR_XMPU2_CFG_R11    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU2_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12Strt
+ */
+#define XDDR_XMPU2_CFG_R12_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12End
+ */
+#define XDDR_XMPU2_CFG_R12_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU2_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12Mstr
+ */
+#define XDDR_XMPU2_CFG_R12_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12
+ */
+#define XDDR_XMPU2_CFG_R12    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU2_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13Strt
+ */
+#define XDDR_XMPU2_CFG_R13_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13End
+ */
+#define XDDR_XMPU2_CFG_R13_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU2_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13Mstr
+ */
+#define XDDR_XMPU2_CFG_R13_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13
+ */
+#define XDDR_XMPU2_CFG_R13    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU2_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14Strt
+ */
+#define XDDR_XMPU2_CFG_R14_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14End
+ */
+#define XDDR_XMPU2_CFG_R14_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU2_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14Mstr
+ */
+#define XDDR_XMPU2_CFG_R14_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14
+ */
+#define XDDR_XMPU2_CFG_R14    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU2_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15Strt
+ */
+#define XDDR_XMPU2_CFG_R15_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15End
+ */
+#define XDDR_XMPU2_CFG_R15_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU2_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15Mstr
+ */
+#define XDDR_XMPU2_CFG_R15_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15
+ */
+#define XDDR_XMPU2_CFG_R15    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU2_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU2_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h
new file mode 100644
index 000000000..416314967
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU3_CFG_H__
+#define __XDDR_XMPU3_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu3Cfg Base Address
+ */
+#define XDDR_XMPU3_CFG_BASEADDR      0xFD030000UL
+
+/**
+ * Register: XddrXmpu3CfgCtrl
+ */
+#define XDDR_XMPU3_CFG_CTRL    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU3_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu3CfgErrSts1
+ */
+#define XDDR_XMPU3_CFG_ERR_STS1    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgErrSts2
+ */
+#define XDDR_XMPU3_CFG_ERR_STS2    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgPoison
+ */
+#define XDDR_XMPU3_CFG_POISON    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU3_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU3_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgIsr
+ */
+#define XDDR_XMPU3_CFG_ISR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU3_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgImr
+ */
+#define XDDR_XMPU3_CFG_IMR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU3_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu3CfgIen
+ */
+#define XDDR_XMPU3_CFG_IEN    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU3_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgIds
+ */
+#define XDDR_XMPU3_CFG_IDS    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU3_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgLock
+ */
+#define XDDR_XMPU3_CFG_LOCK    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU3_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00Strt
+ */
+#define XDDR_XMPU3_CFG_R00_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00End
+ */
+#define XDDR_XMPU3_CFG_R00_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU3_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00Mstr
+ */
+#define XDDR_XMPU3_CFG_R00_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00
+ */
+#define XDDR_XMPU3_CFG_R00    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU3_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01Strt
+ */
+#define XDDR_XMPU3_CFG_R01_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01End
+ */
+#define XDDR_XMPU3_CFG_R01_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU3_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01Mstr
+ */
+#define XDDR_XMPU3_CFG_R01_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01
+ */
+#define XDDR_XMPU3_CFG_R01    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU3_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02Strt
+ */
+#define XDDR_XMPU3_CFG_R02_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02End
+ */
+#define XDDR_XMPU3_CFG_R02_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU3_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02Mstr
+ */
+#define XDDR_XMPU3_CFG_R02_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02
+ */
+#define XDDR_XMPU3_CFG_R02    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU3_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03Strt
+ */
+#define XDDR_XMPU3_CFG_R03_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03End
+ */
+#define XDDR_XMPU3_CFG_R03_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU3_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03Mstr
+ */
+#define XDDR_XMPU3_CFG_R03_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03
+ */
+#define XDDR_XMPU3_CFG_R03    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU3_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04Strt
+ */
+#define XDDR_XMPU3_CFG_R04_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04End
+ */
+#define XDDR_XMPU3_CFG_R04_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU3_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04Mstr
+ */
+#define XDDR_XMPU3_CFG_R04_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04
+ */
+#define XDDR_XMPU3_CFG_R04    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU3_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05Strt
+ */
+#define XDDR_XMPU3_CFG_R05_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05End
+ */
+#define XDDR_XMPU3_CFG_R05_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU3_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05Mstr
+ */
+#define XDDR_XMPU3_CFG_R05_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05
+ */
+#define XDDR_XMPU3_CFG_R05    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU3_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06Strt
+ */
+#define XDDR_XMPU3_CFG_R06_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06End
+ */
+#define XDDR_XMPU3_CFG_R06_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU3_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06Mstr
+ */
+#define XDDR_XMPU3_CFG_R06_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06
+ */
+#define XDDR_XMPU3_CFG_R06    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU3_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07Strt
+ */
+#define XDDR_XMPU3_CFG_R07_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07End
+ */
+#define XDDR_XMPU3_CFG_R07_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU3_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07Mstr
+ */
+#define XDDR_XMPU3_CFG_R07_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07
+ */
+#define XDDR_XMPU3_CFG_R07    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU3_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08Strt
+ */
+#define XDDR_XMPU3_CFG_R08_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08End
+ */
+#define XDDR_XMPU3_CFG_R08_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU3_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08Mstr
+ */
+#define XDDR_XMPU3_CFG_R08_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08
+ */
+#define XDDR_XMPU3_CFG_R08    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU3_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09Strt
+ */
+#define XDDR_XMPU3_CFG_R09_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09End
+ */
+#define XDDR_XMPU3_CFG_R09_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU3_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09Mstr
+ */
+#define XDDR_XMPU3_CFG_R09_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09
+ */
+#define XDDR_XMPU3_CFG_R09    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU3_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10Strt
+ */
+#define XDDR_XMPU3_CFG_R10_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10End
+ */
+#define XDDR_XMPU3_CFG_R10_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU3_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10Mstr
+ */
+#define XDDR_XMPU3_CFG_R10_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10
+ */
+#define XDDR_XMPU3_CFG_R10    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU3_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11Strt
+ */
+#define XDDR_XMPU3_CFG_R11_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11End
+ */
+#define XDDR_XMPU3_CFG_R11_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU3_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11Mstr
+ */
+#define XDDR_XMPU3_CFG_R11_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11
+ */
+#define XDDR_XMPU3_CFG_R11    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU3_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12Strt
+ */
+#define XDDR_XMPU3_CFG_R12_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12End
+ */
+#define XDDR_XMPU3_CFG_R12_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU3_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12Mstr
+ */
+#define XDDR_XMPU3_CFG_R12_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12
+ */
+#define XDDR_XMPU3_CFG_R12    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU3_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13Strt
+ */
+#define XDDR_XMPU3_CFG_R13_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13End
+ */
+#define XDDR_XMPU3_CFG_R13_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU3_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13Mstr
+ */
+#define XDDR_XMPU3_CFG_R13_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13
+ */
+#define XDDR_XMPU3_CFG_R13    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU3_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14Strt
+ */
+#define XDDR_XMPU3_CFG_R14_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14End
+ */
+#define XDDR_XMPU3_CFG_R14_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU3_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14Mstr
+ */
+#define XDDR_XMPU3_CFG_R14_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14
+ */
+#define XDDR_XMPU3_CFG_R14    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU3_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15Strt
+ */
+#define XDDR_XMPU3_CFG_R15_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15End
+ */
+#define XDDR_XMPU3_CFG_R15_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU3_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15Mstr
+ */
+#define XDDR_XMPU3_CFG_R15_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15
+ */
+#define XDDR_XMPU3_CFG_R15    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU3_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU3_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h
new file mode 100644
index 000000000..2df814419
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU4_CFG_H__
+#define __XDDR_XMPU4_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu4Cfg Base Address
+ */
+#define XDDR_XMPU4_CFG_BASEADDR      0xFD040000UL
+
+/**
+ * Register: XddrXmpu4CfgCtrl
+ */
+#define XDDR_XMPU4_CFG_CTRL    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU4_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu4CfgErrSts1
+ */
+#define XDDR_XMPU4_CFG_ERR_STS1    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgErrSts2
+ */
+#define XDDR_XMPU4_CFG_ERR_STS2    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgPoison
+ */
+#define XDDR_XMPU4_CFG_POISON    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU4_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU4_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgIsr
+ */
+#define XDDR_XMPU4_CFG_ISR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU4_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgImr
+ */
+#define XDDR_XMPU4_CFG_IMR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU4_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu4CfgIen
+ */
+#define XDDR_XMPU4_CFG_IEN    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU4_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgIds
+ */
+#define XDDR_XMPU4_CFG_IDS    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU4_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgLock
+ */
+#define XDDR_XMPU4_CFG_LOCK    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU4_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00Strt
+ */
+#define XDDR_XMPU4_CFG_R00_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00End
+ */
+#define XDDR_XMPU4_CFG_R00_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU4_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00Mstr
+ */
+#define XDDR_XMPU4_CFG_R00_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00
+ */
+#define XDDR_XMPU4_CFG_R00    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU4_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01Strt
+ */
+#define XDDR_XMPU4_CFG_R01_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01End
+ */
+#define XDDR_XMPU4_CFG_R01_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU4_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01Mstr
+ */
+#define XDDR_XMPU4_CFG_R01_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01
+ */
+#define XDDR_XMPU4_CFG_R01    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU4_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02Strt
+ */
+#define XDDR_XMPU4_CFG_R02_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02End
+ */
+#define XDDR_XMPU4_CFG_R02_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU4_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02Mstr
+ */
+#define XDDR_XMPU4_CFG_R02_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02
+ */
+#define XDDR_XMPU4_CFG_R02    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU4_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03Strt
+ */
+#define XDDR_XMPU4_CFG_R03_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03End
+ */
+#define XDDR_XMPU4_CFG_R03_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU4_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03Mstr
+ */
+#define XDDR_XMPU4_CFG_R03_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03
+ */
+#define XDDR_XMPU4_CFG_R03    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU4_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04Strt
+ */
+#define XDDR_XMPU4_CFG_R04_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04End
+ */
+#define XDDR_XMPU4_CFG_R04_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU4_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04Mstr
+ */
+#define XDDR_XMPU4_CFG_R04_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04
+ */
+#define XDDR_XMPU4_CFG_R04    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU4_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05Strt
+ */
+#define XDDR_XMPU4_CFG_R05_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05End
+ */
+#define XDDR_XMPU4_CFG_R05_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU4_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05Mstr
+ */
+#define XDDR_XMPU4_CFG_R05_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05
+ */
+#define XDDR_XMPU4_CFG_R05    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU4_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06Strt
+ */
+#define XDDR_XMPU4_CFG_R06_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06End
+ */
+#define XDDR_XMPU4_CFG_R06_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU4_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06Mstr
+ */
+#define XDDR_XMPU4_CFG_R06_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06
+ */
+#define XDDR_XMPU4_CFG_R06    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU4_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07Strt
+ */
+#define XDDR_XMPU4_CFG_R07_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07End
+ */
+#define XDDR_XMPU4_CFG_R07_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU4_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07Mstr
+ */
+#define XDDR_XMPU4_CFG_R07_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07
+ */
+#define XDDR_XMPU4_CFG_R07    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU4_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08Strt
+ */
+#define XDDR_XMPU4_CFG_R08_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08End
+ */
+#define XDDR_XMPU4_CFG_R08_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU4_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08Mstr
+ */
+#define XDDR_XMPU4_CFG_R08_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08
+ */
+#define XDDR_XMPU4_CFG_R08    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU4_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09Strt
+ */
+#define XDDR_XMPU4_CFG_R09_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09End
+ */
+#define XDDR_XMPU4_CFG_R09_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU4_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09Mstr
+ */
+#define XDDR_XMPU4_CFG_R09_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09
+ */
+#define XDDR_XMPU4_CFG_R09    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU4_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10Strt
+ */
+#define XDDR_XMPU4_CFG_R10_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10End
+ */
+#define XDDR_XMPU4_CFG_R10_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU4_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10Mstr
+ */
+#define XDDR_XMPU4_CFG_R10_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10
+ */
+#define XDDR_XMPU4_CFG_R10    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU4_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11Strt
+ */
+#define XDDR_XMPU4_CFG_R11_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11End
+ */
+#define XDDR_XMPU4_CFG_R11_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU4_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11Mstr
+ */
+#define XDDR_XMPU4_CFG_R11_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11
+ */
+#define XDDR_XMPU4_CFG_R11    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU4_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12Strt
+ */
+#define XDDR_XMPU4_CFG_R12_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12End
+ */
+#define XDDR_XMPU4_CFG_R12_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU4_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12Mstr
+ */
+#define XDDR_XMPU4_CFG_R12_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12
+ */
+#define XDDR_XMPU4_CFG_R12    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU4_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13Strt
+ */
+#define XDDR_XMPU4_CFG_R13_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13End
+ */
+#define XDDR_XMPU4_CFG_R13_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU4_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13Mstr
+ */
+#define XDDR_XMPU4_CFG_R13_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13
+ */
+#define XDDR_XMPU4_CFG_R13    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU4_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14Strt
+ */
+#define XDDR_XMPU4_CFG_R14_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14End
+ */
+#define XDDR_XMPU4_CFG_R14_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU4_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14Mstr
+ */
+#define XDDR_XMPU4_CFG_R14_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14
+ */
+#define XDDR_XMPU4_CFG_R14    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU4_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15Strt
+ */
+#define XDDR_XMPU4_CFG_R15_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15End
+ */
+#define XDDR_XMPU4_CFG_R15_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU4_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15Mstr
+ */
+#define XDDR_XMPU4_CFG_R15_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15
+ */
+#define XDDR_XMPU4_CFG_R15    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU4_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU4_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h
new file mode 100644
index 000000000..60811718d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU5_CFG_H__
+#define __XDDR_XMPU5_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu5Cfg Base Address
+ */
+#define XDDR_XMPU5_CFG_BASEADDR      0xFD050000UL
+
+/**
+ * Register: XddrXmpu5CfgCtrl
+ */
+#define XDDR_XMPU5_CFG_CTRL    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU5_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu5CfgErrSts1
+ */
+#define XDDR_XMPU5_CFG_ERR_STS1    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgErrSts2
+ */
+#define XDDR_XMPU5_CFG_ERR_STS2    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgPoison
+ */
+#define XDDR_XMPU5_CFG_POISON    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU5_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU5_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgIsr
+ */
+#define XDDR_XMPU5_CFG_ISR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU5_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgImr
+ */
+#define XDDR_XMPU5_CFG_IMR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU5_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu5CfgIen
+ */
+#define XDDR_XMPU5_CFG_IEN    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU5_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgIds
+ */
+#define XDDR_XMPU5_CFG_IDS    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU5_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgLock
+ */
+#define XDDR_XMPU5_CFG_LOCK    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU5_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00Strt
+ */
+#define XDDR_XMPU5_CFG_R00_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00End
+ */
+#define XDDR_XMPU5_CFG_R00_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU5_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00Mstr
+ */
+#define XDDR_XMPU5_CFG_R00_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00
+ */
+#define XDDR_XMPU5_CFG_R00    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU5_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01Strt
+ */
+#define XDDR_XMPU5_CFG_R01_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01End
+ */
+#define XDDR_XMPU5_CFG_R01_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU5_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01Mstr
+ */
+#define XDDR_XMPU5_CFG_R01_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01
+ */
+#define XDDR_XMPU5_CFG_R01    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU5_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02Strt
+ */
+#define XDDR_XMPU5_CFG_R02_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02End
+ */
+#define XDDR_XMPU5_CFG_R02_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU5_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02Mstr
+ */
+#define XDDR_XMPU5_CFG_R02_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02
+ */
+#define XDDR_XMPU5_CFG_R02    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU5_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03Strt
+ */
+#define XDDR_XMPU5_CFG_R03_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03End
+ */
+#define XDDR_XMPU5_CFG_R03_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU5_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03Mstr
+ */
+#define XDDR_XMPU5_CFG_R03_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03
+ */
+#define XDDR_XMPU5_CFG_R03    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU5_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04Strt
+ */
+#define XDDR_XMPU5_CFG_R04_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04End
+ */
+#define XDDR_XMPU5_CFG_R04_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU5_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04Mstr
+ */
+#define XDDR_XMPU5_CFG_R04_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04
+ */
+#define XDDR_XMPU5_CFG_R04    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU5_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05Strt
+ */
+#define XDDR_XMPU5_CFG_R05_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05End
+ */
+#define XDDR_XMPU5_CFG_R05_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU5_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05Mstr
+ */
+#define XDDR_XMPU5_CFG_R05_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05
+ */
+#define XDDR_XMPU5_CFG_R05    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU5_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06Strt
+ */
+#define XDDR_XMPU5_CFG_R06_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06End
+ */
+#define XDDR_XMPU5_CFG_R06_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU5_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06Mstr
+ */
+#define XDDR_XMPU5_CFG_R06_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06
+ */
+#define XDDR_XMPU5_CFG_R06    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU5_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07Strt
+ */
+#define XDDR_XMPU5_CFG_R07_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07End
+ */
+#define XDDR_XMPU5_CFG_R07_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU5_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07Mstr
+ */
+#define XDDR_XMPU5_CFG_R07_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07
+ */
+#define XDDR_XMPU5_CFG_R07    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU5_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08Strt
+ */
+#define XDDR_XMPU5_CFG_R08_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08End
+ */
+#define XDDR_XMPU5_CFG_R08_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU5_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08Mstr
+ */
+#define XDDR_XMPU5_CFG_R08_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08
+ */
+#define XDDR_XMPU5_CFG_R08    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU5_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09Strt
+ */
+#define XDDR_XMPU5_CFG_R09_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09End
+ */
+#define XDDR_XMPU5_CFG_R09_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU5_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09Mstr
+ */
+#define XDDR_XMPU5_CFG_R09_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09
+ */
+#define XDDR_XMPU5_CFG_R09    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU5_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10Strt
+ */
+#define XDDR_XMPU5_CFG_R10_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10End
+ */
+#define XDDR_XMPU5_CFG_R10_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU5_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10Mstr
+ */
+#define XDDR_XMPU5_CFG_R10_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10
+ */
+#define XDDR_XMPU5_CFG_R10    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU5_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11Strt
+ */
+#define XDDR_XMPU5_CFG_R11_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11End
+ */
+#define XDDR_XMPU5_CFG_R11_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU5_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11Mstr
+ */
+#define XDDR_XMPU5_CFG_R11_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11
+ */
+#define XDDR_XMPU5_CFG_R11    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU5_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12Strt
+ */
+#define XDDR_XMPU5_CFG_R12_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12End
+ */
+#define XDDR_XMPU5_CFG_R12_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU5_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12Mstr
+ */
+#define XDDR_XMPU5_CFG_R12_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12
+ */
+#define XDDR_XMPU5_CFG_R12    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU5_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13Strt
+ */
+#define XDDR_XMPU5_CFG_R13_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13End
+ */
+#define XDDR_XMPU5_CFG_R13_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU5_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13Mstr
+ */
+#define XDDR_XMPU5_CFG_R13_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13
+ */
+#define XDDR_XMPU5_CFG_R13    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU5_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14Strt
+ */
+#define XDDR_XMPU5_CFG_R14_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14End
+ */
+#define XDDR_XMPU5_CFG_R14_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU5_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14Mstr
+ */
+#define XDDR_XMPU5_CFG_R14_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14
+ */
+#define XDDR_XMPU5_CFG_R14    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU5_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15Strt
+ */
+#define XDDR_XMPU5_CFG_R15_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15End
+ */
+#define XDDR_XMPU5_CFG_R15_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU5_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15Mstr
+ */
+#define XDDR_XMPU5_CFG_R15_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15
+ */
+#define XDDR_XMPU5_CFG_R15    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU5_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU5_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h
new file mode 100644
index 000000000..b565b958a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h
@@ -0,0 +1,382 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_H__
+#define __XFPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcr Base Address
+ */
+#define XFPD_SLCR_BASEADDR      0xFD610000UL
+
+/**
+ * Register: XfpdSlcrWprot0
+ */
+#define XFPD_SLCR_WPROT0    ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XFPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XFPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XFPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XFPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrCtrl
+ */
+#define XFPD_SLCR_CTRL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIsr
+ */
+#define XFPD_SLCR_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrImr
+ */
+#define XFPD_SLCR_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrIer
+ */
+#define XFPD_SLCR_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIdr
+ */
+#define XFPD_SLCR_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrItr
+ */
+#define XFPD_SLCR_ITR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrWdtClkSel
+ */
+#define XFPD_SLCR_WDT_CLK_SEL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
+#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XFPD_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XFPD_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIntFpd
+ */
+#define XFPD_SLCR_INT_FPD    ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
+#define XFPD_SLCR_INT_FPD_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT   0UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH   1UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrGpu
+ */
+#define XFPD_SLCR_GPU    ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
+#define XFPD_SLCR_GPU_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_GPU_ARCACHE_SHIFT   7UL
+#define XFPD_SLCR_GPU_ARCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_ARCACHE_MASK    0x00000780UL
+#define XFPD_SLCR_GPU_ARCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_AWCACHE_SHIFT   3UL
+#define XFPD_SLCR_GPU_AWCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_AWCACHE_MASK    0x00000078UL
+#define XFPD_SLCR_GPU_AWCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT   2UL
+#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP1_IDLE_MASK    0x00000004UL
+#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_MASK    0x00000002UL
+#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_IDLE_SHIFT   0UL
+#define XFPD_SLCR_GPU_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_IDLE_MASK    0x00000001UL
+#define XFPD_SLCR_GPU_IDLE_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrGdmaCfg
+ */
+#define XFPD_SLCR_GDMA_CFG    ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XFPD_SLCR_GDMA_CFG_RSTVAL   0x00000048UL
+
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT   5UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH   2UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK    0x00000060UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL  0x2UL
+
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT   0UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH   5UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XfpdSlcrGdma
+ */
+#define XFPD_SLCR_GDMA    ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XFPD_SLCR_GDMA_RSTVAL   0x00003b3bUL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT   12UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK    0x00007000UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT   11UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK    0x00000800UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT   8UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK    0x00000700UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT   4UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK    0x00000070UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK    0x00000008UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT   0UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK    0x00000007UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XfpdSlcrAfiFs
+ */
+#define XFPD_SLCR_AFI_FS    ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
+#define XFPD_SLCR_AFI_FS_RSTVAL   0x00000a00UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT   10UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK    0x00000c00UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL  0x2UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT   8UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK    0x00000300UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XfpdSlcrErrAtbIsr
+ */
+#define XFPD_SLCR_ERR_ATB_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbImr
+ */
+#define XFPD_SLCR_ERR_ATB_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrErrAtbIer
+ */
+#define XFPD_SLCR_ERR_ATB_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XFPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbIdr
+ */
+#define XFPD_SLCR_ERR_ATB_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbCmdstore
+ */
+#define XFPD_SLCR_ATB_CMDSTORE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbRespEn
+ */
+#define XFPD_SLCR_ATB_RESP_EN    ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XFPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbResptype
+ */
+#define XFPD_SLCR_ATB_RESPTYPE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbPrescale
+ */
+#define XFPD_SLCR_ATB_PRESCALE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XFPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h
new file mode 100644
index 000000000..6541a4f1d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h
@@ -0,0 +1,277 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_SECURE_H__
+#define __XFPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcrSecure Base Address
+ */
+#define XFPD_SLCR_SECURE_BASEADDR      0xFD690000UL
+
+/**
+ * Register: XfpdSlcrSecCtrl
+ */
+#define XFPD_SLCR_SEC_CTRL    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIsr
+ */
+#define XFPD_SLCR_SEC_ISR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecImr
+ */
+#define XFPD_SLCR_SEC_IMR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecIer
+ */
+#define XFPD_SLCR_SEC_IER    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIdr
+ */
+#define XFPD_SLCR_SEC_IDR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecItr
+ */
+#define XFPD_SLCR_SEC_ITR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecSata
+ */
+#define XFPD_SLCR_SEC_SATA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XFPD_SLCR_SEC_SATA_RSTVAL   0x0000000eUL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT   3UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT   2UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecPcie
+ */
+#define XFPD_SLCR_SEC_PCIE    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XFPD_SLCR_SEC_PCIE_RSTVAL   0x01ffffffUL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT   24UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK    0x01000000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT   23UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK    0x00800000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT   22UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK    0x00400000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT   21UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK    0x00200000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT   20UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK    0x00100000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT   19UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK    0x00080000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT   18UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK    0x00040000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT   17UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK    0x00020000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT   16UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK    0x00010000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT   15UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK    0x00008000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT   14UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK    0x00004000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT   13UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK    0x00002000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT   12UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK    0x00001000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT   11UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK    0x00000800UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT   10UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK    0x00000400UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT   9UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK    0x00000200UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT   8UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK    0x00000100UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT   7UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK    0x00000080UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT   6UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK    0x00000040UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT   5UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK    0x00000020UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT   4UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK    0x00000010UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT   3UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT   2UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT   0UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecDpdma
+ */
+#define XFPD_SLCR_SEC_DPDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
+#define XFPD_SLCR_SEC_DPDMA_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH   1UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecGdma
+ */
+#define XFPD_SLCR_SEC_GDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
+#define XFPD_SLCR_SEC_GDMA_RSTVAL   0x000000ffUL
+
+#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH   8UL
+#define XFPD_SLCR_SEC_GDMA_TZ_MASK    0x000000ffUL
+#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL  0xffUL
+
+/**
+ * Register: XfpdSlcrSecGic
+ */
+#define XFPD_SLCR_SEC_GIC    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
+#define XFPD_SLCR_SEC_GIC_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT   0UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h
new file mode 100644
index 000000000..75aef19f9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_CFG_H__
+#define __XFPD_XMPU_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuCfg Base Address
+ */
+#define XFPD_XMPU_CFG_BASEADDR      0xFD5D0000UL
+
+/**
+ * Register: XfpdXmpuCfgCtrl
+ */
+#define XFPD_XMPU_CFG_CTRL    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL )
+#define XFPD_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuCfgErrSts1
+ */
+#define XFPD_XMPU_CFG_ERR_STS1    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL )
+#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgErrSts2
+ */
+#define XFPD_XMPU_CFG_ERR_STS2    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL )
+#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgPoison
+ */
+#define XFPD_XMPU_CFG_POISON    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
+#define XFPD_XMPU_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_POISON_BASE_SHIFT   0UL
+#define XFPD_XMPU_CFG_POISON_BASE_WIDTH   20UL
+#define XFPD_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgIsr
+ */
+#define XFPD_XMPU_CFG_ISR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL )
+#define XFPD_XMPU_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgImr
+ */
+#define XFPD_XMPU_CFG_IMR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL )
+#define XFPD_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuCfgIen
+ */
+#define XFPD_XMPU_CFG_IEN    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL )
+#define XFPD_XMPU_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgIds
+ */
+#define XFPD_XMPU_CFG_IDS    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
+#define XFPD_XMPU_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgLock
+ */
+#define XFPD_XMPU_CFG_LOCK    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL )
+#define XFPD_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00Strt
+ */
+#define XFPD_XMPU_CFG_R00_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL )
+#define XFPD_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00End
+ */
+#define XFPD_XMPU_CFG_R00_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL )
+#define XFPD_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00Mstr
+ */
+#define XFPD_XMPU_CFG_R00_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL )
+#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00
+ */
+#define XFPD_XMPU_CFG_R00    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
+#define XFPD_XMPU_CFG_R00_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01Strt
+ */
+#define XFPD_XMPU_CFG_R01_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL )
+#define XFPD_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01End
+ */
+#define XFPD_XMPU_CFG_R01_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL )
+#define XFPD_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01Mstr
+ */
+#define XFPD_XMPU_CFG_R01_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL )
+#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01
+ */
+#define XFPD_XMPU_CFG_R01    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
+#define XFPD_XMPU_CFG_R01_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02Strt
+ */
+#define XFPD_XMPU_CFG_R02_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL )
+#define XFPD_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02End
+ */
+#define XFPD_XMPU_CFG_R02_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL )
+#define XFPD_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02Mstr
+ */
+#define XFPD_XMPU_CFG_R02_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL )
+#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02
+ */
+#define XFPD_XMPU_CFG_R02    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
+#define XFPD_XMPU_CFG_R02_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03Strt
+ */
+#define XFPD_XMPU_CFG_R03_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL )
+#define XFPD_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03End
+ */
+#define XFPD_XMPU_CFG_R03_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL )
+#define XFPD_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03Mstr
+ */
+#define XFPD_XMPU_CFG_R03_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL )
+#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03
+ */
+#define XFPD_XMPU_CFG_R03    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
+#define XFPD_XMPU_CFG_R03_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04Strt
+ */
+#define XFPD_XMPU_CFG_R04_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL )
+#define XFPD_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04End
+ */
+#define XFPD_XMPU_CFG_R04_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL )
+#define XFPD_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04Mstr
+ */
+#define XFPD_XMPU_CFG_R04_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL )
+#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04
+ */
+#define XFPD_XMPU_CFG_R04    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
+#define XFPD_XMPU_CFG_R04_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05Strt
+ */
+#define XFPD_XMPU_CFG_R05_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL )
+#define XFPD_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05End
+ */
+#define XFPD_XMPU_CFG_R05_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL )
+#define XFPD_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05Mstr
+ */
+#define XFPD_XMPU_CFG_R05_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL )
+#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05
+ */
+#define XFPD_XMPU_CFG_R05    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
+#define XFPD_XMPU_CFG_R05_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06Strt
+ */
+#define XFPD_XMPU_CFG_R06_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL )
+#define XFPD_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06End
+ */
+#define XFPD_XMPU_CFG_R06_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL )
+#define XFPD_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06Mstr
+ */
+#define XFPD_XMPU_CFG_R06_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL )
+#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06
+ */
+#define XFPD_XMPU_CFG_R06    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
+#define XFPD_XMPU_CFG_R06_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07Strt
+ */
+#define XFPD_XMPU_CFG_R07_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL )
+#define XFPD_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07End
+ */
+#define XFPD_XMPU_CFG_R07_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL )
+#define XFPD_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07Mstr
+ */
+#define XFPD_XMPU_CFG_R07_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL )
+#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07
+ */
+#define XFPD_XMPU_CFG_R07    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
+#define XFPD_XMPU_CFG_R07_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08Strt
+ */
+#define XFPD_XMPU_CFG_R08_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL )
+#define XFPD_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08End
+ */
+#define XFPD_XMPU_CFG_R08_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL )
+#define XFPD_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08Mstr
+ */
+#define XFPD_XMPU_CFG_R08_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL )
+#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08
+ */
+#define XFPD_XMPU_CFG_R08    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
+#define XFPD_XMPU_CFG_R08_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09Strt
+ */
+#define XFPD_XMPU_CFG_R09_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL )
+#define XFPD_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09End
+ */
+#define XFPD_XMPU_CFG_R09_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL )
+#define XFPD_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09Mstr
+ */
+#define XFPD_XMPU_CFG_R09_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL )
+#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09
+ */
+#define XFPD_XMPU_CFG_R09    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
+#define XFPD_XMPU_CFG_R09_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10Strt
+ */
+#define XFPD_XMPU_CFG_R10_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
+#define XFPD_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10End
+ */
+#define XFPD_XMPU_CFG_R10_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
+#define XFPD_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10Mstr
+ */
+#define XFPD_XMPU_CFG_R10_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
+#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10
+ */
+#define XFPD_XMPU_CFG_R10    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
+#define XFPD_XMPU_CFG_R10_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11Strt
+ */
+#define XFPD_XMPU_CFG_R11_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
+#define XFPD_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11End
+ */
+#define XFPD_XMPU_CFG_R11_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
+#define XFPD_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11Mstr
+ */
+#define XFPD_XMPU_CFG_R11_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
+#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11
+ */
+#define XFPD_XMPU_CFG_R11    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
+#define XFPD_XMPU_CFG_R11_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12Strt
+ */
+#define XFPD_XMPU_CFG_R12_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
+#define XFPD_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12End
+ */
+#define XFPD_XMPU_CFG_R12_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
+#define XFPD_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12Mstr
+ */
+#define XFPD_XMPU_CFG_R12_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
+#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12
+ */
+#define XFPD_XMPU_CFG_R12    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
+#define XFPD_XMPU_CFG_R12_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13Strt
+ */
+#define XFPD_XMPU_CFG_R13_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
+#define XFPD_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13End
+ */
+#define XFPD_XMPU_CFG_R13_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
+#define XFPD_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13Mstr
+ */
+#define XFPD_XMPU_CFG_R13_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
+#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13
+ */
+#define XFPD_XMPU_CFG_R13    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
+#define XFPD_XMPU_CFG_R13_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14Strt
+ */
+#define XFPD_XMPU_CFG_R14_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
+#define XFPD_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14End
+ */
+#define XFPD_XMPU_CFG_R14_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
+#define XFPD_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14Mstr
+ */
+#define XFPD_XMPU_CFG_R14_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
+#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14
+ */
+#define XFPD_XMPU_CFG_R14    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
+#define XFPD_XMPU_CFG_R14_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15Strt
+ */
+#define XFPD_XMPU_CFG_R15_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
+#define XFPD_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15End
+ */
+#define XFPD_XMPU_CFG_R15_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
+#define XFPD_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15Mstr
+ */
+#define XFPD_XMPU_CFG_R15_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
+#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15
+ */
+#define XFPD_XMPU_CFG_R15    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
+#define XFPD_XMPU_CFG_R15_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h
new file mode 100644
index 000000000..39172f1f4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h
@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_SINK_H__
+#define __XFPD_XMPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuSink Base Address
+ */
+#define XFPD_XMPU_SINK_BASEADDR      0xFD4F0000UL
+
+/**
+ * Register: XfpdXmpuSinkErrSts
+ */
+#define XFPD_XMPU_SINK_ERR_STS    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XFPD_XMPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIsr
+ */
+#define XFPD_XMPU_SINK_ISR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XFPD_XMPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkImr
+ */
+#define XFPD_XMPU_SINK_IMR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XFPD_XMPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuSinkIer
+ */
+#define XFPD_XMPU_SINK_IER    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XFPD_XMPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIdr
+ */
+#define XFPD_XMPU_SINK_IDR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XFPD_XMPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h
new file mode 100644
index 000000000..cb4ad4903
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h
@@ -0,0 +1,174 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SECURE_SLCR_H__
+#define __XIOU_SECURE_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSecureSlcr Base Address
+ */
+#define XIOU_SECURE_SLCR_BASEADDR      0xFF240000UL
+
+/**
+ * Register: XiouSecSlcrAxiWprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_WPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT   25UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK    0x0e000000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrAxiRprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_RPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrCtrl
+ */
+#define XIOU_SEC_SLCR_CTRL    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SEC_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIsr
+ */
+#define XIOU_SEC_SLCR_ISR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SEC_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrImr
+ */
+#define XIOU_SEC_SLCR_IMR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SEC_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSecSlcrIer
+ */
+#define XIOU_SEC_SLCR_IER    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SEC_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIdr
+ */
+#define XIOU_SEC_SLCR_IDR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SEC_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrItr
+ */
+#define XIOU_SEC_SLCR_ITR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SEC_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SECURE_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
new file mode 100644
index 000000000..c53954c97
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
@@ -0,0 +1,4029 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SLCR_H__
+#define __XIOU_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSlcr Base Address
+ */
+#define XIOU_SLCR_BASEADDR      0xFF180000UL
+
+/**
+ * Register: XiouSlcrMioPin0
+ */
+#define XIOU_SLCR_MIO_PIN_0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SLCR_MIO_PIN_0_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin1
+ */
+#define XIOU_SLCR_MIO_PIN_1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SLCR_MIO_PIN_1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin2
+ */
+#define XIOU_SLCR_MIO_PIN_2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL )
+#define XIOU_SLCR_MIO_PIN_2_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin3
+ */
+#define XIOU_SLCR_MIO_PIN_3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XIOU_SLCR_MIO_PIN_3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin4
+ */
+#define XIOU_SLCR_MIO_PIN_4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL )
+#define XIOU_SLCR_MIO_PIN_4_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin5
+ */
+#define XIOU_SLCR_MIO_PIN_5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL )
+#define XIOU_SLCR_MIO_PIN_5_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin6
+ */
+#define XIOU_SLCR_MIO_PIN_6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL )
+#define XIOU_SLCR_MIO_PIN_6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin7
+ */
+#define XIOU_SLCR_MIO_PIN_7    ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL )
+#define XIOU_SLCR_MIO_PIN_7_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin8
+ */
+#define XIOU_SLCR_MIO_PIN_8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL )
+#define XIOU_SLCR_MIO_PIN_8_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin9
+ */
+#define XIOU_SLCR_MIO_PIN_9    ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL )
+#define XIOU_SLCR_MIO_PIN_9_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin10
+ */
+#define XIOU_SLCR_MIO_PIN_10    ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL )
+#define XIOU_SLCR_MIO_PIN_10_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin11
+ */
+#define XIOU_SLCR_MIO_PIN_11    ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL )
+#define XIOU_SLCR_MIO_PIN_11_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin12
+ */
+#define XIOU_SLCR_MIO_PIN_12    ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL )
+#define XIOU_SLCR_MIO_PIN_12_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin13
+ */
+#define XIOU_SLCR_MIO_PIN_13    ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL )
+#define XIOU_SLCR_MIO_PIN_13_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin14
+ */
+#define XIOU_SLCR_MIO_PIN_14    ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL )
+#define XIOU_SLCR_MIO_PIN_14_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin15
+ */
+#define XIOU_SLCR_MIO_PIN_15    ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL )
+#define XIOU_SLCR_MIO_PIN_15_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin16
+ */
+#define XIOU_SLCR_MIO_PIN_16    ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SLCR_MIO_PIN_16_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin17
+ */
+#define XIOU_SLCR_MIO_PIN_17    ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SLCR_MIO_PIN_17_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin18
+ */
+#define XIOU_SLCR_MIO_PIN_18    ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SLCR_MIO_PIN_18_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin19
+ */
+#define XIOU_SLCR_MIO_PIN_19    ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SLCR_MIO_PIN_19_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin20
+ */
+#define XIOU_SLCR_MIO_PIN_20    ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SLCR_MIO_PIN_20_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin21
+ */
+#define XIOU_SLCR_MIO_PIN_21    ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SLCR_MIO_PIN_21_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin22
+ */
+#define XIOU_SLCR_MIO_PIN_22    ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL )
+#define XIOU_SLCR_MIO_PIN_22_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin23
+ */
+#define XIOU_SLCR_MIO_PIN_23    ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL )
+#define XIOU_SLCR_MIO_PIN_23_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin24
+ */
+#define XIOU_SLCR_MIO_PIN_24    ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL )
+#define XIOU_SLCR_MIO_PIN_24_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin25
+ */
+#define XIOU_SLCR_MIO_PIN_25    ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL )
+#define XIOU_SLCR_MIO_PIN_25_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin26
+ */
+#define XIOU_SLCR_MIO_PIN_26    ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL )
+#define XIOU_SLCR_MIO_PIN_26_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin27
+ */
+#define XIOU_SLCR_MIO_PIN_27    ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL )
+#define XIOU_SLCR_MIO_PIN_27_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin28
+ */
+#define XIOU_SLCR_MIO_PIN_28    ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL )
+#define XIOU_SLCR_MIO_PIN_28_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin29
+ */
+#define XIOU_SLCR_MIO_PIN_29    ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL )
+#define XIOU_SLCR_MIO_PIN_29_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin30
+ */
+#define XIOU_SLCR_MIO_PIN_30    ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL )
+#define XIOU_SLCR_MIO_PIN_30_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin31
+ */
+#define XIOU_SLCR_MIO_PIN_31    ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL )
+#define XIOU_SLCR_MIO_PIN_31_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin32
+ */
+#define XIOU_SLCR_MIO_PIN_32    ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL )
+#define XIOU_SLCR_MIO_PIN_32_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin33
+ */
+#define XIOU_SLCR_MIO_PIN_33    ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL )
+#define XIOU_SLCR_MIO_PIN_33_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin34
+ */
+#define XIOU_SLCR_MIO_PIN_34    ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL )
+#define XIOU_SLCR_MIO_PIN_34_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin35
+ */
+#define XIOU_SLCR_MIO_PIN_35    ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL )
+#define XIOU_SLCR_MIO_PIN_35_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin36
+ */
+#define XIOU_SLCR_MIO_PIN_36    ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL )
+#define XIOU_SLCR_MIO_PIN_36_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin37
+ */
+#define XIOU_SLCR_MIO_PIN_37    ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL )
+#define XIOU_SLCR_MIO_PIN_37_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin38
+ */
+#define XIOU_SLCR_MIO_PIN_38    ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL )
+#define XIOU_SLCR_MIO_PIN_38_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin39
+ */
+#define XIOU_SLCR_MIO_PIN_39    ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL )
+#define XIOU_SLCR_MIO_PIN_39_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin40
+ */
+#define XIOU_SLCR_MIO_PIN_40    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL )
+#define XIOU_SLCR_MIO_PIN_40_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin41
+ */
+#define XIOU_SLCR_MIO_PIN_41    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL )
+#define XIOU_SLCR_MIO_PIN_41_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin42
+ */
+#define XIOU_SLCR_MIO_PIN_42    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL )
+#define XIOU_SLCR_MIO_PIN_42_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin43
+ */
+#define XIOU_SLCR_MIO_PIN_43    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL )
+#define XIOU_SLCR_MIO_PIN_43_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin44
+ */
+#define XIOU_SLCR_MIO_PIN_44    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL )
+#define XIOU_SLCR_MIO_PIN_44_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin45
+ */
+#define XIOU_SLCR_MIO_PIN_45    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL )
+#define XIOU_SLCR_MIO_PIN_45_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin46
+ */
+#define XIOU_SLCR_MIO_PIN_46    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL )
+#define XIOU_SLCR_MIO_PIN_46_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin47
+ */
+#define XIOU_SLCR_MIO_PIN_47    ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL )
+#define XIOU_SLCR_MIO_PIN_47_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin48
+ */
+#define XIOU_SLCR_MIO_PIN_48    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL )
+#define XIOU_SLCR_MIO_PIN_48_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin49
+ */
+#define XIOU_SLCR_MIO_PIN_49    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL )
+#define XIOU_SLCR_MIO_PIN_49_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin50
+ */
+#define XIOU_SLCR_MIO_PIN_50    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL )
+#define XIOU_SLCR_MIO_PIN_50_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin51
+ */
+#define XIOU_SLCR_MIO_PIN_51    ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL )
+#define XIOU_SLCR_MIO_PIN_51_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin52
+ */
+#define XIOU_SLCR_MIO_PIN_52    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL )
+#define XIOU_SLCR_MIO_PIN_52_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin53
+ */
+#define XIOU_SLCR_MIO_PIN_53    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL )
+#define XIOU_SLCR_MIO_PIN_53_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin54
+ */
+#define XIOU_SLCR_MIO_PIN_54    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL )
+#define XIOU_SLCR_MIO_PIN_54_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin55
+ */
+#define XIOU_SLCR_MIO_PIN_55    ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL )
+#define XIOU_SLCR_MIO_PIN_55_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin56
+ */
+#define XIOU_SLCR_MIO_PIN_56    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL )
+#define XIOU_SLCR_MIO_PIN_56_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin57
+ */
+#define XIOU_SLCR_MIO_PIN_57    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL )
+#define XIOU_SLCR_MIO_PIN_57_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin58
+ */
+#define XIOU_SLCR_MIO_PIN_58    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL )
+#define XIOU_SLCR_MIO_PIN_58_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin59
+ */
+#define XIOU_SLCR_MIO_PIN_59    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL )
+#define XIOU_SLCR_MIO_PIN_59_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin60
+ */
+#define XIOU_SLCR_MIO_PIN_60    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL )
+#define XIOU_SLCR_MIO_PIN_60_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin61
+ */
+#define XIOU_SLCR_MIO_PIN_61    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL )
+#define XIOU_SLCR_MIO_PIN_61_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin62
+ */
+#define XIOU_SLCR_MIO_PIN_62    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL )
+#define XIOU_SLCR_MIO_PIN_62_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin63
+ */
+#define XIOU_SLCR_MIO_PIN_63    ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL )
+#define XIOU_SLCR_MIO_PIN_63_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin64
+ */
+#define XIOU_SLCR_MIO_PIN_64    ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL )
+#define XIOU_SLCR_MIO_PIN_64_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin65
+ */
+#define XIOU_SLCR_MIO_PIN_65    ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL )
+#define XIOU_SLCR_MIO_PIN_65_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin66
+ */
+#define XIOU_SLCR_MIO_PIN_66    ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL )
+#define XIOU_SLCR_MIO_PIN_66_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin67
+ */
+#define XIOU_SLCR_MIO_PIN_67    ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL )
+#define XIOU_SLCR_MIO_PIN_67_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin68
+ */
+#define XIOU_SLCR_MIO_PIN_68    ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL )
+#define XIOU_SLCR_MIO_PIN_68_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin69
+ */
+#define XIOU_SLCR_MIO_PIN_69    ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL )
+#define XIOU_SLCR_MIO_PIN_69_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin70
+ */
+#define XIOU_SLCR_MIO_PIN_70    ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL )
+#define XIOU_SLCR_MIO_PIN_70_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin71
+ */
+#define XIOU_SLCR_MIO_PIN_71    ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL )
+#define XIOU_SLCR_MIO_PIN_71_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin72
+ */
+#define XIOU_SLCR_MIO_PIN_72    ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL )
+#define XIOU_SLCR_MIO_PIN_72_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin73
+ */
+#define XIOU_SLCR_MIO_PIN_73    ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL )
+#define XIOU_SLCR_MIO_PIN_73_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin74
+ */
+#define XIOU_SLCR_MIO_PIN_74    ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL )
+#define XIOU_SLCR_MIO_PIN_74_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin75
+ */
+#define XIOU_SLCR_MIO_PIN_75    ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL )
+#define XIOU_SLCR_MIO_PIN_75_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin76
+ */
+#define XIOU_SLCR_MIO_PIN_76    ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL )
+#define XIOU_SLCR_MIO_PIN_76_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin77
+ */
+#define XIOU_SLCR_MIO_PIN_77    ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL )
+#define XIOU_SLCR_MIO_PIN_77_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl0
+ */
+#define XIOU_SLCR_BANK0_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL )
+#define XIOU_SLCR_BANK0_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl1
+ */
+#define XIOU_SLCR_BANK0_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL )
+#define XIOU_SLCR_BANK0_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl3
+ */
+#define XIOU_SLCR_BANK0_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL )
+#define XIOU_SLCR_BANK0_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl4
+ */
+#define XIOU_SLCR_BANK0_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL )
+#define XIOU_SLCR_BANK0_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl5
+ */
+#define XIOU_SLCR_BANK0_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL )
+#define XIOU_SLCR_BANK0_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl6
+ */
+#define XIOU_SLCR_BANK0_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL )
+#define XIOU_SLCR_BANK0_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Sts
+ */
+#define XIOU_SLCR_BANK0_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL )
+#define XIOU_SLCR_BANK0_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl0
+ */
+#define XIOU_SLCR_BANK1_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL )
+#define XIOU_SLCR_BANK1_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl1
+ */
+#define XIOU_SLCR_BANK1_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL )
+#define XIOU_SLCR_BANK1_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl3
+ */
+#define XIOU_SLCR_BANK1_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL )
+#define XIOU_SLCR_BANK1_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl4
+ */
+#define XIOU_SLCR_BANK1_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL )
+#define XIOU_SLCR_BANK1_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl5
+ */
+#define XIOU_SLCR_BANK1_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL )
+#define XIOU_SLCR_BANK1_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl6
+ */
+#define XIOU_SLCR_BANK1_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL )
+#define XIOU_SLCR_BANK1_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Sts
+ */
+#define XIOU_SLCR_BANK1_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL )
+#define XIOU_SLCR_BANK1_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl0
+ */
+#define XIOU_SLCR_BANK2_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL )
+#define XIOU_SLCR_BANK2_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl1
+ */
+#define XIOU_SLCR_BANK2_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL )
+#define XIOU_SLCR_BANK2_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl3
+ */
+#define XIOU_SLCR_BANK2_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL )
+#define XIOU_SLCR_BANK2_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl4
+ */
+#define XIOU_SLCR_BANK2_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL )
+#define XIOU_SLCR_BANK2_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl5
+ */
+#define XIOU_SLCR_BANK2_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL )
+#define XIOU_SLCR_BANK2_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl6
+ */
+#define XIOU_SLCR_BANK2_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL )
+#define XIOU_SLCR_BANK2_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Sts
+ */
+#define XIOU_SLCR_BANK2_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL )
+#define XIOU_SLCR_BANK2_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioLpbck
+ */
+#define XIOU_SLCR_MIO_LPBCK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL )
+#define XIOU_SLCR_MIO_LPBCK_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT   3UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT   2UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT   1UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT   0UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioMstTri0
+ */
+#define XIOU_SLCR_MIO_MST_TRI0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL )
+#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL   0xffffffffUL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT   31UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK    0x80000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT   30UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK    0x40000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT   29UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK    0x20000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT   28UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK    0x10000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT   27UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK    0x08000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT   26UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK    0x04000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT   25UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK    0x02000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT   24UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK    0x01000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT   23UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK    0x00800000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT   22UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK    0x00400000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT   21UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK    0x00200000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT   20UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK    0x00100000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT   19UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK    0x00080000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT   18UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK    0x00040000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT   17UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK    0x00020000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT   16UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK    0x00010000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT   15UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK    0x00008000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT   14UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK    0x00004000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrMioMstTri1
+ */
+#define XIOU_SLCR_MIO_MST_TRI1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL )
+#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL   0xffffffffUL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT   31UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK    0x80000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT   30UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK    0x40000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT   29UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK    0x20000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT   28UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK    0x10000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT   27UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK    0x08000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT   26UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK    0x04000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT   25UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK    0x02000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT   24UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK    0x01000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT   23UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK    0x00800000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT   22UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK    0x00400000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT   21UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK    0x00200000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT   20UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK    0x00100000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT   19UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK    0x00080000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT   18UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK    0x00040000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT   17UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK    0x00020000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT   16UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK    0x00010000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT   15UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK    0x00008000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT   14UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK    0x00004000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrMioMstTri2
+ */
+#define XIOU_SLCR_MIO_MST_TRI2    ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL )
+#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL   0x00003fffUL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrWdtClkSel
+ */
+#define XIOU_SLCR_WDT_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL )
+#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XIOU_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrCanMioCtrl
+ */
+#define XIOU_SLCR_CAN_MIO_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL )
+#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT   23UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK    0x00800000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT   22UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK    0x00400000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT   15UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK    0x003f8000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT   8UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK    0x00000100UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK    0x00000080UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT   0UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK    0x0000007fUL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrGemClkCtrl
+ */
+#define XIOU_SLCR_GEM_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL )
+#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT   22UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK    0x00400000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT   20UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH   2UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK    0x00300000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   18UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00040000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   17UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00020000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   16UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00010000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   15UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   13UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00002000UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   12UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00001000UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   11UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000800UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   10UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000400UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   8UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000100UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   7UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000080UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   6UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000040UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   5UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000020UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   3UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000008UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   2UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000004UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   0UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdioClkCtrl
+ */
+#define XIOU_SLCR_SDIO_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL )
+#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT   18UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK    0x00040000UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT   17UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK    0x00020000UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT   2UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT   0UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH   2UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK    0x00000003UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrCtrlRegSd
+ */
+#define XIOU_SLCR_CTRL_REG_SD    ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL )
+#define XIOU_SLCR_CTRL_REG_SD_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_SHIFT      15UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_SHIFT      0UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdItapdly
+ */
+#define XIOU_SLCR_SD_ITAPDLY    ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL )
+#define XIOU_SLCR_SD_ITAPDLY_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT      25UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x02000000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   24UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x01000000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   16UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   9UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x00000200UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   8UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x00000100UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdOtapdlysel
+ */
+#define XIOU_SLCR_SD_OTAPDLYSEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL )
+#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   22UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00400000UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_MASK    0x003f0000UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT      6UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00000040UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_MASK    0x0000003fUL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg1
+ */
+#define XIOU_SLCR_SD_CFG_REG1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL )
+#define XIOU_SLCR_SD_CFG_REG1_RSTVAL   0x32403240UL
+
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_SHIFT   23UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_MASK    0x7f800000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   17UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x007e0000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   16UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_SHIFT   7UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_MASK    0x00007f80UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   1UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x0000007eUL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   0UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg2
+ */
+#define XIOU_SLCR_SD_CFG_REG2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL )
+#define XIOU_SLCR_SD_CFG_REG2_RSTVAL   0x0ffc0ffcUL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   28UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x30000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_SHIFT   27UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_MASK    0x08000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_SHIFT   26UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_MASK    0x04000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_SHIFT   25UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_MASK    0x02000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_SHIFT   24UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_MASK    0x01000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_SHIFT   23UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_MASK    0x00800000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_SHIFT   22UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_MASK    0x00400000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_SHIFT   21UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_MASK    0x00200000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   20UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00100000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_SHIFT   19UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_MASK    0x00080000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_SHIFT   18UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_MASK    0x00040000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_SHIFT   16UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_MASK    0x00030000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   12UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x00003000UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_SHIFT   11UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_MASK    0x00000800UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_SHIFT   10UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_MASK    0x00000400UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_SHIFT   9UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_MASK    0x00000200UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_SHIFT   8UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_MASK    0x00000100UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_SHIFT   7UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_MASK    0x00000080UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_SHIFT   6UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_MASK    0x00000040UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_SHIFT   5UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_MASK    0x00000020UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   4UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00000010UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_SHIFT   3UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_MASK    0x00000008UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_SHIFT   2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_MASK    0x00000004UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_SHIFT   0UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_MASK    0x00000003UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg3
+ */
+#define XIOU_SLCR_SD_CFG_REG3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL )
+#define XIOU_SLCR_SD_CFG_REG3_RSTVAL   0x06070607UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   26UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x04000000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_SHIFT   22UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_MASK    0x03c00000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_SHIFT   21UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_MASK    0x00200000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_SHIFT   20UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_MASK    0x00100000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_SHIFT   19UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_MASK    0x00080000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_SHIFT   18UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_MASK    0x00040000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_SHIFT   17UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_MASK    0x00020000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_SHIFT   16UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   10UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x00000400UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_SHIFT   6UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_MASK    0x000003c0UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_SHIFT   5UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_MASK    0x00000020UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_SHIFT   4UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_MASK    0x00000010UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_SHIFT   3UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_MASK    0x00000008UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_SHIFT   2UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_MASK    0x00000004UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_SHIFT   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_MASK    0x00000002UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_SHIFT   0UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrSdInitpreset
+ */
+#define XIOU_SLCR_SD_INITPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL )
+#define XIOU_SLCR_SD_INITPRESET_RSTVAL   0x01000100UL
+
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_DEFVAL  0x100UL
+
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_DEFVAL  0x100UL
+
+/**
+ * Register: XiouSlcrSdDsppreset
+ */
+#define XIOU_SLCR_SD_DSPPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
+#define XIOU_SLCR_SD_DSPPRESET_RSTVAL   0x00040004UL
+
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_DEFVAL  0x4UL
+
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_DEFVAL  0x4UL
+
+/**
+ * Register: XiouSlcrSdHspdpreset
+ */
+#define XIOU_SLCR_SD_HSPDPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL )
+#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdSdr12preset
+ */
+#define XIOU_SLCR_SD_SDR12PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL )
+#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL   0x00040004UL
+
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+
+/**
+ * Register: XiouSlcrSdSdr25preset
+ */
+#define XIOU_SLCR_SD_SDR25PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL )
+#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdSdr50prset
+ */
+#define XIOU_SLCR_SD_SDR50PRSET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL )
+#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL   0x00010001UL
+
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrSdSdr104prst
+ */
+#define XIOU_SLCR_SD_SDR104PRST    ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL )
+#define XIOU_SLCR_SD_SDR104PRST_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdDdr50preset
+ */
+#define XIOU_SLCR_SD_DDR50PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL )
+#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdMaxcur1p8
+ */
+#define XIOU_SLCR_SD_MAXCUR1P8    ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
+#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdMaxcur3p0
+ */
+#define XIOU_SLCR_SD_MAXCUR3P0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL )
+#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdMaxcur3p3
+ */
+#define XIOU_SLCR_SD_MAXCUR3P3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL )
+#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdDllCtrl
+ */
+#define XIOU_SLCR_SD_DLL_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL )
+#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_SHIFT   18UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_MASK    0x00040000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_SHIFT   17UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00020000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_SHIFT   16UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_SHIFT   2UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_MASK    0x00000004UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_SHIFT   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00000002UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_SHIFT   0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCdnCtrl
+ */
+#define XIOU_SLCR_SD_CDN_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL )
+#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrGemCtrl
+ */
+#define XIOU_SLCR_GEM_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL )
+#define XIOU_SLCR_GEM_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_SHIFT   6UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_MASK    0x000000c0UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_SHIFT   4UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_MASK    0x00000030UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_SHIFT   2UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_MASK    0x0000000cUL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_SHIFT   0UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_MASK    0x00000003UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrTtcApbClk
+ */
+#define XIOU_SLCR_TTC_APB_CLK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL )
+#define XIOU_SLCR_TTC_APB_CLK_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT   6UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK    0x000000c0UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT   4UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK    0x00000030UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK    0x0000000cUL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT   0UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK    0x00000003UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrTapdlyBypass
+ */
+#define XIOU_SLCR_TAPDLY_BYPASS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL )
+#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL   0x00000007UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT   2UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK    0x00000004UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL  0x1UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK    0x00000002UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT   0UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK    0x00000001UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrCoherentCtrl
+ */
+#define XIOU_SLCR_COHERENT_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL )
+#define XIOU_SLCR_COHERENT_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT   28UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK    0xf0000000UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT   24UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK    0x0f000000UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_SHIFT   20UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_MASK    0x00f00000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_SHIFT   16UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_MASK    0x000f0000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_SHIFT   12UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_MASK    0x0000f000UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_SHIFT   8UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_MASK    0x00000f00UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_SHIFT   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_MASK    0x000000f0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_SHIFT   0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_MASK    0x0000000fUL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrVideoPssClkSel
+ */
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL )
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK    0x00000002UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL  0x0UL
+
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT   0UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrInterconnectRoute
+ */
+#define XIOU_SLCR_INTERCONNECT_ROUTE    ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL )
+#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT   7UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK    0x00000080UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT   6UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK    0x00000040UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_SHIFT   5UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_MASK    0x00000020UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_SHIFT   4UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_MASK    0x00000010UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_SHIFT   3UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_MASK    0x00000008UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_SHIFT   2UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_MASK    0x00000004UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_SHIFT   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_MASK    0x00000002UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_SHIFT   0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_MASK    0x00000001UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrRamGem0
+ */
+#define XIOU_SLCR_RAM_GEM0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
+#define XIOU_SLCR_RAM_GEM0_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM0_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM0_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM0_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM0_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM0_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM0_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamgem1
+ */
+#define XIOU_SLCR_RAM_GEM1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
+#define XIOU_SLCR_RAM_GEM1_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM1_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM1_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM1_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM1_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM1_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM1_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamGem2
+ */
+#define XIOU_SLCR_RAM_GEM2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
+#define XIOU_SLCR_RAM_GEM2_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM2_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM2_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM2_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM2_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM2_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM2_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamGem3
+ */
+#define XIOU_SLCR_RAM_GEM3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
+#define XIOU_SLCR_RAM_GEM3_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM3_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM3_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM3_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM3_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_GEM3_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_GEM3_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXsdps0
+ */
+#define XIOU_SLCR_RAM_XSDPS0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
+#define XIOU_SLCR_RAM_XSDPS0_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXsdps1
+ */
+#define XIOU_SLCR_RAM_XSDPS1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
+#define XIOU_SLCR_RAM_XSDPS1_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamCan0
+ */
+#define XIOU_SLCR_RAM_CAN0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL )
+#define XIOU_SLCR_RAM_CAN0_RSTVAL   0x005b5b5bUL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT   22UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK    0x00400000UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT   19UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK    0x00380000UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT   16UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK    0x00070000UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamCan1
+ */
+#define XIOU_SLCR_RAM_CAN1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL )
+#define XIOU_SLCR_RAM_CAN1_RSTVAL   0x005b5b5bUL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT   22UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK    0x00400000UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT   19UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK    0x00380000UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT   16UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK    0x00070000UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamLqspi
+ */
+#define XIOU_SLCR_RAM_LQSPI    ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL )
+#define XIOU_SLCR_RAM_LQSPI_RSTVAL   0x00002ddbUL
+
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT   13UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK    0x00002000UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT   10UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK    0x00001c00UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT   7UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK    0x00000380UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXnandps8
+ */
+#define XIOU_SLCR_RAM_XNANDPS8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL )
+#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrCtrl
+ */
+#define XIOU_SLCR_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL )
+#define XIOU_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrIsr
+ */
+#define XIOU_SLCR_ISR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL )
+#define XIOU_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrImr
+ */
+#define XIOU_SLCR_IMR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL )
+#define XIOU_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrIer
+ */
+#define XIOU_SLCR_IER    ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL )
+#define XIOU_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrIdr
+ */
+#define XIOU_SLCR_IDR    ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL )
+#define XIOU_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrItr
+ */
+#define XIOU_SLCR_ITR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL )
+#define XIOU_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h
new file mode 100644
index 000000000..cc05672e4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h
@@ -0,0 +1,5667 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_H__
+#define __XLPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcr Base Address
+ */
+#define XLPD_SLCR_BASEADDR      0xFF410000UL
+
+/**
+ * Register: XlpdSlcrWprot0
+ */
+#define XLPD_SLCR_WPROT0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XLPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XLPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XLPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XLPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrCtrl
+ */
+#define XLPD_SLCR_CTRL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsr
+ */
+#define XLPD_SLCR_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrImr
+ */
+#define XLPD_SLCR_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIer
+ */
+#define XLPD_SLCR_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIdr
+ */
+#define XLPD_SLCR_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrItr
+ */
+#define XLPD_SLCR_ITR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk0
+ */
+#define XLPD_SLCR_SAFETY_CHK0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL )
+#define XLPD_SLCR_SAFETY_CHK0_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk1
+ */
+#define XLPD_SLCR_SAFETY_CHK1    ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL )
+#define XLPD_SLCR_SAFETY_CHK1_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk2
+ */
+#define XLPD_SLCR_SAFETY_CHK2    ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL )
+#define XLPD_SLCR_SAFETY_CHK2_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk3
+ */
+#define XLPD_SLCR_SAFETY_CHK3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XLPD_SLCR_SAFETY_CHK3_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrXcsupmuWdtClkSel
+ */
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL )
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT   0UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH   1UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK    0x00000001UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAdmaCfg
+ */
+#define XLPD_SLCR_ADMA_CFG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL )
+#define XLPD_SLCR_ADMA_CFG_RSTVAL   0x00000028UL
+
+#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT   5UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH   2UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK    0x00000060UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT   0UL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH   5UL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XlpdSlcrAdmaRam
+ */
+#define XLPD_SLCR_ADMA_RAM    ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL )
+#define XLPD_SLCR_ADMA_RAM_RSTVAL   0x00003b3bUL
+
+#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT   12UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK    0x00007000UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT   11UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH   1UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK    0x00000800UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT   8UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK    0x00000700UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT   4UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK    0x00000070UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH   1UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK    0x00000008UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT   0UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK    0x00000007UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIsr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiImr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL )
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL   0x1dcf000fUL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIer
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIdr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL )
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIsr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL )
+#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbImr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL )
+#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIer
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL )
+#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIdr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL )
+#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiReq
+ */
+#define XLPD_SLCR_ISO_AIBAXI_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL )
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiType
+ */
+#define XLPD_SLCR_ISO_AIBAXI_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL )
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL   0x19cf000fUL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiAck
+ */
+#define XLPD_SLCR_ISO_AIBAXI_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL )
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbReq
+ */
+#define XLPD_SLCR_ISO_AIBAPB_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL )
+#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbType
+ */
+#define XLPD_SLCR_ISO_AIBAPB_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL )
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbAck
+ */
+#define XLPD_SLCR_ISO_AIBAPB_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL )
+#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbIsr
+ */
+#define XLPD_SLCR_ERR_ATB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbImr
+ */
+#define XLPD_SLCR_ERR_ATB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAtbIer
+ */
+#define XLPD_SLCR_ERR_ATB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XLPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbIdr
+ */
+#define XLPD_SLCR_ERR_ATB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAtbCmdStoreEn
+ */
+#define XLPD_SLCR_ATB_CMD_STORE_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrAtbRespEn
+ */
+#define XLPD_SLCR_ATB_RESP_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XLPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAtbRespType
+ */
+#define XLPD_SLCR_ATB_RESP_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrAtbPrescale
+ */
+#define XLPD_SLCR_ATB_PRESCALE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XLPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+/**
+ * Register: XlpdSlcrMutex0
+ */
+#define XLPD_SLCR_MUTEX0    ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL )
+#define XLPD_SLCR_MUTEX0_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX0_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX0_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX0_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX0_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex1
+ */
+#define XLPD_SLCR_MUTEX1    ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL )
+#define XLPD_SLCR_MUTEX1_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX1_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX1_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX1_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX1_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex2
+ */
+#define XLPD_SLCR_MUTEX2    ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL )
+#define XLPD_SLCR_MUTEX2_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX2_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX2_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX2_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX2_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex3
+ */
+#define XLPD_SLCR_MUTEX3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL )
+#define XLPD_SLCR_MUTEX3_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX3_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX3_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX3_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX3_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqSts
+ */
+#define XLPD_SLCR_GICP0_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL )
+#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqMsk
+ */
+#define XLPD_SLCR_GICP0_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL )
+#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqEn
+ */
+#define XLPD_SLCR_GICP0_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL )
+#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqDis
+ */
+#define XLPD_SLCR_GICP0_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL )
+#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqTrig
+ */
+#define XLPD_SLCR_GICP0_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL )
+#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqSts
+ */
+#define XLPD_SLCR_GICP1_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL )
+#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqMsk
+ */
+#define XLPD_SLCR_GICP1_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL )
+#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqEn
+ */
+#define XLPD_SLCR_GICP1_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL )
+#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqDis
+ */
+#define XLPD_SLCR_GICP1_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL )
+#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqTrig
+ */
+#define XLPD_SLCR_GICP1_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL )
+#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqSts
+ */
+#define XLPD_SLCR_GICP2_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL )
+#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqMsk
+ */
+#define XLPD_SLCR_GICP2_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL )
+#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqEn
+ */
+#define XLPD_SLCR_GICP2_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL )
+#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqDis
+ */
+#define XLPD_SLCR_GICP2_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL )
+#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqTrig
+ */
+#define XLPD_SLCR_GICP2_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL )
+#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqSts
+ */
+#define XLPD_SLCR_GICP3_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL )
+#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqMsk
+ */
+#define XLPD_SLCR_GICP3_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL )
+#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqEn
+ */
+#define XLPD_SLCR_GICP3_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL )
+#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqDis
+ */
+#define XLPD_SLCR_GICP3_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL )
+#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqTrig
+ */
+#define XLPD_SLCR_GICP3_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL )
+#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqSts
+ */
+#define XLPD_SLCR_GICP4_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL )
+#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqMsk
+ */
+#define XLPD_SLCR_GICP4_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL )
+#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqEn
+ */
+#define XLPD_SLCR_GICP4_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL )
+#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqDis
+ */
+#define XLPD_SLCR_GICP4_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL )
+#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqTrig
+ */
+#define XLPD_SLCR_GICP4_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL )
+#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqSts
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqMsk
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL   0x000000ffUL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqEn
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqDis
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL )
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqTrig
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAfiFs
+ */
+#define XLPD_SLCR_AFI_FS    ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL )
+#define XLPD_SLCR_AFI_FS_RSTVAL   0x00000200UL
+
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT   8UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH   2UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK    0x00000300UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XlpdSlcrCci
+ */
+#define XLPD_SLCR_CCI    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL )
+#define XLPD_SLCR_CCI_RSTVAL   0x03801c07UL
+
+#define XLPD_SLCR_CCI_SPR_SHIFT   28UL
+#define XLPD_SLCR_CCI_SPR_WIDTH   4UL
+#define XLPD_SLCR_CCI_SPR_MASK    0xf0000000UL
+#define XLPD_SLCR_CCI_SPR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT   27UL
+#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS4_MASK    0x08000000UL
+#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT   26UL
+#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS3_MASK    0x04000000UL
+#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT   25UL
+#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS2_MASK    0x02000000UL
+#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT   24UL
+#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS1_MASK    0x01000000UL
+#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT   23UL
+#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS0_MASK    0x00800000UL
+#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT   18UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH   5UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_MASK    0x007c0000UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT   17UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_MASK    0x00020000UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT   16UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_MASK    0x00010000UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT   13UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH   3UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_MASK    0x0000e000UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT   12UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK    0x00001000UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT   11UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK    0x00000800UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT   10UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK    0x00000400UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT   6UL
+#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH   4UL
+#define XLPD_SLCR_CCI_ECOREVNUM_MASK    0x000003c0UL
+#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA2_SHIFT   5UL
+#define XLPD_SLCR_CCI_ASA2_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA2_MASK    0x00000020UL
+#define XLPD_SLCR_CCI_ASA2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA1_SHIFT   4UL
+#define XLPD_SLCR_CCI_ASA1_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA1_MASK    0x00000010UL
+#define XLPD_SLCR_CCI_ASA1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA0_SHIFT   3UL
+#define XLPD_SLCR_CCI_ASA0_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA0_MASK    0x00000008UL
+#define XLPD_SLCR_CCI_ASA0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_OWO2_SHIFT   2UL
+#define XLPD_SLCR_CCI_OWO2_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO2_MASK    0x00000004UL
+#define XLPD_SLCR_CCI_OWO2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_OWO1_SHIFT   1UL
+#define XLPD_SLCR_CCI_OWO1_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO1_MASK    0x00000002UL
+#define XLPD_SLCR_CCI_OWO1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_OWO0_SHIFT   0UL
+#define XLPD_SLCR_CCI_OWO0_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO0_MASK    0x00000001UL
+#define XLPD_SLCR_CCI_OWO0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrCciAddrmap
+ */
+#define XLPD_SLCR_CCI_ADDRMAP    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL )
+#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL   0x00c000ffUL
+
+#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT   30UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_MASK    0xc0000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT   28UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_MASK    0x30000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT   26UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_MASK    0x0c000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT   24UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_MASK    0x03000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT   22UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_MASK    0x00c00000UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT   20UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_MASK    0x00300000UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT   18UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_MASK    0x000c0000UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT   16UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_MASK    0x00030000UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT   14UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_MASK    0x0000c000UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT   12UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_MASK    0x00003000UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT   10UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_MASK    0x00000c00UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT   8UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_MASK    0x00000300UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT   6UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_MASK    0x000000c0UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT   4UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_MASK    0x00000030UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_1_MASK    0x0000000cUL
+#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT   0UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_MASK    0x00000003UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrCciQvnprealloc
+ */
+#define XLPD_SLCR_CCI_QVNPREALLOC    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL )
+#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL   0x00330330UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT   20UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK    0x00f00000UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT   16UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK    0x000f0000UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT   8UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK    0x00000f00UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK    0x000000f0UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrSmmu
+ */
+#define XLPD_SLCR_SMMU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL )
+#define XLPD_SLCR_SMMU_RSTVAL   0x0000003fUL
+
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT   7UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH   1UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK    0x00000080UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SMMU_CTTW_SHIFT   6UL
+#define XLPD_SLCR_SMMU_CTTW_WIDTH   1UL
+#define XLPD_SLCR_SMMU_CTTW_MASK    0x00000040UL
+#define XLPD_SLCR_SMMU_CTTW_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT   5UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK    0x00000020UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT   4UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK    0x00000010UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT   3UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK    0x00000008UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT   2UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK    0x00000004UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK    0x00000002UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT   0UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK    0x00000001UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrApu
+ */
+#define XLPD_SLCR_APU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL )
+#define XLPD_SLCR_APU_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT   3UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_MASK    0x00000008UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT   2UL
+#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_CMNT_MASK    0x00000004UL
+#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_INNER_SHIFT   1UL
+#define XLPD_SLCR_APU_BRDC_INNER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_INNER_MASK    0x00000002UL
+#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT   0UL
+#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_OUTER_MASK    0x00000001UL
+#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h
new file mode 100644
index 000000000..aff3bf2fa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h
@@ -0,0 +1,141 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_SECURE_H__
+#define __XLPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcrSecure Base Address
+ */
+#define XLPD_SLCR_SECURE_BASEADDR      0xFF4B0000UL
+
+/**
+ * Register: XlpdSlcrSecCtrl
+ */
+#define XLPD_SLCR_SEC_CTRL    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIsr
+ */
+#define XLPD_SLCR_SEC_ISR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecImr
+ */
+#define XLPD_SLCR_SEC_IMR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrSecIer
+ */
+#define XLPD_SLCR_SEC_IER    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIdr
+ */
+#define XLPD_SLCR_SEC_IDR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecItr
+ */
+#define XLPD_SLCR_SEC_ITR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecRpu
+ */
+#define XLPD_SLCR_SEC_RPU    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XLPD_SLCR_SEC_RPU_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecAdma
+ */
+#define XLPD_SLCR_SEC_ADMA    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
+#define XLPD_SLCR_SEC_ADMA_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT   0UL
+#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH   8UL
+#define XLPD_SLCR_SEC_ADMA_TZ_MASK    0x000000ffUL
+#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecSafetyChk
+ */
+#define XLPD_SLCR_SEC_SAFETY_CHK    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT   0UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH   32UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecUsb
+ */
+#define XLPD_SLCR_SEC_USB    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
+#define XLPD_SLCR_SEC_USB_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h
new file mode 100644
index 000000000..a5145eac7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h
@@ -0,0 +1,858 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_H__
+#define __XLPD_XPPU_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppu Base Address
+ */
+#define XLPD_XPPU_BASEADDR      0xFF980000UL
+
+/**
+ * Register: XlpdXppuCtrl
+ */
+#define XLPD_XPPU_CTRL    ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
+#define XLPD_XPPU_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT   2UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK    0x00000004UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK    0x00000002UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_EN_SHIFT   0UL
+#define XLPD_XPPU_CTRL_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_EN_MASK    0x00000001UL
+#define XLPD_XPPU_CTRL_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts1
+ */
+#define XLPD_XPPU_ERR_STS1    ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
+#define XLPD_XPPU_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts2
+ */
+#define XLPD_XPPU_ERR_STS2    ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
+#define XLPD_XPPU_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuPoison
+ */
+#define XLPD_XPPU_POISON    ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
+#define XLPD_XPPU_POISON_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_POISON_BASE_SHIFT   0UL
+#define XLPD_XPPU_POISON_BASE_WIDTH   20UL
+#define XLPD_XPPU_POISON_BASE_MASK    0x000fffffUL
+#define XLPD_XPPU_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIsr
+ */
+#define XLPD_XPPU_ISR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
+#define XLPD_XPPU_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ISR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_ISR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_ISR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_ISR_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_ISR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_ISR_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_ISR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_ISR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_ISR_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_ISR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_ISR_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_ISR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_ISR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuImr
+ */
+#define XLPD_XPPU_IMR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
+#define XLPD_XPPU_IMR_RSTVAL   0x000000efUL
+
+#define XLPD_XPPU_IMR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IMR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IMR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IMR_APER_TZ_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IMR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IMR_APER_PERM_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IMR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IMR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IMR_MID_RO_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IMR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IMR_MID_MISS_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IMR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IMR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuIen
+ */
+#define XLPD_XPPU_IEN    ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
+#define XLPD_XPPU_IEN_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IEN_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IEN_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IEN_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IEN_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IEN_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IEN_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IEN_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IEN_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IEN_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IEN_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IEN_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IEN_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IEN_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIds
+ */
+#define XLPD_XPPU_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
+#define XLPD_XPPU_IDS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IDS_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IDS_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IDS_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IDS_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IDS_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IDS_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IDS_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IDS_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IDS_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IDS_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IDS_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IDS_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IDS_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMMstrIds
+ */
+#define XLPD_XPPU_M_MSTR_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
+#define XLPD_XPPU_M_MSTR_IDS_RSTVAL   0x00000014UL
+
+#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT   0UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH   32UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL  0x14UL
+
+/**
+ * Register: XlpdXppuMAperture32b
+ */
+#define XLPD_XPPU_M_APERTURE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
+#define XLPD_XPPU_M_APERTURE_32B_RSTVAL   0x00000080UL
+
+#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMAperture64kb
+ */
+#define XLPD_XPPU_M_APERTURE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
+#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL   0x00000100UL
+
+#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL  0x100UL
+
+/**
+ * Register: XlpdXppuMAperture1mb
+ */
+#define XLPD_XPPU_M_APERTURE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
+#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL   0x00000010UL
+
+#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMAperture512mb
+ */
+#define XLPD_XPPU_M_APERTURE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
+#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuBase32b
+ */
+#define XLPD_XPPU_BASE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
+#define XLPD_XPPU_BASE_32B_RSTVAL   0xff990000UL
+
+#define XLPD_XPPU_BASE_32B_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_32B_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_32B_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL  0xff990000UL
+
+/**
+ * Register: XlpdXppuBase64kb
+ */
+#define XLPD_XPPU_BASE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
+#define XLPD_XPPU_BASE_64KB_RSTVAL   0xff000000UL
+
+#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_64KB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL  0xff000000UL
+
+/**
+ * Register: XlpdXppuBase1mb
+ */
+#define XLPD_XPPU_BASE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
+#define XLPD_XPPU_BASE_1MB_RSTVAL   0xfe000000UL
+
+#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_1MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL  0xfe000000UL
+
+/**
+ * Register: XlpdXppuBase512mb
+ */
+#define XLPD_XPPU_BASE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
+#define XLPD_XPPU_BASE_512MB_RSTVAL   0xc0000000UL
+
+#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_512MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL  0xc0000000UL
+
+/**
+ * Register: XlpdXppuMstrId00
+ */
+#define XLPD_XPPU_MSTR_ID00    ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
+#define XLPD_XPPU_MSTR_ID00_RSTVAL   0x83ff0040UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL  0x3ffUL
+
+#define XLPD_XPPU_MSTR_ID00_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID00_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL  0x40UL
+
+/**
+ * Register: XlpdXppuMstrId01
+ */
+#define XLPD_XPPU_MSTR_ID01    ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
+#define XLPD_XPPU_MSTR_ID01_RSTVAL   0x03f00000UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID01_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID01_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId02
+ */
+#define XLPD_XPPU_MSTR_ID02    ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
+#define XLPD_XPPU_MSTR_ID02_RSTVAL   0x83f00010UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID02_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID02_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMstrId03
+ */
+#define XLPD_XPPU_MSTR_ID03    ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
+#define XLPD_XPPU_MSTR_ID03_RSTVAL   0x83c00080UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL  0x3c0UL
+
+#define XLPD_XPPU_MSTR_ID03_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID03_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId04
+ */
+#define XLPD_XPPU_MSTR_ID04    ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
+#define XLPD_XPPU_MSTR_ID04_RSTVAL   0x83c30080UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID04_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID04_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId05
+ */
+#define XLPD_XPPU_MSTR_ID05    ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
+#define XLPD_XPPU_MSTR_ID05_RSTVAL   0x03c30081UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID05_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID05_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL  0x81UL
+
+/**
+ * Register: XlpdXppuMstrId06
+ */
+#define XLPD_XPPU_MSTR_ID06    ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
+#define XLPD_XPPU_MSTR_ID06_RSTVAL   0x03c30082UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID06_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID06_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL  0x82UL
+
+/**
+ * Register: XlpdXppuMstrId07
+ */
+#define XLPD_XPPU_MSTR_ID07    ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
+#define XLPD_XPPU_MSTR_ID07_RSTVAL   0x83c30083UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID07_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID07_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL  0x83UL
+
+/**
+ * Register: XlpdXppuMstrId08
+ */
+#define XLPD_XPPU_MSTR_ID08    ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
+#define XLPD_XPPU_MSTR_ID08_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID08_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId09
+ */
+#define XLPD_XPPU_MSTR_ID09    ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
+#define XLPD_XPPU_MSTR_ID09_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID09_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId10
+ */
+#define XLPD_XPPU_MSTR_ID10    ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
+#define XLPD_XPPU_MSTR_ID10_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID10_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId11
+ */
+#define XLPD_XPPU_MSTR_ID11    ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
+#define XLPD_XPPU_MSTR_ID11_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID11_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId12
+ */
+#define XLPD_XPPU_MSTR_ID12    ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
+#define XLPD_XPPU_MSTR_ID12_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID12_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId13
+ */
+#define XLPD_XPPU_MSTR_ID13    ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
+#define XLPD_XPPU_MSTR_ID13_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID13_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId14
+ */
+#define XLPD_XPPU_MSTR_ID14    ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
+#define XLPD_XPPU_MSTR_ID14_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID14_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId15
+ */
+#define XLPD_XPPU_MSTR_ID15    ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
+#define XLPD_XPPU_MSTR_ID15_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID15_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId16
+ */
+#define XLPD_XPPU_MSTR_ID16    ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
+#define XLPD_XPPU_MSTR_ID16_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID16_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId17
+ */
+#define XLPD_XPPU_MSTR_ID17    ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
+#define XLPD_XPPU_MSTR_ID17_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID17_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId18
+ */
+#define XLPD_XPPU_MSTR_ID18    ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
+#define XLPD_XPPU_MSTR_ID18_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID18_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId19
+ */
+#define XLPD_XPPU_MSTR_ID19    ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
+#define XLPD_XPPU_MSTR_ID19_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID19_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h
new file mode 100644
index 000000000..95f7e20a2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h
@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_SINK_H__
+#define __XLPD_XPPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppuSink Base Address
+ */
+#define XLPD_XPPU_SINK_BASEADDR      0xFF9C0000UL
+
+/**
+ * Register: XlpdXppuSinkErrSts
+ */
+#define XLPD_XPPU_SINK_ERR_STS    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XLPD_XPPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIsr
+ */
+#define XLPD_XPPU_SINK_ISR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XLPD_XPPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkImr
+ */
+#define XLPD_XPPU_SINK_IMR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XLPD_XPPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuSinkIer
+ */
+#define XLPD_XPPU_SINK_IER    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XLPD_XPPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIdr
+ */
+#define XLPD_XPPU_SINK_IDR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XLPD_XPPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h
new file mode 100644
index 000000000..5e3631f3e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XOCM_XMPU_CFG_H__
+#define __XOCM_XMPU_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XocmXmpuCfg Base Address
+ */
+#define XOCM_XMPU_CFG_BASEADDR      0xFFA70000UL
+
+/**
+ * Register: XocmXmpuCfgCtrl
+ */
+#define XOCM_XMPU_CFG_CTRL    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL )
+#define XOCM_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XocmXmpuCfgErrSts1
+ */
+#define XOCM_XMPU_CFG_ERR_STS1    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL )
+#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgErrSts2
+ */
+#define XOCM_XMPU_CFG_ERR_STS2    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL )
+#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgPoison
+ */
+#define XOCM_XMPU_CFG_POISON    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
+#define XOCM_XMPU_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_POISON_BASE_SHIFT   0UL
+#define XOCM_XMPU_CFG_POISON_BASE_WIDTH   20UL
+#define XOCM_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgIsr
+ */
+#define XOCM_XMPU_CFG_ISR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL )
+#define XOCM_XMPU_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgImr
+ */
+#define XOCM_XMPU_CFG_IMR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL )
+#define XOCM_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XocmXmpuCfgIen
+ */
+#define XOCM_XMPU_CFG_IEN    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL )
+#define XOCM_XMPU_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgIds
+ */
+#define XOCM_XMPU_CFG_IDS    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
+#define XOCM_XMPU_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgLock
+ */
+#define XOCM_XMPU_CFG_LOCK    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL )
+#define XOCM_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00Strt
+ */
+#define XOCM_XMPU_CFG_R00_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL )
+#define XOCM_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00End
+ */
+#define XOCM_XMPU_CFG_R00_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL )
+#define XOCM_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00Mstr
+ */
+#define XOCM_XMPU_CFG_R00_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL )
+#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00
+ */
+#define XOCM_XMPU_CFG_R00    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
+#define XOCM_XMPU_CFG_R00_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01Strt
+ */
+#define XOCM_XMPU_CFG_R01_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL )
+#define XOCM_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01End
+ */
+#define XOCM_XMPU_CFG_R01_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL )
+#define XOCM_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01Mstr
+ */
+#define XOCM_XMPU_CFG_R01_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL )
+#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01
+ */
+#define XOCM_XMPU_CFG_R01    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
+#define XOCM_XMPU_CFG_R01_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02Strt
+ */
+#define XOCM_XMPU_CFG_R02_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL )
+#define XOCM_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02End
+ */
+#define XOCM_XMPU_CFG_R02_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL )
+#define XOCM_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02Mstr
+ */
+#define XOCM_XMPU_CFG_R02_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL )
+#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02
+ */
+#define XOCM_XMPU_CFG_R02    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
+#define XOCM_XMPU_CFG_R02_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03Strt
+ */
+#define XOCM_XMPU_CFG_R03_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL )
+#define XOCM_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03End
+ */
+#define XOCM_XMPU_CFG_R03_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL )
+#define XOCM_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03Mstr
+ */
+#define XOCM_XMPU_CFG_R03_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL )
+#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03
+ */
+#define XOCM_XMPU_CFG_R03    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
+#define XOCM_XMPU_CFG_R03_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04Strt
+ */
+#define XOCM_XMPU_CFG_R04_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL )
+#define XOCM_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04End
+ */
+#define XOCM_XMPU_CFG_R04_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL )
+#define XOCM_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04Mstr
+ */
+#define XOCM_XMPU_CFG_R04_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL )
+#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04
+ */
+#define XOCM_XMPU_CFG_R04    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
+#define XOCM_XMPU_CFG_R04_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05Strt
+ */
+#define XOCM_XMPU_CFG_R05_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL )
+#define XOCM_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05End
+ */
+#define XOCM_XMPU_CFG_R05_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL )
+#define XOCM_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05Mstr
+ */
+#define XOCM_XMPU_CFG_R05_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL )
+#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05
+ */
+#define XOCM_XMPU_CFG_R05    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
+#define XOCM_XMPU_CFG_R05_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06Strt
+ */
+#define XOCM_XMPU_CFG_R06_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL )
+#define XOCM_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06End
+ */
+#define XOCM_XMPU_CFG_R06_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL )
+#define XOCM_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06Mstr
+ */
+#define XOCM_XMPU_CFG_R06_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL )
+#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06
+ */
+#define XOCM_XMPU_CFG_R06    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
+#define XOCM_XMPU_CFG_R06_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07Strt
+ */
+#define XOCM_XMPU_CFG_R07_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL )
+#define XOCM_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07End
+ */
+#define XOCM_XMPU_CFG_R07_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL )
+#define XOCM_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07Mstr
+ */
+#define XOCM_XMPU_CFG_R07_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL )
+#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07
+ */
+#define XOCM_XMPU_CFG_R07    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
+#define XOCM_XMPU_CFG_R07_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08Strt
+ */
+#define XOCM_XMPU_CFG_R08_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL )
+#define XOCM_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08End
+ */
+#define XOCM_XMPU_CFG_R08_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL )
+#define XOCM_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08Mstr
+ */
+#define XOCM_XMPU_CFG_R08_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL )
+#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08
+ */
+#define XOCM_XMPU_CFG_R08    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
+#define XOCM_XMPU_CFG_R08_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09Strt
+ */
+#define XOCM_XMPU_CFG_R09_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL )
+#define XOCM_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09End
+ */
+#define XOCM_XMPU_CFG_R09_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL )
+#define XOCM_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09Mstr
+ */
+#define XOCM_XMPU_CFG_R09_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL )
+#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09
+ */
+#define XOCM_XMPU_CFG_R09    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
+#define XOCM_XMPU_CFG_R09_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10Strt
+ */
+#define XOCM_XMPU_CFG_R10_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
+#define XOCM_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10End
+ */
+#define XOCM_XMPU_CFG_R10_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
+#define XOCM_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10Mstr
+ */
+#define XOCM_XMPU_CFG_R10_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
+#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10
+ */
+#define XOCM_XMPU_CFG_R10    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
+#define XOCM_XMPU_CFG_R10_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11Strt
+ */
+#define XOCM_XMPU_CFG_R11_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
+#define XOCM_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11End
+ */
+#define XOCM_XMPU_CFG_R11_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
+#define XOCM_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11Mstr
+ */
+#define XOCM_XMPU_CFG_R11_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
+#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11
+ */
+#define XOCM_XMPU_CFG_R11    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
+#define XOCM_XMPU_CFG_R11_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12Strt
+ */
+#define XOCM_XMPU_CFG_R12_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
+#define XOCM_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12End
+ */
+#define XOCM_XMPU_CFG_R12_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
+#define XOCM_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12Mstr
+ */
+#define XOCM_XMPU_CFG_R12_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
+#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12
+ */
+#define XOCM_XMPU_CFG_R12    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
+#define XOCM_XMPU_CFG_R12_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13Strt
+ */
+#define XOCM_XMPU_CFG_R13_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
+#define XOCM_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13End
+ */
+#define XOCM_XMPU_CFG_R13_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
+#define XOCM_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13Mstr
+ */
+#define XOCM_XMPU_CFG_R13_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
+#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13
+ */
+#define XOCM_XMPU_CFG_R13    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
+#define XOCM_XMPU_CFG_R13_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14Strt
+ */
+#define XOCM_XMPU_CFG_R14_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
+#define XOCM_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14End
+ */
+#define XOCM_XMPU_CFG_R14_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
+#define XOCM_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14Mstr
+ */
+#define XOCM_XMPU_CFG_R14_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
+#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14
+ */
+#define XOCM_XMPU_CFG_R14    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
+#define XOCM_XMPU_CFG_R14_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15Strt
+ */
+#define XOCM_XMPU_CFG_R15_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
+#define XOCM_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15End
+ */
+#define XOCM_XMPU_CFG_R15_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
+#define XOCM_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15Mstr
+ */
+#define XOCM_XMPU_CFG_R15_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
+#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15
+ */
+#define XOCM_XMPU_CFG_R15    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
+#define XOCM_XMPU_CFG_R15_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XOCM_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c
new file mode 100644
index 000000000..f14251511
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include <unistd.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c
new file mode 100644
index 000000000..fc2f89d6c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include <signal.h>
+#include <unistd.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) int _kill(pid_t pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) int kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
+
+__attribute__((weak)) int _kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c
new file mode 100644
index 000000000..106c45c89
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <sys/types.h>
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c
new file mode 100644
index 000000000..55cdd4992
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c
@@ -0,0 +1,285 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file mpu.c
+*
+* This file contains initial configuration of the MPU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 5.04	pkp  12/18/15 Updated MPU initialization as per the proper address map
+* 6.00  pkp  06/27/16 moving the Init_MPU code to .boot section since it is a
+*                     part of processor boot process
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xreg_cortexr5.h"
+#include "xil_mpu.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+static const struct {
+	u64 size;
+	unsigned int encoding;
+}region_size[] = {
+	{ 0x20, REGION_32B },
+	{ 0x40, REGION_64B },
+	{ 0x80, REGION_128B },
+	{ 0x100, REGION_256B },
+	{ 0x200, REGION_512B },
+	{ 0x400, REGION_1K },
+	{ 0x800, REGION_2K },
+	{ 0x1000, REGION_4K },
+	{ 0x2000, REGION_8K },
+	{ 0x4000, REGION_16K },
+	{ 0x8000, REGION_32K },
+	{ 0x10000, REGION_64K },
+	{ 0x20000, REGION_128K },
+	{ 0x40000, REGION_256K },
+	{ 0x80000, REGION_512K },
+	{ 0x100000, REGION_1M },
+	{ 0x200000, REGION_2M },
+	{ 0x400000, REGION_4M },
+	{ 0x800000, REGION_8M },
+	{ 0x1000000, REGION_16M },
+	{ 0x2000000, REGION_32M },
+	{ 0x4000000, REGION_64M },
+	{ 0x8000000, REGION_128M },
+	{ 0x10000000, REGION_256M },
+	{ 0x20000000, REGION_512M },
+	{ 0x40000000, REGION_1G },
+	{ 0x80000000, REGION_2G },
+	{ 0x100000000, REGION_4G },
+};
+
+/************************** Function Prototypes ******************************/
+void Init_MPU(void) __attribute__((__section__(".boot")));
+static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
+static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
+
+/*****************************************************************************
+*
+* Initialize MPU for a given address map and Enabled the background Region in
+* MPU with default memory attributes for rest of address range for Cortex R5
+* processor.
+*
+* @param	None.
+*
+* @return	None.
+*
+*
+******************************************************************************/
+
+void Init_MPU(void)
+{
+	u32 Addr;
+	u32 RegSize;
+	u32 Attrib;
+	u32 RegNum = 0, i;
+	u64 size;
+
+	Xil_DisableMPURegions();
+
+	Addr = 0x00000000U;
+#ifdef	XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
+	/* If the DDR is present, configure region as per DDR size */
+	size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
+	if (size < 0x80000000) {
+		/* Lookup the size.  */
+		for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
+			if (size <= region_size[i].size) {
+				RegSize = region_size[i].encoding;
+				break;
+			}
+		}
+	} else {
+		/* if the DDR size is > 2GB, truncate it to 2GB */
+		RegSize = REGION_2G;
+	}
+#else
+	/* For DDRless system, configure region for TCM */
+	RegSize = REGION_256K;
+#endif
+	Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/*
+	 * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
+	 * 512 MB - LPD-PL interface
+	 * 256 MB - FPD-PL (HPM0) interface
+	 * 256 MB - FPD-PL (HPM1) interface
+	 */
+	Addr = 0x80000000;
+	RegSize = REGION_1G;
+	Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
+	Addr = 0xC0000000U;
+	RegSize = REGION_512M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
+	Addr = 0xE0000000U;
+	RegSize = REGION_256M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
+	Addr = 0xF8000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
+	Addr = 0xF9000000U;
+	RegSize = REGION_1M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
+	Addr = 0xFD000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
+	Addr = 0xFE000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/*
+	 * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
+	 * CSU, PMU, TCM, OCM
+	 */
+	Addr = 0xFF000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
+	Addr = 0xFFFC0000U;
+	RegSize = REGION_256K;
+	Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW  ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+
+	/* A total of 10 MPU regions are allocated with another 6 being free for users */
+
+}
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section of memory with starting address addr
+* of the region size defined by reg_size having attributes attrib of region number
+* reg_num
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	attrib specifies the attributes for that memory region.
+* @param	reg_size specifies the size for that memory region.
+* @param	reg_num specifies the number for that memory region.
+* @return	None.
+*
+*
+******************************************************************************/
+static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
+{
+	u32 Local_reg_size = reg_size;
+
+	Local_reg_size = Local_reg_size<<1U;
+	Local_reg_size |= REGION_EN;
+	dsb();
+	mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+	isb();
+	mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); 		/* Set base address of a region */
+	mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); 	/* Set the control attribute */
+	mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size);	/* set the region size and enable it*/
+	dsb();
+	isb();						/* synchronize context on this processor */
+}
+
+
+/*****************************************************************************
+*
+* Disable all the MPU regions if any of them is enabled
+*
+* @param	None.
+*
+* @return	None.
+*
+*
+******************************************************************************/
+static void Xil_DisableMPURegions(void)
+{
+	u32 Temp;
+	u32 Index;
+	for (Index = 0; Index <= 15; Index++) {
+		mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
+		Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
+		Temp &= (~REGION_EN);
+		dsb();
+		mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
+		dsb();
+		isb();
+	}
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c
new file mode 100644
index 000000000..4b51839fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+  (void *)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c
new file mode 100644
index 000000000..3c6430886
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c); 
+
+#ifdef __cplusplus
+}
+#endif 
+
+void outbyte(char c) {
+	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c
new file mode 100644
index 000000000..74d70ee4a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c
@@ -0,0 +1,32 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr != (char8)0) {
+    outbyte (*ptr);
+	ptr++;
+  }
+#else
+(void)ptr;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c
new file mode 100644
index 000000000..aaf9edee7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+  char8  buf[9];
+  s32  cnt;
+  s32 i;
+  char8  *ptr;
+  u32  digit;
+  for(i = 0; i<9; i++) {
+	buf[i] = '0';
+  }
+
+  ptr = buf;
+  for (cnt = 7 ; cnt >= 0 ; cnt--) {
+    digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+    if ((digit <= 9U) && (ptr != NULL)) {
+		digit += (u32)'0';
+		*ptr = ((char8) digit);
+		ptr += 1;
+	} else if (ptr != NULL) {
+		digit += ((u32)'a' - (u32)10);
+		*ptr = ((char8)digit);
+		ptr += 1;
+	} else {
+		/*Made for MisraC Compliance*/;
+	}
+  }
+
+  if(ptr != NULL) {
+	  *ptr = (char8) 0;
+  }
+  print (buf);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c
new file mode 100644
index 000000000..7f7b7d261
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c
new file mode 100644
index 000000000..64d5156af
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <errno.h>
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+  char8 *base;
+  static char8 *heap_ptr = HeapBase;
+
+  base = heap_ptr;
+  if(heap_ptr != NULL) {
+	heap_ptr += nbytes;
+  }
+
+/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
+  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
+    return base;
+  }	else {
+    errno = ENOMEM;
+    return ((char8 *)-1);
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c
new file mode 100644
index 000000000..74c7ec215
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c
@@ -0,0 +1,126 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex R5 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 5.04  pkp		 02/19/16 sleep routine is modified to use TTC3 if present
+*						  else it will use set of assembly instructions to
+*						  provide the required delay
+* 5.04	pkp		 03/09/16 Assembly routine for sleep is modified to avoid
+*						  disabling the interrupt
+* 5.04	pkp		 03/11/16 Compare the counter value to previously read value
+*						  to detect the overflow for TTC3
+* 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
+* </pre>
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds.
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		The sleep API is implemented using TTC3 counter 0 timer if present.
+*			When TTC3 is absent, sleep is implemented using assembly
+*			instructions which is tested with instruction and data caches
+*			enabled and it gives proper delay. It may give more delay than
+*			exepcted when caches are disabled. If interrupt comes when sleep
+*			using assembly instruction is being executed, the delay may be
+*			greater than what is expected since once the interrupt is served
+*			count resumes from where it was interrupted unlike the case of TTC3
+*			where counter keeps running while interrupt is being served.
+*
+****************************************************************************/
+
+unsigned sleep(unsigned int seconds)
+{
+#ifdef SLEEP_TIMER_BASEADDR
+	u64 tEnd;
+	u64 tCur;
+	u32 TimeHighVal;
+	XTime TimeLowVal1;
+	XTime TimeLowVal2;
+
+	TimeHighVal = 0;
+
+	XTime_GetTime(&TimeLowVal1);
+	tEnd  = (u64)TimeLowVal1 + (((u64) seconds) * COUNTS_PER_SECOND);
+
+	do
+	{
+
+	    XTime_GetTime(&TimeLowVal2);
+	    if (TimeLowVal2 < TimeLowVal1) {
+				TimeHighVal++;
+		}
+
+		TimeLowVal1 = TimeLowVal2;
+	    tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
+
+	} while (tCur < tEnd);
+
+	return 0;
+#else
+	__asm__ __volatile__ (
+			" push {r0,r1}		\n\t"
+			" mov r0, %[sec]	\n\t"
+			" 1: \n\t"
+			" mov r1, %[iter] 	\n\t"
+			" 2:				\n\t"
+			" subs r1, r1, #0x1 \n\t"
+			" bne   2b    		\n\t"
+			" subs r0,r0,#0x1 	\n\t"
+			"  bne 1b 			\n\t"
+			" pop {r0,r1} 		\n\t"
+			:: [iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds)
+	);
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h
new file mode 100644
index 000000000..27add6605
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int usleep(unsigned long useconds);
+unsigned sleep(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c
new file mode 100644
index 000000000..bff3ed24f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file uart.c
+*
+* This file contains APIs for configuring the UART.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/* Register offsets */
+#define UART_CR_OFFSET		0x00000000U
+#define UART_MR_OFFSET		0x00000004U
+#define UART_BAUDGEN_OFFSET	0x00000018U
+#define UART_BAUDDIV_OFFSET	0x00000034U
+
+#define MAX_BAUD_ERROR_RATE	0x00000003U	/* max % error allowed */
+#define UART_BAUDRATE	115200U
+#define CSU_VERSION_REG     0xFFCA0044U
+
+void Init_Uart(void);
+
+void Init_Uart(void)
+{
+#ifdef STDOUT_BASEADDRESS
+	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 InputClk;
+   u32 BaudRate = UART_BAUDRATE;
+
+#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
+	InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
+#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
+	InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
+#else
+	/* STDIO is not set or axi_uart is being used for STDIO */
+	return;
+#endif
+InputClk = 25000000U;
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 0x00000001U));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 0x00000001U));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		} else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100U) / BaudRate;
+	if (MAX_BAUD_ERROR_RATE < PercentError) {
+		return;
+	}
+
+	/* set CD and BDIV */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
+
+    /*
+     * Veloce specific code
+     */
+    if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 0x00000002U);
+	    Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 0x00000004U);
+    }
+
+	/*
+	 * 8 data, 1 stop, 0 parity bits
+	 * sel_clk=uart_clk=APB clock
+	 */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
+
+	/* enable Tx/Rx and reset Tx/Rx data path */
+	Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
+
+	return;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c
new file mode 100644
index 000000000..84e44a47c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+  (void *)path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c
new file mode 100644
index 000000000..ff01dfd73
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c
@@ -0,0 +1,128 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex R5 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 5.04  pkp		 02/19/16 usleep routine is modified to use TTC3 if present
+*						  else it will use set of assembly instructions to
+*						  provide the required delay
+* 5.04	pkp		 03/09/16 Assembly routine for usleep is modified to avoid
+*						  disabling the interrupt
+* 5.04	pkp		 03/11/16 Compare the counter value to previously read value
+*						  to detect the overflow for TTC3
+* 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
+* </pre>
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexr5.h"
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 always
+*
+* @note		The usleep API is implemented using TTC3 counter 0 timer if present
+*			When TTC3 is absent, usleep is implemented using assembly
+*			instructions which is tested with instruction and data caches
+*			enabled and it gives proper delay. It may give more delay than
+*			exepcted when caches are disabled. If interrupt comes when usleep
+*			using assembly instruction is being executed, the delay may be
+*			greater than what is expected since once the interrupt is served
+*			count resumes from where it was interrupted unlike the case of TTC3
+*			where counter keeps running while interrupt is being served.
+*
+****************************************************************************/
+
+int usleep(unsigned long useconds)
+{
+
+#ifdef SLEEP_TIMER_BASEADDR
+	u64 tEnd;
+	u64 tCur;
+	u32 TimeHighVal;
+	XTime TimeLowVal1;
+	XTime TimeLowVal2;
+
+	TimeHighVal = 0;
+
+	XTime_GetTime(&TimeLowVal1);
+	tEnd  = (u64)TimeLowVal1 + (((u64) useconds) * COUNTS_PER_USECOND);
+
+	do
+	{
+		XTime_GetTime(&TimeLowVal2);
+	    if (TimeLowVal2 < TimeLowVal1) {
+				TimeHighVal++;
+		}
+		TimeLowVal1 = TimeLowVal2;
+		tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
+	} while (tCur < tEnd);
+
+	return 0;
+#else
+	__asm__ __volatile__ (
+			" push {r0,r1}		\n\t"
+			" mov r0, %[usec]	\n\t"
+			" 1: \n\t"
+			" mov r1, %[iter] 	\n\t"
+			" 2:				\n\t"
+			" subs r1, r1, #0x1 \n\t"
+			" bne   2b    		\n\t"
+			" subs r0,r0,#0x1 	\n\t"
+			"  bne 1b 			\n\t"
+			" pop {r0,r1} 		\n\t"
+			:: [iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds)
+	);
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c
new file mode 100644
index 000000000..0a3616328
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c
@@ -0,0 +1,231 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 6.0   mus  27/07/16 Consolidated vectors for a53,a9 and r5 processor
+*                     and added UndefinedException for a53 32 bit and r5
+*                     processor
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h
new file mode 100644
index 000000000..bb599b560
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c
new file mode 100644
index 000000000..aaa879e73
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h
new file mode 100644
index 000000000..787212ca7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h
new file mode 100644
index 000000000..650946bd0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG  /* prevent circular inclusions */
+#define XDEBUG  /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x)  x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h
new file mode 100644
index 000000000..3d97bebd4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h
new file mode 100644
index 000000000..f18601874
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S
new file mode 100644
index 000000000..6715a6ce5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S
@@ -0,0 +1,149 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/10/14 First release
+* 5.04  pkp  12/18/15 Initialized global constructor for C++ applications
+* 5.04  pkp  02/19/16 Added timer configuration using XTime_StartTimer API when
+*		      TTC3 is present
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "xparameters.h"
+	.file	"xil-crt0.S"
+	.section ".got2","aw"
+	.align	2
+
+	.text
+.Lsbss_start:
+	.long	__sbss_start
+
+.Lsbss_end:
+	.long	__sbss_end
+
+.Lbss_start:
+	.long	__bss_start__
+
+.Lbss_end:
+	.long	__bss_end__
+
+.Lstack:
+	.long	__stack
+
+.set RPU_0_PWRCTL,	0xFF9A0108
+.set RPU_1_PWRCTL,	0xFF9A0208
+.set MPIDR_AFF0,	0xFF
+.set PWRCTL_MASK,	0x1
+
+	.globl	_startup
+
+_startup:
+	bl      __cpu_init		/* Initialize the CPU first (BSP provides this) */
+	mrc	p15, 0, r0,  c0,  c0, 5	/* Read MPIDR register */
+	ands	r0, r0, #MPIDR_AFF0	/* Get affinity level 0 */
+	bne	core1
+	ldr	r10, =RPU_0_PWRCTL	/* Load PWRCTRL address for core 0 */
+	b	test_boot_status
+
+core1:
+	ldr	r10, =RPU_1_PWRCTL	/* Load PWRCTRL address for core 1 */
+
+test_boot_status:
+	ldr	r11, [r10]		/* Read PWRCTRL register */
+	ands	r11, r11, #PWRCTL_MASK	/* Extract and test core's PWRCTRL */
+
+	/* if warm reset, skip the clearing of BSS and SBSS */
+	bne	.Lenclbss
+
+	mov	r0, #0
+
+	/* clear sbss */
+	ldr 	r1,.Lsbss_start		/* calculate beginning of the SBSS */
+	ldr	r2,.Lsbss_end		/* calculate end of the SBSS */
+
+.Lloop_sbss:
+	cmp	r1,r2
+	bge	.Lenclsbss		/* If no SBSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_sbss
+
+.Lenclsbss:
+	/* clear bss */
+	ldr	r1,.Lbss_start		/* calculate beginning of the BSS */
+	ldr	r2,.Lbss_end		/* calculate end of the BSS */
+
+.Lloop_bss:
+	cmp	r1,r2
+	bge	.Lenclbss		/* If no BSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_bss
+
+.Lenclbss:
+
+	/* set stack pointer */
+	ldr	r13,.Lstack		/* stack address */
+
+	/* configure the timer if TTC3 is present */
+#ifdef SLEEP_TIMER_BASEADDR
+	bl XTime_StartTimer
+#endif
+
+	/* run global constructors */
+	bl __libc_init_array
+
+	/* make sure argc and argv are valid */
+	mov	r0, #0
+	mov	r1, #0
+
+	bl	main			/* Jump to main C code */
+
+	/* Cleanup global constructors */
+	bl __libc_fini_array
+
+	bl	exit
+
+.Lexit:	/* should never get here */
+	b .Lexit
+
+.Lstart:
+	.size	_startup,.Lstart-_startup
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c
new file mode 100644
index 000000000..3087fe80f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c
@@ -0,0 +1,146 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+s32 Xil_AssertWait = 1;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implement assert. Currently, it calls a user-defined callback function
+* if one has been set.  Then, it potentially enters an infinite loop depending
+* on the value of the Xil_AssertWait variable.
+*
+* @param    file is the name of the filename of the source
+* @param    line is the linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+	/* if the callback has been set then invoke it */
+	if (Xil_AssertCallbackRoutine != 0) {
+		(*Xil_AssertCallbackRoutine)(File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (Xil_AssertWait != 0) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param    routine is the callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+	Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param    NullParameter is an arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void *) NullParameter;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h
new file mode 100644
index 000000000..1e3c17b50
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h
@@ -0,0 +1,191 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param    Expression is the expression to evaluate. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
+* so that asserts which fail allow execution to continue.
+*
+* @param    Expression is the expression to evaluate. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	    case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c
new file mode 100644
index 000000000..2ba080dff
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c
@@ -0,0 +1,580 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexr5.h"
+#include "xil_exception.h"
+
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
+
+
+extern s32  _stack_end;
+extern s32  __undef_stack;
+
+/****************************************************************************/
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+*
+* Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
+		/* invalidate the Data cache */
+		Xil_DCacheInvalidate();
+
+		/* enable the Data cache */
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	}
+}
+
+/****************************************************************************
+*
+* Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	/* clean and invalidate the Data cache */
+	Xil_DCacheFlush();
+
+	/* disable the Data cache */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	u32 currmask;
+	u32 stack_start,stack_end,stack_size;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+
+	stack_end = (u32 )&_stack_end;
+	stack_start = (u32 )&__undef_stack;
+	stack_size = stack_start-stack_end;
+
+	/* Flush stack memory to save return address */
+	Xil_DCacheFlushRange(stack_end, stack_size);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+	/*invalidate all D cache*/
+	mtcp(XREG_CP15_INVAL_DC_ALL, 0);
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are lost and are NOT written to system memory before the line is
+* invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+		/* Wait for invalidate to complete */
+	dsb();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+		/* Select L1 Data cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+
+			Xil_DCacheFlushLine(tempadr);
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+
+			Xil_DCacheFlushLine(tempend);
+		}
+
+		while (tempadr < tempend) {
+
+		/* Invalidate Data cache line */
+		asm_inval_dc_line_mva_poc(tempadr);
+
+		tempadr += cacheline;
+		}
+	}
+
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way, WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+
+	/* Determine Cache Size */
+
+	CacheSize = (CsidReg >> 13U) & 0x000001FFU;
+	CacheSize += 0x00000001U;
+	CacheSize *= (u32)128;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x000003ffU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+			/* Flush by Set/Way */
+			asm_clean_inval_dc_line_sw(C7Reg);
+
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for flush to complete */
+	dsb();
+	mtcpsr(currmask);
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+		/* Wait for flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+* Flush the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the written to system memory first before the
+* before the line is invalidated.
+*
+* @param	Start address of range to be flushed.
+* @param	Length of range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0x00000000U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr &= ~(cacheline - 1U);
+
+		while (LocalAddr < end) {
+			/* Flush Data cache line */
+			asm_clean_inval_dc_line_mva_poc(LocalAddr);
+
+			LocalAddr += cacheline;
+		}
+	}
+	dsb();
+	mtcpsr(currmask);
+}
+/****************************************************************************
+*
+* Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+	mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+	/* Wait for store to complete */
+	dsb();
+	isb();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Enable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
+		/* invalidate the instruction cache */
+		mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+		/* enable the instruction cache */
+		CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	}
+}
+
+/****************************************************************************
+*
+* Disable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	dsb();
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+		/* disable the instruction cache */
+
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the entire instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+	/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate an instruction cache line.	If the instruction specified by the
+* parameter adr is cached by the instruction cache, the cacheline containing
+* that instruction is invalidated.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
+
+		/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the instruction cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0x00000000U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+
+			/* Invalidate L1 I-cache line */
+			asm_inval_ic_line_mva_pou(LocalAddr);
+
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h
new file mode 100644
index 000000000..581db3f16
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h
@@ -0,0 +1,89 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* Contains required functions for the ARM cache functionality
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
+
+#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+void Xil_DCacheInvalidateLine(INTPTR adr);
+void Xil_DCacheFlushLine(INTPTR adr);
+void Xil_DCacheStoreLine(INTPTR adr);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_ICacheInvalidateLine(INTPTR adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
new file mode 100644
index 000000000..6e8cfa75f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
new file mode 100644
index 000000000..66f722d92
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
@@ -0,0 +1,331 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
+* Handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SyncAbortHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_UndefinedExceptionHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_PrefetchAbortHandler, NULL},
+	{Xil_DataAbortHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr;       /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr;   /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr;   /* Address of instruction causing Undefined
+							     exception */
+#endif
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void *)Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* The function is a common API used to initialize exception handlers across all
+* processors supported. For ARM CortexA53,R5,A9, the exception handlers are being
+* initialized statically and hence this function does not do anything.
+* However, it is still present to avoid any compilation issues in case an
+* application uses this API and also to take care of backward compatibility
+* issues (in earlier versions of BSPs, this API was being used to initialize
+* exception handlers).
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	return;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the exception source and the
+* associated Handler that is to run when the exception is recognized. The
+* argument provided in this call as the Data is used as the argument
+* for the Handler when it is called.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+		See xil_exception_l.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*		Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[Exception_id].Handler = Handler;
+	XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* Removes the Handler for a specific exception Id. The stub Handler is then
+* registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*		See xil_exception_l.h for further information.
+
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+	Xil_ExceptionRegisterHandler(Exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+#else
+/*****************************************************************************/
+/**
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+	u32 FaultStatus;
+
+        xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+	        mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+	    #else
+	        { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+	        FaultStatus = Reg; }
+	    #endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register  %x\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+	u32 FaultStatus;
+
+    xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+			mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+	    #else
+			{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+			FaultStatus = Reg; }
+		#endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register  %x\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+/*****************************************************************************/
+/**
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr);
+	while(1) {
+		;
+	}
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
new file mode 100644
index 000000000..434ef2a6a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
@@ -0,0 +1,245 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+#else
+#define XIL_EXCEPTION_ID_RESET			0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
+#define XIL_EXCEPTION_ID_SWI_INT		2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_IRQ_INT		5U
+#define XIL_EXCEPTION_ID_FIQ_INT		6U
+#define XIL_EXCEPTION_ID_LAST			6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*		C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask)	\
+		{								\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+		}
+#endif
+/****************************************************************************/
+/**
+* Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*		C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask)	\
+		{									\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+		}
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* Enable nested interrupts by clearing the I and F bits it CPSR
+*
+* @return   None.
+*
+* @note     This macro is supposed to be used from interrupt handlers. In the
+*			interrupt handler the interrupts are disabled by default (I and F
+*			are 1). To allow nesting of interrupts, this macro should be
+*			used. It clears the I and F bits by changing the ARM mode to
+*			system mode. Once these bits are cleared and provided the
+*			preemption of interrupt conditions are met in the GIC, nesting of
+*			interrupts will start happening.
+*			Caution: This macro must be used with caution. Before calling this
+*			macro, the user must ensure that the source of the current IRQ
+*			is appropriately cleared. Otherwise, as soon as we clear the I and
+*			F bits, there can be an infinite loop of interrupts with an
+*			eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("mrs     lr, spsr");  \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}");
+
+/****************************************************************************/
+/**
+* Disable the nested interrupts by setting the I and F bits.
+*
+* @return   None.
+*
+* @note     This macro is meant to be called in the interrupt service routines.
+*			This macro cannot be used independently. It can only be used when
+*			nesting of interrupts have been enabled by using the macro
+*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
+*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+*			point. The user then must call this macro before exiting the interrupt
+*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
+*			hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h
new file mode 100644
index 000000000..d4434d07f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
new file mode 100644
index 000000000..31de05581
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.  These functions encapsulate Cortex A53 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* </pre>
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
new file mode 100644
index 000000000..06d89dcc3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
@@ -0,0 +1,351 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+#  define INST_SYNC		mbar(0)
+#  define DATA_SYNC		mbar(1)
+# else
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 64-bit memory location by reading the
+* specified Value to the the specified address.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+	volatile u8 *LocalAddr = (volatile u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+	volatile u16 *LocalAddr = (volatile u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+	volatile u32 *LocalAddr = (volatile u32 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 64-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+# else
+# define Xil_In16BE	Xil_In16
+# define Xil_In32BE	Xil_In32
+# define Xil_Out16BE	Xil_Out16
+# define Xil_Out32BE	Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In16(Addr);
+	return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In32(Addr);
+	return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+	Value = Xil_EndianSwap16(Value);
+	Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+	Value = Xil_EndianSwap32(Value);
+	Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h
new file mode 100644
index 000000000..ebafde87d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h
new file mode 100644
index 000000000..8e43e8227
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API
+* defined for MPU in R5. R5 does not have mmu and for usage of similiar API
+* the file has been created.
+*
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.0	pkp  2/12/15 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_mpu.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c
new file mode 100644
index 000000000..7c028c515
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c
@@ -0,0 +1,258 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mpu.c
+*
+* This file provides APIs for enabling/disabling MPU and setting the memory
+* attributes for sections, in the MPU translation table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mpu.h"
+#include "xdebug.h"
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+static const struct {
+	u64 size;
+	unsigned int encoding;
+}region_size[] = {
+	{ 0x20, REGION_32B },
+	{ 0x40, REGION_64B },
+	{ 0x80, REGION_128B },
+	{ 0x100, REGION_256B },
+	{ 0x200, REGION_512B },
+	{ 0x400, REGION_1K },
+	{ 0x800, REGION_2K },
+	{ 0x1000, REGION_4K },
+	{ 0x2000, REGION_8K },
+	{ 0x4000, REGION_16K },
+	{ 0x8000, REGION_32K },
+	{ 0x10000, REGION_64K },
+	{ 0x20000, REGION_128K },
+	{ 0x40000, REGION_256K },
+	{ 0x80000, REGION_512K },
+	{ 0x100000, REGION_1M },
+	{ 0x200000, REGION_2M },
+	{ 0x400000, REGION_4M },
+	{ 0x800000, REGION_8M },
+	{ 0x1000000, REGION_16M },
+	{ 0x2000000, REGION_32M },
+	{ 0x4000000, REGION_64M },
+	{ 0x8000000, REGION_128M },
+	{ 0x10000000, REGION_256M },
+	{ 0x20000000, REGION_512M },
+	{ 0x40000000, REGION_1G },
+	{ 0x80000000, REGION_2G },
+	{ 0x100000000, REGION_4G },
+};
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section of memory with starting address addr
+* of the region size 1MB having attributes attrib
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	attrib specifies the attributes for that memory region.
+* @return	None.
+*
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
+{
+	INTPTR Localaddr = addr;
+	Localaddr &= (~(0xFFFFFU));
+	/* Setting the MPU region with given attribute with 1MB size */
+	Xil_SetMPURegion(Localaddr, 0x100000, attrib);
+}
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section of memory with starting address addr
+* of the region size size and having attributes attrib
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	size is the size of the region.
+* @param	attrib specifies the attributes for that memory region.
+* @return	None.
+*
+*
+******************************************************************************/
+void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
+{
+	u32 Regionsize = 0;
+	INTPTR Localaddr = addr;
+	u32 NextAvailableMemRegion;
+	unsigned int i;
+
+	Xil_DCacheFlush();
+	Xil_ICacheInvalidate();
+	NextAvailableMemRegion = mfcp(XREG_CP15_MPU_MEMORY_REG_NUMBER);
+	NextAvailableMemRegion++;
+	if (NextAvailableMemRegion > 16) {
+		xdbg_printf(DEBUG, "No regions available\r\n");
+		return;
+	}
+	mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
+	isb();
+
+	/* Lookup the size.  */
+	for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
+		if (size <= region_size[i].size) {
+			Regionsize = region_size[i].encoding;
+			break;
+		}
+	}
+
+	Localaddr &= ~(region_size[i].size - 1);
+
+	Regionsize <<= 1;
+	Regionsize |= REGION_EN;
+	dsb();
+	mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);	/* Set base address of a region */
+	mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);	/* Set the control attribute */
+	mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);	/* set the region size and enable it*/
+	dsb();
+	isb();
+}
+/*****************************************************************************
+*
+* Enable MPU for Cortex R5 processor. This function invalidates I cache and
+* flush the D Caches before enabling the MPU.
+*
+*
+* @param	None.
+* @return	None.
+*
+******************************************************************************/
+void Xil_EnableMPU(void)
+{
+	u32 CtrlReg, Reg;
+	s32 DCacheStatus=0, ICacheStatus=0;
+	/* enable caches only if they are disabled */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
+		DCacheStatus=1;
+	}
+	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
+		ICacheStatus=1;
+	}
+
+	if(DCacheStatus != 0) {
+		Xil_DCacheDisable();
+	}
+	if(ICacheStatus != 0){
+		Xil_ICacheDisable();
+	}
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+	Reg |= 0x00000001U;
+	dsb();
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+	isb();
+	/* enable caches only if they are disabled in routine*/
+	if(DCacheStatus != 0) {
+		Xil_DCacheEnable();
+	}
+	if(ICacheStatus != 0) {
+		Xil_ICacheEnable();
+	}
+}
+
+/*****************************************************************************
+*
+* Disable MPU for Cortex R5 processors. This function invalidates I cache and
+* flush the D Caches before disabling the MPU.
+*
+* @param	None.
+*
+* @return	None.
+*
+******************************************************************************/
+void Xil_DisableMPU(void)
+{
+	u32 CtrlReg, Reg;
+	s32 DCacheStatus=0, ICacheStatus=0;
+	/* enable caches only if they are disabled */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
+		DCacheStatus=1;
+	}
+	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
+		ICacheStatus=1;
+	}
+
+	if(DCacheStatus != 0) {
+		Xil_DCacheDisable();
+	}
+	if(ICacheStatus != 0){
+		Xil_ICacheDisable();
+	}
+
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+	Reg &= ~(0x00000001U);
+	dsb();
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+	isb();
+	/* enable caches only if they are disabled in routine*/
+	if(DCacheStatus != 0) {
+		Xil_DCacheEnable();
+	}
+	if(ICacheStatus != 0) {
+		Xil_ICacheEnable();
+	}
+}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
new file mode 100644
index 000000000..a55be916e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MPU_H
+#define XIL_MPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#include "xil_types.h"
+/***************************** Include Files *********************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMPU(void);
+void Xil_DisableMPU(void);
+void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MPU_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
new file mode 100644
index 000000000..9dffed148
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
@@ -0,0 +1,438 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+    s32 len;
+    s32 num1;
+    s32 num2;
+    char8 pad_character;
+    s32 do_padding;
+    s32 left_flag;
+    s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+    s32 i;
+
+    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+		i=(par->len);
+        for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+            outbyte( par->pad_character);
+#endif
+		}
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+static void outs(const charptr lp, struct params_s *par)
+{
+    charptr LocalPtr;
+	LocalPtr = lp;
+    /* pad on left if needed                         */
+	if(LocalPtr != NULL) {
+		par->len = (s32)strlen( LocalPtr);
+	}
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+		(par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+        outbyte(*LocalPtr);
+		LocalPtr += 1;
+#endif
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp)                      */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[32];
+    const char8 digits[] = "0123456789ABCDEF";
+    u32 num;
+    for(i = 0; i<32; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = n;
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+	outbyte( outbuf[i] );
+		i--;
+#endif
+}
+    padding( par->left_flag, par);
+}
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a 64-bit number to the output  */
+/* buffer as directed by the padding and positioning */
+/* flags. 											 */
+/*                                                   */
+#if defined (__aarch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[64];
+    const char8 digits[] = "0123456789ABCDEF";
+    u64 num;
+    for(i = 0; i<64; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+	outbyte( outbuf[i] );
+		i--;
+}
+    padding( par->left_flag, par);
+}
+#endif
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+static s32 getnum( charptr* linep)
+{
+    s32 n;
+    s32 ResultIsDigit = 0;
+    charptr cptr;
+    n = 0;
+    cptr = *linep;
+	if(cptr != NULL){
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    while (ResultIsDigit != 0) {
+		if(cptr != NULL){
+			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+			cptr += 1;
+			if(cptr != NULL){
+				ResultIsDigit = isdigit(((s32)*cptr));
+			}
+		}
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    *linep = ((charptr )(cptr));
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floating point        */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+void xil_printf( const char8 *ctrl1, ...)
+{
+	s32 Check;
+#if defined (__aarch64__)
+    s32 long_flag;
+#endif
+    s32 dot_flag;
+
+    params_t par;
+
+    char8 ch;
+    va_list argp;
+    char8 *ctrl = (char8 *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+            outbyte(*ctrl);
+			ctrl += 1;
+#endif
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag = 0;
+#if defined (__aarch64__)
+		long_flag = 0;
+#endif
+        par.unsigned_flag = 0;
+		par.left_flag = 0;
+		par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+		par.num1=0;
+		par.len=0;
+
+ try_next:
+		if(ctrl != NULL) {
+			ctrl += 1;
+		}
+		if(ctrl != NULL) {
+			ch = *ctrl;
+		}
+		else {
+			ch = *ctrl;
+		}
+
+        if (isdigit((s32)ch) != 0) {
+            if (dot_flag != 0) {
+                par.num2 = getnum(&ctrl);
+			}
+            else {
+                if (ch == '0') {
+                    par.pad_character = '0';
+				}
+				if(ctrl != NULL) {
+			par.num1 = getnum(&ctrl);
+				}
+                par.do_padding = 1;
+            }
+            if(ctrl != NULL) {
+			ctrl -= 1;
+			}
+            goto try_next;
+        }
+
+        switch (tolower((s32)ch)) {
+            case '%':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( '%');
+#endif
+                Check = 1;
+                break;
+
+            case '-':
+                par.left_flag = 1;
+                Check = 0;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                Check = 0;
+                break;
+
+            case 'l':
+            #if defined (__aarch64__)
+                long_flag = 1;
+            #endif
+                Check = 0;
+                break;
+
+            case 'u':
+                par.unsigned_flag = 1;
+                /* fall through */
+            case 'i':
+            case 'd':
+                #if defined (__aarch64__)
+                if (long_flag != 0){
+			        outnum1((s64)va_arg(argp, s64), 10L, &par);
+                }
+                else {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+                #else
+                    outnum( va_arg(argp, s32), 10L, &par);
+                #endif
+				Check = 1;
+                break;
+            case 'p':
+                #if defined (__aarch64__)
+                par.unsigned_flag = 1;
+			    outnum1((s64)va_arg(argp, s64), 16L, &par);
+			    Check = 1;
+                break;
+                #endif
+            case 'X':
+            case 'x':
+                par.unsigned_flag = 1;
+                #if defined (__aarch64__)
+                if (long_flag != 0) {
+				    outnum1((s64)va_arg(argp, s64), 16L, &par);
+				}
+				else {
+				    outnum((s32)va_arg(argp, s32), 16L, &par);
+                }
+                #else
+                outnum((s32)va_arg(argp, s32), 16L, &par);
+                #endif
+                Check = 1;
+                break;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                Check = 1;
+                break;
+
+            case 'c':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( va_arg( argp, s32));
+#endif
+                Check = 1;
+                break;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x07));
+#endif
+                        break;
+                    case 'h':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x08));
+#endif
+                        break;
+                    case 'r':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+#endif
+                        break;
+                    case 'n':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+                        outbyte( ((char8)0x0A));
+#endif
+                        break;
+                    default:
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( *ctrl);
+#endif
+                        break;
+                }
+                ctrl += 1;
+                Check = 0;
+                break;
+
+            default:
+		Check = 1;
+		break;
+        }
+        if(Check == 1) {
+			if(ctrl != NULL) {
+				ctrl += 1;
+			}
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+
+/*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
new file mode 100644
index 000000000..2be5c5734
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
@@ -0,0 +1,44 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
new file mode 100644
index 000000000..a2c4b0bbf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
@@ -0,0 +1,366 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* </pre>
+*
+* @note
+*
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+/**
+* Perform DCache range related API test such as Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange. This test function writes a constant value
+* to the Data array, flushes the range, writes a new value, then invalidates
+* the corresponding range.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheRange(void)
+{
+	s32 Index;
+	s32 Status = 0;
+	u32 CtrlReg;
+	INTPTR Value;
+
+	xil_printf("-- Cache Range Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A00505;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    flush range done\r\n");
+
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A00505) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("	Flush worked\r\n");
+	}
+	else {
+		xil_printf("Error: flush dcache range not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+		#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+		#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0C505;
+
+
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    invalidate dcache range done\r\n");
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0A05;
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A0A05) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+
+	if (!Status) {
+		xil_printf("    Invalidate worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache range not working\r\n");
+	}
+	xil_printf("-- Cache Range Test Complete --\r\n");
+	return Status;
+
+}
+
+/**
+* Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value, then invalidates
+* the DCache.
+*
+* @return
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheAll(void)
+{
+	s32 Index;
+	s32 Status;
+	INTPTR Value;
+	u32 CtrlReg;
+
+	xil_printf("-- Cache All Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50500A0A;
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlush();
+	xil_printf("    flush all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+
+		if (Value != 0x50500A0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Flush all worked\r\n");
+	}
+	else {
+		xil_printf("Error: Flush dcache all not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x505FFA0A;
+
+	Xil_DCacheFlush();
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidate();
+
+	xil_printf("    invalidate all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50CFA0A;
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0x50CFA0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate all worked\r\n");
+	}
+	else {
+			xil_printf("Error: Invalidate dcache all not working\r\n");
+	}
+
+	xil_printf("-- DCache all Test Complete --\n\r");
+
+	return Status;
+}
+
+
+/**
+* Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+s32 Xil_TestICacheRange(void)
+{
+
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+	xil_printf("-- Invalidate icache range done --\r\n");
+
+	return 0;
+}
+
+/**
+* Perform Xil_ICacheInvalidate().
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+s32 Xil_TestICacheAll(void)
+{
+	Xil_ICacheInvalidate();
+	xil_printf("-- Invalidate icache all done --\r\n");
+	return 0;
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h
new file mode 100644
index 000000000..b3c416cd0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* This file contains utility functions to test cache.
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
new file mode 100644
index 000000000..a68d7652f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
@@ -0,0 +1,301 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param	Data is the 16-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+	return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param	Data is the 32-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+	u16 Lo16;
+	u16 Hi16;
+
+	u16 Swap16Lo;
+	u16 Swap16Hi;
+
+	Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+	Lo16 = (u16)(Data & 0x0000FFFFU);
+
+	Swap16Lo = Swap16(Lo16);
+	Swap16Hi = Swap16(Hi16);
+
+	return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide register IO test where the register is
+* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
+* values.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+	u8 ValueIn;
+	s32 Index;
+	s32 Status = 0;
+
+	for (Index = 0; Index < Length; Index++) {
+		Xil_Out8((INTPTR)Addr, Value);
+
+		ValueIn = Xil_In8((INTPTR)Addr);
+
+		if ((Value != ValueIn) && (Status == 0)) {
+			Status = -1;
+			break;
+		}
+	}
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide register IO test. Each location is tested
+* by sequentially writing a 16-bit wide register, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function performs the following
+* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
+* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
+* read-in value before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+	u16 *TempAddr16;
+	u16 ValueIn = 0U;
+	s32 Index;
+	TempAddr16 = Addr;
+	Xil_AssertNonvoid(TempAddr16 != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out16LE((INTPTR)TempAddr16, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out16BE((INTPTR)TempAddr16, Value);
+			break;
+		default:
+			Xil_Out16((INTPTR)TempAddr16, Value);
+			break;
+		}
+
+		ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out16((INTPTR)TempAddr16, Value);
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+			break;
+		default:
+			ValueIn = Xil_In16((INTPTR)TempAddr16);
+			break;
+		}
+
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr16 += sizeof(u16);
+	}
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide register IO test. Each location is tested
+* by sequentially writing a 32-bit wide regsiter, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function perform the following
+* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
+* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
+* before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+	u32 *TempAddr;
+	u32 ValueIn = 0U;
+	s32 Index;
+	TempAddr = Addr;
+	Xil_AssertNonvoid(TempAddr != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out32LE((INTPTR)TempAddr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out32BE((INTPTR)TempAddr, Value);
+			break;
+		default:
+			Xil_Out32((INTPTR)TempAddr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In32((INTPTR)TempAddr);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out32((INTPTR)TempAddr, Value);
+
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In32LE((INTPTR)TempAddr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In32BE((INTPTR)TempAddr);
+			break;
+		default:
+			ValueIn = Xil_In32((INTPTR)TempAddr);
+			break;
+		}
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr += sizeof(u32);
+	}
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h
new file mode 100644
index 000000000..fba0c1060
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.h
+*
+* This file contains utility functions to teach endian related memory
+* IO functions.
+*
+* <b>Memory test description</b>
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
new file mode 100644
index 000000000..19a3b6608
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
@@ -0,0 +1,882 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u32 Val;
+	u32 FirtVal;
+	u32 WordMem32;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			*(Addr+I) = Val;
+			Val++;
+		}
+
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			WordMem32 = *(Addr+I);
+
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (1U << j);
+
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u32) RotateLeft(Val, 32U);
+			}
+
+			/*
+			 * Restore the reference 'val' to the
+			 * initial value
+			 */
+			Val = 1U << j;
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+
+				WordMem32 = *(Addr+I);
+
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = (u32)RotateLeft(Val, 32U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible
+		 * initial test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = ~(1U << j);
+
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = ~(1U << j);
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+				WordMem32 = *(Addr+I);
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* Read the location */
+			WordMem32 = *(Addr+I);
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+
+			if ((WordMem32 ^ Val) != 0x00000000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u32)0) {
+			Val = 0xDEADBEEFU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+
+			/* read memory location */
+
+			WordMem32 = *(Addr+I);
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant Pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u16 Val;
+	u16 FirtVal;
+	u16 WordMem16;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (u16)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u16)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones
+			 * test to test for bad
+			 * data bits
+			 */
+
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u16) (~((INTPTR)(&Addr[I])));
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			Val = (u16) (~((INTPTR) (&Addr[I])));
+			if ((WordMem16 ^ Val) != 0x0000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+		if (Pattern == (u16)0) {
+			Val = 0xDEADU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u8 Val;
+	u8 FirtVal;
+	u8 WordMem8;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			Val = (u8)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u8)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test to test
+			 * for bad data bits
+			 */
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			if ((WordMem8 ^ Val) != 0x00U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u8)0) {
+			Val = 0xA5U;
+		}
+		else {
+			Val = Pattern;
+		}
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting unsigned long value of the rotate left
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+	/*
+	 * set the Width of the Input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	Msb = LocalInput & MsbMask;
+
+	ReturnVal = LocalInput << 1U;
+
+	if (Msb != 0x00000000U) {
+		ReturnVal = ReturnVal | (u32)0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the right one bit position
+*
+* @param    Input is value to be rotated to the right
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting u32 value of the rotate right
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << 1U) - 1U;
+
+	/*
+	 * set the width of the input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	ReturnVal = LocalInput >> 1U;
+
+	Lsb = LocalInput & 0x00000001U;
+
+	if (Lsb != 0x00000000U) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
new file mode 100644
index 000000000..4cbfd878b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+*
+* This file contains utility functions to test memory.
+*
+* <b>Memory test description</b>
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* <pre>
+* XIL_TESTMEM_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+*	incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XIL_TESTMEM_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* </pre>
+*
+* <i>WARNING</i>
+*
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+*
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE	1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0x00U
+#define XIL_TESTMEM_INCREMENT       0x01U
+#define XIL_TESTMEM_WALKONES        0x02U
+#define XIL_TESTMEM_WALKZEROS       0x03U
+#define XIL_TESTMEM_INVERSEADDR     0x04U
+#define XIL_TESTMEM_FIXEDPATTERN    0x05U
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
new file mode 100644
index 000000000..e8b78b7c6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
@@ -0,0 +1,200 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/**
+ * xbasic_types.h does not typedef s* or u64
+ */
+
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * UPPER_32_BITS - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * LOWER_32_BITS - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
new file mode 100644
index 000000000..2f527c90a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
@@ -0,0 +1,320 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex R5 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp  	02/29/14 Initial version
+* 6.0   mus     08/18/16 Defined ARMR5 flag
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XPARAMETERS_PS_H_
+#define XPARAMETERS_PS_H_
+
+#ifndef ARMR5
+#define ARMR5 ARMR5
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XEMACPS_2_INTR		XPS_GEM2_INT_ID
+#define XPAR_XEMACPS_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
+#define XPAR_XEMACPS_3_INTR		XPS_GEM3_INT_ID
+#define XPAR_XEMACPS_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_LPD_SWDT_INT_ID
+#define XPAR_XWDTPS_1_INTR		XPS_FPD_SWDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XTTCPS_6_INTR		XPS_TTC2_0_INT_ID
+#define XPAR_XTTCPS_7_INTR		XPS_TTC2_1_INT_ID
+#define XPAR_XTTCPS_8_INTR		XPS_TTC2_2_INT_ID
+#define XPAR_XTTCPS_9_INTR		XPS_TTC3_0_INT_ID
+#define XPAR_XTTCPS_10_INTR		XPS_TTC3_1_INT_ID
+#define XPAR_XTTCPS_11_INTR		XPS_TTC3_2_INT_ID
+#define XPAR_XNANDPS8_0_INTR        	XPS_NAND_INT_ID
+#define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
+#define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
+#define XPAR_XADMAPS_2_INTR		XPS_ADMA_CH2_INT_ID
+#define XPAR_XADMAPS_3_INTR 		XPS_ADMA_CH3_INT_ID
+#define XPAR_XADMAPS_4_INTR		XPS_ADMA_CH4_INT_ID
+#define XPAR_XADMAPS_5_INTR 		XPS_ADMA_CH5_INT_ID
+#define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
+#define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
+#define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
+#define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
+#define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
+#define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
+#define XPAR_XZDMAPS_2_INTR 		XPS_ZDMA_CH2_INT_ID
+#define XPAR_XZDMAPS_3_INTR 		XPS_ZDMA_CH3_INT_ID
+#define XPAR_XZDMAPS_4_INTR		XPS_ZDMA_CH4_INT_ID
+#define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
+#define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
+#define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
+#define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
+#define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
+#define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB3_0_ENDPT_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB3_1_ENDPT_INT_ID
+#define	XPAR_XRTCPSU_ALARM_INTR 	XPS_RTC_ALARM_INT_ID
+#define	XPAR_XRTCPSU_SECONDS_INTR	XPS_RTC_SEC_INT_ID
+#define XPAR_XAPMPS_0_INTR		XPS_APM0_INT_ID
+#define XPAR_XAPMPS_1_INTR		XPS_APM1_INT_ID
+#define XPAR_XAPMPS_2_INTR		XPS_APM2_INT_ID
+#define XPAR_XAPMPS_5_INTR		XPS_APM5_INT_ID
+#define XPAR_XSYSMONPSU_INTR		XPS_AMS_INT_ID
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00002000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_SYS_CTRL_BASEADDR	0xFF180000U
+#define XPS_SCU_PERIPH_BASE		0xF9000000U
+
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_FPGA0_INT_ID		121U
+#define XPS_FPGA1_INT_ID		122U
+#define XPS_FPGA2_INT_ID		123U
+#define XPS_FPGA3_INT_ID		124U
+#define XPS_FPGA4_INT_ID		125U
+#define XPS_FPGA5_INT_ID		126U
+#define XPS_FPGA6_INT_ID		127U
+#define XPS_FPGA7_INT_ID		128U
+#define XPS_FPGA8_INT_ID		136U
+#define XPS_FPGA9_INT_ID		137U
+#define XPS_FPGA10_INT_ID		138U
+#define XPS_FPGA11_INT_ID		139U
+#define XPS_FPGA12_INT_ID		140U
+#define XPS_FPGA13_INT_ID		141U
+#define XPS_FPGA14_INT_ID		142U
+#define XPS_FPGA15_INT_ID		143U
+
+/* Updated Interrupt-IDs */
+#define XPS_OCMINTR_INT_ID		(10U + 32U)
+#define XPS_NAND_INT_ID        		(14U + 32U)
+#define XPS_QSPI_INT_ID			(15U + 32U)
+#define XPS_GPIO_INT_ID			(16U + 32U)
+#define XPS_I2C0_INT_ID			(17U + 32U)
+#define XPS_I2C1_INT_ID			(18U + 32U)
+#define XPS_SPI0_INT_ID			(19U + 32U)
+#define XPS_SPI1_INT_ID			(20U + 32U)
+#define XPS_UART0_INT_ID		(21U + 32U)
+#define XPS_UART1_INT_ID		(22U + 32U)
+#define XPS_CAN0_INT_ID			(23U + 32U)
+#define XPS_CAN1_INT_ID			(24U + 32U)
+#define	XPS_RTC_ALARM_INT_ID 	(26U + 32U)
+#define	XPS_RTC_SEC_INT_ID	 	(27U + 32U)
+#define XPS_LPD_SWDT_INT_ID		(52U + 32U)
+#define XPS_FPD_SWDT_INT_ID		(113U + 32U)
+#define XPS_TTC0_0_INT_ID		(36U + 32U)
+#define XPS_TTC0_1_INT_ID		(37U + 32U)
+#define XPS_TTC0_2_INT_ID 		(38U + 32U)
+#define XPS_TTC1_0_INT_ID		(39U + 32U)
+#define XPS_TTC1_1_INT_ID		(40U + 32U)
+#define XPS_TTC1_2_INT_ID		(41U + 32U)
+#define XPS_TTC2_0_INT_ID		(42U + 32U)
+#define XPS_TTC2_1_INT_ID		(43U + 32U)
+#define XPS_TTC2_2_INT_ID		(44U + 32U)
+#define XPS_TTC3_0_INT_ID		(45U + 32U)
+#define XPS_TTC3_1_INT_ID		(46U + 32U)
+#define XPS_TTC3_2_INT_ID		(47U + 32U)
+#define XPS_SDIO0_INT_ID		(48U + 32U)
+#define XPS_SDIO1_INT_ID		(49U + 32U)
+#define XPS_AMS_INT_ID			(56U + 32U)
+#define XPS_GEM0_INT_ID			(57U + 32U)
+#define XPS_GEM0_WAKE_INT_ID		(58U + 32U)
+#define XPS_GEM1_INT_ID			(59U + 32U)
+#define XPS_GEM1_WAKE_INT_ID		(60U + 32U)
+#define XPS_GEM2_INT_ID			(61U + 32U)
+#define XPS_GEM2_WAKE_INT_ID		(62U + 32U)
+#define XPS_GEM3_INT_ID			(63U + 32U)
+#define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
+#define XPS_USB3_0_ENDPT_INT_ID		(65U + 32U)
+#define XPS_USB3_1_ENDPT_INT_ID		(70U + 32U)
+#define XPS_ADMA_CH0_INT_ID		(77U + 32U)
+#define XPS_ADMA_CH1_INT_ID		(78U + 32U)
+#define XPS_ADMA_CH2_INT_ID		(79U + 32U)
+#define XPS_ADMA_CH3_INT_ID		(80U + 32U)
+#define XPS_ADMA_CH4_INT_ID		(81U + 32U)
+#define XPS_ADMA_CH5_INT_ID		(82U + 32U)
+#define XPS_ADMA_CH6_INT_ID		(83U + 32U)
+#define XPS_ADMA_CH7_INT_ID		(84U + 32U)
+#define XPS_CSU_DMA_INT_ID		(86U + 32U)
+#define XPS_XMPU_LPD_INT_ID		(88U + 32U)
+#define XPS_ZDMA_CH0_INT_ID		(124U + 32U)
+#define XPS_ZDMA_CH1_INT_ID		(125U + 32U)
+#define XPS_ZDMA_CH2_INT_ID		(126U + 32U)
+#define XPS_ZDMA_CH3_INT_ID		(127U + 32U)
+#define XPS_ZDMA_CH4_INT_ID		(128U + 32U)
+#define XPS_ZDMA_CH5_INT_ID		(129U + 32U)
+#define XPS_ZDMA_CH6_INT_ID		(130U + 32U)
+#define XPS_ZDMA_CH7_INT_ID		(131U + 32U)
+#define XPS_XMPU_FPD_INT_ID		(134U + 32U)
+#define XPS_FPD_CCI_INT_ID		(154U + 32U)
+#define XPS_FPD_SMMU_INT_ID		(155U + 32U)
+#define XPS_APM0_INT_ID		(123U + 32U)
+#define XPS_APM1_INT_ID		(25U + 32U)
+#define XPS_APM2_INT_ID		(25U + 32U)
+#define XPS_APM5_INT_ID		(123U + 32U)
+
+/* REDEFINES for TEST APP */
+#define XPAR_PSU_UART_0_INTR        XPS_UART0_INT_ID
+#define XPAR_PSU_UART_1_INTR        XPS_UART1_INT_ID
+#define XPAR_PSU_USB_0_INTR     XPS_USB0_INT_ID
+#define XPAR_PSU_USB_1_INTR     XPS_USB1_INT_ID
+#define XPAR_PSU_I2C_0_INTR     XPS_I2C0_INT_ID
+#define XPAR_PSU_I2C_1_INTR     XPS_I2C1_INT_ID
+#define XPAR_PSU_SPI_0_INTR     XPS_SPI0_INT_ID
+#define XPAR_PSU_SPI_1_INTR     XPS_SPI1_INT_ID
+#define XPAR_PSU_CAN_0_INTR     XPS_CAN0_INT_ID
+#define XPAR_PSU_CAN_1_INTR     XPS_CAN1_INT_ID
+#define XPAR_PSU_GPIO_0_INTR        XPS_GPIO_INT_ID
+#define XPAR_PSU_ETHERNET_0_INTR    XPS_GEM0_INT_ID
+#define XPAR_PSU_ETHERNET_0_WAKE_INTR   XPS_GEM0_WAKE_INT_ID
+#define XPAR_PSU_ETHERNET_1_INTR    XPS_GEM1_INT_ID
+#define XPAR_PSU_ETHERNET_1_WAKE_INTR   XPS_GEM1_WAKE_INT_ID
+#define XPAR_PSU_ETHERNET_2_INTR    XPS_GEM2_INT_ID
+#define XPAR_PSU_ETHERNET_2_WAKE_INTR   XPS_GEM2_WAKE_INT_ID
+#define XPAR_PSU_ETHERNET_3_INTR    XPS_GEM3_INT_ID
+#define XPAR_PSU_ETHERNET_3_WAKE_INTR   XPS_GEM3_WAKE_INT_ID
+#define XPAR_PSU_QSPI_0_INTR        XPS_QSPI_INT_ID
+#define XPAR_PSU_WDT_0_INTR    		XPS_LPD_SWDT_INT_ID
+#define XPAR_PSU_WDT_1_INTR     	XPS_FPD_SWDT_INT_ID
+#define XPAR_PSU_XADC_0_INTR        XPS_SYSMON_INT_ID
+#define XPAR_PSU_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PSU_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PSU_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PSU_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PSU_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PSU_TTC_5_INTR         XPS_TTC1_2_INT_ID
+#define XPAR_PSU_TTC_6_INTR			XPS_TTC2_0_INT_ID
+#define XPAR_PSU_TTC_7_INTR			XPS_TTC2_1_INT_ID
+#define XPAR_PSU_TTC_8_INTR			XPS_TTC2_2_INT_ID
+#define XPAR_PSU_TTC_9_INTR			XPS_TTC3_0_INT_ID
+#define XPAR_PSU_TTC_10_INTR		XPS_TTC3_1_INT_ID
+#define XPAR_PSU_TTC_11_INTR		XPS_TTC3_2_INT_ID
+
+#define XPAR_XADCPS_NUM_INSTANCES 1U
+#define XPAR_XADCPS_0_DEVICE_ID   0U
+#define XPAR_XADCPS_0_BASEADDR	  (0xF8007000U)
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
new file mode 100644
index 000000000..9d4560a98
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
@@ -0,0 +1,135 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about platform
+*
+* @param    None.
+*
+* @return   The information about platform defined in xplatform_info.h
+*
+* @note     None.
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+	return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+	return XPLAT_MICROBLAZE;
+#else
+	return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about zynq ultrascale MP platform
+*
+* @param    None.
+*
+* @return   The information about zynq ultrascale MP platform defined in
+*			xplatform_info.h
+*
+* @note     None.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+	u32 reg;
+	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+	return reg;
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about PS Silicon version
+*
+* @param    None.
+*
+* @return   The information about PS Silicon version.
+*
+* @note     None.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info()
+{
+	u32 reg;
+	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+			& XPS_VERSION_INFO_MASK);
+	return reg;
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
new file mode 100644
index 000000000..7028a83af
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* This file contains definitions for various platforms available
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
new file mode 100644
index 000000000..0851408cc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
@@ -0,0 +1,292 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-R5
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function disables the Cortex R5 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+	/* Disable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the Cortex R5 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+	/* Enable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets the Cortex R5 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+	u32 Reg;
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#else
+	{ register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+	  Reg = C15Reg; }
+#endif
+	Reg |= (1U << 2U); /* reset event counters */
+	mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function configures the Cortex R5 event counters controller, with the
+* event codes, in a configuration selected by the user and enables the counters.
+*
+* @param	PmcrCfg is configuration value based on which the event counters
+*		are configured.
+*		Use XPM_CNTRCFG* values defined in xpm_counter.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+	u32 Counter;
+	static PmcrEventCfg32 PmcrEvents[] = {
+		{
+			XPM_EVENT_SOFTINCR,
+			XPM_EVENT_INSRFETCH_CACHEREFILL,
+			XPM_EVENT_INSTRFECT_TLBREFILL,
+			XPM_EVENT_DATA_CACHEREFILL,
+			XPM_EVENT_DATA_CACHEACCESS,
+			XPM_EVENT_DATA_TLBREFILL
+		},
+		{
+			XPM_EVENT_DATA_READS,
+			XPM_EVENT_DATA_WRITE,
+			XPM_EVENT_EXCEPTION,
+			XPM_EVENT_EXCEPRETURN,
+			XPM_EVENT_CHANGECONTEXT,
+			XPM_EVENT_SW_CHANGEPC
+		},
+		{
+			XPM_EVENT_IMMEDBRANCH,
+			XPM_EVENT_UNALIGNEDACCESS,
+			XPM_EVENT_BRANCHMISS,
+			XPM_EVENT_CLOCKCYCLES,
+			XPM_EVENT_BRANCHPREDICT,
+			XPM_EVENT_JAVABYTECODE
+		},
+		{
+			XPM_EVENT_SWJAVABYTECODE,
+			XPM_EVENT_JAVABACKBRANCH,
+			XPM_EVENT_COHERLINEMISS,
+			XPM_EVENT_COHERLINEHIT,
+			XPM_EVENT_INSTRSTALL,
+			XPM_EVENT_DATASTALL
+		},
+		{
+			XPM_EVENT_MAINTLBSTALL,
+			XPM_EVENT_STREXPASS,
+			XPM_EVENT_STREXFAIL,
+			XPM_EVENT_DATAEVICT,
+			XPM_EVENT_NODISPATCH,
+			XPM_EVENT_ISSUEEMPTY
+		},
+		{
+			XPM_EVENT_INSTRRENAME,
+			XPM_EVENT_PREDICTFUNCRET,
+			XPM_EVENT_MAINEXEC,
+			XPM_EVENT_SECEXEC,
+			XPM_EVENT_LDRSTR,
+			XPM_EVENT_FLOATRENAME
+		},
+		{
+			XPM_EVENT_NEONRENAME,
+			XPM_EVENT_PLDSTALL,
+			XPM_EVENT_WRITESTALL,
+			XPM_EVENT_INSTRTLBSTALL,
+			XPM_EVENT_DATATLBSTALL,
+			XPM_EVENT_INSTR_uTLBSTALL
+		},
+		{
+			XPM_EVENT_DATA_uTLBSTALL,
+			XPM_EVENT_DMB_STALL,
+			XPM_EVENT_INT_CLKEN,
+			XPM_EVENT_DE_CLKEN,
+			XPM_EVENT_INSTRISB,
+			XPM_EVENT_INSTRDSB
+		},
+		{
+			XPM_EVENT_INSTRDMB,
+			XPM_EVENT_EXTINT,
+			XPM_EVENT_PLE_LRC,
+			XPM_EVENT_PLE_LRS,
+			XPM_EVENT_PLE_FLUSH,
+			XPM_EVENT_PLE_CMPL
+		},
+		{
+			XPM_EVENT_PLE_OVFL,
+			XPM_EVENT_PLE_PROG,
+			XPM_EVENT_PLE_LRC,
+			XPM_EVENT_PLE_LRS,
+			XPM_EVENT_PLE_FLUSH,
+			XPM_EVENT_PLE_CMPL
+		},
+		{
+			XPM_EVENT_DATASTALL,
+			XPM_EVENT_INSRFETCH_CACHEREFILL,
+			XPM_EVENT_INSTRFECT_TLBREFILL,
+			XPM_EVENT_DATA_CACHEREFILL,
+			XPM_EVENT_DATA_CACHEACCESS,
+			XPM_EVENT_DATA_TLBREFILL
+		},
+	};
+	const u32 *ptr = PmcrEvents[PmcrCfg];
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		/* Selecet event counter */
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+		/* Set the event */
+		mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+	}
+
+	Xpm_ResetEventCounters();
+	Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the event counters and returns the counter values.
+*
+* @param	PmCtrValue is a pointer to an array of type u32 PmCtrValue[6].
+*		It is an output parameter which is used to return the PM
+*		counter values.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+	u32 Counter;
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+		PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#else
+		{ register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+		  PmCtrValue[Counter] = Cp15Reg; }
+#endif
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h
new file mode 100644
index 000000000..5679d4bb5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h
@@ -0,0 +1,571 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* This header file contains APIs for configuring and controlling the Cortex-R5
+* Performance Monitor Events.
+* Cortex-R5 Performance Monitor has 6 event counters which can be used to
+* count a variety of events described in Coretx-R5 TRM. This file defines
+* configurations, where value configures the event counters to count a
+* set of events.
+*
+* Xpm_SetEvents can be used to set the event counters to count a set of events
+* and Xpm_GetEventCounters can be used to read the counter values.
+*
+* @note
+*
+* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include <stdint.h>
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-R5 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-R5 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-R5 processor which also miss in all the other
+ * Cortex-R5 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-R5 processor which hit in another Cortex-R5
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-R5 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ *    - b00 no instructions renamed
+ *    - b01 one instruction renamed
+ *    - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-R5 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config		PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
+ *			  XPM_EVENT_DATA_WRITE,
+ *			  XPM_EVENT_EXCEPTION,
+ *			  XPM_EVENT_EXCEPRETURN,
+ *			  XPM_EVENT_CHANGECONTEXT,
+ *			  XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
+ *			  XPM_EVENT_UNALIGNEDACCESS,
+ *			  XPM_EVENT_BRANCHMISS,
+ *			  XPM_EVENT_CLOCKCYCLES,
+ *			  XPM_EVENT_BRANCHPREDICT,
+ *			  XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
+ *			  XPM_EVENT_JAVABACKBRANCH,
+ *			  XPM_EVENT_COHERLINEMISS,
+ *			  XPM_EVENT_COHERLINEHIT,
+ *			  XPM_EVENT_INSTRSTALL,
+ *			  XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
+ *			  XPM_EVENT_STREXPASS,
+ *			  XPM_EVENT_STREXFAIL,
+ *			  XPM_EVENT_DATAEVICT,
+ *			  XPM_EVENT_NODISPATCH,
+ *			  XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
+ *			  XPM_EVENT_PREDICTFUNCRET,
+ *			  XPM_EVENT_MAINEXEC,
+ *			  XPM_EVENT_SECEXEC,
+ *			  XPM_EVENT_LDRSTR,
+ *			  XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
+ *			  XPM_EVENT_PLDSTALL,
+ *			  XPM_EVENT_WRITESTALL,
+ *			  XPM_EVENT_INSTRTLBSTALL,
+ *			  XPM_EVENT_DATATLBSTALL,
+ *			  XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
+ *			  XPM_EVENT_DMB_STALL,
+ *			  XPM_EVENT_INT_CLKEN,
+ *			  XPM_EVENT_DE_CLKEN,
+ *			  XPM_EVENT_INSTRISB,
+ *			  XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
+ *			  XPM_EVENT_EXTINT,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
+ *			  XPM_EVENT_PLE_PROG,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1	0
+#define XPM_CNTRCFG2	1
+#define XPM_CNTRCFG3	2
+#define XPM_CNTRCFG4	3
+#define XPM_CNTRCFG5	4
+#define XPM_CNTRCFG6	5
+#define XPM_CNTRCFG7	6
+#define XPM_CNTRCFG8	7
+#define XPM_CNTRCFG9	8
+#define XPM_CNTRCFG10	9
+#define XPM_CNTRCFG11	10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
new file mode 100644
index 000000000..aff19d5a9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* This header file contains macros for using inline assembler code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_H /* by using protection macros */
+
+#include "xreg_cortexr5.h"
+#include "xpseudo_asm_gcc.h"
+
+#endif /* XPSEUDO_ASM_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
new file mode 100644
index 000000000..b475c90e7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
@@ -0,0 +1,249 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u64 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mrs	%0, cpsr\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+#define mtcpsr(v)	__asm__ __volatile__(\
+			  "msr	cpsr,%0\n"\
+			  : : "r" (v)\
+			)
+
+#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)
+
+#define mfgpr(rn)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#endif
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u64 rval;\
+			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v)	__asm__ __volatile__(\
+			 "mcr " rn "\n"\
+			 : : "r" (v)\
+			);
+
+#define mfcp(rn)	({u32 rval; \
+			 __asm__ __volatile__(\
+			   "mrc " rn "\n"\
+			   : "=r" (rval)\
+			 );\
+			 rval;\
+			 })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h
new file mode 100644
index 000000000..9d28c0acb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h
@@ -0,0 +1,445 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexr5.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, IAR, ARMCC compiler.
+*
+* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+#ifndef XREG_CORTEXR5_H	/* prevent circular inclusions */
+#define XREG_CORTEXR5_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20U
+#define XREG_CPSR_MODE_BITS			0x1FU
+#define XREG_CPSR_SYSTEM_MODE			0x1FU
+#define XREG_CPSR_UNDEFINED_MODE		0x1BU
+#define XREG_CPSR_DATA_ABORT_MODE		0x17U
+#define XREG_CPSR_SVC_MODE			0x13U
+#define XREG_CPSR_IRQ_MODE			0x12U
+#define XREG_CPSR_FIQ_MODE			0x11U
+#define XREG_CPSR_USER_MODE			0x10U
+
+#define XREG_CPSR_IRQ_ENABLE			0x80U
+#define XREG_CPSR_FIQ_ENABLE			0x40U
+
+#define XREG_CPSR_N_BIT				0x80000000U
+#define XREG_CPSR_Z_BIT				0x40000000U
+#define XREG_CPSR_C_BIT				0x20000000U
+#define XREG_CPSR_V_BIT				0x10000000U
+
+/*MPU region definitions*/
+#define REGION_32B     0x00000004U
+#define REGION_64B     0x00000005U
+#define REGION_128B    0x00000006U
+#define REGION_256B    0x00000007U
+#define REGION_512B    0x00000008U
+#define REGION_1K      0x00000009U
+#define REGION_2K      0x0000000AU
+#define REGION_4K      0x0000000BU
+#define REGION_8K      0x0000000CU
+#define REGION_16K     0x0000000DU
+#define REGION_32K     0x0000000EU
+#define REGION_64K     0x0000000FU
+#define REGION_128K    0x00000010U
+#define REGION_256K    0x00000011U
+#define REGION_512K    0x00000012U
+#define REGION_1M      0x00000013U
+#define REGION_2M      0x00000014U
+#define REGION_4M      0x00000015U
+#define REGION_8M      0x00000016U
+#define REGION_16M     0x00000017U
+#define REGION_32M     0x00000018U
+#define REGION_64M     0x00000019U
+#define REGION_128M    0x0000001AU
+#define REGION_256M    0x0000001BU
+#define REGION_512M    0x0000001CU
+#define REGION_1G      0x0000001DU
+#define REGION_2G      0x0000001EU
+#define REGION_4G      0x0000001FU
+
+#define REGION_EN  0x00000001U
+
+
+
+#define SHAREABLE				0x00000004U 	/*shareable */
+#define STRONG_ORDERD_SHARED	0x00000000U	/*strongly ordered, always shareable*/
+
+#define DEVICE_SHARED			0x00000001U	/*device, shareable*/
+#define DEVICE_NONSHARED		0x00000010U	/*device, non shareable*/
+
+#define NORM_NSHARED_WT_NWA		0x00000002U 	/*Outer and Inner write-through, no write-allocate non-shareable*/
+#define NORM_SHARED_WT_NWA		0x00000006U 	/*Outer and Inner write-through, no write-allocate shareable*/
+
+#define NORM_NSHARED_WB_NWA 	0x00000003U 	/*Outer and Inner write-back, no write-allocate non shareable*/
+#define NORM_SHARED_WB_NWA 		0x00000007U 	/*Outer and Inner write-back, no write-allocate shareable*/
+
+#define NORM_NSHARED_NCACHE 	0x00000008U 	/*Outer and Inner Non cacheable  non shareable*/
+#define NORM_SHARED_NCACHE 		0x0000000CU 	/*Outer and Inner Non cacheable shareable*/
+
+#define NORM_NSHARED_WB_WA 		0x0000000BU 	/*Outer and Inner write-back non shared*/
+#define NORM_SHARED_WB_WA 		0x0000000FU 	/*Outer and Inner write-back shared*/
+
+/* inner and outer cache policies can be combined for different combinations */
+
+#define NORM_IN_POLICY_NCACHE	0x00000020U	/*inner non cacheable*/
+#define NORM_IN_POLICY_WB_WA	0x00000021U	/*inner write back write allocate*/
+#define NORM_IN_POLICY_WT_NWA	0x00000022U	/*inner write through no write allocate*/
+#define NORM_IN_POLICY_WB_NWA	0x00000023U	/*inner write back no write allocate*/
+
+#define NORM_OUT_POLICY_NCACHE	0x00000020U	/*outer non cacheable*/
+#define NORM_OUT_POLICY_WB_WA	0x00000028U	/*outer write back write allocate*/
+#define NORM_OUT_POLICY_WT_NWA	0x00000030U	/*outer write through no write allocate*/
+#define NORM_OUT_POLICY_WB_NWA	0x00000038U	/*outer write back no write allocate*/
+
+#define NO_ACCESS				(0x00000000U<<8U)	/*No access*/
+#define PRIV_RW_USER_NA			(0x00000001U<<8U) /*Privileged access only*/
+#define PRIV_RW_USER_RO			(0x00000002U<<8U) /*Writes in User mode generate permission faults*/
+#define	PRIV_RW_USER_RW			(0x00000003U<<8U)	/*Full Access*/
+#define PRIV_RO_USER_NA			(0x00000005U<<8U) /*Privileged eead only*/
+#define PRIV_RO_USER_RO			(0x00000006U<<8U) /*Privileged/User read-only*/
+
+#define EXECUTE_NEVER  			(0x00000001U<<12U)  /* Bit 12*/
+
+
+/* CP15 defines */
+
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MPU_TYPE			"p15, 0, %0,  c0,  c0, 4"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
+#define XREG_CP15_INST_FEATURE_5		"p15, 0, %0,  c0,  c2, 5"
+
+#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
+#define XREG_CP15_CONTROL_V_BIT			0x00002000U
+#define XREG_CP15_CONTROL_I_BIT			0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
+#define XREG_CP15_CONTROL_B_BIT			0x00000080U
+#define XREG_CP15_CONTROL_C_BIT			0x00000004U
+#define XREG_CP15_CONTROL_A_BIT			0x00000002U
+#define XREG_CP15_CONTROL_M_BIT			0x00000001U
+/* C2 Register Defines */
+/* Not Used */
+
+/* C3 Register Defines */
+/* Not Used */
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+
+#define XREG_CP15_MPU_REG_BASEADDR			"p15, 0, %0,  c6,  c1, 0"
+#define XREG_CP15_MPU_REG_SIZE_EN			"p15, 0, %0,  c6,  c1, 2"
+#define XREG_CP15_MPU_REG_ACCESS_CTRL		"p15, 0, %0,  c6,  c1, 4"
+
+#define XREG_CP15_MPU_MEMORY_REG_NUMBER			"p15, 0, %0,  c6,  c2, 0"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex R5.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE		"p15, 0, %0,  c7,  c5, 7"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+
+#define XREG_CP15_INVAL_DC_ALL		"p15, 0, %0,  c15, c5, 0"
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex R5.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+
+#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+
+/* C8 Register Defines */
+/* Not Used */
+
+
+/* C9 Register Defines */
+
+#define XREG_CP15_ATCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 1"
+#define XREG_CP15_BTCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 0"
+#define XREG_CP15_TCM_SELECTION				"p15, 0, %0,  c9, c2, 0"
+
+#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+
+/* C10 Register Defines */
+/* Not used */
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+/* Not used */
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_SEC_AUX_CTRL			"p15, 0, %0, c15,  c0, 0"
+
+
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2			c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24U)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0x000000FFU << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(0X00000001U << 23U)
+#define XREG_FPSID_ARCH_BIT		(16U)
+#define XREG_FPSID_ARCH_MASK		(0x0000000FU  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8U)
+#define XREG_FPSID_PART_MASK		(0x000000FFU << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4U)
+#define XREG_FPSID_VARIANT_MASK		(0x0000000FU  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0U)
+#define XREG_FPSID_REV_MASK		(0x0000000FU  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(0X00000001U << 31U)
+#define XREG_FPSCR_Z_BIT		(0X00000001U << 30U)
+#define XREG_FPSCR_C_BIT		(0X00000001U << 29U)
+#define XREG_FPSCR_V_BIT		(0X00000001U << 28U)
+#define XREG_FPSCR_QC			(0X00000001U << 27U)
+#define XREG_FPSCR_AHP			(0X00000001U << 26U)
+#define XREG_FPSCR_DEFAULT_NAN		(0X00000001U << 25U)
+#define XREG_FPSCR_FLUSHTOZERO		(0X00000001U << 24U)
+#define XREG_FPSCR_ROUND_NEAREST	(0X00000000U << 22U)
+#define XREG_FPSCR_ROUND_PLUSINF	(0X00000001U << 22U)
+#define XREG_FPSCR_ROUND_MINUSINF	(0X00000002U << 22U)
+#define XREG_FPSCR_ROUND_TOZERO		(0X00000003U << 22U)
+#define XREG_FPSCR_RMODE_BIT		(22U)
+#define XREG_FPSCR_RMODE_MASK		(0X00000003U << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20U)
+#define XREG_FPSCR_STRIDE_MASK		(0X00000003U << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16U)
+#define XREG_FPSCR_LENGTH_MASK		(0X00000007U << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(0X00000001U << 7U)
+#define XREG_FPSCR_IXC			(0X00000001U << 4U)
+#define XREG_FPSCR_UFC			(0X00000001U << 3U)
+#define XREG_FPSCR_OFC			(0X00000001U << 2U)
+#define XREG_FPSCR_DZC			(0X00000001U << 1U)
+#define XREG_FPSCR_IOC			(0X00000001U << 0U)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28U)
+#define XREG_MVFR0_RMODE_MASK		(0x0000000FU << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24U)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20U)
+#define XREG_MVFR0_SQRT_MASK		(0x0000000FU << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16U)
+#define XREG_MVFR0_DIVIDE_MASK		(0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(12U)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8U)
+#define XREG_MVFR0_DP_MASK		(0x0000000FU << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4U)
+#define XREG_MVFR0_SP_MASK		(0x0000000FU << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0U)
+#define XREG_MVFR0_A_SIMD_MASK		(0x0000000FU << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(0X00000001U << 31U)
+#define XREG_FPEXC_EN			(0X00000001U << 30U)
+#define XREG_FPEXC_DEX			(0X00000001U << 29U)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXR5_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h
new file mode 100644
index 000000000..4873e85eb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h
@@ -0,0 +1,432 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /* controller completed polling the
+						   device for status */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c
new file mode 100644
index 000000000..a9db4df7f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex R5 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp    08/29/14 First release
+* 5.04  pkp	   02/19/16 XTime_StartTimer API is added to configure TTC3 timer
+*						when present. XTime_GetTime is modified to give 64bit
+*						output using timer overflow when TTC3 present.
+*						XTime_SetTime is modified to configure TTC3 counter
+*						value when present.
+* 5.04	pkp	   03/11/16 XTime_StartTimer is modified to avoid enabling the
+*						overflow interrupt and XTime_GetTime & XTime_SetTime
+*						are modified to read and write TTC counter value
+*						respectively
+* 5.04	pkp
+* 6.0   mus    08/11/16  Removed implementation of XTime_SetTime API, since
+*                        TTC counter value register is read only.
+*
+* </pre>
+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xdebug.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+#define RST_LPD_IOU2 					0xFF5E0238U
+#define RST_LPD_IOU2_TTC3_RESET_MASK	0x00004000U
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/* Function definitions are applicable only when TTC3 is present*/
+#ifdef SLEEP_TIMER_BASEADDR
+/****************************************************************************
+*
+* Start the TTC timer.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In multiprocessor environment reference time will reset/lost for
+*		all processors, when this function called by any one processor.
+*
+****************************************************************************/
+void XTime_StartTimer(void)
+{
+	u32 LpdRst;
+	u32 TimerPrescalar;
+	u32 TimerCntrl;
+
+	LpdRst = Xil_In32(RST_LPD_IOU2);
+	if ((LpdRst & RST_LPD_IOU2_TTC3_RESET_MASK) != 0 ) {
+			LpdRst = LpdRst & (~RST_LPD_IOU2_TTC3_RESET_MASK);
+			Xil_Out32(RST_LPD_IOU2, LpdRst);
+
+	} else {
+		TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
+								SLEEP_TIMER_CNTR_CNTRL_OFFSET);
+		/* check if Timer is disabled */
+		if ((TimerCntrl & SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK) == 0) {
+			TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR +
+									SLEEP_TIMER_CLK_CNTRL_OFFSET);
+
+		/* check if Timer is configured with proper functionalty for sleep */
+			if ((TimerPrescalar & SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK) == 0)
+						return;
+		}
+	}
+	/* Disable the timer to configure */
+	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
+							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
+	TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK;
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
+				TimerCntrl);
+
+	/* Disable the prescalar */
+	TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR +
+								SLEEP_TIMER_CLK_CNTRL_OFFSET);
+	TimerPrescalar = TimerPrescalar & (~SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CLK_CNTRL_OFFSET,
+				TimerPrescalar);
+
+	/* Enable the Timer */
+	TimerCntrl = SLEEP_TIMER_COUNTER_CONTROL_RST_MASK &
+					(~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
+				TimerCntrl);
+
+}
+/****************************************************************************
+*
+* Set the time in the Timer Counter Register.
+*
+* @param	Value to be written to the Timer Counter Register.
+*
+* @return	None.
+*
+* @note		In multiprocessor environment reference time will reset/lost for
+*		all processors, when this function called by any one processor.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+/*Timer cannot be set to desired value, so the API is left unimplemented*/
+    xdbg_printf(XDBG_DEBUG_GENERAL,
+                "XTime_SetTime:Timer cannot be set to desired value,so API is not implemented\n");
+}
+
+/****************************************************************************
+*
+* Get the time from the Timer Counter Register.
+*
+* @param	Pointer to the location to be updated with the time.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+	*Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +
+								SLEEP_TIMER_CNTR_VAL_OFFSET);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h
new file mode 100644
index 000000000..36c416d5a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+* 5.04  pkp	   02/19/16 Added timer configuration register offset definitions
+* 5.04	pkp	   03/11/16 Removed definitions for overflow interrupt register
+*						and mask
+* </pre>
+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xparameters.h"
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Constant Definitions *****************************/
+
+#ifdef SLEEP_TIMER_BASEADDR
+
+#define COUNTS_PER_SECOND				SLEEP_TIMER_FREQUENCY
+#define COUNTS_PER_USECOND 				COUNTS_PER_SECOND/1000000
+
+/* Timer Register Offset*/
+#define SLEEP_TIMER_CLK_CNTRL_OFFSET 		0x00000000U
+#define SLEEP_TIMER_CNTR_CNTRL_OFFSET		0x0000000CU
+#define SLEEP_TIMER_CNTR_VAL_OFFSET			0x00000018U
+
+/*Timer register values*/
+#define SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK    0x00000001U
+#define SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK    0x00000001U
+#define SLEEP_TIMER_COUNTER_CONTROL_RST_MASK    0x00000010U
+#else
+#define ITERS_PER_SEC  (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4)
+#define ITERS_PER_USEC  (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000)
+#define IRQ_FIQ_MASK 	0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/* The following definitions are applicable only when TTC3 is present*/
+#ifdef SLEEP_TIMER_BASEADDR
+typedef u32 XTime;
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile
deleted file mode 100644
index b832910b8..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xsysmonpsu_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling sysmonpsu"
-
-xsysmonpsu_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xsysmonpsu_includes
-
-xsysmonpsu_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
deleted file mode 100644
index a30a257fb..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
+++ /dev/null
@@ -1,1749 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsysmonpsu.c
-*
-* Functions in this file are the minimum required functions for the XSysMonPsu
-* driver. See xsysmonpsu.h for a detailed description of the driver.
-*
-* @note 	None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	    Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.0   kvn    12/15/15 First release.
-*              02/15/16 Corrected Assert function call in
-*                       XSysMonPsu_GetMonitorStatus API.
-*              03/03/16 Added Temperature remote channel for Setsingle
-*                       channel API. Also corrected external mux channel
-*                       numbers.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xsysmonpsu.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-static void XSysMonPsu_StubHandler(void *CallBackRef);
-
-/************************** Variable Definitions ****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function initializes XSysMonPsu device/instance. This function
-* must be called prior to using the System Monitor device.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	ConfigPtr points to the XSysMonPsu device configuration structure.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. If the address translation is not used then the
-*		physical address is passed.
-*		Unexpected errors may occur if the address mapping is changed
-*		after this function is invoked.
-*
-* @return
-*		- XST_SUCCESS if successful.
-*
-* @note		The user needs to first call the XSysMonPsu_LookupConfig() API
-*		which returns the Configuration structure pointer which is
-*		passed as a parameter to the XSysMonPsu_CfgInitialize() API.
-*
-******************************************************************************/
-s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigPtr,
-			  u32 EffectiveAddr)
-{
-	u32 PsSysmonControlStatus;
-	u32 PlSysmonControlStatus;
-
-	/* Assert the input arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	/* Set the values read from the device config and the base address. */
-	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-
-
-	/* Set all handlers to stub values, let user configure this data later. */
-	InstancePtr->Handler = XSysMonPsu_StubHandler;
-
-	/* Reset the device such that it is in a known state. */
-	XSysMonPsu_Reset(InstancePtr);
-
-	PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
-
-	/* Check if the PS Sysmon is in Idle / ready state or not */
-	while(PsSysmonControlStatus != XSYSMONPSU_PS_SYSMON_READY) {
-		PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
-	}
-
-	PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-			XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
-
-	/* Check if the PL Sysmon is accessible to PS Sysmon or not */
-	while((PlSysmonControlStatus & XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK)
-				!= XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK) {
-		PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
-	}
-
-	/* Indicate the instance is now ready to use, initialized without error */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-	return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is a stub handler that is the default handler such that if the
-* application has not set the handler when interrupts are enabled, this
-* function will be called.
-*
-* @param	CallBackRef is unused by this function.
-* @param	Event is unused by this function.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void XSysMonPsu_StubHandler(void *CallBackRef)
-{
-	(void *) CallBackRef;
-
-	/* Assert occurs always since this is a stub and should never be called */
-	Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-*
-* This function resets the SystemMonitor
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-*
-* @return	None.
-*
-* @note		Upon reset, all Maximum and Minimum status registers will be
-*		reset to their default values. Currently running and any averaging
-*		will restart. Refer to the device data sheet for the device status and
-*		register values after the reset.
-*
-******************************************************************************/
-void XSysMonPsu_Reset(XSysMonPsu *InstancePtr)
-{
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	/* RESET the PS SYSMON */
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPS_BA_OFFSET +
-			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
-
-	/* RESET the PL SYSMON */
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET +
-			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the contents of the Status Register.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	A 32-bit value representing the contents of the Status Register.
-*		Use the XSYSMONPSU_MON_STS_* constants defined in xsysmonpsu_hw.h to
-*		interpret the returned value.
-*
-* @note		None.
-*****************************************************************************/
-u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 Status;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read the Sysmon Status Register and return the value. */
-	Status = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_MON_STS_OFFSET);
-
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function starts the ADC conversion in the Single Channel event driven
-* sampling mode. The EOC bit in Status Register will be set once the conversion
-* is finished. Refer to the device specification for more details.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-*
-* @return	None.
-*
-* @note		The default state of the CONVST bit is a logic 0. The conversion
-*		is started when the CONVST bit is set to 1 from 0.
-*		This bit is self-clearing so that the next conversion
-*		can be started by setting this bit.
-*
-*****************************************************************************/
-void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr)
-{
-	u32 ControlStatus;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Start the conversion by setting the CONVST bit to 1 only if auto-convst
-	 * bit is not enabled. This convst bit is self-clearing.
-	 */
-	ControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
-
-	if ((ControlStatus & XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK )
-			!= XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK) {
-		XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_PS_SYSMON_CSTS_OFFSET,
-					(ControlStatus | (u32)XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK));
-	}
-}
-
-/****************************************************************************/
-/**
-*
-* Get the ADC converted data for the specified channel.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Channel is the channel number. Use the XSM_CH_* defined in
-*		the file xsysmonpsu.h. The valid channels for PS / PL SysMon are 0 - 6,
-*		8 - 10 and 13 - 37. For AMS, 38 - 53 channels are valid.
-* @param	Block is the value that tells whether it is for PS Sysmon block
-*       or PL Sysmon block or the AMS controller register region.
-*
-* @return	A 16-bit value representing the ADC converted data for the
-*		specified channel. The System Monitor device guarantees
-* 		a 10 bit resolution for the ADC converted data and data is the
-*		10 MSB bits of the 16 data read from the device.
-*
-* @note		Please make sure that the proper channel number is passed.
-*
-*****************************************************************************/
-u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block)
-{
-	u16 AdcData;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
-			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
-			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
-			  ((Channel >= XSM_CH_SUPPLY4) &&
-			  (Channel <= XSM_CH_RESERVE1)));
-	Xil_AssertNonvoid((Block == XSYSMON_PS)||(Block == XSYSMON_PL)
-						||(Block == XSYSMON_AMS));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					Block);
-
-	/*
-	 * Read the selected ADC converted data for the specified channel
-	 * and return the value.
-	 */
-	if (Channel <= XSM_CH_AUX_MAX) {
-		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + ((u32)Channel << 2U)));
-	} else if ((Channel >= XSM_CH_SUPPLY7) && (Channel <= XSM_CH_TEMP_REMTE)){
-		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_ADC_CH_OFFSET +
-				(((u32)Channel - XSM_CH_SUPPLY7) << 2U)));
-	} else {
-		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_AMS_CH_OFFSET +
-				(((u32)Channel - XSM_CH_VCC_PSLL0) << 2U)));
-	}
-
-	return AdcData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the calibration coefficient data for the specified
-* parameter.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	CoeffType specifies the calibration coefficient
-*		to be read. Use XSM_CALIB_* constants defined in xsysmonpsu.h to
-*		specify the calibration coefficient to be read.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	A 16-bit value representing the calibration coefficient.
-*		The System Monitor device guarantees a 10 bit resolution for
-*		the ADC converted data and data is the 10 MSB bits of the 16
-*		data read from the device.
-*
-* @note		None.
-*
-*****************************************************************************/
-u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType,
-		u32 SysmonBlk)
-{
-	u16 CalibData;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(CoeffType <= XSM_CALIB_GAIN_ERROR_COEFF);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read the selected calibration coefficient. */
-	CalibData = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_CAL_SUP_OFF_OFFSET + ((u32)CoeffType << 2U));
-
-	return CalibData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the Minimum/Maximum measurement for one of the
-* XSM_MIN_* or XSM_MAX_* constants defined in xsysmonpsu.h
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	MeasurementType specifies the parameter for which the
-*		Minimum/Maximum measurement has to be read.
-*		Use XSM_MAX_* and XSM_MIN_* constants defined in xsysmonpsu.h to
-*		specify the data to be read.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	A 16-bit value representing the maximum/minimum measurement for
-*		specified parameter.
-*		The System Monitor device guarantees a 10 bit resolution for
-*		the ADC converted data and data is the 10 MSB bits of  16 bit
-*		data read from the device.
-*
-*****************************************************************************/
-u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
-		u32 SysmonBlk)
-{
-	u16 MinMaxData;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((MeasurementType <= XSM_MAX_SUPPLY6) ||
-			((MeasurementType >= XSM_MIN_SUPPLY4) &&
-			(MeasurementType <= XSM_MIN_SUPPLY6)) ||
-			((MeasurementType >= XSM_MAX_SUPPLY7) &&
-			(MeasurementType <= XSM_MAX_TEMP_REMOTE)) ||
-			((MeasurementType >= XSM_MIN_SUPPLY7) &&
-			(MeasurementType <= XSM_MIN_TEMP_REMOTE)));
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read and return the specified Minimum/Maximum measurement. */
-	MinMaxData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress +
-							XSM_MIN_MAX_CH_OFFSET + ((u32)MeasurementType << 2U)));
-
-	return MinMaxData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of samples of averaging that is to be done for
-* all the channels in both the single channel mode and sequence mode of
-* operations.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Average is the number of samples of averaging programmed to the
-*		Configuration Register 0. Use the XSM_AVG_* definitions defined
-*		in xsysmonpsu.h file :
-*		- XSM_AVG_0_SAMPLES for no averaging
-*		- XSM_AVG_16_SAMPLES for 16 samples of averaging
-*		- XSM_AVG_64_SAMPLES for 64 samples of averaging
-*		- XSM_AVG_256_SAMPLES for 256 samples of averaging
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XSysMonPsu_SetAvg(XSysMonPsu *InstancePtr, u8 Average, u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Average <= XSM_AVG_256_SAMPLES);
-	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Write the averaging value into the Configuration Register 0. */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET)
-						& (u32)(~XSYSMONPSU_CFG_REG0_AVRGNG_MASK);
-	RegValue |= (((u32) Average << XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT));
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
-			 RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the number of samples of averaging configured for all
-* the channels in the Configuration Register 0.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	The averaging read from the Configuration Register 0 is
-*		returned. Use the XSM_AVG_* bit definitions defined in xsysmonpsu.h
-*		file to interpret the returned value :
-*		- XSM_AVG_0_SAMPLES means no averaging
-*		- XSM_AVG_16_SAMPLES means 16 samples of averaging
-*		- XSM_AVG_64_SAMPLES means 64 samples of averaging
-*		- XSM_AVG_256_SAMPLES means 256 samples of averaging
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XSysMonPsu_GetAvg(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 Average;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read the averaging value from the Configuration Register 0. */
-	Average = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-				XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
-
-	return (u8)(Average >> XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the given parameters in the Configuration Register 0 in
-* the single channel mode.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Channel is the channel number for conversion. The valid
-*		channels are 0 - 6, 8 - 10, 13 - 37.
-* @param	IncreaseAcqCycles is a boolean parameter which specifies whether
-*		the Acquisition time for the external channels has to be
-*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
-*		default 4 ADCCLK cycles (specify FALSE). This parameter is
-*		only valid for the external channels.
-* @param	IsEventMode is a boolean parameter that specifies continuous
-*		sampling (specify FALSE) or event driven sampling mode (specify
-*		TRUE) for the given channel.
-* @param	IsDifferentialMode is a boolean parameter which specifies
-*		unipolar(specify FALSE) or differential mode (specify TRUE) for
-*		the analog inputs. The 	input mode is only valid for the
-*		external channels.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return
-*		- XST_SUCCESS if the given values were written successfully to
-*		the Configuration Register 0.
-*		- XST_FAILURE if the channel sequencer is enabled or the input
-*		parameters are not valid for the selected channel.
-*
-* @note
-*		- The number of samples for the averaging for all the channels
-*		is set by using the function XSysMonPsu_SetAvg.
-*		- The calibration of the device is done by doing a ADC
-*		conversion on the calibration channel(channel 8). The input
-*		parameters IncreaseAcqCycles, IsDifferentialMode and
-*		IsEventMode are not valid for this channel.
-*
-*****************************************************************************/
-s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
-				u32 IncreaseAcqCycles, u32 IsEventMode,
-				u32 IsDifferentialMode, u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-	s32 Status;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
-			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
-			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
-			  ((Channel >= XSM_CH_SUPPLY4) &&
-			  (Channel <= XSM_CH_TEMP_REMTE)));
-	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
-			  (IncreaseAcqCycles == FALSE));
-	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
-	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
-			  (IsDifferentialMode == FALSE));
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Check if the device is in single channel mode else return failure */
-	if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
-				!= XSM_SEQ_MODE_SINGCHAN)) {
-		Status = (s32)XST_FAILURE;
-		goto End;
-	}
-
-	/* Read the Configuration Register 0 and extract out Averaging value. */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
-
-	/*
-	 * Select the number of acquisition cycles. The acquisition cycles is
-	 * only valid for the external channels.
-	 */
-	if (IncreaseAcqCycles == TRUE) {
-		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
-		    || (Channel == XSM_CH_VPVN)) {
-			RegValue |= XSYSMONPSU_CFG_REG0_ACQ_MASK;
-		} else {
-			Status = (s32)XST_FAILURE;
-			goto End;
-		}
-	}
-
-	/*
-	 * Select the input mode. The input mode is only valid for the
-	 * external channels.
-	 */
-	if (IsDifferentialMode == TRUE) {
-
-		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
-		    || (Channel == XSM_CH_VPVN)) {
-			RegValue |= XSYSMONPSU_CFG_REG0_BU_MASK;
-		} else {
-			Status = (s32)XST_FAILURE;
-			goto End;
-		}
-	}
-
-	/* Select the ADC mode. */
-	if (IsEventMode == TRUE) {
-		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
-	}
-
-	/* Write the given values into the Configuration Register 0. */
-	RegValue |= ((u32)Channel & XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
-			 RegValue);
-
-	Status = (s32)XST_SUCCESS;
-
-End:
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the alarm outputs for the specified alarms in the
-* Configuration Registers 1:
-*
-*		- OT for Over Temperature (XSYSMONPSU_CFR_REG1_ALRM_OT_MASK)
-*		- ALM0 for On board Temperature (XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK)
-*		- ALM1 for SUPPLY1 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY1_MASK)
-*		- ALM2 for SUPPLY2 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY2_MASK)
-* 		- ALM3 for SUPPLY3 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY3_MASK)
-* 		- ALM4 for SUPPLY4 (XSYSMONPSU_CFR_REG1_ALRM__SUPPLY4_MASK)
-*		- ALM5 for SUPPLY5 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY5_MASK)
-* 		- ALM6 for SUPPLY6 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY6_MASK)
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
-*		in the Configuration Register 1.
-*		Bit positions of 1 will be enabled. Bit positions of 0 will be
-*		disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
-*		masks defined in xsysmonpsu.h.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	None.
-*
-* @note		The implementation of the alarm enables in the Configuration
-*		register 1 is such that the alarms for bit positions of 0 will
-*		be enabled and alarms for bit positions of 1 will be disabled.
-*		The alarm outputs specified by the AlmEnableMask are negated
-*		before writing to the Configuration Register 1 because it
-*		was Disable register bits.
-*
-*****************************************************************************/
-void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
-		u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(AlmEnableMask <= XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
-	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG1_OFFSET);
-	RegValue &= (u32)(~XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
-	RegValue |= (~AlmEnableMask & (u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
-
-	/*
-	 * Enable/disables the alarm enables for the specified alarm bits in the
-	 * Configuration Register 1.
-	 */
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
-			 RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of the alarm output enables in the
-* Configuration Register 1.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	This is the bit-mask of the enabled alarm outputs in the
-*		Configuration Register 1. Use the masks XSYSMONPSU_CFG_REG1_ALRM_*_MASK
-*		masks defined in xsysmonpsu.h to interpret the returned value.
-*
-*		Bit positions of 1 indicate that the alarm output is enabled.
-*		Bit positions of 0 indicate that the alarm output is disabled.
-*
-*
-* @note		The implementation of the alarm enables in the Configuration
-*		register 1 is such that alarms for the bit positions of 1 will
-*		be disabled and alarms for bit positions of 0 will be enabled.
-*		The enabled alarm outputs returned by this function is the
-*		negated value of the the data read from the Configuration
-*		Register 1.
-*
-*****************************************************************************/
-u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Read the status of alarm output enables from the Configuration
-	 * Register 1.
-	 */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK;
-	RegValue = (~RegValue & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
-
-	return RegValue;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the specified Channel Sequencer Mode in the Configuration
-* Register 1 :
-*		- Default safe mode (XSM_SEQ_MODE_SAFE)
-*		- One pass through sequence (XSM_SEQ_MODE_ONEPASS)
-*		- Continuous channel sequencing (XSM_SEQ_MODE_CONTINPASS)
-*		- Single Channel/Sequencer off (XSM_SEQ_MODE_SINGCHAN)
-*		- Olympus sampling mode (XSM_SEQ_MODE_OYLMPUS)
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SequencerMode is the sequencer mode to be set.
-*		Use XSM_SEQ_MODE_* bits defined in xsysmonpsu.h.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	None.
-*
-* @note		Only one of the modes can be enabled at a time.
-*
-*****************************************************************************/
-void XSysMonPsu_SetSequencerMode(XSysMonPsu *InstancePtr, u8 SequencerMode,
-		u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((SequencerMode <= XSM_SEQ_MODE_SINGCHAN) ||
-			(SequencerMode == XSM_SEQ_MODE_OYLMPUS));
-	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Set the specified sequencer mode in the Configuration Register 1. */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG1_OFFSET);
-	RegValue &= (u32)(~ XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
-	RegValue |= (((u32)SequencerMode  << XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT) &
-					XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
-	XSysmonPsu_WriteReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG1_OFFSET, RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel sequencer mode from the Configuration
-* Register 1.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	The channel sequencer mode :
-*		- XSM_SEQ_MODE_SAFE : Default safe mode
-*		- XSM_SEQ_MODE_ONEPASS : One pass through sequence
-*		- XSM_SEQ_MODE_CONTINPASS : Continuous channel sequencing
-*		- XSM_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
-*		- XSM_SEQ_MODE_OLYMPUS : Olympus sampling mode
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XSysMonPsu_GetSequencerMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u8 SequencerMode;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read the channel sequencer mode from the Configuration Register 1. */
-	SequencerMode =  ((u8) ((XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK) >>
-			XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT));
-
-	return SequencerMode;
-}
-
-/****************************************************************************/
-/**
-*
-* The function enables the Event mode or Continuous mode in the sequencer mode.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	IsEventMode is a boolean parameter that specifies continuous
-*		sampling (specify FALSE) or event driven sampling mode (specify
-*		TRUE) for the channel.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XSysMonPsu_SetSequencerEvent(XSysMonPsu *InstancePtr, u32 IsEventMode,
-		u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
-	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read the Configuration Register 0. */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG0_OFFSET);
-
-	/* Set the ADC mode. */
-	if (IsEventMode == TRUE) {
-		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
-	} else {
-		RegValue &= (u32)(~XSYSMONPSU_CFG_REG0_EC_MASK);
-	}
-
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
-			 RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* The function returns the mode of the sequencer.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	Returns the Sequencer mode. XSYSMONPSU_EVENT_MODE for Event mode
-* 		and XSYSMONPSU_CONTINUOUS_MODE for continuous mode.
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XSysMonPsu_GetSequencerEvent(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	s32 Mode;
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read the Configuration Register 0. */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG0_OFFSET);
-
-	RegValue &= XSYSMONPSU_CFG_REG0_EC_MASK;
-
-	if (RegValue == XSYSMONPSU_CFG_REG0_EC_MASK) {
-		Mode = XSYSMONPSU_EVENT_MODE;
-	} else {
-		Mode = XSYSMONPSU_CONTINUOUS_MODE;
-	}
-
-	return Mode;
-}
-
-/****************************************************************************/
-/**
-*
-* The function enables the external mux and connects a channel to the mux.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Channel is the channel number used to connect to the external
-*		Mux. The valid channels are 0 to 5 and 16 to 31.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return
-*		- XST_SUCCESS if the given values were written successfully to
-*		the Configuration Register 0.
-*		- XST_FAILURE if the channel sequencer is enabled or the input
-*		parameters are not valid for the selected channel.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((Channel <= XSM_CH_VREFN) ||
-			  ((Channel >= XSM_CH_AUX_MIN) &&
-			  (Channel <= XSM_CH_AUX_MAX)));
-	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Read the Configuration Register 0 and the clear the channel selection
-	 * bits.
-	 */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG0_OFFSET);
-	RegValue &= ~(XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
-
-	/* Enable the External Mux and select the channel. */
-	RegValue |= (XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK | (u32)Channel);
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
-			 RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* The function returns the external mux channel.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	Returns the channel number used to connect to the external
-*		Mux. The valid channels are 0 to 6, 8 to 16, and 31 to 36..
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Read the Configuration Register 0 and derive the channel selection
-	 * bits.
-	 */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG0_OFFSET);
-	RegValue &= XSYSMONPSU_CFG_REG0_MUX_CH_MASK;
-
-	return RegValue;
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the frequency of the ADCCLK by configuring the DCLK to
-* ADCCLK ratio in the Configuration Register #2.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
-*		Valid values of the divisor are
-*		PS:
-*		 - 0 means divide by 8.
-*		 - 1,2 means divide by 2.
-*		 - 3 to 255 means divide by that value.
-*       PL:
-*		 - 0,1,2 means divide by 2.
-*		 - 3 to 255 means divide by that value.
-*		Refer to the device specification for more details.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	None.
-*
-* @note		- The ADCCLK is an internal clock used by the ADC and is
-*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-*		divided by the user selection in the Configuration Register 2.
-*		- There is no Assert on the minimum value of the Divisor.
-*
-*****************************************************************************/
-void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor,
-            u32 SysmonBlk)
-{
-	u32 RegValue;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Read the Configuration Register 2 and the clear the clock divisor
-	 * bits.
-	 */
-	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_CFG_REG2_OFFSET);
-	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);
-
-	/* Write the divisor value into the Configuration Register 2. */
-	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
-					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
-			 RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function gets the ADCCLK divisor from the Configuration Register 2.
-*
-* @param	InstancePtr is a pointer to the XSysMon instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	The divisor read from the Configuration Register 2.
-*
-* @note		The ADCCLK is an internal clock used by the ADC and is
-*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-*		divided by the user selection in the Configuration Register 2.
-*
-*****************************************************************************/
-u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u16 Divisor;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Read the divisor value from the Configuration Register 2. */
-	Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
-							XSYSMONPSU_CFG_REG2_OFFSET);
-
-	return (u8) (Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified channels in the ADC Channel Selection
-* Sequencer Registers. The sequencer must be in the Safe Mode before writing
-* to these registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	ChEnableMask is the bit mask of all the channels to be enabled.
-*		Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
-*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
-*		be disabled.
-*		The ChEnableMask is a 32 bit mask that is written to the two
-*		16 bit ADC Channel Selection Sequencer Registers.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return
-*		- XST_SUCCESS if the given values were written successfully to
-*		the ADC Channel Selection Sequencer Registers.
-*		- XST_FAILURE if the channel sequencer is enabled.
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
-		u32 SysmonBlk)
-{
-	s32 Status;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/*
-	 * The sequencer must be in the Default Safe Mode before writing
-	 * to these registers. Return XST_FAILURE if the channel sequencer
-	 * is enabled.
-	 */
-	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk) != XSM_SEQ_MODE_SAFE)) {
-		Status = (s32)XST_FAILURE;
-		goto End;
-	}
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Enable the specified channels in the ADC Channel Selection Sequencer
-	 * Registers.
-	 */
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET,
-			 (ChEnableMask & XSYSMONPSU_SEQ_CH0_VALID_MASK));
-
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET,
-			 (ChEnableMask >> XSM_SEQ_CH_SHIFT) &
-			 XSYSMONPSU_SEQ_CH1_VALID_MASK);
-
-	Status = (s32)XST_SUCCESS;
-
-End:
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel enable bits status from the ADC Channel
-* Selection Sequencer Registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	Gets the channel enable bits. Use XSYSMONPSU_SEQ_CH* defined in
-*		xsysmonpsu_hw.h to interpret the Channel numbers. Bit masks of 1
-*		are the channels that are enabled and bit mask of 0 are
-*		the channels that are disabled.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 RegVal;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Read the channel enable bits for all the channels from the ADC
-	 * Channel Selection Register.
-	 */
-	RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_CH0_OFFSET) & XSYSMONPSU_SEQ_CH0_VALID_MASK;
-	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
-					XSM_SEQ_CH_SHIFT;
-
-	return RegVal;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the averaging for the specified channels in the ADC
-* Channel Averaging Enable Sequencer Registers. The sequencer must be in
-* the Safe Mode before writing to these registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	AvgEnableChMask is the bit mask of all the channels for which
-*		averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
-*		xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
-*		enabled for bit masks of 1 and disabled for bit mask of 0.
-*		The AvgEnableChMask is a 32 bit mask that is written to the
-*		two 16 bit ADC Channel Averaging Enable Sequencer Registers.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return
-*		- XST_SUCCESS if the given values were written successfully to
-*		the ADC Channel Averaging Enables Sequencer Registers.
-*		- XST_FAILURE if the channel sequencer is enabled.
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
-		u32 SysmonBlk)
-{
-	s32 Status;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * The sequencer must be disabled for writing any of these registers.
-	 * Return XST_FAILURE if the channel sequencer is enabled.
-	 */
-	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
-	                                     != XSM_SEQ_MODE_SAFE)) {
-		Status = (s32)XST_FAILURE;
-		goto End;
-	}
-
-	/*
-	 * Enable/disable the averaging for the specified channels in the
-	 * ADC Channel Averaging Enables Sequencer Registers.
-	 */
-	XSysmonPsu_WriteReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
-			(AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
-
-	XSysmonPsu_WriteReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
-			 (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
-			 XSYSMONPSU_SEQ_AVERAGE1_MASK);
-
-	Status = (s32)XST_SUCCESS;
-End:
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the channels for which the averaging has been enabled
-* in the ADC Channel Averaging Enables Sequencer Registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @returns 	The status of averaging (enabled/disabled) for all the channels.
-*		Use XSYSMONPSU_SEQ_AVERAGE* defined in xsysmonpsu_hw.h to interpret the
-*		Channel numbers. Bit masks of 1 are the channels for which
-*		averaging is enabled and bit mask of 0 are the channels for
-*		averaging is disabled.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 RegVal;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Read the averaging enable status for all the channels from the
-	 * ADC Channel Averaging Enables Sequencer Registers.
-	 */
-	RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_AVERAGE0_OFFSET) & XSYSMONPSU_SEQ_AVERAGE0_MASK;
-	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_AVERAGE1_OFFSET) & XSYSMONPSU_SEQ_AVERAGE1_MASK) <<
-			XSM_SEQ_CH_SHIFT;
-
-	return RegVal;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Analog input mode for the specified channels in the
-* ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be in
-* the Safe Mode before writing to these registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	InputModeChMask is the bit mask of all the channels for which
-*		the input mode is differential mode. Use XSYSMONPSU_SEQ_INPUT_MDE*
-*		defined in xsysmonpsu_hw.h to specify the channel numbers. Differential
-*		or  Bipolar input mode will be set for bit masks of 1 and unipolar input
-*		mode for bit masks of 0.
-*		The InputModeChMask is a 32 bit mask that is written to the two
-*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return
-*		- XST_SUCCESS if the given values were written successfully to
-*		the ADC Channel Analog-Input Mode Sequencer Registers.
-*		- XST_FAILURE if the channel sequencer is enabled.
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
-		u32 SysmonBlk)
-{
-	s32 Status;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/*
-	 * The sequencer must be in the Safe Mode before writing to
-	 * these registers. Return XST_FAILURE if the channel sequencer
-	 * is enabled.
-	 */
-	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
-	                                      != XSM_SEQ_MODE_SAFE)) {
-		Status = (s32)XST_FAILURE;
-		goto End;
-	}
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Set the input mode for the specified channels in the ADC Channel
-	 * Analog-Input Mode Sequencer Registers.
-	 */
-	XSysmonPsu_WriteReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET,
-			 (InputModeChMask & XSYSMONPSU_SEQ_INPUT_MDE0_MASK));
-
-	XSysmonPsu_WriteReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET,
-			 (InputModeChMask >> XSM_SEQ_CH_SHIFT) &
-			 XSYSMONPSU_SEQ_INPUT_MDE1_MASK);
-
-	Status = (s32)XST_SUCCESS;
-
-End:
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Analog input mode for all the channels from
-* the ADC Channel Analog-Input Mode Sequencer Registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @returns 	The input mode for all the channels.
-*		Use XSYSMONPSU_SEQ_INPUT_MDE* defined in xsysmonpsu_hw.h to interpret the
-*		Channel numbers. Bit masks of 1 are the channels for which
-*		input mode is differential/Bipolar and bit mask of 0 are the channels
-*		for which input mode is unipolar.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 InputMode;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 *  Get the input mode for all the channels from the ADC Channel
-	 * Analog-Input Mode Sequencer Registers.
-	 */
-	InputMode = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE0_MASK;
-	InputMode |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE1_MASK) <<
-				XSM_SEQ_CH_SHIFT;
-
-	return InputMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of Acquisition cycles in the ADC Channel
-* Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
-* before writing to these registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	AcqCyclesChMask is the bit mask of all the channels for which
-*		the number of acquisition cycles is to be extended.
-*		Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to specify the Channel
-*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
-*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
-*		bit masks of 0.
-*		The AcqCyclesChMask is a 32 bit mask that is written to the two
-*		16 bit ADC Channel Acquisition Time Sequencer Registers.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return
-*		- XST_SUCCESS if the given values were written successfully to
-*		the Channel Sequencer Registers.
-*		- XST_FAILURE if the channel sequencer is enabled.
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
-		u32 SysmonBlk)
-{
-	s32 Status;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/*
-	 * The sequencer must be in the Safe Mode before writing
-	 * to these registers. Return XST_FAILURE if the channel
-	 * sequencer is enabled.
-	 */
-	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
-	                                     != XSM_SEQ_MODE_SAFE)) {
-		Status = (s32)XST_FAILURE;
-		goto End;
-	}
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Set the Acquisition time for the specified channels in the
-	 * ADC Channel Acquisition Time Sequencer Registers.
-	 */
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ0_OFFSET,
-			 (AcqCyclesChMask & XSYSMONPSU_SEQ_ACQ0_MASK));
-
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
-			 (AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) & XSYSMONPSU_SEQ_ACQ1_MASK);
-
-	Status = (s32)XST_SUCCESS;
-
-End:
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of acquisition time from the ADC Channel Acquisition
-* Time Sequencer Registers.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @returns 	The acquisition time for all the channels.
-*		Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to interpret the
-*		Channel numbers. Bit masks of 1 are the channels for which
-*		acquisition cycles are extended and bit mask of 0 are the
-*		channels for which acquisition cycles are not extended.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
-{
-	u32 RegValAcq;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Get the Acquisition cycles for the specified channels from the ADC
-	 * Channel Acquisition Time Sequencer Registers.
-	 */
-	RegValAcq = XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_SEQ_ACQ0_OFFSET) & XSYSMONPSU_SEQ_ACQ0_MASK;
-	RegValAcq |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
-					XSYSMONPSU_SEQ_ACQ1_OFFSET) & XSYSMONPSU_SEQ_ACQ1_MASK) <<
-					XSM_SEQ_CH_SHIFT;
-
-	return RegValAcq;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the contents of the given Alarm Threshold Register.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	AlarmThrReg is the index of an Alarm Threshold Register to
-*		be set. Use XSM_ATR_* constants defined in xsysmonpsu.h to
-*		specify the index.
-* @param	Value is the 16-bit threshold value to write into the register.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
-		u16 Value, u32 SysmonBlk)
-{
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
-			((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
-			(AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
-	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/* Write the value into the specified Alarm Threshold Register. */
-	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_ALRM_TEMP_UPR_OFFSET +
-			((u32)AlarmThrReg << 2U), Value);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the specified Alarm Threshold Register.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	AlarmThrReg is the index of an Alarm Threshold Register
-*		to be read. Use XSM_ATR_* constants defined in xsysmonpsu.h
-*		to specify the index.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
-*       block or PL Sysmon block register region.
-*
-* @return	A 16-bit value representing the contents of the selected Alarm
-*		Threshold Register.
-*
-* @note		None.
-*
-*****************************************************************************/
-u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
-		u32 SysmonBlk)
-{
-	u16 AlarmThreshold;
-	u32 EffectiveBaseAddress;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
-			((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
-			(AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
-	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
-
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
-	/*
-	 * Read the specified Alarm Threshold Register and return
-	 * the value.
-	 */
-	AlarmThreshold = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
-			XSYSMONPSU_ALRM_TEMP_UPR_OFFSET + ((u32)AlarmThrReg << 2));
-
-	return AlarmThreshold;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the conversion to be automatic for PS SysMon.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-*
-* @return	None
-*
-* @note		In the auto-trigger mode, sample rate is of 1 Million samples.
-*
-*****************************************************************************/
-void XSysMonPsu_SetPSAutoConversion(XSysMonPsu *InstancePtr)
-{
-	u32 PSSysMonStatusReg;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Set the automatic conversion triggering in PS control register. */
-	PSSysMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
-	PSSysMonStatusReg |= XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK;
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
-			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET, PSSysMonStatusReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the AMS monitor status.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-*
-* @return	Returns the monitor status. See XSYSMONPSU_MON_STS_*_MASK
-* 		definations present in xsysmonpsu_hw.h for knowing the status.
-*
-* @note		None
-* .
-*****************************************************************************/
-u32 XSysMonPsu_GetMonitorStatus(XSysMonPsu *InstancePtr)
-{
-	u32 AMSMonStatusReg;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read the AMS monitor status. This gives tells about JTAG Locked / ADC
-	 * busy / ADC Current Channel number and its ADC output.
-	 */
-	AMSMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-			XSYSMONPSU_MON_STS_OFFSET);
-
-	return AMSMonStatusReg;
-}
-
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
deleted file mode 100644
index ae55db9ce..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xsysmonpsu.h
-*
-* The XSysMon driver supports the Xilinx System Monitor device.
-*
-* The System Monitor device has the following features:
-*	- PL Sysmon instance has 10-bit, 200-KSPS (kilo samples per second)
-*		Analog-to-Digital Converter (ADC)
-*	- PS Sysmon instance has 10-bit, 1000-KSPS ADC.
-*	- Monitoring of on-chip supply voltages and temperature
-*	- 1 dedicated differential analog-input pair and
-*	  16 auxiliary differential analog-input pairs
-*	- Automatic alarms based on user defined limits for the on-chip
-*	  supply voltages and temperature
-*	- Automatic Channel Sequencer, programmable averaging, programmable
-*	  acquisition time for the external inputs, unipolar or differential
-*	  input selection for the external inputs
-*	- Inbuilt Calibration
-*	- Optional interrupt request generation
-*	- External Mux
-*
-*
-* The user should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the System Monitor device.
-*
-*
-* <b> System Monitor Channel Sequencer Modes </b>
-*
-* The  System Monitor Channel Sequencer supports the following operating modes:
-*
-*   - <b> Default </b>: This is the default mode after power up.
-*		In this mode of operation the System Monitor operates in
-*		a sequence mode, monitoring the on chip sensors:
-*		Temperature, VCCINT, and VCCAUX.
-*   - <b> One pass through sequence </b>: In this mode the System Monitor
-*		converts the channels enabled in the Sequencer Channel Enable
-*		registers for a single pass and then stops.
-*   - <b> Continuous cycling of sequence </b>: In this mode the System Monitor
-*		converts the channels enabled in the Sequencer Channel Enable
-*		registers continuously.
-*   - <b> Single channel mode</b>: In this mode the System Monitor Channel
-*		Sequencer is disabled and the System Monitor operates in a
-*		Single Channel Mode.
-*		The System Monitor can operate either in a Continuous or Event
-*		driven sampling mode in the single channel mode.
-*
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the System Monitor device.
-*
-* XSysMonPsu_CfgInitialize() API is used to initialize the System Monitor
-* device. The user needs to first call the XSysMonPsu_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XSysMonPsu_CfgInitialize() API.
-*
-*
-* <b>Interrupts</b>
-*
-* The System Monitor device supports interrupt driven mode and the default
-* operation mode is polling mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* device in interrupt mode.
-*
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* <b> Building the driver </b>
-*
-* The XSysMonPsu driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-* <b> Limitations of the driver </b>
-*
-* System Monitor device can be accessed through the JTAG port and the AXI
-* interface. The driver implementation does not support the simultaneous access
-* of the device by both these interfaces. The user has to take care of this
-* situation in the user application code.
-*
-*
-*
-* <br><br>
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    12/15/15 First release
-*              02/15/16 Corrected Assert function call in
-*                       XSysMonPsu_GetMonitorStatus API.
-*              03/03/16 Added Temperature remote channel for Setsingle
-*                       channel API. Also corrected external mux channel
-*                       numbers.
-*
-* </pre>
-*
-******************************************************************************/
-
-
-#ifndef XSYSMONPSU_H_			/* prevent circular inclusions */
-#define XSYSMONPSU_H_			/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xsysmonpsu_hw.h"
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XSM_CH_TEMP 		0x0U  /**< On Chip Temperature */
-#define XSM_CH_SUPPLY1		0x1U  /**< SUPPLY1 VCC_PSINTLP */
-#define XSM_CH_SUPPLY2		0x2U  /**< SUPPLY2 VCC_PSINTFP */
-#define XSM_CH_VPVN 		0x3U  /**< VP/VN Dedicated analog inputs */
-#define XSM_CH_VREFP		0x4U  /**< VREFP */
-#define XSM_CH_VREFN		0x5U  /**< VREFN */
-#define XSM_CH_SUPPLY3		0x6U  /**< SUPPLY3 VCC_PSAUX */
-#define XSM_CH_SUPPLY_CALIB	0x08U /**< Supply Calib Data Reg */
-#define XSM_CH_ADC_CALIB	0x09U /**< ADC Offset Channel Reg */
-#define XSM_CH_GAINERR_CALIB 	0x0AU /**< Gain Error Channel Reg  */
-#define XSM_CH_SUPPLY4		0x0DU /**< SUPPLY4 VCC_PSDDR_504 */
-#define XSM_CH_SUPPLY5		0x0EU /**< SUPPLY5 VCC_PSIO3_503 */
-#define XSM_CH_SUPPLY6		0x0FU /**< SUPPLY6 VCC_PSIO0_500 */
-#define XSM_CH_AUX_MIN		16U   /**< Channel number for 1st Aux Channel */
-#define XSM_CH_AUX_MAX		31U   /**< Channel number for Last Aux channel */
-#define XSM_CH_SUPPLY7      32U   /**< SUPPLY7 VCC_PSIO1_501 */
-#define XSM_CH_SUPPLY8      33U   /**< SUPPLY8 VCC_PSIO2_502 */
-#define XSM_CH_SUPPLY9      34U   /**< SUPPLY9 PS_MGTRAVCC */
-#define XSM_CH_SUPPLY10     35U   /**< SUPPLY10 PS_MGTRAVTT */
-#define XSM_CH_VCCAMS       36U   /**< VCCAMS */
-#define XSM_CH_TEMP_REMTE   37U   /**< Temperature Remote */
-#define XSM_CH_VCC_PSLL0    38U   /**< VCC_PSLL0 */
-#define XSM_CH_VCC_PSLL1    39U   /**< VCC_PSLL1 */
-#define XSM_CH_VCC_PSLL2    40U   /**< VCC_PSLL2 */
-#define XSM_CH_VCC_PSLL3    41U   /**< VCC_PSLL3 */
-#define XSM_CH_VCC_PSLL4    42U   /**< VCC_PSLL4 */
-#define XSM_CH_VCC_PSBATT   43U   /**< VCC_PSBATT */
-#define XSM_CH_VCCINT       44U   /**< VCCINT */
-#define XSM_CH_VCCBRAM      45U   /**< VCCBRAM */
-#define XSM_CH_VCCAUX       46U   /**< VCCAUX */
-#define XSM_CH_VCC_PSDDRPLL 47U   /**< VCC_PSDDRPLL */
-#define XSM_CH_DDRPHY_VREF  48U   /**< DDRPHY_VREF */
-#define XSM_CH_DDRPHY_AT0   49U   /**< DDRPHY_AT0 */
-#define XSM_CH_PSGT_AT0     50U   /**< PSGT_AT0 */
-#define XSM_CH_PSGT_AT1     51U   /**< PSGT_AT0 */
-#define XSM_CH_RESERVE0     52U   /**< PSGT_AT0 */
-#define XSM_CH_RESERVE1     53U   /**< PSGT_AT0 */
-
-/*@}*/
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XSM_CALIB_SUPPLY_OFFSET_COEFF 0U /**< Supply Offset Calib Coefficient */
-#define XSM_CALIB_ADC_OFFSET_COEFF    1U /**< ADC Offset Calib Coefficient */
-#define XSM_CALIB_GAIN_ERROR_COEFF    2U /**< Gain Error Calib Coefficient*/
-
-/*@}*/
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XSM_MAX_TEMP		0U    /**< Maximum Temperature Data */
-#define XSM_MAX_SUPPLY1		1U    /**< Maximum SUPPLY1 Data */
-#define XSM_MAX_SUPPLY2		2U    /**< Maximum SUPPLY2 Data */
-#define XSM_MAX_SUPPLY3		3U    /**< Maximum SUPPLY3 Data */
-#define XSM_MIN_TEMP		4U    /**< Minimum Temperature Data */
-#define XSM_MIN_SUPPLY1		5U    /**< Minimum SUPPLY1 Data */
-#define XSM_MIN_SUPPLY2     6U    /**< Minimum SUPPLY2 Data */
-#define XSM_MIN_SUPPLY3     7U    /**< Minimum SUPPLY3 Data */
-#define XSM_MAX_SUPPLY4		8U    /**< Maximum SUPPLY4 Data */
-#define XSM_MAX_SUPPLY5		9U    /**< Maximum SUPPLY5 Data */
-#define XSM_MAX_SUPPLY6		0xAU  /**< Maximum SUPPLY6 Data */
-#define XSM_MIN_SUPPLY4     0xCU  /**< Minimum SUPPLY4 Data */
-#define XSM_MIN_SUPPLY5     0xDU  /**< Minimum SUPPLY5 Data */
-#define XSM_MIN_SUPPLY6     0xEU  /**< Minimum SUPPLY6 Data */
-#define XSM_MAX_SUPPLY7		0x80U  /**< Maximum SUPPLY7 Data */
-#define XSM_MAX_SUPPLY8		0x81U  /**< Maximum SUPPLY8 Data */
-#define XSM_MAX_SUPPLY9		0x82U  /**< Maximum SUPPLY9 Data */
-#define XSM_MAX_SUPPLY10	0x83U  /**< Maximum SUPPLY10 Data */
-#define XSM_MAX_VCCAMS  	0x84U  /**< Maximum VCCAMS Data */
-#define XSM_MAX_TEMP_REMOTE  	0x85U  /**< Maximum Remote Temperature Data */
-#define XSM_MIN_SUPPLY7     0x88U  /**< Minimum SUPPLY7 Data */
-#define XSM_MIN_SUPPLY8     0x89U  /**< Minimum SUPPLY8 Data */
-#define XSM_MIN_SUPPLY9     0x8AU  /**< Minimum SUPPLY9 Data */
-#define XSM_MIN_SUPPLY10    0x8BU  /**< Minimum SUPPLY10 Data */
-#define XSM_MIN_VCCAMS      0x8CU  /**< Minimum VCCAMS Data */
-#define XSM_MIN_TEMP_REMOTE     0x8DU  /**< Minimum Remote Temperature Data */
-
-/*@}*/
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XSM_AVG_0_SAMPLES	0U /**< No Averaging */
-#define XSM_AVG_16_SAMPLES	1U /**< Average 16 samples */
-#define XSM_AVG_64_SAMPLES	2U /**< Average 64 samples */
-#define XSM_AVG_256_SAMPLES	3U /**< Average 256 samples */
-
-/*@}*/
-
-/**
- * @name Channel Sequencer Modes of operation.
- * @{
- */
-#define XSM_SEQ_MODE_SAFE	 0U /**< Default Safe Mode */
-#define XSM_SEQ_MODE_ONEPASS	 1U /**< Onepass through Sequencer */
-#define XSM_SEQ_MODE_CONTINPASS	 2U /**< Continuous Cycling Seqquencer */
-#define XSM_SEQ_MODE_SINGCHAN	 3U /**< Single channel - No Sequencing */
-#define XSM_SEQ_MODE_OYLMPUS	 6U /**< Olympus mode */
-
-/*@}*/
-
-/**
- * @name Clock Divisor values range.
- * @{
- */
-#define XSM_CLK_DIV_MIN	 0U /**< Minimum Clock Divisor value */
-#define XSM_CLK_DIV_MAX	 255U /**< Maximum Clock Divisor value */
-
-/*@}*/
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XSM_ATR_TEMP_UPPER	 0U   /**< High user Temperature limit */
-#define XSM_ATR_SUP1_UPPER	 1U   /**< Supply1 high voltage limit */
-#define XSM_ATR_SUP2_UPPER	 2U   /**< Supply2 high voltage limit */
-#define XSM_ATR_OT_UPPER	 3U   /**< Upper Over Temperature limit */
-#define XSM_ATR_TEMP_LOWER	 4U   /**< Low user Temperature */
-#define XSM_ATR_SUP1_LOWER	 5U   /**< Suuply1 low voltage limit */
-#define XSM_ATR_SUP2_LOWER	 6U   /**< Supply2 low voltage limit */
-#define XSM_ATR_OT_LOWER	 7U   /**< Lower Over Temperature limit */
-#define XSM_ATR_SUP3_UPPER	 8U   /**< Supply3 high voltage limit */
-#define XSM_ATR_SUP4_UPPER 	 9U   /**< Supply4 high voltage limit */
-#define XSM_ATR_SUP5_UPPER 	 0xAU /**< Supply5 high voltage limit */
-#define XSM_ATR_SUP6_UPPER 	 0xBU /**< Supply6 high voltage limit */
-#define XSM_ATR_SUP3_LOWER	 0xCU /**< Supply3 low voltage limit */
-#define XSM_ATR_SUP4_LOWER 	 0xDU /**< Supply4 low voltage limit */
-#define XSM_ATR_SUP5_LOWER 	 0xEU /**< Supply5 low voltage limit */
-#define XSM_ATR_SUP6_LOWER 	 0xFU /**< Supply6 low voltage limit */
-#define XSM_ATR_SUP7_UPPER	 0x10U /**< Supply7 high voltage limit */
-#define XSM_ATR_SUP8_UPPER	 0x11U /**< Supply8 high voltage limit */
-#define XSM_ATR_SUP9_UPPER	 0x12U /**< Supply9 high voltage limit */
-#define XSM_ATR_SUP10_UPPER	 0x13U /**< Supply10 high voltage limit */
-#define XSM_ATR_VCCAMS_UPPER	 0x14U /**< VCCAMS high voltage limit */
-#define XSM_ATR_TEMP_RMTE_UPPER	 0x15U /**< High remote Temperature limit */
-#define XSM_ATR_SUP7_LOWER	 0x18U /**< Supply7 low voltage limit */
-#define XSM_ATR_SUP8_LOWER	 0x19U /**< Supply8 low voltage limit */
-#define XSM_ATR_SUP9_LOWER	 0x1AU /**< Supply9 low voltage limit */
-#define XSM_ATR_SUP10_LOWER	 0x1BU /**< Supply10 low voltage limit */
-#define XSM_ATR_VCCAMS_LOWER	 0x1CU /**< VCCAMS low voltage limit */
-#define XSM_ATR_TEMP_RMTE_LOWER	 0x1DU /**< Low remote Temperature limit */
-
-/*@}*/
-
-/**
- * @name Alarm masks for channels in Configuration registers 1
- * @{
- */
-#define XSM_CFR_ALM_SUPPLY6_MASK	0x0800 /**< Alarm 6 - SUPPLY6 */
-#define XSM_CFR_ALM_SUPPLY5_MASK	0x0400 /**< Alarm 5 - SUPPLY5 */
-#define XSM_CFR_ALM_SUPPLY4_MASK	0x0200 /**< Alarm 4 - SUPPLY4 */
-#define XSM_CFR_ALM_SUPPLY3_MASK 	0x0100 /**< Alarm 3 - SUPPLY3 */
-#define XSM_CFR_ALM_SUPPLY2_MASK	0x0008 /**< Alarm 2 - SUPPLY2 */
-#define XSM_CFR_ALM_SUPPLY1_MASK	0x0004 /**< Alarm 1 - SUPPLY1 */
-#define XSM_CFR_ALM_TEMP_MASK		0x0002 /**< Alarm 0 - Temperature */
-#define XSM_CFR_ALM_OT_MASK		0x0001 /**< Over Temperature Alarm */
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the handler, and is passed back to the upper layer
- *		when the handler is called. It is used to find the device driver
- *		instance.
- *
- ******************************************************************************/
-typedef void (*XSysMonPsu_Handler) (void *CallBackRef);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID of device */
-	u32 BaseAddress;		/**< Register base address */
-} XSysMonPsu_Config;
-
-/**
- * The XSysmonPsu driver instance data. The user is required to allocate a
- * variable of this type for the SYSMON device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XSysMonPsu_Config Config; 	/**< Device configuration */
-	u32 IsReady;				/**< Device is initialized and ready */
-	XSysMonPsu_Handler Handler;
-	void *CallBackRef;			/**< Callback reference for event handler */
-} XSysMonPsu;
-
-/* BaseAddress Offsets */
-#define XSYSMON_PS 1U
-#define XSYSMON_PL 2U
-#define XSYSMON_AMS 3U
-#define XPS_BA_OFFSET   0x00000800U
-#define XPL_BA_OFFSET   0x00000C00U
-#define XSM_ADC_CH_OFFSET 0x00000200U
-#define XSM_AMS_CH_OFFSET 0x00000060U
-#define XSM_MIN_MAX_CH_OFFSET 0x00000080U
-
-/************************* Variable Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro converts System Monitor Raw Data to Temperature(centigrades)
-* for On-Chip Sensors.
-*
-* @param	AdcData is the SysMon Raw ADC Data.
-*
-* @return 	The Temperature in centigrades.
-*
-* @note		C-Style signature:
-*		float XSysMon_RawToTemperature_OnChip(u32 AdcData)
-*
-*****************************************************************************/
-#define XSysMonPsu_RawToTemperature_OnChip(AdcData)				\
-	((((float)(AdcData)/65536.0f)/0.00199451786f ) - 273.6777f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts System Monitor Raw Data to Temperature(centigrades)
-* for external reference.
-*
-* @param	AdcData is the SysMon Raw ADC Data.
-*
-* @return 	The Temperature in centigrades.
-*
-* @note		C-Style signature:
-*		float XSysMon_RawToTemperature_ExternalRef(u32 AdcData)
-*
-*****************************************************************************/
-#define XSysMonPsu_RawToTemperature_ExternalRef(AdcData)			\
-	((((float)(AdcData)/65536.0f)/0.00198842814f ) - 273.8195f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts System Monitor Raw Data to Voltage(volts).
-*
-* @param	AdcData is the System Monitor ADC Raw Data.
-*
-* @return 	The Voltage in volts.
-*
-* @note		C-Style signature:
-*		float XSysMon_RawToVoltage(u32 AdcData)
-*
-*****************************************************************************/
-#define XSysMonPsu_RawToVoltage(AdcData) 					\
-	((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to System Monitor Raw Data
-* for On-Chip Sensors.
-*
-* @param	Temperature is the Temperature in centigrades to be
-*		converted to System Monitor ADC Raw Data.
-*
-* @return 	The System Monitor ADC Raw Data.
-*
-* @note		C-Style signature:
-*		int XSysMon_TemperatureToRaw_OnChip(float Temperature)
-*
-*****************************************************************************/
-#define XSysMonPsu_TemperatureToRaw_OnChip(Temperature)				\
-	((int)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to System Monitor Raw Data
-* for external reference.
-*
-* @param	Temperature is the Temperature in centigrades to be
-*		converted to System Monitor ADC Raw Data.
-*
-* @return 	The System Monitor ADC Raw Data.
-*
-* @note		C-Style signature:
-*		int XSysMon_TemperatureToRaw_ExternalRef(float Temperature)
-*
-*****************************************************************************/
-#define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature)		\
-	((int)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to System Monitor Raw Data.
-*
-* @param	Voltage is the Voltage in volts to be converted to
-*		System Monitor/ADC Raw Data.
-*
-* @return 	The System Monitor ADC Raw Data.
-*
-* @note		C-Style signature:
-*		int XSysMon_VoltageToRaw(float Voltage)
-*
-*****************************************************************************/
-#define XSysMonPsu_VoltageToRaw(Voltage)			 		\
-	((s32)((Voltage)*65536.0f/3.0f))
-
-/****************************************************************************/
-/**
-*
-* This static inline macro calculates the effective baseaddress based on the
-* Sysmon instance. For PS Sysmon, use additional offset XPS_BA_OFFSET and For
-* PL Sysmon, use additional offset XPL_BA_OFFSET.
-*
-* @param	BaseAddress is the starting address of the SysMon block in
-* 		register database.
-* @param	SysmonBlk is the value that tells whether it is for PS Sysmon block
-*       or PL Sysmon block or the AMS controller register region.
-*
-* @return 	Returns the effective baseaddress of the sysmon instance.
-*
-*****************************************************************************/
-static inline u32 XSysMonPsu_GetEffBaseAddress(u32 BaseAddress, u32 SysmonBlk)
-	{
-		u32 EffBaseAddr;
-
-		if (SysmonBlk == XSYSMON_PS) {
-			EffBaseAddr = BaseAddress + XPS_BA_OFFSET;
-		} else if(SysmonBlk == XSYSMON_PL) {
-			EffBaseAddr = BaseAddress + XPL_BA_OFFSET;
-		} else {
-			EffBaseAddr = BaseAddress;
-		}
-
-		return EffBaseAddr;
-	}
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xsysmonpsu.c */
-s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigPtr,
-			  u32 EffectiveAddr);
-void XSysMonPsu_Reset(XSysMonPsu *InstancePtr);
-void XSysMonPsu_Reset_FromLPD(XSysMonPsu *InstancePtr);
-u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr);
-u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
-u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType, u32 SysmonBlk);
-u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
-		u32 SysmonBlk);
-void XSysMonPsu_SetAvg(XSysMonPsu *InstancePtr, u8 Average, u32 SysmonBlk);
-u8 XSysMonPsu_GetAvg(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
-				u32 IncreaseAcqCycles, u32 IsEventMode,
-				u32 IsDifferentialMode, u32 SysmonBlk);
-void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
-		u32 SysmonBlk);
-u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-void XSysMonPsu_SetSequencerMode(XSysMonPsu *InstancePtr, u8 SequencerMode,
-		u32 SysmonBlk);
-u8 XSysMonPsu_GetSequencerMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-void XSysMonPsu_SetSequencerEvent(XSysMonPsu *InstancePtr, u32 IsEventMode,
-		u32 SysmonBlk);
-s32 XSysMonPsu_GetSequencerEvent(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
-u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk);
-u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
-		u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
-		u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
-		u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
-		u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
-		u16 Value, u32 SysmonBlk);
-u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
-		u32 SysmonBlk);
-void XSysMonPsu_SetPSAutoConversion(XSysMonPsu *InstancePtr);
-u32 XSysMonPsu_GetMonitorStatus(XSysMonPsu *InstancePtr);
-
-/* interrupt functions in xsysmonpsu_intr.c */
-void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask);
-void XSysMonPsu_IntrDisable(XSysMonPsu *InstancePtr, u64 Mask);
-u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr);
-u64 XSysMonPsu_IntrGetStatus(XSysMonPsu *InstancePtr);
-void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask);
-
-/* Functions in xsysmonpsu_selftest.c */
-s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr);
-
-/* Functions in xsysmonpsu_sinit.c */
-XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId);
-
-
-#endif /* XSYSMONPSU_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
deleted file mode 100644
index ace39e369..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xsysmonpsu.h"
-
-/*
-* The configuration table for devices
-*/
-
-XSysMonPsu_Config XSysMonPsu_ConfigTable[] =
-{
-	{
-		XPAR_PSU_AMS_DEVICE_ID,
-		XPAR_PSU_AMS_BASEADDR
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
deleted file mode 100644
index 3012bf327..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
+++ /dev/null
@@ -1,2268 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsysmonpsu_hw.h
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xsysmonpsu.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.0   kvn	  12/15/15 First release
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSYSMONPSU_HW_H__
-#define XSYSMONPSU_HW_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/**
- * XSysmonPsu Base Address
- */
-#define XSYSMONPSU_BASEADDR      0xFFA50000U
-
-/**
- * Register: XSysmonPsuMisc
- */
-#define XSYSMONPSU_MISC_OFFSET   0x00000000U
-#define XSYSMONPSU_MISC_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MISC_SLVERR_EN_DRP_SHIFT   1U
-#define XSYSMONPSU_MISC_SLVERR_EN_DRP_WIDTH   1U
-#define XSYSMONPSU_MISC_SLVERR_EN_DRP_MASK    0x00000002U
-
-#define XSYSMONPSU_MISC_SLVERR_EN_SHIFT   0U
-#define XSYSMONPSU_MISC_SLVERR_EN_WIDTH   1U
-#define XSYSMONPSU_MISC_SLVERR_EN_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuIsr0
- */
-#define XSYSMONPSU_ISR_0_OFFSET   0x00000010U
-#define XSYSMONPSU_ISR_0_MASK	  0xffffffffU
-#define XSYSMONPSU_ISR_0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_15_SHIFT   31U
-#define XSYSMONPSU_ISR_0_PL_ALM_15_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_15_MASK    0x80000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_14_SHIFT   30U
-#define XSYSMONPSU_ISR_0_PL_ALM_14_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_14_MASK    0x40000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_13_SHIFT   29U
-#define XSYSMONPSU_ISR_0_PL_ALM_13_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_13_MASK    0x20000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_12_SHIFT   28U
-#define XSYSMONPSU_ISR_0_PL_ALM_12_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_12_MASK    0x10000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_11_SHIFT   27U
-#define XSYSMONPSU_ISR_0_PL_ALM_11_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_11_MASK    0x08000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_10_SHIFT   26U
-#define XSYSMONPSU_ISR_0_PL_ALM_10_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_10_MASK    0x04000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_9_SHIFT   25U
-#define XSYSMONPSU_ISR_0_PL_ALM_9_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_9_MASK    0x02000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_8_SHIFT   24U
-#define XSYSMONPSU_ISR_0_PL_ALM_8_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_8_MASK    0x01000000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_7_SHIFT   23U
-#define XSYSMONPSU_ISR_0_PL_ALM_7_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_7_MASK    0x00800000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_6_SHIFT   22U
-#define XSYSMONPSU_ISR_0_PL_ALM_6_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_6_MASK    0x00400000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_5_SHIFT   21U
-#define XSYSMONPSU_ISR_0_PL_ALM_5_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_5_MASK    0x00200000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_4_SHIFT   20U
-#define XSYSMONPSU_ISR_0_PL_ALM_4_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_4_MASK    0x00100000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_3_SHIFT   19U
-#define XSYSMONPSU_ISR_0_PL_ALM_3_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_3_MASK    0x00080000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_2_SHIFT   18U
-#define XSYSMONPSU_ISR_0_PL_ALM_2_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_2_MASK    0x00040000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_1_SHIFT   17U
-#define XSYSMONPSU_ISR_0_PL_ALM_1_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_1_MASK    0x00020000U
-
-#define XSYSMONPSU_ISR_0_PL_ALM_0_SHIFT   16U
-#define XSYSMONPSU_ISR_0_PL_ALM_0_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PL_ALM_0_MASK    0x00010000U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_15_SHIFT   15U
-#define XSYSMONPSU_ISR_0_PS_ALM_15_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_15_MASK    0x00008000U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_14_SHIFT   14U
-#define XSYSMONPSU_ISR_0_PS_ALM_14_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_14_MASK    0x00004000U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_13_SHIFT   13U
-#define XSYSMONPSU_ISR_0_PS_ALM_13_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_13_MASK    0x00002000U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_12_SHIFT   12U
-#define XSYSMONPSU_ISR_0_PS_ALM_12_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_12_MASK    0x00001000U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_11_SHIFT   11U
-#define XSYSMONPSU_ISR_0_PS_ALM_11_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_11_MASK    0x00000800U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_10_SHIFT   10U
-#define XSYSMONPSU_ISR_0_PS_ALM_10_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_10_MASK    0x00000400U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_9_SHIFT   9U
-#define XSYSMONPSU_ISR_0_PS_ALM_9_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_9_MASK    0x00000200U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_8_SHIFT   8U
-#define XSYSMONPSU_ISR_0_PS_ALM_8_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_8_MASK    0x00000100U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_7_SHIFT   7U
-#define XSYSMONPSU_ISR_0_PS_ALM_7_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_7_MASK    0x00000080U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_6_SHIFT   6U
-#define XSYSMONPSU_ISR_0_PS_ALM_6_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_6_MASK    0x00000040U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_5_SHIFT   5U
-#define XSYSMONPSU_ISR_0_PS_ALM_5_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_5_MASK    0x00000020U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_4_SHIFT   4U
-#define XSYSMONPSU_ISR_0_PS_ALM_4_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_4_MASK    0x00000010U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_3_SHIFT   3U
-#define XSYSMONPSU_ISR_0_PS_ALM_3_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_3_MASK    0x00000008U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_2_SHIFT   2U
-#define XSYSMONPSU_ISR_0_PS_ALM_2_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_2_MASK    0x00000004U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_1_SHIFT   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_1_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_1_MASK    0x00000002U
-
-#define XSYSMONPSU_ISR_0_PS_ALM_0_SHIFT   0U
-#define XSYSMONPSU_ISR_0_PS_ALM_0_WIDTH   1U
-#define XSYSMONPSU_ISR_0_PS_ALM_0_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuIsr1
- */
-#define XSYSMONPSU_ISR_1_OFFSET   0x00000014U
-#define XSYSMONPSU_ISR_1_MASK	  0xe000001fU
-#define XSYSMONPSU_ISR_1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_SHIFT   31U
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_WIDTH   1U
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_MASK    0x80000000U
-
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
-
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
-#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
-
-#define XSYSMONPSU_ISR_1_EOS_SHIFT   4U
-#define XSYSMONPSU_ISR_1_EOS_WIDTH   1U
-#define XSYSMONPSU_ISR_1_EOS_MASK    0x00000010U
-
-#define XSYSMONPSU_ISR_1_EOC_SHIFT   3U
-#define XSYSMONPSU_ISR_1_EOC_WIDTH   1U
-#define XSYSMONPSU_ISR_1_EOC_MASK    0x00000008U
-
-#define XSYSMONPSU_ISR_1_PL_OT_SHIFT   2U
-#define XSYSMONPSU_ISR_1_PL_OT_WIDTH   1U
-#define XSYSMONPSU_ISR_1_PL_OT_MASK    0x00000004U
-
-#define XSYSMONPSU_ISR_1_PS_LPD_OT_SHIFT   1U
-#define XSYSMONPSU_ISR_1_PS_LPD_OT_WIDTH   1U
-#define XSYSMONPSU_ISR_1_PS_LPD_OT_MASK    0x00000002U
-
-#define XSYSMONPSU_ISR_1_PS_FPD_OT_SHIFT   0U
-#define XSYSMONPSU_ISR_1_PS_FPD_OT_WIDTH   1U
-#define XSYSMONPSU_ISR_1_PS_FPD_OT_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuImr0
- */
-#define XSYSMONPSU_IMR_0_OFFSET   0x00000018U
-#define XSYSMONPSU_IMR_0_RSTVAL   0xffffffffU
-
-#define XSYSMONPSU_IMR_0_PL_ALM_15_SHIFT   31U
-#define XSYSMONPSU_IMR_0_PL_ALM_15_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_15_MASK    0x80000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_14_SHIFT   30U
-#define XSYSMONPSU_IMR_0_PL_ALM_14_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_14_MASK    0x40000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_13_SHIFT   29U
-#define XSYSMONPSU_IMR_0_PL_ALM_13_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_13_MASK    0x20000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_12_SHIFT   28U
-#define XSYSMONPSU_IMR_0_PL_ALM_12_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_12_MASK    0x10000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_11_SHIFT   27U
-#define XSYSMONPSU_IMR_0_PL_ALM_11_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_11_MASK    0x08000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_10_SHIFT   26U
-#define XSYSMONPSU_IMR_0_PL_ALM_10_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_10_MASK    0x04000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_9_SHIFT   25U
-#define XSYSMONPSU_IMR_0_PL_ALM_9_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_9_MASK    0x02000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_8_SHIFT   24U
-#define XSYSMONPSU_IMR_0_PL_ALM_8_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_8_MASK    0x01000000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_7_SHIFT   23U
-#define XSYSMONPSU_IMR_0_PL_ALM_7_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_7_MASK    0x00800000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_6_SHIFT   22U
-#define XSYSMONPSU_IMR_0_PL_ALM_6_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_6_MASK    0x00400000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_5_SHIFT   21U
-#define XSYSMONPSU_IMR_0_PL_ALM_5_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_5_MASK    0x00200000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_4_SHIFT   20U
-#define XSYSMONPSU_IMR_0_PL_ALM_4_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_4_MASK    0x00100000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_3_SHIFT   19U
-#define XSYSMONPSU_IMR_0_PL_ALM_3_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_3_MASK    0x00080000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_2_SHIFT   18U
-#define XSYSMONPSU_IMR_0_PL_ALM_2_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_2_MASK    0x00040000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_1_SHIFT   17U
-#define XSYSMONPSU_IMR_0_PL_ALM_1_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_1_MASK    0x00020000U
-
-#define XSYSMONPSU_IMR_0_PL_ALM_0_SHIFT   16U
-#define XSYSMONPSU_IMR_0_PL_ALM_0_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PL_ALM_0_MASK    0x00010000U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_15_SHIFT   15U
-#define XSYSMONPSU_IMR_0_PS_ALM_15_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_15_MASK    0x00008000U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_14_SHIFT   14U
-#define XSYSMONPSU_IMR_0_PS_ALM_14_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_14_MASK    0x00004000U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_13_SHIFT   13U
-#define XSYSMONPSU_IMR_0_PS_ALM_13_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_13_MASK    0x00002000U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_12_SHIFT   12U
-#define XSYSMONPSU_IMR_0_PS_ALM_12_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_12_MASK    0x00001000U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_11_SHIFT   11U
-#define XSYSMONPSU_IMR_0_PS_ALM_11_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_11_MASK    0x00000800U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_10_SHIFT   10U
-#define XSYSMONPSU_IMR_0_PS_ALM_10_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_10_MASK    0x00000400U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_9_SHIFT   9U
-#define XSYSMONPSU_IMR_0_PS_ALM_9_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_9_MASK    0x00000200U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_8_SHIFT   8U
-#define XSYSMONPSU_IMR_0_PS_ALM_8_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_8_MASK    0x00000100U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_7_SHIFT   7U
-#define XSYSMONPSU_IMR_0_PS_ALM_7_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_7_MASK    0x00000080U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_6_SHIFT   6U
-#define XSYSMONPSU_IMR_0_PS_ALM_6_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_6_MASK    0x00000040U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_5_SHIFT   5U
-#define XSYSMONPSU_IMR_0_PS_ALM_5_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_5_MASK    0x00000020U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_4_SHIFT   4U
-#define XSYSMONPSU_IMR_0_PS_ALM_4_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_4_MASK    0x00000010U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_3_SHIFT   3U
-#define XSYSMONPSU_IMR_0_PS_ALM_3_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_3_MASK    0x00000008U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_2_SHIFT   2U
-#define XSYSMONPSU_IMR_0_PS_ALM_2_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_2_MASK    0x00000004U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_1_SHIFT   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_1_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_1_MASK    0x00000002U
-
-#define XSYSMONPSU_IMR_0_PS_ALM_0_SHIFT   0U
-#define XSYSMONPSU_IMR_0_PS_ALM_0_WIDTH   1U
-#define XSYSMONPSU_IMR_0_PS_ALM_0_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuImr1
- */
-#define XSYSMONPSU_IMR_1_OFFSET   0x0000001CU
-#define XSYSMONPSU_IMR_1_RSTVAL   0xe000001fU
-
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_SHIFT   31U
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_WIDTH   1U
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_MASK    0x80000000U
-
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
-
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
-#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
-
-#define XSYSMONPSU_IMR_1_EOS_SHIFT   4U
-#define XSYSMONPSU_IMR_1_EOS_WIDTH   1U
-#define XSYSMONPSU_IMR_1_EOS_MASK    0x00000010U
-
-#define XSYSMONPSU_IMR_1_EOC_SHIFT   3U
-#define XSYSMONPSU_IMR_1_EOC_WIDTH   1U
-#define XSYSMONPSU_IMR_1_EOC_MASK    0x00000008U
-
-#define XSYSMONPSU_IMR_1_PL_OT_SHIFT   2U
-#define XSYSMONPSU_IMR_1_PL_OT_WIDTH   1U
-#define XSYSMONPSU_IMR_1_PL_OT_MASK    0x00000004U
-
-#define XSYSMONPSU_IMR_1_PS_LPD_OT_SHIFT   1U
-#define XSYSMONPSU_IMR_1_PS_LPD_OT_WIDTH   1U
-#define XSYSMONPSU_IMR_1_PS_LPD_OT_MASK    0x00000002U
-
-#define XSYSMONPSU_IMR_1_PS_FPD_OT_SHIFT   0U
-#define XSYSMONPSU_IMR_1_PS_FPD_OT_WIDTH   1U
-#define XSYSMONPSU_IMR_1_PS_FPD_OT_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuIer0
- */
-#define XSYSMONPSU_IER_0_OFFSET   0x00000020U
-#define XSYSMONPSU_IXR_0_MASK     0xFFFFFFFFU
-#define XSYSMONPSU_IER_0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_15_SHIFT   31U
-#define XSYSMONPSU_IER_0_PL_ALM_15_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_15_MASK    0x80000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_14_SHIFT   30U
-#define XSYSMONPSU_IER_0_PL_ALM_14_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_14_MASK    0x40000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_13_SHIFT   29U
-#define XSYSMONPSU_IER_0_PL_ALM_13_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_13_MASK    0x20000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_12_SHIFT   28U
-#define XSYSMONPSU_IER_0_PL_ALM_12_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_12_MASK    0x10000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_11_SHIFT   27U
-#define XSYSMONPSU_IER_0_PL_ALM_11_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_11_MASK    0x08000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_10_SHIFT   26U
-#define XSYSMONPSU_IER_0_PL_ALM_10_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_10_MASK    0x04000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_9_SHIFT   25U
-#define XSYSMONPSU_IER_0_PL_ALM_9_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_9_MASK    0x02000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_8_SHIFT   24U
-#define XSYSMONPSU_IER_0_PL_ALM_8_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_8_MASK    0x01000000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_7_SHIFT   23U
-#define XSYSMONPSU_IER_0_PL_ALM_7_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_7_MASK    0x00800000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_6_SHIFT   22U
-#define XSYSMONPSU_IER_0_PL_ALM_6_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_6_MASK    0x00400000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_5_SHIFT   21U
-#define XSYSMONPSU_IER_0_PL_ALM_5_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_5_MASK    0x00200000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_4_SHIFT   20U
-#define XSYSMONPSU_IER_0_PL_ALM_4_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_4_MASK    0x00100000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_3_SHIFT   19U
-#define XSYSMONPSU_IER_0_PL_ALM_3_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_3_MASK    0x00080000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_2_SHIFT   18U
-#define XSYSMONPSU_IER_0_PL_ALM_2_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_2_MASK    0x00040000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_1_SHIFT   17U
-#define XSYSMONPSU_IER_0_PL_ALM_1_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_1_MASK    0x00020000U
-
-#define XSYSMONPSU_IER_0_PL_ALM_0_SHIFT   16U
-#define XSYSMONPSU_IER_0_PL_ALM_0_WIDTH   1U
-#define XSYSMONPSU_IER_0_PL_ALM_0_MASK    0x00010000U
-
-#define XSYSMONPSU_IER_0_PS_ALM_15_SHIFT   15U
-#define XSYSMONPSU_IER_0_PS_ALM_15_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_15_MASK    0x00008000U
-
-#define XSYSMONPSU_IER_0_PS_ALM_14_SHIFT   14U
-#define XSYSMONPSU_IER_0_PS_ALM_14_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_14_MASK    0x00004000U
-
-#define XSYSMONPSU_IER_0_PS_ALM_13_SHIFT   13U
-#define XSYSMONPSU_IER_0_PS_ALM_13_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_13_MASK    0x00002000U
-
-#define XSYSMONPSU_IER_0_PS_ALM_12_SHIFT   12U
-#define XSYSMONPSU_IER_0_PS_ALM_12_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_12_MASK    0x00001000U
-
-#define XSYSMONPSU_IER_0_PS_ALM_11_SHIFT   11U
-#define XSYSMONPSU_IER_0_PS_ALM_11_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_11_MASK    0x00000800U
-
-#define XSYSMONPSU_IER_0_PS_ALM_10_SHIFT   10U
-#define XSYSMONPSU_IER_0_PS_ALM_10_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_10_MASK    0x00000400U
-
-#define XSYSMONPSU_IER_0_PS_ALM_9_SHIFT   9U
-#define XSYSMONPSU_IER_0_PS_ALM_9_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_9_MASK    0x00000200U
-
-#define XSYSMONPSU_IER_0_PS_ALM_8_SHIFT   8U
-#define XSYSMONPSU_IER_0_PS_ALM_8_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_8_MASK    0x00000100U
-
-#define XSYSMONPSU_IER_0_PS_ALM_7_SHIFT   7U
-#define XSYSMONPSU_IER_0_PS_ALM_7_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_7_MASK    0x00000080U
-
-#define XSYSMONPSU_IER_0_PS_ALM_6_SHIFT   6U
-#define XSYSMONPSU_IER_0_PS_ALM_6_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_6_MASK    0x00000040U
-
-#define XSYSMONPSU_IER_0_PS_ALM_5_SHIFT   5U
-#define XSYSMONPSU_IER_0_PS_ALM_5_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_5_MASK    0x00000020U
-
-#define XSYSMONPSU_IER_0_PS_ALM_4_SHIFT   4U
-#define XSYSMONPSU_IER_0_PS_ALM_4_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_4_MASK    0x00000010U
-
-#define XSYSMONPSU_IER_0_PS_ALM_3_SHIFT   3U
-#define XSYSMONPSU_IER_0_PS_ALM_3_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_3_MASK    0x00000008U
-
-#define XSYSMONPSU_IER_0_PS_ALM_2_SHIFT   2U
-#define XSYSMONPSU_IER_0_PS_ALM_2_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_2_MASK    0x00000004U
-
-#define XSYSMONPSU_IER_0_PS_ALM_1_SHIFT   1U
-#define XSYSMONPSU_IER_0_PS_ALM_1_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_1_MASK    0x00000002U
-
-#define XSYSMONPSU_IER_0_PS_ALM_0_SHIFT   0U
-#define XSYSMONPSU_IER_0_PS_ALM_0_WIDTH   1U
-#define XSYSMONPSU_IER_0_PS_ALM_0_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuIer1
- */
-#define XSYSMONPSU_IER_1_OFFSET   0x00000024U
-#define XSYSMONPSU_IXR_1_MASK     0xE000001FU
-#define XSYSMONPSU_IER_1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_SHIFT   31U
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_WIDTH   1U
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_MASK    0x80000000U
-
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
-
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
-#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
-
-#define XSYSMONPSU_IER_1_EOS_SHIFT   4U
-#define XSYSMONPSU_IER_1_EOS_WIDTH   1U
-#define XSYSMONPSU_IER_1_EOS_MASK    0x00000010U
-
-#define XSYSMONPSU_IER_1_EOC_SHIFT   3U
-#define XSYSMONPSU_IER_1_EOC_WIDTH   1U
-#define XSYSMONPSU_IER_1_EOC_MASK    0x00000008U
-
-#define XSYSMONPSU_IER_1_PL_OT_SHIFT   2U
-#define XSYSMONPSU_IER_1_PL_OT_WIDTH   1U
-#define XSYSMONPSU_IER_1_PL_OT_MASK    0x00000004U
-
-#define XSYSMONPSU_IER_1_PS_LPD_OT_SHIFT   1U
-#define XSYSMONPSU_IER_1_PS_LPD_OT_WIDTH   1U
-#define XSYSMONPSU_IER_1_PS_LPD_OT_MASK    0x00000002U
-
-#define XSYSMONPSU_IER_1_PS_FPD_OT_SHIFT   0U
-#define XSYSMONPSU_IER_1_PS_FPD_OT_WIDTH   1U
-#define XSYSMONPSU_IER_1_PS_FPD_OT_MASK    0x00000001U
-
-#define XSYSMONPSU_IXR_1_SHIFT  32U
-
-/**
- * Register: XSysmonPsuIdr0
- */
-#define XSYSMONPSU_IDR_0_OFFSET   0x00000028U
-#define XSYSMONPSU_IDR_0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_15_SHIFT   31U
-#define XSYSMONPSU_IDR_0_PL_ALM_15_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_15_MASK    0x80000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_14_SHIFT   30U
-#define XSYSMONPSU_IDR_0_PL_ALM_14_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_14_MASK    0x40000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_13_SHIFT   29U
-#define XSYSMONPSU_IDR_0_PL_ALM_13_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_13_MASK    0x20000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_12_SHIFT   28U
-#define XSYSMONPSU_IDR_0_PL_ALM_12_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_12_MASK    0x10000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_11_SHIFT   27U
-#define XSYSMONPSU_IDR_0_PL_ALM_11_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_11_MASK    0x08000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_10_SHIFT   26U
-#define XSYSMONPSU_IDR_0_PL_ALM_10_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_10_MASK    0x04000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_9_SHIFT   25U
-#define XSYSMONPSU_IDR_0_PL_ALM_9_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_9_MASK    0x02000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_8_SHIFT   24U
-#define XSYSMONPSU_IDR_0_PL_ALM_8_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_8_MASK    0x01000000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_7_SHIFT   23U
-#define XSYSMONPSU_IDR_0_PL_ALM_7_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_7_MASK    0x00800000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_6_SHIFT   22U
-#define XSYSMONPSU_IDR_0_PL_ALM_6_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_6_MASK    0x00400000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_5_SHIFT   21U
-#define XSYSMONPSU_IDR_0_PL_ALM_5_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_5_MASK    0x00200000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_4_SHIFT   20U
-#define XSYSMONPSU_IDR_0_PL_ALM_4_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_4_MASK    0x00100000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_3_SHIFT   19U
-#define XSYSMONPSU_IDR_0_PL_ALM_3_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_3_MASK    0x00080000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_2_SHIFT   18U
-#define XSYSMONPSU_IDR_0_PL_ALM_2_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_2_MASK    0x00040000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_1_SHIFT   17U
-#define XSYSMONPSU_IDR_0_PL_ALM_1_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_1_MASK    0x00020000U
-
-#define XSYSMONPSU_IDR_0_PL_ALM_0_SHIFT   16U
-#define XSYSMONPSU_IDR_0_PL_ALM_0_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PL_ALM_0_MASK    0x00010000U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_15_SHIFT   15U
-#define XSYSMONPSU_IDR_0_PS_ALM_15_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_15_MASK    0x00008000U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_14_SHIFT   14U
-#define XSYSMONPSU_IDR_0_PS_ALM_14_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_14_MASK    0x00004000U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_13_SHIFT   13U
-#define XSYSMONPSU_IDR_0_PS_ALM_13_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_13_MASK    0x00002000U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_12_SHIFT   12U
-#define XSYSMONPSU_IDR_0_PS_ALM_12_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_12_MASK    0x00001000U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_11_SHIFT   11U
-#define XSYSMONPSU_IDR_0_PS_ALM_11_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_11_MASK    0x00000800U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_10_SHIFT   10U
-#define XSYSMONPSU_IDR_0_PS_ALM_10_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_10_MASK    0x00000400U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_9_SHIFT   9U
-#define XSYSMONPSU_IDR_0_PS_ALM_9_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_9_MASK    0x00000200U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_8_SHIFT   8U
-#define XSYSMONPSU_IDR_0_PS_ALM_8_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_8_MASK    0x00000100U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_7_SHIFT   7U
-#define XSYSMONPSU_IDR_0_PS_ALM_7_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_7_MASK    0x00000080U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_6_SHIFT   6U
-#define XSYSMONPSU_IDR_0_PS_ALM_6_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_6_MASK    0x00000040U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_5_SHIFT   5U
-#define XSYSMONPSU_IDR_0_PS_ALM_5_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_5_MASK    0x00000020U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_4_SHIFT   4U
-#define XSYSMONPSU_IDR_0_PS_ALM_4_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_4_MASK    0x00000010U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_3_SHIFT   3U
-#define XSYSMONPSU_IDR_0_PS_ALM_3_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_3_MASK    0x00000008U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_2_SHIFT   2U
-#define XSYSMONPSU_IDR_0_PS_ALM_2_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_2_MASK    0x00000004U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_1_SHIFT   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_1_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_1_MASK    0x00000002U
-
-#define XSYSMONPSU_IDR_0_PS_ALM_0_SHIFT   0U
-#define XSYSMONPSU_IDR_0_PS_ALM_0_WIDTH   1U
-#define XSYSMONPSU_IDR_0_PS_ALM_0_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuIdr1
- */
-#define XSYSMONPSU_IDR_1_OFFSET   0x0000002CU
-#define XSYSMONPSU_IDR_1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_SHIFT   31U
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_WIDTH   1U
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_MASK    0x80000000U
-
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
-
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
-#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
-
-#define XSYSMONPSU_IDR_1_EOS_SHIFT   4U
-#define XSYSMONPSU_IDR_1_EOS_WIDTH   1U
-#define XSYSMONPSU_IDR_1_EOS_MASK    0x00000010U
-
-#define XSYSMONPSU_IDR_1_EOC_SHIFT   3U
-#define XSYSMONPSU_IDR_1_EOC_WIDTH   1U
-#define XSYSMONPSU_IDR_1_EOC_MASK    0x00000008U
-
-#define XSYSMONPSU_IDR_1_PL_OT_SHIFT   2U
-#define XSYSMONPSU_IDR_1_PL_OT_WIDTH   1U
-#define XSYSMONPSU_IDR_1_PL_OT_MASK    0x00000004U
-
-#define XSYSMONPSU_IDR_1_PS_LPD_OT_SHIFT   1U
-#define XSYSMONPSU_IDR_1_PS_LPD_OT_WIDTH   1U
-#define XSYSMONPSU_IDR_1_PS_LPD_OT_MASK    0x00000002U
-
-#define XSYSMONPSU_IDR_1_PS_FPD_OT_SHIFT   0U
-#define XSYSMONPSU_IDR_1_PS_FPD_OT_WIDTH   1U
-#define XSYSMONPSU_IDR_1_PS_FPD_OT_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuPsSysmonSts
- */
-#define XSYSMONPSU_PS_SYSMON_CSTS_OFFSET   0x00000040U
-#define XSYSMONPSU_PS_SYSMON_CSTS_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_SHIFT   24U
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_WIDTH   4U
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_MASK    0x0f000000U
-
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_SHIFT   16U
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_WIDTH   1U
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_MASK    0x00010000U
-
-#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_SHIFT   3U
-#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_WIDTH   1U
-#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK    0x00000008U
-
-#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_SHIFT   2U
-#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_WIDTH   1U
-#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK    0x00000004U
-
-#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_SHIFT   1U
-#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_WIDTH   1U
-#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_MASK    0x00000002U
-
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_SHIFT   0U
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_WIDTH   1U
-#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_MASK    0x00000001U
-
-#define XSYSMONPSU_PS_SYSMON_READY 0x08010000U
-
-/**
- * Register: XSysmonPsuPlSysmonSts
- */
-#define XSYSMONPSU_PL_SYSMON_CSTS_OFFSET   0x00000044U
-#define XSYSMONPSU_PL_SYSMON_CSTS_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_SHIFT   0U
-#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_WIDTH   1U
-#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuMonSts
- */
-#define XSYSMONPSU_MON_STS_OFFSET   0x00000050U
-#define XSYSMONPSU_MON_STS_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MON_STS_JTAG_LCKD_SHIFT   23U
-#define XSYSMONPSU_MON_STS_JTAG_LCKD_WIDTH   1U
-#define XSYSMONPSU_MON_STS_JTAG_LCKD_MASK    0x00800000U
-
-#define XSYSMONPSU_MON_STS_BSY_SHIFT   22U
-#define XSYSMONPSU_MON_STS_BSY_WIDTH   1U
-#define XSYSMONPSU_MON_STS_BSY_MASK    0x00400000U
-
-#define XSYSMONPSU_MON_STS_CH_SHIFT   16U
-#define XSYSMONPSU_MON_STS_CH_WIDTH   6U
-#define XSYSMONPSU_MON_STS_CH_MASK    0x003f0000U
-
-#define XSYSMONPSU_MON_STS_DATA_SHIFT   0U
-#define XSYSMONPSU_MON_STS_DATA_WIDTH   16U
-#define XSYSMONPSU_MON_STS_DATA_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccPspll0
- */
-#define XSYSMONPSU_VCC_PSPLL0_OFFSET   0x00000060U
-#define XSYSMONPSU_VCC_PSPLL0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCC_PSPLL0_VAL_SHIFT   0U
-#define XSYSMONPSU_VCC_PSPLL0_VAL_WIDTH   16U
-#define XSYSMONPSU_VCC_PSPLL0_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccPspll1
- */
-#define XSYSMONPSU_VCC_PSPLL1_OFFSET   0x00000064U
-#define XSYSMONPSU_VCC_PSPLL1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCC_PSPLL1_VAL_SHIFT   0U
-#define XSYSMONPSU_VCC_PSPLL1_VAL_WIDTH   16U
-#define XSYSMONPSU_VCC_PSPLL1_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccPspll2
- */
-#define XSYSMONPSU_VCC_PSPLL2_OFFSET   0x00000068U
-#define XSYSMONPSU_VCC_PSPLL2_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCC_PSPLL2_VAL_SHIFT   0U
-#define XSYSMONPSU_VCC_PSPLL2_VAL_WIDTH   16U
-#define XSYSMONPSU_VCC_PSPLL2_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccPspll3
- */
-#define XSYSMONPSU_VCC_PSPLL3_OFFSET   0x0000006CU
-#define XSYSMONPSU_VCC_PSPLL3_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCC_PSPLL3_VAL_SHIFT   0U
-#define XSYSMONPSU_VCC_PSPLL3_VAL_WIDTH   16U
-#define XSYSMONPSU_VCC_PSPLL3_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccPspll4
- */
-#define XSYSMONPSU_VCC_PSPLL4_OFFSET   0x00000070U
-#define XSYSMONPSU_VCC_PSPLL4_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCC_PSPLL4_VAL_SHIFT   0U
-#define XSYSMONPSU_VCC_PSPLL4_VAL_WIDTH   16U
-#define XSYSMONPSU_VCC_PSPLL4_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccPsbatt
- */
-#define XSYSMONPSU_VCC_PSBATT_OFFSET   0x00000074U
-#define XSYSMONPSU_VCC_PSBATT_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCC_PSBATT_VAL_SHIFT   0U
-#define XSYSMONPSU_VCC_PSBATT_VAL_WIDTH   16U
-#define XSYSMONPSU_VCC_PSBATT_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccint
- */
-#define XSYSMONPSU_VCCINT_OFFSET   0x00000078U
-#define XSYSMONPSU_VCCINT_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCCINT_VAL_SHIFT   0U
-#define XSYSMONPSU_VCCINT_VAL_WIDTH   16U
-#define XSYSMONPSU_VCCINT_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccbram
- */
-#define XSYSMONPSU_VCCBRAM_OFFSET   0x0000007CU
-#define XSYSMONPSU_VCCBRAM_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCCBRAM_VAL_SHIFT   0U
-#define XSYSMONPSU_VCCBRAM_VAL_WIDTH   16U
-#define XSYSMONPSU_VCCBRAM_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccaux
- */
-#define XSYSMONPSU_VCCAUX_OFFSET   0x00000080U
-#define XSYSMONPSU_VCCAUX_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCCAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VCCAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VCCAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccPsddrpll
- */
-#define XSYSMONPSU_VCC_PSDDRPLL_OFFSET   0x00000084U
-#define XSYSMONPSU_VCC_PSDDRPLL_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCC_PSDDRPLL_VAL_SHIFT   0U
-#define XSYSMONPSU_VCC_PSDDRPLL_VAL_WIDTH   16U
-#define XSYSMONPSU_VCC_PSDDRPLL_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuDdrphyVref
- */
-#define XSYSMONPSU_DDRPHY_VREF_OFFSET   0x00000088U
-#define XSYSMONPSU_DDRPHY_VREF_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_DDRPHY_VREF_VAL_SHIFT   0U
-#define XSYSMONPSU_DDRPHY_VREF_VAL_WIDTH   16U
-#define XSYSMONPSU_DDRPHY_VREF_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuDdrphyAto
- */
-#define XSYSMONPSU_DDRPHY_ATO_OFFSET   0x0000008CU
-#define XSYSMONPSU_DDRPHY_ATO_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_DDRPHY_ATO_VAL_SHIFT   0U
-#define XSYSMONPSU_DDRPHY_ATO_VAL_WIDTH   16U
-#define XSYSMONPSU_DDRPHY_ATO_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuPsgtAt0
- */
-#define XSYSMONPSU_PSGT_AT0_OFFSET   0x00000090U
-#define XSYSMONPSU_PSGT_AT0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_PSGT_AT0_VAL_SHIFT   0U
-#define XSYSMONPSU_PSGT_AT0_VAL_WIDTH   16U
-#define XSYSMONPSU_PSGT_AT0_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuPsgtAt1
- */
-#define XSYSMONPSU_PSGT_AT1_OFFSET   0x00000094U
-#define XSYSMONPSU_PSGT_AT1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_PSGT_AT1_VAL_SHIFT   0U
-#define XSYSMONPSU_PSGT_AT1_VAL_WIDTH   16U
-#define XSYSMONPSU_PSGT_AT1_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuReserve0
- */
-#define XSYSMONPSU_RESERVE0_OFFSET   0x00000098U
-#define XSYSMONPSU_RESERVE0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_RESERVE0_VAL_SHIFT   0U
-#define XSYSMONPSU_RESERVE0_VAL_WIDTH   16U
-#define XSYSMONPSU_RESERVE0_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuReserve1
- */
-#define XSYSMONPSU_RESERVE1_OFFSET   0x0000009CU
-#define XSYSMONPSU_RESERVE1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_RESERVE1_VAL_SHIFT   0U
-#define XSYSMONPSU_RESERVE1_VAL_WIDTH   16U
-#define XSYSMONPSU_RESERVE1_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuTemp
- */
-#define XSYSMONPSU_TEMP_OFFSET   0x00000000U
-#define XSYSMONPSU_TEMP_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_TEMP_SHIFT   0U
-#define XSYSMONPSU_TEMP_WIDTH   16U
-#define XSYSMONPSU_TEMP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup1
- */
-#define XSYSMONPSU_SUP1_OFFSET   0x00000004U
-#define XSYSMONPSU_SUP1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP1_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP1_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP1_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup2
- */
-#define XSYSMONPSU_SUP2_OFFSET   0x00000008U
-#define XSYSMONPSU_SUP2_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP2_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP2_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP2_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVpVn
- */
-#define XSYSMONPSU_VP_VN_OFFSET   0x0000000CU
-#define XSYSMONPSU_VP_VN_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VP_VN_SHIFT   0U
-#define XSYSMONPSU_VP_VN_WIDTH   16U
-#define XSYSMONPSU_VP_VN_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVrefp
- */
-#define XSYSMONPSU_VREFP_OFFSET   0x00000010U
-#define XSYSMONPSU_VREFP_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VREFP_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_VREFP_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_VREFP_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVrefn
- */
-#define XSYSMONPSU_VREFN_OFFSET   0x00000014U
-#define XSYSMONPSU_VREFN_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VREFN_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_VREFN_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_VREFN_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup3
- */
-#define XSYSMONPSU_SUP3_OFFSET   0x00000018U
-#define XSYSMONPSU_SUP3_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP3_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP3_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP3_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuCalSupOff
- */
-#define XSYSMONPSU_CAL_SUP_OFF_OFFSET   0x00000020U
-#define XSYSMONPSU_CAL_SUP_OFF_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_CAL_SUP_OFF_VAL_SHIFT   0U
-#define XSYSMONPSU_CAL_SUP_OFF_VAL_WIDTH   16U
-#define XSYSMONPSU_CAL_SUP_OFF_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuCalAdcBiplrOff
- */
-#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_OFFSET   0x00000024U
-#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_SHIFT   0U
-#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_WIDTH   16U
-#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuCalGainErr
- */
-#define XSYSMONPSU_CAL_GAIN_ERR_OFFSET   0x00000028U
-#define XSYSMONPSU_CAL_GAIN_ERR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_CAL_GAIN_ERR_VAL_SHIFT   0U
-#define XSYSMONPSU_CAL_GAIN_ERR_VAL_WIDTH   16U
-#define XSYSMONPSU_CAL_GAIN_ERR_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup4
- */
-#define XSYSMONPSU_SUP4_OFFSET   0x00000034U
-#define XSYSMONPSU_SUP4_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP4_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP4_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP4_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup5
- */
-#define XSYSMONPSU_SUP5_OFFSET   0x00000038U
-#define XSYSMONPSU_SUP5_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP5_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP5_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP5_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup6
- */
-#define XSYSMONPSU_SUP6_OFFSET   0x0000003CU
-#define XSYSMONPSU_SUP6_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP6_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP6_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP6_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux00
- */
-#define XSYSMONPSU_VAUX00_OFFSET   0x00000040U
-#define XSYSMONPSU_VAUX00_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX00_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX00_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX00_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux01
- */
-#define XSYSMONPSU_VAUX01_OFFSET   0x00000044U
-#define XSYSMONPSU_VAUX01_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX01_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX01_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX01_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux02
- */
-#define XSYSMONPSU_VAUX02_OFFSET   0x00000048U
-#define XSYSMONPSU_VAUX02_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX02_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX02_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX02_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux03
- */
-#define XSYSMONPSU_VAUX03_OFFSET   0x0000004CU
-#define XSYSMONPSU_VAUX03_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX03_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX03_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX03_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux04
- */
-#define XSYSMONPSU_VAUX04_OFFSET   0x00000050U
-#define XSYSMONPSU_VAUX04_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX04_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX04_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX04_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux05
- */
-#define XSYSMONPSU_VAUX05_OFFSET   0x00000054U
-#define XSYSMONPSU_VAUX05_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX05_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX05_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX05_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux06
- */
-#define XSYSMONPSU_VAUX06_OFFSET   0x00000058U
-#define XSYSMONPSU_VAUX06_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX06_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX06_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX06_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux07
- */
-#define XSYSMONPSU_VAUX07_OFFSET   0x0000005CU
-#define XSYSMONPSU_VAUX07_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX07_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX07_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX07_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux08
- */
-#define XSYSMONPSU_VAUX08_OFFSET   0x00000060U
-#define XSYSMONPSU_VAUX08_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX08_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX08_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX08_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux09
- */
-#define XSYSMONPSU_VAUX09_OFFSET   0x00000064U
-#define XSYSMONPSU_VAUX09_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX09_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX09_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX09_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux0a
- */
-#define XSYSMONPSU_VAUX0A_OFFSET   0x00000068U
-#define XSYSMONPSU_VAUX0A_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX0A_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX0A_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX0A_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux0b
- */
-#define XSYSMONPSU_VAUX0B_OFFSET   0x0000006CU
-#define XSYSMONPSU_VAUX0B_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX0B_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX0B_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX0B_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux0c
- */
-#define XSYSMONPSU_VAUX0C_OFFSET   0x00000070U
-#define XSYSMONPSU_VAUX0C_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX0C_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX0C_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX0C_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux0d
- */
-#define XSYSMONPSU_VAUX0D_OFFSET   0x00000074U
-#define XSYSMONPSU_VAUX0D_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX0D_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX0D_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX0D_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux0e
- */
-#define XSYSMONPSU_VAUX0E_OFFSET   0x00000078U
-#define XSYSMONPSU_VAUX0E_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX0E_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX0E_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX0E_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVaux0f
- */
-#define XSYSMONPSU_VAUX0F_OFFSET   0x0000007CU
-#define XSYSMONPSU_VAUX0F_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VAUX0F_VAUX_VAL_SHIFT   0U
-#define XSYSMONPSU_VAUX0F_VAUX_VAL_WIDTH   16U
-#define XSYSMONPSU_VAUX0F_VAUX_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxTemp
- */
-#define XSYSMONPSU_MAX_TEMP_OFFSET   0x00000080U
-#define XSYSMONPSU_MAX_TEMP_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_TEMP_SHIFT   0U
-#define XSYSMONPSU_MAX_TEMP_WIDTH   16U
-#define XSYSMONPSU_MAX_TEMP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup1
- */
-#define XSYSMONPSU_MAX_SUP1_OFFSET   0x00000084U
-#define XSYSMONPSU_MAX_SUP1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP1_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP1_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP1_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup2
- */
-#define XSYSMONPSU_MAX_SUP2_OFFSET   0x00000088U
-#define XSYSMONPSU_MAX_SUP2_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP2_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP2_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP2_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup3
- */
-#define XSYSMONPSU_MAX_SUP3_OFFSET   0x0000008CU
-#define XSYSMONPSU_MAX_SUP3_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP3_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP3_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP3_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinTemp
- */
-#define XSYSMONPSU_MIN_TEMP_OFFSET   0x00000090U
-#define XSYSMONPSU_MIN_TEMP_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_TEMP_SHIFT   0U
-#define XSYSMONPSU_MIN_TEMP_WIDTH   16U
-#define XSYSMONPSU_MIN_TEMP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup1
- */
-#define XSYSMONPSU_MIN_SUP1_OFFSET   0x00000094U
-#define XSYSMONPSU_MIN_SUP1_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP1_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP1_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP1_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup2
- */
-#define XSYSMONPSU_MIN_SUP2_OFFSET   0x00000098U
-#define XSYSMONPSU_MIN_SUP2_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP2_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP2_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP2_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup3
- */
-#define XSYSMONPSU_MIN_SUP3_OFFSET   0x0000009CU
-#define XSYSMONPSU_MIN_SUP3_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP3_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP3_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP3_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup4
- */
-#define XSYSMONPSU_MAX_SUP4_OFFSET   0x000000A0U
-#define XSYSMONPSU_MAX_SUP4_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP4_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP4_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP4_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup5
- */
-#define XSYSMONPSU_MAX_SUP5_OFFSET   0x000000A4U
-#define XSYSMONPSU_MAX_SUP5_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP5_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP5_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP5_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup6
- */
-#define XSYSMONPSU_MAX_SUP6_OFFSET   0x000000A8U
-#define XSYSMONPSU_MAX_SUP6_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP6_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP6_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP6_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup4
- */
-#define XSYSMONPSU_MIN_SUP4_OFFSET   0x000000B0U
-#define XSYSMONPSU_MIN_SUP4_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP4_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP4_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP4_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup5
- */
-#define XSYSMONPSU_MIN_SUP5_OFFSET   0x000000B4U
-#define XSYSMONPSU_MIN_SUP5_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP5_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP5_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP5_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup6
- */
-#define XSYSMONPSU_MIN_SUP6_OFFSET   0x000000B8U
-#define XSYSMONPSU_MIN_SUP6_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP6_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP6_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP6_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuStsFlag
- */
-#define XSYSMONPSU_STS_FLAG_OFFSET   0x000000FCU
-#define XSYSMONPSU_STS_FLAG_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_SHIFT   15U
-#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_WIDTH   1U
-#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_MASK    0x00008000U
-
-#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_SHIFT   14U
-#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_WIDTH   1U
-#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_MASK    0x00004000U
-
-#define XSYSMONPSU_STS_FLAG_JTAG_DISD_SHIFT   11U
-#define XSYSMONPSU_STS_FLAG_JTAG_DISD_WIDTH   1U
-#define XSYSMONPSU_STS_FLAG_JTAG_DISD_MASK    0x00000800U
-
-#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_SHIFT   10U
-#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_WIDTH   1U
-#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_MASK    0x00000400U
-
-#define XSYSMONPSU_STS_FLAG_INTRNL_REF_SHIFT   9U
-#define XSYSMONPSU_STS_FLAG_INTRNL_REF_WIDTH   1U
-#define XSYSMONPSU_STS_FLAG_INTRNL_REF_MASK    0x00000200U
-
-#define XSYSMONPSU_STS_FLAG_DISD_SHIFT   8U
-#define XSYSMONPSU_STS_FLAG_DISD_WIDTH   1U
-#define XSYSMONPSU_STS_FLAG_DISD_MASK    0x00000100U
-
-#define XSYSMONPSU_STS_FLAG_ALM_6_3_SHIFT   4U
-#define XSYSMONPSU_STS_FLAG_ALM_6_3_WIDTH   4U
-#define XSYSMONPSU_STS_FLAG_ALM_6_3_MASK    0x000000f0U
-
-#define XSYSMONPSU_STS_FLAG_OT_SHIFT   3U
-#define XSYSMONPSU_STS_FLAG_OT_WIDTH   1U
-#define XSYSMONPSU_STS_FLAG_OT_MASK    0x00000008U
-
-#define XSYSMONPSU_STS_FLAG_ALM_2_0_SHIFT   0U
-#define XSYSMONPSU_STS_FLAG_ALM_2_0_WIDTH   3U
-#define XSYSMONPSU_STS_FLAG_ALM_2_0_MASK    0x00000007U
-
-/**
- * Register: XSysmonPsuCfgReg0
- */
-#define XSYSMONPSU_CFG_REG0_OFFSET   0x00000100U
-#define XSYSMONPSU_CFG_REG0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT   12U
-#define XSYSMONPSU_CFG_REG0_AVRGNG_WIDTH   2U
-#define XSYSMONPSU_CFG_REG0_AVRGNG_MASK    0x00003000U
-
-#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_SHIFT   11U
-#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_WIDTH   1U
-#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK    0x00000800U
-
-#define XSYSMONPSU_CFG_REG0_BU_SHIFT   10U
-#define XSYSMONPSU_CFG_REG0_BU_WIDTH   1U
-#define XSYSMONPSU_CFG_REG0_BU_MASK    0x00000400U
-
-#define XSYSMONPSU_CFG_REG0_EC_SHIFT   9U
-#define XSYSMONPSU_CFG_REG0_EC_WIDTH   1U
-#define XSYSMONPSU_CFG_REG0_EC_MASK    0x00000200U
-
-#define XSYSMONPSU_EVENT_MODE	1
-#define XSYSMONPSU_CONTINUOUS_MODE 2
-
-#define XSYSMONPSU_CFG_REG0_ACQ_SHIFT   8U
-#define XSYSMONPSU_CFG_REG0_ACQ_WIDTH   1U
-#define XSYSMONPSU_CFG_REG0_ACQ_MASK    0x00000100U
-
-#define XSYSMONPSU_CFG_REG0_MUX_CH_SHIFT   0U
-#define XSYSMONPSU_CFG_REG0_MUX_CH_WIDTH   6U
-#define XSYSMONPSU_CFG_REG0_MUX_CH_MASK    0x0000003fU
-
-/**
- * Register: XSysmonPsuCfgReg1
- */
-#define XSYSMONPSU_CFG_REG1_OFFSET   0x00000104U
-#define XSYSMONPSU_CFG_REG1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT   12U
-#define XSYSMONPSU_CFG_REG1_SEQ_MDE_WIDTH   4U
-#define XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK    0x0000f000U
-
-#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_SHIFT   8U
-#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_WIDTH   4U
-#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_MASK    0x00000f00U
-
-#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_SHIFT   1U
-#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_WIDTH   3U
-#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_MASK    0x0000000eU
-
-#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_SHIFT   0U
-#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_WIDTH   1U
-#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_MASK    0x00000001U
-
-#define XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK 0x00000f0fU
-#define XSYSMONPSU_CFR_REG1_ALRM_SUP6_MASK		0x0800U
-#define XSYSMONPSU_CFR_REG1_ALRM_SUP5_MASK		0x0400U
-#define XSYSMONPSU_CFR_REG1_ALRM_SUP4_MASK		0x0200U
-#define XSYSMONPSU_CFR_REG1_ALRM_SUP3_MASK		0x0100U
-#define XSYSMONPSU_CFR_REG1_ALRM_SUP2_MASK		0x0008U
-#define XSYSMONPSU_CFR_REG1_ALRM_SUP1_MASK		0x0004U
-#define XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK		0x0002U
-#define XSYSMONPSU_CFR_REG1_ALRM_OT_MASK		0x0001U
-
-/**
- * Register: XSysmonPsuCfgReg2
- */
-#define XSYSMONPSU_CFG_REG2_OFFSET   0x00000108U
-#define XSYSMONPSU_CFG_REG2_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT   8U
-#define XSYSMONPSU_CFG_REG2_CLK_DVDR_WIDTH   8U
-#define XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK    0x0000ff00U
-
-#define XSYSMONPSU_CLK_DVDR_MIN_VAL			0U
-#define XSYSMONPSU_CLK_DVDR_MAX_VAL			255U
-
-#define XSYSMONPSU_CFG_REG2_PWR_DOWN_SHIFT   4U
-#define XSYSMONPSU_CFG_REG2_PWR_DOWN_WIDTH   4U
-#define XSYSMONPSU_CFG_REG2_PWR_DOWN_MASK    0x000000f0U
-
-#define XSYSMONPSU_CFG_REG2_TST_CH_EN_SHIFT   2U
-#define XSYSMONPSU_CFG_REG2_TST_CH_EN_WIDTH   1U
-#define XSYSMONPSU_CFG_REG2_TST_CH_EN_MASK    0x00000004U
-
-#define XSYSMONPSU_CFG_REG2_TST_MDE_SHIFT   0U
-#define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH   2U
-#define XSYSMONPSU_CFG_REG2_TST_MDE_MASK    0x00000003U
-
-/**
- * Register: XSysmonPsuSeqCh0
- */
-#define XSYSMONPSU_SEQ_CH0_OFFSET   0x00000120U
-#define XSYSMONPSU_SEQ_CH0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SEQ_CH0_CUR_MON_SHIFT   15U
-#define XSYSMONPSU_SEQ_CH0_CUR_MON_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_CUR_MON_MASK    0x00008000U
-
-#define XSYSMONPSU_SEQ_CH0_SUP3_SHIFT   14U
-#define XSYSMONPSU_SEQ_CH0_SUP3_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_SUP3_MASK    0x00004000U
-
-#define XSYSMONPSU_SEQ_CH0_VREFN_SHIFT   13U
-#define XSYSMONPSU_SEQ_CH0_VREFN_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_VREFN_MASK    0x00002000U
-
-#define XSYSMONPSU_SEQ_CH0_VREFP_SHIFT   12U
-#define XSYSMONPSU_SEQ_CH0_VREFP_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_VREFP_MASK    0x00001000U
-
-#define XSYSMONPSU_SEQ_CH0_VP_VN_SHIFT   11U
-#define XSYSMONPSU_SEQ_CH0_VP_VN_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_VP_VN_MASK    0x00000800U
-
-#define XSYSMONPSU_SEQ_CH0_SUP2_SHIFT   10U
-#define XSYSMONPSU_SEQ_CH0_SUP2_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_SUP2_MASK    0x00000400U
-
-#define XSYSMONPSU_SEQ_CH0_SUP1_SHIFT   9U
-#define XSYSMONPSU_SEQ_CH0_SUP1_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_SUP1_MASK    0x00000200U
-
-#define XSYSMONPSU_SEQ_CH0_TEMP_SHIFT   8U
-#define XSYSMONPSU_SEQ_CH0_TEMP_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_TEMP_MASK    0x00000100U
-
-#define XSYSMONPSU_SEQ_CH0_SUP6_SHIFT   7U
-#define XSYSMONPSU_SEQ_CH0_SUP6_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_SUP6_MASK    0x00000080U
-
-#define XSYSMONPSU_SEQ_CH0_SUP5_SHIFT   6U
-#define XSYSMONPSU_SEQ_CH0_SUP5_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_SUP5_MASK    0x00000040U
-
-#define XSYSMONPSU_SEQ_CH0_SUP4_SHIFT   5U
-#define XSYSMONPSU_SEQ_CH0_SUP4_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_SUP4_MASK    0x00000020U
-
-#define XSYSMONPSU_SEQ_CH0_TST_CH_SHIFT   3U
-#define XSYSMONPSU_SEQ_CH0_TST_CH_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_TST_CH_MASK    0x00000008U
-
-#define XSYSMONPSU_SEQ_CH0_CALIBRTN_SHIFT   0U
-#define XSYSMONPSU_SEQ_CH0_CALIBRTN_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH0_CALIBRTN_MASK    0x00000001U
-
-#define XSYSMONPSU_SEQ_CH0_VALID_MASK     0x0000FFE9U
-
-/**
- * Register: XSysmonPsuSeqCh1
- */
-#define XSYSMONPSU_SEQ_CH1_OFFSET         0x00000124U
-#define XSYSMONPSU_SEQ_CH1_VALID_MASK     0x0000FFFFU
-#define XSYSMONPSU_SEQ_CH1_RSTVAL         0x00000000U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX0F_SHIFT   15U
-#define XSYSMONPSU_SEQ_CH1_VAUX0F_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX0F_MASK    0x00008000U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX0E_SHIFT   14U
-#define XSYSMONPSU_SEQ_CH1_VAUX0E_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX0E_MASK    0x00004000U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX0D_SHIFT   13U
-#define XSYSMONPSU_SEQ_CH1_VAUX0D_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX0D_MASK    0x00002000U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX0C_SHIFT   12U
-#define XSYSMONPSU_SEQ_CH1_VAUX0C_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX0C_MASK    0x00001000U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX0B_SHIFT   11U
-#define XSYSMONPSU_SEQ_CH1_VAUX0B_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX0B_MASK    0x00000800U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX0A_SHIFT   10U
-#define XSYSMONPSU_SEQ_CH1_VAUX0A_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX0A_MASK    0x00000400U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX09_SHIFT   9U
-#define XSYSMONPSU_SEQ_CH1_VAUX09_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX09_MASK    0x00000200U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX08_SHIFT   8U
-#define XSYSMONPSU_SEQ_CH1_VAUX08_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX08_MASK    0x00000100U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX07_SHIFT   7U
-#define XSYSMONPSU_SEQ_CH1_VAUX07_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX07_MASK    0x00000080U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX06_SHIFT   6U
-#define XSYSMONPSU_SEQ_CH1_VAUX06_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX06_MASK    0x00000040U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX05_SHIFT   5U
-#define XSYSMONPSU_SEQ_CH1_VAUX05_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX05_MASK    0x00000020U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX04_SHIFT   4U
-#define XSYSMONPSU_SEQ_CH1_VAUX04_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX04_MASK    0x00000010U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX03_SHIFT   3U
-#define XSYSMONPSU_SEQ_CH1_VAUX03_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX03_MASK    0x00000008U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX02_SHIFT   2U
-#define XSYSMONPSU_SEQ_CH1_VAUX02_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX02_MASK    0x00000004U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX01_SHIFT   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX01_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX01_MASK    0x00000002U
-
-#define XSYSMONPSU_SEQ_CH1_VAUX00_SHIFT   0U
-#define XSYSMONPSU_SEQ_CH1_VAUX00_WIDTH   1U
-#define XSYSMONPSU_SEQ_CH1_VAUX00_MASK    0x00000001U
-
-#define XSM_SEQ_CH_SHIFT                  16U
-
-/**
- * Register: XSysmonPsuSeqAverage0
- */
-#define XSYSMONPSU_SEQ_AVERAGE0_OFFSET   0x00000128U
-#define XSYSMONPSU_SEQ_AVERAGE0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SEQ_AVERAGE0_SHIFT   0U
-#define XSYSMONPSU_SEQ_AVERAGE0_WIDTH   16U
-#define XSYSMONPSU_SEQ_AVERAGE0_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSeqAverage1
- */
-#define XSYSMONPSU_SEQ_AVERAGE1_OFFSET   0x0000012CU
-#define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SEQ_AVERAGE1_SHIFT   0U
-#define XSYSMONPSU_SEQ_AVERAGE1_WIDTH   16U
-#define XSYSMONPSU_SEQ_AVERAGE1_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSeqInputMde0
- */
-#define XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET   0x00000130U
-#define XSYSMONPSU_SEQ_INPUT_MDE0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SEQ_INPUT_MDE0_SHIFT   0U
-#define XSYSMONPSU_SEQ_INPUT_MDE0_WIDTH   16U
-#define XSYSMONPSU_SEQ_INPUT_MDE0_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSeqInputMde1
- */
-#define XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET   0x00000134U
-#define XSYSMONPSU_SEQ_INPUT_MDE1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SEQ_INPUT_MDE1_SHIFT   0U
-#define XSYSMONPSU_SEQ_INPUT_MDE1_WIDTH   16U
-#define XSYSMONPSU_SEQ_INPUT_MDE1_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSeqAcq0
- */
-#define XSYSMONPSU_SEQ_ACQ0_OFFSET   0x00000138U
-#define XSYSMONPSU_SEQ_ACQ0_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SEQ_ACQ0_SHIFT   0U
-#define XSYSMONPSU_SEQ_ACQ0_WIDTH   16U
-#define XSYSMONPSU_SEQ_ACQ0_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSeqAcq1
- */
-#define XSYSMONPSU_SEQ_ACQ1_OFFSET   0x0000013CU
-#define XSYSMONPSU_SEQ_ACQ1_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SEQ_ACQ1_SHIFT   0U
-#define XSYSMONPSU_SEQ_ACQ1_WIDTH   16U
-#define XSYSMONPSU_SEQ_ACQ1_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmTempUpr
- */
-#define XSYSMONPSU_ALRM_TEMP_UPR_OFFSET   0x00000140U
-#define XSYSMONPSU_ALRM_TEMP_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_TEMP_UPR_SHIFT   0U
-#define XSYSMONPSU_ALRM_TEMP_UPR_WIDTH   16U
-#define XSYSMONPSU_ALRM_TEMP_UPR_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup1Upr
- */
-#define XSYSMONPSU_ALRM_SUP1_UPR_OFFSET   0x00000144U
-#define XSYSMONPSU_ALRM_SUP1_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup2Upr
- */
-#define XSYSMONPSU_ALRM_SUP2_UPR_OFFSET   0x00000148U
-#define XSYSMONPSU_ALRM_SUP2_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmOtUpr
- */
-#define XSYSMONPSU_ALRM_OT_UPR_OFFSET   0x0000014CU
-#define XSYSMONPSU_ALRM_OT_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_OT_UPR_TEMP_SHIFT   0U
-#define XSYSMONPSU_ALRM_OT_UPR_TEMP_WIDTH   16U
-#define XSYSMONPSU_ALRM_OT_UPR_TEMP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmTempLwr
- */
-#define XSYSMONPSU_ALRM_TEMP_LWR_OFFSET   0x00000150U
-#define XSYSMONPSU_ALRM_TEMP_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_TEMP_LWR_SHIFT   1U
-#define XSYSMONPSU_ALRM_TEMP_LWR_WIDTH   15U
-#define XSYSMONPSU_ALRM_TEMP_LWR_MASK    0x0000fffeU
-
-#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_SHIFT   0U
-#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_WIDTH   1U
-#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuAlrmSup1Lwr
- */
-#define XSYSMONPSU_ALRM_SUP1_LWR_OFFSET   0x00000154U
-#define XSYSMONPSU_ALRM_SUP1_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup2Lwr
- */
-#define XSYSMONPSU_ALRM_SUP2_LWR_OFFSET   0x00000158U
-#define XSYSMONPSU_ALRM_SUP2_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmOtLwr
- */
-#define XSYSMONPSU_ALRM_OT_LWR_OFFSET   0x0000015CU
-#define XSYSMONPSU_ALRM_OT_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_OT_LWR_TEMP_SHIFT   1U
-#define XSYSMONPSU_ALRM_OT_LWR_TEMP_WIDTH   15U
-#define XSYSMONPSU_ALRM_OT_LWR_TEMP_MASK    0x0000fffeU
-
-#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_SHIFT   0U
-#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_WIDTH   1U
-#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuAlrmSup3Upr
- */
-#define XSYSMONPSU_ALRM_SUP3_UPR_OFFSET   0x00000160U
-#define XSYSMONPSU_ALRM_SUP3_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup4Upr
- */
-#define XSYSMONPSU_ALRM_SUP4_UPR_OFFSET   0x00000164U
-#define XSYSMONPSU_ALRM_SUP4_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup5Upr
- */
-#define XSYSMONPSU_ALRM_SUP5_UPR_OFFSET   0x00000168U
-#define XSYSMONPSU_ALRM_SUP5_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup6Upr
- */
-#define XSYSMONPSU_ALRM_SUP6_UPR_OFFSET   0x0000016CU
-#define XSYSMONPSU_ALRM_SUP6_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup3Lwr
- */
-#define XSYSMONPSU_ALRM_SUP3_LWR_OFFSET   0x00000170U
-#define XSYSMONPSU_ALRM_SUP3_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup4Lwr
- */
-#define XSYSMONPSU_ALRM_SUP4_LWR_OFFSET   0x00000174U
-#define XSYSMONPSU_ALRM_SUP4_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup5Lwr
- */
-#define XSYSMONPSU_ALRM_SUP5_LWR_OFFSET   0x00000178U
-#define XSYSMONPSU_ALRM_SUP5_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup6Lwr
- */
-#define XSYSMONPSU_ALRM_SUP6_LWR_OFFSET   0x0000017CU
-#define XSYSMONPSU_ALRM_SUP6_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup7Upr
- */
-#define XSYSMONPSU_ALRM_SUP7_UPR_OFFSET   0x00000180U
-#define XSYSMONPSU_ALRM_SUP7_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup8Upr
- */
-#define XSYSMONPSU_ALRM_SUP8_UPR_OFFSET   0x00000184U
-#define XSYSMONPSU_ALRM_SUP8_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup9Upr
- */
-#define XSYSMONPSU_ALRM_SUP9_UPR_OFFSET   0x00000188U
-#define XSYSMONPSU_ALRM_SUP9_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup10Upr
- */
-#define XSYSMONPSU_ALRM_SUP10_UPR_OFFSET   0x0000018CU
-#define XSYSMONPSU_ALRM_SUP10_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmVccamsUpr
- */
-#define XSYSMONPSU_ALRM_VCCAMS_UPR_OFFSET   0x00000190U
-#define XSYSMONPSU_ALRM_VCCAMS_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmTremoteUpr
- */
-#define XSYSMONPSU_ALRM_TREMOTE_UPR_OFFSET   0x00000194U
-#define XSYSMONPSU_ALRM_TREMOTE_UPR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_SHIFT   0U
-#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_WIDTH   16U
-#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup7Lwr
- */
-#define XSYSMONPSU_ALRM_SUP7_LWR_OFFSET   0x000001A0U
-#define XSYSMONPSU_ALRM_SUP7_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup8Lwr
- */
-#define XSYSMONPSU_ALRM_SUP8_LWR_OFFSET   0x000001A4U
-#define XSYSMONPSU_ALRM_SUP8_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup9Lwr
- */
-#define XSYSMONPSU_ALRM_SUP9_LWR_OFFSET   0x000001A8U
-#define XSYSMONPSU_ALRM_SUP9_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmSup10Lwr
- */
-#define XSYSMONPSU_ALRM_SUP10_LWR_OFFSET   0x000001ACU
-#define XSYSMONPSU_ALRM_SUP10_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmVccamsLwr
- */
-#define XSYSMONPSU_ALRM_VCCAMS_LWR_OFFSET   0x000001B0U
-#define XSYSMONPSU_ALRM_VCCAMS_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_SHIFT   0U
-#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_WIDTH   16U
-#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuAlrmTremoteLwr
- */
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_OFFSET   0x000001B4U
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_SHIFT   1U
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_WIDTH   15U
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_MASK    0x0000fffeU
-
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_SHIFT   0U
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH   1U
-#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK    0x00000001U
-
-/**
- * Register: XSysmonPsuSup7
- */
-#define XSYSMONPSU_SUP7_OFFSET   0x00000200U
-#define XSYSMONPSU_SUP7_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP7_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP7_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP7_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup8
- */
-#define XSYSMONPSU_SUP8_OFFSET   0x00000204U
-#define XSYSMONPSU_SUP8_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP8_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP8_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP8_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup9
- */
-#define XSYSMONPSU_SUP9_OFFSET   0x00000208U
-#define XSYSMONPSU_SUP9_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP9_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP9_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP9_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuSup10
- */
-#define XSYSMONPSU_SUP10_OFFSET   0x0000020CU
-#define XSYSMONPSU_SUP10_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_SUP10_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_SUP10_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_SUP10_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuVccams
- */
-#define XSYSMONPSU_VCCAMS_OFFSET   0x00000210U
-#define XSYSMONPSU_VCCAMS_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_VCCAMS_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_VCCAMS_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_VCCAMS_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuTempRemte
- */
-#define XSYSMONPSU_TEMP_REMTE_OFFSET   0x00000214U
-#define XSYSMONPSU_TEMP_REMTE_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_TEMP_REMTE_SHIFT   0U
-#define XSYSMONPSU_TEMP_REMTE_WIDTH   16U
-#define XSYSMONPSU_TEMP_REMTE_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup7
- */
-#define XSYSMONPSU_MAX_SUP7_OFFSET   0x00000280U
-#define XSYSMONPSU_MAX_SUP7_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP7_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP7_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP7_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup8
- */
-#define XSYSMONPSU_MAX_SUP8_OFFSET   0x00000284U
-#define XSYSMONPSU_MAX_SUP8_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP8_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP8_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP8_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup9
- */
-#define XSYSMONPSU_MAX_SUP9_OFFSET   0x00000288U
-#define XSYSMONPSU_MAX_SUP9_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP9_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP9_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP9_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxSup10
- */
-#define XSYSMONPSU_MAX_SUP10_OFFSET   0x0000028CU
-#define XSYSMONPSU_MAX_SUP10_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_SUP10_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_SUP10_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_SUP10_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxVccams
- */
-#define XSYSMONPSU_MAX_VCCAMS_OFFSET   0x00000290U
-#define XSYSMONPSU_MAX_VCCAMS_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMaxTempRemte
- */
-#define XSYSMONPSU_MAX_TEMP_REMTE_OFFSET   0x00000294U
-#define XSYSMONPSU_MAX_TEMP_REMTE_RSTVAL   0x00000000U
-
-#define XSYSMONPSU_MAX_TEMP_REMTE_SHIFT   0U
-#define XSYSMONPSU_MAX_TEMP_REMTE_WIDTH   16U
-#define XSYSMONPSU_MAX_TEMP_REMTE_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup7
- */
-#define XSYSMONPSU_MIN_SUP7_OFFSET   0x000002A0U
-#define XSYSMONPSU_MIN_SUP7_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP7_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP7_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP7_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup8
- */
-#define XSYSMONPSU_MIN_SUP8_OFFSET   0x000002A4U
-#define XSYSMONPSU_MIN_SUP8_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP8_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP8_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP8_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup9
- */
-#define XSYSMONPSU_MIN_SUP9_OFFSET   0x000002A8U
-#define XSYSMONPSU_MIN_SUP9_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP9_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP9_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP9_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinSup10
- */
-#define XSYSMONPSU_MIN_SUP10_OFFSET   0x000002ACU
-#define XSYSMONPSU_MIN_SUP10_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_SUP10_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_SUP10_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_SUP10_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinVccams
- */
-#define XSYSMONPSU_MIN_VCCAMS_OFFSET   0x000002B0U
-#define XSYSMONPSU_MIN_VCCAMS_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_SHIFT   0U
-#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_WIDTH   16U
-#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_MASK    0x0000ffffU
-
-/**
- * Register: XSysmonPsuMinTempRemte
- */
-#define XSYSMONPSU_MIN_TEMP_REMTE_OFFSET   0x000002B4U
-#define XSYSMONPSU_MIN_TEMP_REMTE_RSTVAL   0x0000ffffU
-
-#define XSYSMONPSU_MIN_TEMP_REMTE_SHIFT   0U
-#define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH   16U
-#define XSYSMONPSU_MIN_TEMP_REMTE_MASK    0x0000ffffU
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param	RegisterAddr is the register address in the address
-* 			space of the SYSMONPSU device.
-*
-* @return	The 32-bit value of the register
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XSysmonPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param	RegisterAddr is the register address in the address
-* 			space of the SYSMONPSU device.
-* @param	Data is the 32-bit value to write to the register.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XSysmonPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XSYSMONPSU_HW_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c
deleted file mode 100644
index b178c2e11..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsysmonpsu_intr.c
-*
-* This file contains functions related to SYSMONPSU interrupt handling.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.0   kvn    12/15/15 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xsysmonpsu.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified interrupts in the device.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Mask is the 64 bit-mask of the interrupts to be enabled.
-*		Bit positions of 1 will be enabled. Bit positions of 0 will
-*		keep the previous setting. This mask is formed by OR'ing
-*		XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* bits defined in
-*		xsysmonpsu_hw.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask)
-{
-	u32 RegValue;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Enable the specified interrupts in the AMS Interrupt Enable Register. */
-	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_IER_0_OFFSET);
-	RegValue |= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_0_OFFSET,
-			  RegValue);
-
-	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_IER_1_OFFSET);
-	RegValue |= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_1_OFFSET,
-			  RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified interrupts in the device.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Mask is the 64 bit-mask of the interrupts to be disabled.
-*		Bit positions of 1 will be disabled. Bit positions of 0 will
-*		keep the previous setting. This mask is formed by OR'ing
-*		XSYSMONPSU_IDR_0_* and XSYSMONPSU_IDR_1_* bits defined in
-*		xsysmonpsu_hw.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XSysMonPsu_IntrDisable(XSysMonPsu *InstancePtr, u64 Mask)
-{
-	u32 RegValue;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Disable the specified interrupts in the AMS Interrupt Disable Register. */
-	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_IDR_0_OFFSET);
-	RegValue |= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IDR_0_OFFSET,
-			  RegValue);
-
-	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_IDR_1_OFFSET);
-	RegValue |= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IDR_1_OFFSET,
-			  RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the enabled interrupts read from the Interrupt Enable
-* Register (IER). Use the XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* constants
-* defined in xsysmonpsu_hw.h to interpret the returned value.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-*
-* @return	A 64-bit value representing the contents of the Interrupt Mask
-* 			Registers (IMR1 IMR0).
-*
-* @note		None.
-*
-*****************************************************************************/
-u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr)
-{
-	u64 MaskedInterrupts;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Return the value read from the AMS Interrupt Mask Register. */
-	MaskedInterrupts = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-                         XSYSMONPSU_IMR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
-	MaskedInterrupts |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-                         XSYSMONPSU_IMR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
-                          << XSYSMONPSU_IXR_1_SHIFT;
-
-	return (~MaskedInterrupts);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt status read from Interrupt Status
-* Register(ISR). Use the XSYSMONPSU_ISR_0_* and XSYSMONPSU_ISR_1_ constants
-* defined in xsysmonpsu_hw.h to interpret the returned value.
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-*
-* @return	A 64-bit value representing the contents of the Interrupt Status
-* 			Registers (ISR1 ISR0).
-*
-* @note		None.
-*
-*****************************************************************************/
-u64 XSysMonPsu_IntrGetStatus(XSysMonPsu *InstancePtr)
-{
-	u64 IntrStatusRegister;
-
-	/* Assert the arguments. */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Return the value read from the AMS ISR. */
-	IntrStatusRegister = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-                           XSYSMONPSU_ISR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
-	IntrStatusRegister |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-                           XSYSMONPSU_ISR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
-                           << XSYSMONPSU_IXR_1_SHIFT;
-
-	return IntrStatusRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified interrupts in the Interrupt Status
-* Register (ISR).
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-* @param	Mask is the 64 bit-mask of the interrupts to be cleared.
-*		Bit positions of 1 will be cleared. Bit positions of 0 will not
-* 		change the previous interrupt status. This mask is formed by
-* 		OR'ing the XSYSMONPSU_ISR_0_* and XSYSMONPSU_ISR_1_* bits
-* 		which are defined in xsysmonpsu_hw.h.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask)
-{
-	u32 RegValue;
-
-	/* Assert the arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Clear the specified interrupts in the Interrupt Status register. */
-	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_ISR_0_OFFSET);
-	RegValue &= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_0_OFFSET,
-			  RegValue);
-
-	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
-					XSYSMONPSU_ISR_1_OFFSET);
-	RegValue &= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_1_OFFSET,
-			  RegValue);
-}
-
-
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c
deleted file mode 100644
index 5b709be14..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsysmon_selftest.c
-*
-* This file contains a diagnostic self test function for the XSysMon driver.
-* The self test function does a simple read/write test of the Alarm Threshold
-* Register.
-*
-* See xsysmonpsu.h for more information.
-*
-* @note	None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.0   kvn   12/15/15  First release
-*
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xsysmonpsu.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constant defines the test value to be written
- * to the Alarm Threshold Register
- */
-#define XSM_ATR_TEST_VALUE 		0x55U
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. The test
-*	- Resets the device,
-*	- Writes a value into the Alarm Threshold register and reads it back
-*	for comparison.
-*	- Resets the device again.
-*
-*
-* @param	InstancePtr is a pointer to the XSysMonPsu instance.
-*
-* @return
-*		- XST_SUCCESS if the value read from the Alarm Threshold
-*		register is the same as the value written.
-*		- XST_FAILURE Otherwise
-*
-* @note		This is a destructive test in that resets of the device are
-*		performed. Refer to the device specification for the
-*		device status after the reset operation.
-*
-******************************************************************************/
-s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr)
-{
-	s32 Status;
-	u32 RegValue;
-
-	/* Assert the argument */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Reset the device to get it back to its default state */
-	XSysMonPsu_Reset(InstancePtr);
-
-	/*
-	 * Write a value into the Alarm Threshold registers, read it back, and
-	 * do the comparison
-	 */
-	XSysMonPsu_SetAlarmThreshold(InstancePtr, XSM_ATR_SUP1_UPPER,
-				  XSM_ATR_TEST_VALUE, XSYSMON_PS);
-	RegValue = (u32)XSysMonPsu_GetAlarmThreshold(InstancePtr,
-					XSM_ATR_SUP1_UPPER, XSYSMON_PS);
-
-	if (RegValue == XSM_ATR_TEST_VALUE) {
-		Status = XST_SUCCESS;
-	} else {
-		Status = XST_FAILURE;
-	}
-
-	/* Reset the device again to its default state. */
-	XSysMonPsu_Reset(InstancePtr);
-
-	/* Return the test result. */
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c
deleted file mode 100644
index 34249a209..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsysmonpsu_sinit.c
-*
-* This file contains the implementation of the XSysMonPsu driver's static
-* initialization functionality.
-*
-* @note		None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	    Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.0   kvn    12/15/15 First release.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xsysmonpsu.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern XSysMonPsu_Config XSysMonPsu_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* This function looks for the device configuration based on the unique device
-* ID. The table XSysmonPsu_ConfigTable[] contains the configuration information
-* for each device in the system.
-*
-* @param	DeviceId is the unique device ID of the device being looked up.
-*
-* @return	A pointer to the configuration table entry corresponding to the
-*		given device ID, or NULL if no match is found.
-*
-* @note		None.
-*
-******************************************************************************/
-XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId)
-{
-	XSysMonPsu_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index = 0U; Index < (u32)XPAR_XSYSMONPSU_NUM_INSTANCES; Index++) {
-		if (XSysMonPsu_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XSysMonPsu_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return CfgPtr;
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile
new file mode 100644
index 000000000..b832910b8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsysmonpsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sysmonpsu"
+
+xsysmonpsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsysmonpsu_includes
+
+xsysmonpsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
new file mode 100644
index 000000000..b047a4599
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
@@ -0,0 +1,1809 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu.c
+*
+* Functions in this file are the minimum required functions for the XSysMonPsu
+* driver. See xsysmonpsu.h for a detailed description of the driver.
+*
+* @note 	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	    Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn    12/15/15 First release.
+*              02/15/16 Corrected Assert function call in
+*                       XSysMonPsu_GetMonitorStatus API.
+*              03/03/16 Added Temperature remote channel for Setsingle
+*                       channel API. Also corrected external mux channel
+*                       numbers.
+* 1.1   kvn    05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0   vns    08/14/16 Fixed CR #956780, added support for enabling/disabling
+*                       SEQ_CH2 and SEQ_AVG2 registers, modified function
+*                       prototypes of XSysMonPsu_GetSeqAvgEnables,
+*                       XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+*                       XSysMonPsu_GetSeqChEnables,
+*                       XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+*                       XSysMonPsu_SetSeqAcqTime
+*                       and XSysMonPsu_GetSeqAcqTime to provide support for
+*                       set/get 64 bit value.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsysmonpsu.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void XSysMonPsu_StubHandler(void *CallBackRef);
+
+/************************** Variable Definitions ****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes XSysMonPsu device/instance. This function
+* must be called prior to using the System Monitor device.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	ConfigPtr points to the XSysMonPsu device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XSysMonPsu_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XSysMonPsu_CfgInitialize() API.
+*
+******************************************************************************/
+s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigPtr,
+			  u32 EffectiveAddr)
+{
+	u32 PsSysmonControlStatus;
+	u32 PlSysmonControlStatus;
+
+	/* Assert the input arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/* Set the values read from the device config and the base address. */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+
+	/* Set all handlers to stub values, let user configure this data later. */
+	InstancePtr->Handler = XSysMonPsu_StubHandler;
+
+	/* Reset the device such that it is in a known state. */
+	XSysMonPsu_Reset(InstancePtr);
+
+	PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+
+	/* Check if the PS Sysmon is in Idle / ready state or not */
+	while(PsSysmonControlStatus != XSYSMONPSU_PS_SYSMON_READY) {
+		PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+	}
+
+	PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
+
+	/* Check if the PL Sysmon is accessible to PS Sysmon or not */
+	while((PlSysmonControlStatus & XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK)
+				!= XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK) {
+		PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
+	}
+
+	/* Indicate the instance is now ready to use, initialized without error */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XSysMonPsu_StubHandler(void *CallBackRef)
+{
+	(void *) CallBackRef;
+
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the SystemMonitor
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	None.
+*
+* @note		Upon reset, all Maximum and Minimum status registers will be
+*		reset to their default values. Currently running and any averaging
+*		will restart. Refer to the device data sheet for the device status and
+*		register values after the reset.
+*
+******************************************************************************/
+void XSysMonPsu_Reset(XSysMonPsu *InstancePtr)
+{
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* RESET the PS SYSMON */
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPS_BA_OFFSET +
+			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
+
+	/* RESET the PL SYSMON */
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET +
+			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the contents of the Status Register.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 32-bit value representing the contents of the Status Register.
+*		Use the XSYSMONPSU_MON_STS_* constants defined in xsysmonpsu_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*****************************************************************************/
+u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the Sysmon Status Register and return the value. */
+	Status = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_MON_STS_OFFSET);
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function starts the ADC conversion in the Single Channel event driven
+* sampling mode. The EOC bit in Status Register will be set once the conversion
+* is finished. Refer to the device specification for more details.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	None.
+*
+* @note		The default state of the CONVST bit is a logic 0. The conversion
+*		is started when the CONVST bit is set to 1 from 0.
+*		This bit is self-clearing so that the next conversion
+*		can be started by setting this bit.
+*
+*****************************************************************************/
+void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr)
+{
+	u32 ControlStatus;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Start the conversion by setting the CONVST bit to 1 only if auto-convst
+	 * bit is not enabled. This convst bit is self-clearing.
+	 */
+	ControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+
+	if ((ControlStatus & XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK )
+			!= XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK) {
+		XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_PS_SYSMON_CSTS_OFFSET,
+					(ControlStatus | (u32)XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK));
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Channel is the channel number. Use the XSM_CH_* defined in
+*		the file xsysmonpsu.h. The valid channels for PS / PL SysMon are 0 - 6,
+*		8 - 10 and 13 - 37. For AMS, 38 - 53 channels are valid.
+* @param	Block is the value that tells whether it is for PS Sysmon block
+*       or PL Sysmon block or the AMS controller register region.
+*
+* @return	A 16-bit value representing the ADC converted data for the
+*		specified channel. The System Monitor device guarantees
+* 		a 10 bit resolution for the ADC converted data and data is the
+*		10 MSB bits of the 16 data read from the device.
+*
+* @note		Please make sure that the proper channel number is passed.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block)
+{
+	u16 AdcData;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
+			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
+			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
+			  ((Channel >= XSM_CH_SUPPLY4) &&
+			  (Channel <= XSM_CH_RESERVE1)));
+	Xil_AssertNonvoid((Block == XSYSMON_PS)||(Block == XSYSMON_PL)
+						||(Block == XSYSMON_AMS));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					Block);
+
+	/*
+	 * Read the selected ADC converted data for the specified channel
+	 * and return the value.
+	 */
+	if (Channel <= XSM_CH_AUX_MAX) {
+		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + ((u32)Channel << 2U)));
+	} else if ((Channel >= XSM_CH_SUPPLY7) && (Channel <= XSM_CH_TEMP_REMTE)){
+		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_ADC_CH_OFFSET +
+				(((u32)Channel - XSM_CH_SUPPLY7) << 2U)));
+	} else {
+		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_AMS_CH_OFFSET +
+				(((u32)Channel - XSM_CH_VCC_PSLL0) << 2U)));
+	}
+
+	return AdcData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	CoeffType specifies the calibration coefficient
+*		to be read. Use XSM_CALIB_* constants defined in xsysmonpsu.h to
+*		specify the calibration coefficient to be read.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 16-bit value representing the calibration coefficient.
+*		The System Monitor device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType,
+		u32 SysmonBlk)
+{
+	u16 CalibData;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(CoeffType <= XSM_CALIB_GAIN_ERROR_COEFF);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the selected calibration coefficient. */
+	CalibData = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CAL_SUP_OFF_OFFSET + ((u32)CoeffType << 2U));
+
+	return CalibData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* XSM_MIN_* or XSM_MAX_* constants defined in xsysmonpsu.h
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	MeasurementType specifies the parameter for which the
+*		Minimum/Maximum measurement has to be read.
+*		Use XSM_MAX_* and XSM_MIN_* constants defined in xsysmonpsu.h to
+*		specify the data to be read.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 16-bit value representing the maximum/minimum measurement for
+*		specified parameter.
+*		The System Monitor device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of  16 bit
+*		data read from the device.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
+		u32 SysmonBlk)
+{
+	u16 MinMaxData;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((MeasurementType <= XSM_MAX_SUPPLY6) ||
+			((MeasurementType >= XSM_MIN_SUPPLY4) &&
+			(MeasurementType <= XSM_MIN_SUPPLY6)) ||
+			((MeasurementType >= XSM_MAX_SUPPLY7) &&
+			(MeasurementType <= XSM_MAX_TEMP_REMOTE)) ||
+			((MeasurementType >= XSM_MIN_SUPPLY7) &&
+			(MeasurementType <= XSM_MIN_TEMP_REMOTE)));
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read and return the specified Minimum/Maximum measurement. */
+	MinMaxData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+							XSM_MIN_MAX_CH_OFFSET + ((u32)MeasurementType << 2U)));
+
+	return MinMaxData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Average is the number of samples of averaging programmed to the
+*		Configuration Register 0. Use the XSM_AVG_* definitions defined
+*		in xsysmonpsu.h file :
+*		- XSM_AVG_0_SAMPLES for no averaging
+*		- XSM_AVG_16_SAMPLES for 16 samples of averaging
+*		- XSM_AVG_64_SAMPLES for 64 samples of averaging
+*		- XSM_AVG_256_SAMPLES for 256 samples of averaging
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAvg(XSysMonPsu *InstancePtr, u8 Average, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Average <= XSM_AVG_256_SAMPLES);
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Write the averaging value into the Configuration Register 0. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET)
+						& (u32)(~XSYSMONPSU_CFG_REG0_AVRGNG_MASK);
+	RegValue |= (((u32) Average << XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT));
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	The averaging read from the Configuration Register 0 is
+*		returned. Use the XSM_AVG_* bit definitions defined in xsysmonpsu.h
+*		file to interpret the returned value :
+*		- XSM_AVG_0_SAMPLES means no averaging
+*		- XSM_AVG_16_SAMPLES means 16 samples of averaging
+*		- XSM_AVG_64_SAMPLES means 64 samples of averaging
+*		- XSM_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XSysMonPsu_GetAvg(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 Average;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the averaging value from the Configuration Register 0. */
+	Average = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+				XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
+
+	return (u8)(Average >> XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Channel is the channel number for conversion. The valid
+*		channels are 0 - 6, 8 - 10, 13 - 37.
+* @param	IncreaseAcqCycles is a boolean parameter which specifies whether
+*		the Acquisition time for the external channels has to be
+*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+*		default 4 ADCCLK cycles (specify FALSE). This parameter is
+*		only valid for the external channels.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the given channel.
+* @param	IsDifferentialMode is a boolean parameter which specifies
+*		unipolar(specify FALSE) or differential mode (specify TRUE) for
+*		the analog inputs. The 	input mode is only valid for the
+*		external channels.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note
+*		- The number of samples for the averaging for all the channels
+*		is set by using the function XSysMonPsu_SetAvg.
+*		- The calibration of the device is done by doing a ADC
+*		conversion on the calibration channel(channel 8). The input
+*		parameters IncreaseAcqCycles, IsDifferentialMode and
+*		IsEventMode are not valid for this channel.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
+				u32 IncreaseAcqCycles, u32 IsEventMode,
+				u32 IsDifferentialMode, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+	s32 Status;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
+			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
+			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
+			  ((Channel >= XSM_CH_SUPPLY4) &&
+			  (Channel <= XSM_CH_TEMP_REMTE)));
+	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+			  (IncreaseAcqCycles == FALSE));
+	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+			  (IsDifferentialMode == FALSE));
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Check if the device is in single channel mode else return failure */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
+				!= XSM_SEQ_MODE_SINGCHAN)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the Configuration Register 0 and extract out Averaging value. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
+
+	/*
+	 * Select the number of acquisition cycles. The acquisition cycles is
+	 * only valid for the external channels.
+	 */
+	if (IncreaseAcqCycles == TRUE) {
+		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
+		    || (Channel == XSM_CH_VPVN)) {
+			RegValue |= XSYSMONPSU_CFG_REG0_ACQ_MASK;
+		} else {
+			Status = (s32)XST_FAILURE;
+			goto End;
+		}
+	}
+
+	/*
+	 * Select the input mode. The input mode is only valid for the
+	 * external channels.
+	 */
+	if (IsDifferentialMode == TRUE) {
+
+		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
+		    || (Channel == XSM_CH_VPVN)) {
+			RegValue |= XSYSMONPSU_CFG_REG0_BU_MASK;
+		} else {
+			Status = (s32)XST_FAILURE;
+			goto End;
+		}
+	}
+
+	/* Select the ADC mode. */
+	if (IsEventMode == TRUE) {
+		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
+	}
+
+	/* Write the given values into the Configuration Register 0. */
+	RegValue |= ((u32)Channel & XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Registers 1:
+*
+*		- OT for Over Temperature (XSYSMONPSU_CFR_REG1_ALRM_OT_MASK)
+*		- ALM0 for On board Temperature (XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK)
+*		- ALM1 for SUPPLY1 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY1_MASK)
+*		- ALM2 for SUPPLY2 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY2_MASK)
+* 		- ALM3 for SUPPLY3 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY3_MASK)
+* 		- ALM4 for SUPPLY4 (XSYSMONPSU_CFR_REG1_ALRM__SUPPLY4_MASK)
+*		- ALM5 for SUPPLY5 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY5_MASK)
+* 		- ALM6 for SUPPLY6 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY6_MASK)
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+*		in the Configuration Registers 1 and 3.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will be
+*		disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
+*		masks defined in xsysmonpsu.h, but XSM_CFR_ALM_SUPPLY8_MASK to
+*		XSM_CFR_ALM_SUPPLY13_MASK are applicable only for PS.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that the alarms for bit positions of 0 will
+*		be enabled and alarms for bit positions of 1 will be disabled.
+*		The alarm outputs specified by the AlmEnableMask are negated
+*		before writing to the Configuration Register 1 because it
+*		was Disable register bits.
+*		Upper 16 bits of AlmEnableMask are applicable only for PS.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
+		u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(AlmEnableMask <=
+			(XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK |
+			(XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT)));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG1_OFFSET);
+	RegValue &= (u32)(~XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+	RegValue |= (~AlmEnableMask & (u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+
+	/*
+	 * Enable/disables the alarm enables for the specified alarm bits in the
+	 * Configuration Register 1.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
+			 RegValue);
+	/* Upper 16 bits of AlmEnableMask are valid only for PS */
+	if (SysmonBlk == XSYSMON_PS) {
+		RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG3_OFFSET);
+		RegValue &= (u32)(~XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+		RegValue |= (~(AlmEnableMask >> XSM_CFG_ALARM_SHIFT) &
+				(u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG3_OFFSET, RegValue);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	This is the bit-mask of the enabled alarm outputs in the
+*		Configuration Register 1. Use the masks XSYSMONPSU_CFG_REG1_ALRM_*_MASK
+*		masks defined in xsysmonpsu.h to interpret the returned value.
+*
+*		Bit positions of 1 indicate that the alarm output is enabled.
+*		Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that alarms for the bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The enabled alarm outputs returned by this function is the
+*		negated value of the the data read from the Configuration
+*		Register 1. Upper 16 bits of return value are valid only if the
+*		channel selected is PS.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+	u32 ReadReg;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the status of alarm output enables from the Configuration
+	 * Register 1.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK;
+	RegValue = (~RegValue & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+
+	if (SysmonBlk == XSYSMON_PS) {
+		ReadReg = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG3_OFFSET) & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK;
+		ReadReg = (~ReadReg & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+		RegValue |= ReadReg << XSM_CFG_ALARM_SHIFT;
+	}
+
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+*		- Default safe mode (XSM_SEQ_MODE_SAFE)
+*		- One pass through sequence (XSM_SEQ_MODE_ONEPASS)
+*		- Continuous channel sequencing (XSM_SEQ_MODE_CONTINPASS)
+*		- Single Channel/Sequencer off (XSM_SEQ_MODE_SINGCHAN)
+*		- Olympus sampling mode (XSM_SEQ_MODE_OYLMPUS)
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SequencerMode is the sequencer mode to be set.
+*		Use XSM_SEQ_MODE_* bits defined in xsysmonpsu.h.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		Only one of the modes can be enabled at a time.
+*
+*****************************************************************************/
+void XSysMonPsu_SetSequencerMode(XSysMonPsu *InstancePtr, u8 SequencerMode,
+		u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SequencerMode <= XSM_SEQ_MODE_SINGCHAN) ||
+			(SequencerMode == XSM_SEQ_MODE_OYLMPUS));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Set the specified sequencer mode in the Configuration Register 1. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG1_OFFSET);
+	RegValue &= (u32)(~ XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
+	RegValue |= (((u32)SequencerMode  << XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT) &
+					XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG1_OFFSET, RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	The channel sequencer mode :
+*		- XSM_SEQ_MODE_SAFE : Default safe mode
+*		- XSM_SEQ_MODE_ONEPASS : One pass through sequence
+*		- XSM_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+*		- XSM_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+*		- XSM_SEQ_MODE_OLYMPUS : Olympus sampling mode
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XSysMonPsu_GetSequencerMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u8 SequencerMode;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the channel sequencer mode from the Configuration Register 1. */
+	SequencerMode =  ((u8) ((XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK) >>
+			XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT));
+
+	return SequencerMode;
+}
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the channel.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetSequencerEvent(XSysMonPsu *InstancePtr, u32 IsEventMode,
+		u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the Configuration Register 0. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+
+	/* Set the ADC mode. */
+	if (IsEventMode == TRUE) {
+		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
+	} else {
+		RegValue &= (u32)(~XSYSMONPSU_CFG_REG0_EC_MASK);
+	}
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* The function returns the mode of the sequencer.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	Returns the Sequencer mode. XSYSMONPSU_EVENT_MODE for Event mode
+* 		and XSYSMONPSU_CONTINUOUS_MODE for continuous mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_GetSequencerEvent(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	s32 Mode;
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the Configuration Register 0. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+
+	RegValue &= XSYSMONPSU_CFG_REG0_EC_MASK;
+
+	if (RegValue == XSYSMONPSU_CFG_REG0_EC_MASK) {
+		Mode = XSYSMONPSU_EVENT_MODE;
+	} else {
+		Mode = XSYSMONPSU_CONTINUOUS_MODE;
+	}
+
+	return Mode;
+}
+
+/****************************************************************************/
+/**
+*
+* The function enables the external mux and connects a channel to the mux.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Channel is the channel number used to connect to the external
+*		Mux. The valid channels are 0 to 5 and 16 to 31.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Channel <= XSM_CH_VREFN) ||
+			  ((Channel >= XSM_CH_AUX_MIN) &&
+			  (Channel <= XSM_CH_AUX_MAX)));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the Configuration Register 0 and the clear the channel selection
+	 * bits.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+	RegValue &= ~(XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
+
+	/* Enable the External Mux and select the channel. */
+	RegValue |= (XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK | (u32)Channel);
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* The function returns the external mux channel.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	Returns the channel number used to connect to the external
+*		Mux. The valid channels are 0 to 6, 8 to 16, and 31 to 36..
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the Configuration Register 0 and derive the channel selection
+	 * bits.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+	RegValue &= XSYSMONPSU_CFG_REG0_MUX_CH_MASK;
+
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
+*		Valid values of the divisor are
+*		PS:
+*		 - 0 means divide by 8.
+*		 - 1,2 means divide by 2.
+*		 - 3 to 255 means divide by that value.
+*       PL:
+*		 - 0,1,2 means divide by 2.
+*		 - 3 to 255 means divide by that value.
+*		Refer to the device specification for more details.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		- The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*		- There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor,
+            u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the Configuration Register 2 and the clear the clock divisor
+	 * bits.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG2_OFFSET);
+	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);
+
+	/* Write the divisor value into the Configuration Register 2. */
+	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
+					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
+			 RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param	InstancePtr is a pointer to the XSysMon instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	The divisor read from the Configuration Register 2.
+*
+* @note		The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u16 Divisor;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the divisor value from the Configuration Register 2. */
+	Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
+							XSYSMONPSU_CFG_REG2_OFFSET);
+
+	return (u8) (Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be in the Safe Mode before writing
+* to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	ChEnableMask is the bit mask of all the channels to be enabled.
+*		Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
+*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+*		be disabled.
+*		The ChEnableMask is a 64 bit mask that is written to the three
+*		16 bit ADC Channel Selection Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Selection Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/*
+	 * The sequencer must be in the Default Safe Mode before writing
+	 * to these registers. Return XST_FAILURE if the channel sequencer
+	 * is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk) != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Enable the specified channels in the ADC Channel Selection Sequencer
+	 * Registers.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET,
+			 (ChEnableMask & XSYSMONPSU_SEQ_CH0_VALID_MASK));
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET,
+			 (ChEnableMask >> XSM_SEQ_CH_SHIFT) &
+			 XSYSMONPSU_SEQ_CH1_VALID_MASK);
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET,
+				 (ChEnableMask >> XSM_SEQ_CH2_SHIFT) &
+			 XSYSMONPSU_SEQ_CH2_VALID_MASK);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	Gets the channel enable bits. Use XSYSMONPSU_SEQ_CH* defined in
+*		xsysmonpsu_hw.h to interpret the Channel numbers. Bit masks of 1
+*		are the channels that are enabled and bit mask of 0 are
+*		the channels that are disabled.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u64 RegVal;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the channel enable bits for all the channels from the ADC
+	 * Channel Selection Register.
+	 */
+	RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_CH0_OFFSET) & XSYSMONPSU_SEQ_CH0_VALID_MASK;
+	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
+					XSM_SEQ_CH_SHIFT;
+	RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_CH2_OFFSET) &
+			XSYSMONPSU_SEQ_CH2_VALID_MASK) << XSM_SEQ_CH2_SHIFT;
+
+	return RegVal;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be in
+* the Safe Mode before writing to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AvgEnableChMask is the bit mask of all the channels for which
+*		averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
+*		xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
+*		enabled for bit masks of 1 and disabled for bit mask of 0.
+*		The AvgEnableChMask is a 64 bit mask that is written to the
+*		three 16 bit ADC Channel Averaging Enable Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Averaging Enables Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers.
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
+	                                     != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+	} else {
+		/* Calculate the effective baseaddress based on the Sysmon instance. */
+		EffectiveBaseAddress =
+				XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+						SysmonBlk);
+		/*
+		 * Enable/disable the averaging for the specified channels in the
+		 * ADC Channel Averaging Enables Sequencer Registers.
+		 */
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+				XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
+				(AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
+
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+				XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
+				 (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
+				 XSYSMONPSU_SEQ_AVERAGE1_MASK);
+
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+				XSYSMONPSU_SEQ_AVERAGE2_OFFSET,
+				 (AvgEnableChMask >> XSM_SEQ_CH2_SHIFT) &
+				 XSYSMONPSU_SEQ_AVERAGE2_MASK);
+
+		Status = (s32)XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @returns 	The status of averaging (enabled/disabled) for all the channels.
+*		Use XSYSMONPSU_SEQ_AVERAGE* defined in xsysmonpsu_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		averaging is enabled and bit mask of 0 are the channels for
+*		averaging is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u64 RegVal;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the averaging enable status for all the channels from the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE0_OFFSET) & XSYSMONPSU_SEQ_AVERAGE0_MASK;
+	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE1_OFFSET) & XSYSMONPSU_SEQ_AVERAGE1_MASK) <<
+			XSM_SEQ_CH_SHIFT;
+	RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE2_OFFSET) &
+			XSYSMONPSU_SEQ_AVERAGE2_MASK) << XSM_SEQ_CH2_SHIFT;
+
+	return RegVal;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the
+* ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be in
+* the Safe Mode before writing to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	InputModeChMask is the bit mask of all the channels for which
+*		the input mode is differential mode. Use XSYSMONPSU_SEQ_INPUT_MDE*
+*		defined in xsysmonpsu_hw.h to specify the channel numbers. Differential
+*		or  Bipolar input mode will be set for bit masks of 1 and unipolar input
+*		mode for bit masks of 0.
+*		The InputModeChMask is a 64 bit mask that is written to the three
+*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Analog-Input Mode Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/*
+	 * The sequencer must be in the Safe Mode before writing to
+	 * these registers. Return XST_FAILURE if the channel sequencer
+	 * is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
+	                                      != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Set the input mode for the specified channels in the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET,
+			 (InputModeChMask & XSYSMONPSU_SEQ_INPUT_MDE0_MASK));
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET,
+			 (InputModeChMask >> XSM_SEQ_CH_SHIFT) &
+			 XSYSMONPSU_SEQ_INPUT_MDE1_MASK);
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+		XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET,
+		 (InputModeChMask >> XSM_SEQ_CH2_SHIFT) &
+		 XSYSMONPSU_SEQ_INPUT_MDE2_MASK);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @returns 	The input mode for all the channels.
+*		Use XSYSMONPSU_SEQ_INPUT_MDE* defined in xsysmonpsu_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		input mode is differential/Bipolar and bit mask of 0 are the channels
+*		for which input mode is unipolar.
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u64 InputMode;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 *  Get the input mode for all the channels from the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	InputMode = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE0_MASK;
+	InputMode |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE1_MASK) <<
+				XSM_SEQ_CH_SHIFT;
+	InputMode |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET) &
+			XSYSMONPSU_SEQ_INPUT_MDE2_MASK) << XSM_SEQ_CH2_SHIFT;
+
+	return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
+* before writing to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AcqCyclesChMask is the bit mask of all the channels for which
+*		the number of acquisition cycles is to be extended.
+*		Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to specify the Channel
+*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
+*		bit masks of 0.
+*		The AcqCyclesChMask is a 64 bit mask that is written to the three
+*		16 bit ADC Channel Acquisition Time Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Channel Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/*
+	 * The sequencer must be in the Safe Mode before writing
+	 * to these registers. Return XST_FAILURE if the channel
+	 * sequencer is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
+	                                     != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Set the Acquisition time for the specified channels in the
+	 * ADC Channel Acquisition Time Sequencer Registers.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ0_OFFSET,
+			 (AcqCyclesChMask & XSYSMONPSU_SEQ_ACQ0_MASK));
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
+			 (AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) & XSYSMONPSU_SEQ_ACQ1_MASK);
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET,
+			(AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT) &
+					XSYSMONPSU_SEQ_ACQ2_MASK);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition time from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @returns 	The acquisition time for all the channels.
+*		Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		acquisition cycles are extended and bit mask of 0 are the
+*		channels for which acquisition cycles are not extended.
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u64 RegValAcq;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Get the Acquisition cycles for the specified channels from the ADC
+	 * Channel Acquisition Time Sequencer Registers.
+	 */
+	RegValAcq = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_SEQ_ACQ0_OFFSET) & XSYSMONPSU_SEQ_ACQ0_MASK;
+	RegValAcq |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_SEQ_ACQ1_OFFSET) & XSYSMONPSU_SEQ_ACQ1_MASK) <<
+					XSM_SEQ_CH_SHIFT;
+	RegValAcq |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_ACQ2_OFFSET) &
+			XSYSMONPSU_SEQ_ACQ2_MASK) << XSM_SEQ_CH2_SHIFT;
+
+	return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register to
+*		be set. Use XSM_ATR_* constants defined in xsysmonpsu.h to
+*		specify the index.
+* @param	Value is the 16-bit threshold value to write into the register.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u16 Value, u32 SysmonBlk)
+{
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
+			((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
+			(AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Write the value into the specified Alarm Threshold Register. */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_ALRM_TEMP_UPR_OFFSET +
+			((u32)AlarmThrReg << 2U), Value);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register
+*		to be read. Use XSM_ATR_* constants defined in xsysmonpsu.h
+*		to specify the index.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 16-bit value representing the contents of the selected Alarm
+*		Threshold Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u32 SysmonBlk)
+{
+	u16 AlarmThreshold;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
+			((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
+			(AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the specified Alarm Threshold Register and return
+	 * the value.
+	 */
+	AlarmThreshold = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_ALRM_TEMP_UPR_OFFSET + ((u32)AlarmThrReg << 2));
+
+	return AlarmThreshold;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the conversion to be automatic for PS SysMon.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	None
+*
+* @note		In the auto-trigger mode, sample rate is of 1 Million samples.
+*
+*****************************************************************************/
+void XSysMonPsu_SetPSAutoConversion(XSysMonPsu *InstancePtr)
+{
+	u32 PSSysMonStatusReg;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Set the automatic conversion triggering in PS control register. */
+	PSSysMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+	PSSysMonStatusReg |= XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK;
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET, PSSysMonStatusReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the AMS monitor status.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	Returns the monitor status. See XSYSMONPSU_MON_STS_*_MASK
+* 		definations present in xsysmonpsu_hw.h for knowing the status.
+*
+* @note		None
+* .
+*****************************************************************************/
+u32 XSysMonPsu_GetMonitorStatus(XSysMonPsu *InstancePtr)
+{
+	u32 AMSMonStatusReg;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the AMS monitor status. This gives tells about JTAG Locked / ADC
+	 * busy / ADC Current Channel number and its ADC output.
+	 */
+	AMSMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_MON_STS_OFFSET);
+
+	return AMSMonStatusReg;
+}
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
new file mode 100644
index 000000000..ba090c5aa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
@@ -0,0 +1,610 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xsysmonpsu.h
+*
+* The XSysMon driver supports the Xilinx System Monitor device.
+*
+* The System Monitor device has the following features:
+*	- PL Sysmon instance has 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- PS Sysmon instance has 10-bit, 1000-KSPS ADC.
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*	- External Mux
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the System Monitor device.
+*
+*
+* <b> System Monitor Channel Sequencer Modes </b>
+*
+* The  System Monitor Channel Sequencer supports the following operating modes:
+*
+*   - <b> Default </b>: This is the default mode after power up.
+*		In this mode of operation the System Monitor operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   - <b> One pass through sequence </b>: In this mode the System Monitor
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   - <b> Continuous cycling of sequence </b>: In this mode the System Monitor
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   - <b> Single channel mode</b>: In this mode the System Monitor Channel
+*		Sequencer is disabled and the System Monitor operates in a
+*		Single Channel Mode.
+*		The System Monitor can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the System Monitor device.
+*
+* XSysMonPsu_CfgInitialize() API is used to initialize the System Monitor
+* device. The user needs to first call the XSysMonPsu_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XSysMonPsu_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The System Monitor device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XSysMonPsu driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+* <b> Limitations of the driver </b>
+*
+* System Monitor device can be accessed through the JTAG port and the AXI
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to take care of this
+* situation in the user application code.
+*
+*
+*
+* <br><br>
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    12/15/15 First release
+*              02/15/16 Corrected Assert function call in
+*                       XSysMonPsu_GetMonitorStatus API.
+*              03/03/16 Added Temperature remote channel for Setsingle
+*                       channel API. Also corrected external mux channel
+*                       numbers.
+* 1.1   kvn    05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0   vns    08/14/16 Fixed CR #956780, added support for enabling/disabling
+*                       SEQ_CH2 and SEQ_AVG2 registers, modified function
+*                       prototypes of XSysMonPsu_GetSeqAvgEnables,
+*                       XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+*                       XSysMonPsu_GetSeqChEnables,
+*                       XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+*                       XSysMonPsu_SetSeqAcqTime
+*                       and XSysMonPsu_GetSeqAcqTime to provide support for
+*                       set/get 64 bit value.
+*                       Added constants XSM_CFR_ALM_SUPPLY*(8-31)_MASKs to
+*                       provide support for enabling extra PS alarams.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef XSYSMONPSU_H_			/* prevent circular inclusions */
+#define XSYSMONPSU_H_			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xsysmonpsu_hw.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XSM_CH_TEMP 		0x0U  /**< On Chip Temperature */
+#define XSM_CH_SUPPLY1		0x1U  /**< SUPPLY1 VCC_PSINTLP */
+#define XSM_CH_SUPPLY2		0x2U  /**< SUPPLY2 VCC_PSINTFP */
+#define XSM_CH_VPVN 		0x3U  /**< VP/VN Dedicated analog inputs */
+#define XSM_CH_VREFP		0x4U  /**< VREFP */
+#define XSM_CH_VREFN		0x5U  /**< VREFN */
+#define XSM_CH_SUPPLY3		0x6U  /**< SUPPLY3 VCC_PSAUX */
+#define XSM_CH_SUPPLY_CALIB	0x08U /**< Supply Calib Data Reg */
+#define XSM_CH_ADC_CALIB	0x09U /**< ADC Offset Channel Reg */
+#define XSM_CH_GAINERR_CALIB 	0x0AU /**< Gain Error Channel Reg  */
+#define XSM_CH_SUPPLY4		0x0DU /**< SUPPLY4 VCC_PSDDR_504 */
+#define XSM_CH_SUPPLY5		0x0EU /**< SUPPLY5 VCC_PSIO3_503 */
+#define XSM_CH_SUPPLY6		0x0FU /**< SUPPLY6 VCC_PSIO0_500 */
+#define XSM_CH_AUX_MIN		16U   /**< Channel number for 1st Aux Channel */
+#define XSM_CH_AUX_MAX		31U   /**< Channel number for Last Aux channel */
+#define XSM_CH_SUPPLY7      32U   /**< SUPPLY7 VCC_PSIO1_501 */
+#define XSM_CH_SUPPLY8      33U   /**< SUPPLY8 VCC_PSIO2_502 */
+#define XSM_CH_SUPPLY9      34U   /**< SUPPLY9 PS_MGTRAVCC */
+#define XSM_CH_SUPPLY10     35U   /**< SUPPLY10 PS_MGTRAVTT */
+#define XSM_CH_VCCAMS       36U   /**< VCCAMS */
+#define XSM_CH_TEMP_REMTE   37U   /**< Temperature Remote */
+#define XSM_CH_VCC_PSLL0    38U   /**< VCC_PSLL0 */
+#define XSM_CH_VCC_PSLL1    39U   /**< VCC_PSLL1 */
+#define XSM_CH_VCC_PSLL2    40U   /**< VCC_PSLL2 */
+#define XSM_CH_VCC_PSLL3    41U   /**< VCC_PSLL3 */
+#define XSM_CH_VCC_PSLL4    42U   /**< VCC_PSLL4 */
+#define XSM_CH_VCC_PSBATT   43U   /**< VCC_PSBATT */
+#define XSM_CH_VCCINT       44U   /**< VCCINT */
+#define XSM_CH_VCCBRAM      45U   /**< VCCBRAM */
+#define XSM_CH_VCCAUX       46U   /**< VCCAUX */
+#define XSM_CH_VCC_PSDDRPLL 47U   /**< VCC_PSDDRPLL */
+#define XSM_CH_DDRPHY_VREF  48U   /**< DDRPHY_VREF */
+#define XSM_CH_DDRPHY_AT0   49U   /**< DDRPHY_AT0 */
+#define XSM_CH_PSGT_AT0     50U   /**< PSGT_AT0 */
+#define XSM_CH_PSGT_AT1     51U   /**< PSGT_AT0 */
+#define XSM_CH_RESERVE0     52U   /**< PSGT_AT0 */
+#define XSM_CH_RESERVE1     53U   /**< PSGT_AT0 */
+
+/*@}*/
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XSM_CALIB_SUPPLY_OFFSET_COEFF 0U /**< Supply Offset Calib Coefficient */
+#define XSM_CALIB_ADC_OFFSET_COEFF    1U /**< ADC Offset Calib Coefficient */
+#define XSM_CALIB_GAIN_ERROR_COEFF    2U /**< Gain Error Calib Coefficient*/
+
+/*@}*/
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XSM_MAX_TEMP		0U    /**< Maximum Temperature Data */
+#define XSM_MAX_SUPPLY1		1U    /**< Maximum SUPPLY1 Data */
+#define XSM_MAX_SUPPLY2		2U    /**< Maximum SUPPLY2 Data */
+#define XSM_MAX_SUPPLY3		3U    /**< Maximum SUPPLY3 Data */
+#define XSM_MIN_TEMP		4U    /**< Minimum Temperature Data */
+#define XSM_MIN_SUPPLY1		5U    /**< Minimum SUPPLY1 Data */
+#define XSM_MIN_SUPPLY2     6U    /**< Minimum SUPPLY2 Data */
+#define XSM_MIN_SUPPLY3     7U    /**< Minimum SUPPLY3 Data */
+#define XSM_MAX_SUPPLY4		8U    /**< Maximum SUPPLY4 Data */
+#define XSM_MAX_SUPPLY5		9U    /**< Maximum SUPPLY5 Data */
+#define XSM_MAX_SUPPLY6		0xAU  /**< Maximum SUPPLY6 Data */
+#define XSM_MIN_SUPPLY4     0xCU  /**< Minimum SUPPLY4 Data */
+#define XSM_MIN_SUPPLY5     0xDU  /**< Minimum SUPPLY5 Data */
+#define XSM_MIN_SUPPLY6     0xEU  /**< Minimum SUPPLY6 Data */
+#define XSM_MAX_SUPPLY7		0x80U  /**< Maximum SUPPLY7 Data */
+#define XSM_MAX_SUPPLY8		0x81U  /**< Maximum SUPPLY8 Data */
+#define XSM_MAX_SUPPLY9		0x82U  /**< Maximum SUPPLY9 Data */
+#define XSM_MAX_SUPPLY10	0x83U  /**< Maximum SUPPLY10 Data */
+#define XSM_MAX_VCCAMS  	0x84U  /**< Maximum VCCAMS Data */
+#define XSM_MAX_TEMP_REMOTE  	0x85U  /**< Maximum Remote Temperature Data */
+#define XSM_MIN_SUPPLY7     0x88U  /**< Minimum SUPPLY7 Data */
+#define XSM_MIN_SUPPLY8     0x89U  /**< Minimum SUPPLY8 Data */
+#define XSM_MIN_SUPPLY9     0x8AU  /**< Minimum SUPPLY9 Data */
+#define XSM_MIN_SUPPLY10    0x8BU  /**< Minimum SUPPLY10 Data */
+#define XSM_MIN_VCCAMS      0x8CU  /**< Minimum VCCAMS Data */
+#define XSM_MIN_TEMP_REMOTE     0x8DU  /**< Minimum Remote Temperature Data */
+
+/*@}*/
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XSM_AVG_0_SAMPLES	0U /**< No Averaging */
+#define XSM_AVG_16_SAMPLES	1U /**< Average 16 samples */
+#define XSM_AVG_64_SAMPLES	2U /**< Average 64 samples */
+#define XSM_AVG_256_SAMPLES	3U /**< Average 256 samples */
+
+/*@}*/
+
+/**
+ * @name Channel Sequencer Modes of operation.
+ * @{
+ */
+#define XSM_SEQ_MODE_SAFE	 0U /**< Default Safe Mode */
+#define XSM_SEQ_MODE_ONEPASS	 1U /**< Onepass through Sequencer */
+#define XSM_SEQ_MODE_CONTINPASS	 2U /**< Continuous Cycling Seqquencer */
+#define XSM_SEQ_MODE_SINGCHAN	 3U /**< Single channel - No Sequencing */
+#define XSM_SEQ_MODE_OYLMPUS	 6U /**< Olympus mode */
+
+/*@}*/
+
+/**
+ * @name Clock Divisor values range.
+ * @{
+ */
+#define XSM_CLK_DIV_MIN	 0U /**< Minimum Clock Divisor value */
+#define XSM_CLK_DIV_MAX	 255U /**< Maximum Clock Divisor value */
+
+/*@}*/
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XSM_ATR_TEMP_UPPER	 0U   /**< High user Temperature limit */
+#define XSM_ATR_SUP1_UPPER	 1U   /**< Supply1 high voltage limit */
+#define XSM_ATR_SUP2_UPPER	 2U   /**< Supply2 high voltage limit */
+#define XSM_ATR_OT_UPPER	 3U   /**< Upper Over Temperature limit */
+#define XSM_ATR_TEMP_LOWER	 4U   /**< Low user Temperature */
+#define XSM_ATR_SUP1_LOWER	 5U   /**< Suuply1 low voltage limit */
+#define XSM_ATR_SUP2_LOWER	 6U   /**< Supply2 low voltage limit */
+#define XSM_ATR_OT_LOWER	 7U   /**< Lower Over Temperature limit */
+#define XSM_ATR_SUP3_UPPER	 8U   /**< Supply3 high voltage limit */
+#define XSM_ATR_SUP4_UPPER 	 9U   /**< Supply4 high voltage limit */
+#define XSM_ATR_SUP5_UPPER 	 0xAU /**< Supply5 high voltage limit */
+#define XSM_ATR_SUP6_UPPER 	 0xBU /**< Supply6 high voltage limit */
+#define XSM_ATR_SUP3_LOWER	 0xCU /**< Supply3 low voltage limit */
+#define XSM_ATR_SUP4_LOWER 	 0xDU /**< Supply4 low voltage limit */
+#define XSM_ATR_SUP5_LOWER 	 0xEU /**< Supply5 low voltage limit */
+#define XSM_ATR_SUP6_LOWER 	 0xFU /**< Supply6 low voltage limit */
+#define XSM_ATR_SUP7_UPPER	 0x10U /**< Supply7 high voltage limit */
+#define XSM_ATR_SUP8_UPPER	 0x11U /**< Supply8 high voltage limit */
+#define XSM_ATR_SUP9_UPPER	 0x12U /**< Supply9 high voltage limit */
+#define XSM_ATR_SUP10_UPPER	 0x13U /**< Supply10 high voltage limit */
+#define XSM_ATR_VCCAMS_UPPER	 0x14U /**< VCCAMS high voltage limit */
+#define XSM_ATR_TEMP_RMTE_UPPER	 0x15U /**< High remote Temperature limit */
+#define XSM_ATR_SUP7_LOWER	 0x18U /**< Supply7 low voltage limit */
+#define XSM_ATR_SUP8_LOWER	 0x19U /**< Supply8 low voltage limit */
+#define XSM_ATR_SUP9_LOWER	 0x1AU /**< Supply9 low voltage limit */
+#define XSM_ATR_SUP10_LOWER	 0x1BU /**< Supply10 low voltage limit */
+#define XSM_ATR_VCCAMS_LOWER	 0x1CU /**< VCCAMS low voltage limit */
+#define XSM_ATR_TEMP_RMTE_LOWER	 0x1DU /**< Low remote Temperature limit */
+
+/*@}*/
+
+/**
+ * @name Alarm masks for channels in Configuration registers 1
+ * @{
+ */
+#define XSM_CFR_ALM_SUPPLY13_MASK	0x200000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY12_MASK	0x100000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY11_MASK	0x080000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY10_MASK	0x040000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY9_MASK	0x020000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY8_MASK	0x010000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY6_MASK	0x0800 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY5_MASK	0x0400 /**< Alarm 5 - SUPPLY5 */
+#define XSM_CFR_ALM_SUPPLY4_MASK	0x0200 /**< Alarm 4 - SUPPLY4 */
+#define XSM_CFR_ALM_SUPPLY3_MASK 	0x0100 /**< Alarm 3 - SUPPLY3 */
+#define XSM_CFR_ALM_SUPPLY2_MASK	0x0008 /**< Alarm 2 - SUPPLY2 */
+#define XSM_CFR_ALM_SUPPLY1_MASK	0x0004 /**< Alarm 1 - SUPPLY1 */
+#define XSM_CFR_ALM_TEMP_MASK		0x0002 /**< Alarm 0 - Temperature */
+#define XSM_CFR_ALM_OT_MASK		0x0001 /**< Over Temperature Alarm */
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ *
+ ******************************************************************************/
+typedef void (*XSysMonPsu_Handler) (void *CallBackRef);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddress;		/**< Register base address */
+} XSysMonPsu_Config;
+
+/**
+ * The XSysmonPsu driver instance data. The user is required to allocate a
+ * variable of this type for the SYSMON device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSysMonPsu_Config Config; 	/**< Device configuration */
+	u32 IsReady;				/**< Device is initialized and ready */
+	XSysMonPsu_Handler Handler;
+	void *CallBackRef;			/**< Callback reference for event handler */
+} XSysMonPsu;
+
+/* BaseAddress Offsets */
+#define XSYSMON_PS 1U
+#define XSYSMON_PL 2U
+#define XSYSMON_AMS 3U
+#define XPS_BA_OFFSET   0x00000800U
+#define XPL_BA_OFFSET   0x00000C00U
+#define XSM_ADC_CH_OFFSET 0x00000200U
+#define XSM_AMS_CH_OFFSET 0x00000060U
+#define XSM_MIN_MAX_CH_OFFSET 0x00000080U
+
+/************************* Variable Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro converts System Monitor Raw Data to Temperature(centigrades)
+* for On-Chip Sensors.
+*
+* @param	AdcData is the SysMon Raw ADC Data.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XSysMon_RawToTemperature_OnChip(u32 AdcData)
+*
+*****************************************************************************/
+#define XSysMonPsu_RawToTemperature_OnChip(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00199451786f ) - 273.6777f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts System Monitor Raw Data to Temperature(centigrades)
+* for external reference.
+*
+* @param	AdcData is the SysMon Raw ADC Data.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XSysMon_RawToTemperature_ExternalRef(u32 AdcData)
+*
+*****************************************************************************/
+#define XSysMonPsu_RawToTemperature_ExternalRef(AdcData)			\
+	((((float)(AdcData)/65536.0f)/0.00198842814f ) - 273.8195f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts System Monitor Raw Data to Voltage(volts).
+*
+* @param	AdcData is the System Monitor ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XSysMon_RawToVoltage(u32 AdcData)
+*
+*****************************************************************************/
+#define XSysMonPsu_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to System Monitor Raw Data
+* for On-Chip Sensors.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to System Monitor ADC Raw Data.
+*
+* @return 	The System Monitor ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XSysMon_TemperatureToRaw_OnChip(float Temperature)
+*
+*****************************************************************************/
+#define XSysMonPsu_TemperatureToRaw_OnChip(Temperature)				\
+	((s32)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to System Monitor Raw Data
+* for external reference.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to System Monitor ADC Raw Data.
+*
+* @return 	The System Monitor ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XSysMon_TemperatureToRaw_ExternalRef(float Temperature)
+*
+*****************************************************************************/
+#define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature)		\
+	((s32)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to System Monitor Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		System Monitor/ADC Raw Data.
+*
+* @return 	The System Monitor ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XSysMon_VoltageToRaw(float Voltage)
+*
+*****************************************************************************/
+#define XSysMonPsu_VoltageToRaw(Voltage)			 		\
+	((s32)((Voltage)*65536.0f/3.0f))
+
+/****************************************************************************/
+/**
+*
+* This static inline macro calculates the effective baseaddress based on the
+* Sysmon instance. For PS Sysmon, use additional offset XPS_BA_OFFSET and For
+* PL Sysmon, use additional offset XPL_BA_OFFSET.
+*
+* @param	BaseAddress is the starting address of the SysMon block in
+* 		register database.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon block
+*       or PL Sysmon block or the AMS controller register region.
+*
+* @return 	Returns the effective baseaddress of the sysmon instance.
+*
+*****************************************************************************/
+static inline u32 XSysMonPsu_GetEffBaseAddress(u32 BaseAddress, u32 SysmonBlk)
+	{
+		u32 EffBaseAddr;
+
+		if (SysmonBlk == XSYSMON_PS) {
+			EffBaseAddr = BaseAddress + XPS_BA_OFFSET;
+		} else if(SysmonBlk == XSYSMON_PL) {
+			EffBaseAddr = BaseAddress + XPL_BA_OFFSET;
+		} else {
+			EffBaseAddr = BaseAddress;
+		}
+
+		return EffBaseAddr;
+	}
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xsysmonpsu.c */
+s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigPtr,
+			  u32 EffectiveAddr);
+void XSysMonPsu_Reset(XSysMonPsu *InstancePtr);
+void XSysMonPsu_Reset_FromLPD(XSysMonPsu *InstancePtr);
+u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr);
+u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block);
+u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType, u32 SysmonBlk);
+u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
+		u32 SysmonBlk);
+void XSysMonPsu_SetAvg(XSysMonPsu *InstancePtr, u8 Average, u32 SysmonBlk);
+u8 XSysMonPsu_GetAvg(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
+				u32 IncreaseAcqCycles, u32 IsEventMode,
+				u32 IsDifferentialMode, u32 SysmonBlk);
+void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
+		u32 SysmonBlk);
+u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetSequencerMode(XSysMonPsu *InstancePtr, u8 SequencerMode,
+		u32 SysmonBlk);
+u8 XSysMonPsu_GetSequencerMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetSequencerEvent(XSysMonPsu *InstancePtr, u32 IsEventMode,
+		u32 SysmonBlk);
+s32 XSysMonPsu_GetSequencerEvent(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
+u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk);
+u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
+		u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
+		u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
+		u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
+		u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u16 Value, u32 SysmonBlk);
+u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u32 SysmonBlk);
+void XSysMonPsu_SetPSAutoConversion(XSysMonPsu *InstancePtr);
+u32 XSysMonPsu_GetMonitorStatus(XSysMonPsu *InstancePtr);
+
+/* interrupt functions in xsysmonpsu_intr.c */
+void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask);
+void XSysMonPsu_IntrDisable(XSysMonPsu *InstancePtr, u64 Mask);
+u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr);
+u64 XSysMonPsu_IntrGetStatus(XSysMonPsu *InstancePtr);
+void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask);
+
+/* Functions in xsysmonpsu_selftest.c */
+s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr);
+
+/* Functions in xsysmonpsu_sinit.c */
+XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId);
+
+
+#endif /* XSYSMONPSU_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
new file mode 100644
index 000000000..b692531ad
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsysmonpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSysMonPsu_Config XSysMonPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_AMS_DEVICE_ID,
+		XPAR_PSU_AMS_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
new file mode 100644
index 000000000..80266ebf9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
@@ -0,0 +1,2321 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu_hw.h
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xsysmonpsu.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn	  12/15/15 First release
+* 2.0   vns    08/14/16  Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2,
+*                        SEQ_CH2 and SEQ_AVG2 offsets and bit masks
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSYSMONPSU_HW_H__
+#define XSYSMONPSU_HW_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/**
+ * XSysmonPsu Base Address
+ */
+#define XSYSMONPSU_BASEADDR      0xFFA50000U
+
+/**
+ * Register: XSysmonPsuMisc
+ */
+#define XSYSMONPSU_MISC_OFFSET   0x00000000U
+#define XSYSMONPSU_MISC_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MISC_SLVERR_EN_DRP_SHIFT   1U
+#define XSYSMONPSU_MISC_SLVERR_EN_DRP_WIDTH   1U
+#define XSYSMONPSU_MISC_SLVERR_EN_DRP_MASK    0x00000002U
+
+#define XSYSMONPSU_MISC_SLVERR_EN_SHIFT   0U
+#define XSYSMONPSU_MISC_SLVERR_EN_WIDTH   1U
+#define XSYSMONPSU_MISC_SLVERR_EN_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIsr0
+ */
+#define XSYSMONPSU_ISR_0_OFFSET   0x00000010U
+#define XSYSMONPSU_ISR_0_MASK	  0xffffffffU
+#define XSYSMONPSU_ISR_0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_ISR_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_ISR_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_ISR_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_ISR_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_ISR_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_ISR_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_ISR_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_ISR_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_ISR_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_ISR_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_ISR_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_ISR_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_ISR_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_ISR_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_ISR_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_ISR_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_ISR_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_ISR_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_ISR_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_ISR_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_ISR_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_ISR_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_ISR_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_ISR_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_ISR_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_ISR_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_ISR_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_ISR_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_ISR_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_ISR_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_ISR_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIsr1
+ */
+#define XSYSMONPSU_ISR_1_OFFSET   0x00000014U
+#define XSYSMONPSU_ISR_1_MASK	  0xe000001fU
+#define XSYSMONPSU_ISR_1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_ISR_1_EOS_SHIFT   4U
+#define XSYSMONPSU_ISR_1_EOS_WIDTH   1U
+#define XSYSMONPSU_ISR_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_ISR_1_EOC_SHIFT   3U
+#define XSYSMONPSU_ISR_1_EOC_WIDTH   1U
+#define XSYSMONPSU_ISR_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_ISR_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_ISR_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_ISR_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_ISR_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_ISR_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_ISR_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_ISR_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_ISR_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_ISR_1_PS_FPD_OT_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuImr0
+ */
+#define XSYSMONPSU_IMR_0_OFFSET   0x00000018U
+#define XSYSMONPSU_IMR_0_RSTVAL   0xffffffffU
+
+#define XSYSMONPSU_IMR_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_IMR_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_IMR_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_IMR_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_IMR_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_IMR_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_IMR_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_IMR_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_IMR_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_IMR_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_IMR_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_IMR_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_IMR_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_IMR_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_IMR_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_IMR_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_IMR_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_IMR_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_IMR_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_IMR_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_IMR_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_IMR_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_IMR_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_IMR_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_IMR_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_IMR_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_IMR_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_IMR_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_IMR_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_IMR_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_IMR_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_IMR_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuImr1
+ */
+#define XSYSMONPSU_IMR_1_OFFSET   0x0000001CU
+#define XSYSMONPSU_IMR_1_RSTVAL   0xe000001fU
+
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_IMR_1_EOS_SHIFT   4U
+#define XSYSMONPSU_IMR_1_EOS_WIDTH   1U
+#define XSYSMONPSU_IMR_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_IMR_1_EOC_SHIFT   3U
+#define XSYSMONPSU_IMR_1_EOC_WIDTH   1U
+#define XSYSMONPSU_IMR_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_IMR_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_IMR_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_IMR_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_IMR_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_IMR_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_IMR_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_IMR_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_IMR_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_IMR_1_PS_FPD_OT_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIer0
+ */
+#define XSYSMONPSU_IER_0_OFFSET   0x00000020U
+#define XSYSMONPSU_IXR_0_MASK     0xFFFFFFFFU
+#define XSYSMONPSU_IER_0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_IER_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_IER_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_IER_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_IER_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_IER_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_IER_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_IER_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_IER_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_IER_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_IER_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_IER_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_IER_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_IER_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_IER_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_IER_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_IER_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_IER_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_IER_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_IER_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_IER_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_IER_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_IER_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_IER_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_IER_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_IER_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_IER_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_IER_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_IER_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_IER_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_IER_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_IER_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_IER_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_IER_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_IER_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_IER_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_IER_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_IER_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_IER_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_IER_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_IER_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_IER_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_IER_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_IER_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIer1
+ */
+#define XSYSMONPSU_IER_1_OFFSET   0x00000024U
+#define XSYSMONPSU_IXR_1_MASK     0xE000001FU
+#define XSYSMONPSU_IER_1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_IER_1_EOS_SHIFT   4U
+#define XSYSMONPSU_IER_1_EOS_WIDTH   1U
+#define XSYSMONPSU_IER_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_IER_1_EOC_SHIFT   3U
+#define XSYSMONPSU_IER_1_EOC_WIDTH   1U
+#define XSYSMONPSU_IER_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_IER_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_IER_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_IER_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_IER_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_IER_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_IER_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_IER_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_IER_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_IER_1_PS_FPD_OT_MASK    0x00000001U
+
+#define XSYSMONPSU_IXR_1_SHIFT  32U
+
+/**
+ * Register: XSysmonPsuIdr0
+ */
+#define XSYSMONPSU_IDR_0_OFFSET   0x00000028U
+#define XSYSMONPSU_IDR_0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_IDR_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_IDR_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_IDR_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_IDR_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_IDR_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_IDR_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_IDR_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_IDR_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_IDR_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_IDR_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_IDR_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_IDR_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_IDR_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_IDR_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_IDR_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_IDR_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_IDR_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_IDR_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_IDR_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_IDR_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_IDR_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_IDR_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_IDR_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_IDR_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_IDR_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_IDR_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_IDR_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_IDR_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_IDR_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_IDR_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_IDR_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIdr1
+ */
+#define XSYSMONPSU_IDR_1_OFFSET   0x0000002CU
+#define XSYSMONPSU_IDR_1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_IDR_1_EOS_SHIFT   4U
+#define XSYSMONPSU_IDR_1_EOS_WIDTH   1U
+#define XSYSMONPSU_IDR_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_IDR_1_EOC_SHIFT   3U
+#define XSYSMONPSU_IDR_1_EOC_WIDTH   1U
+#define XSYSMONPSU_IDR_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_IDR_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_IDR_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_IDR_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_IDR_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_IDR_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_IDR_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_IDR_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_IDR_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_IDR_1_PS_FPD_OT_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuPsSysmonSts
+ */
+#define XSYSMONPSU_PS_SYSMON_CSTS_OFFSET   0x00000040U
+#define XSYSMONPSU_PS_SYSMON_CSTS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_SHIFT   24U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_WIDTH   4U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_MASK    0x0f000000U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_SHIFT   16U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_MASK    0x00010000U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_SHIFT   3U
+#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK    0x00000008U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_SHIFT   2U
+#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK    0x00000004U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_SHIFT   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_MASK    0x00000002U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_SHIFT   0U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_MASK    0x00000001U
+
+#define XSYSMONPSU_PS_SYSMON_READY 0x08010000U
+
+/**
+ * Register: XSysmonPsuPlSysmonSts
+ */
+#define XSYSMONPSU_PL_SYSMON_CSTS_OFFSET   0x00000044U
+#define XSYSMONPSU_PL_SYSMON_CSTS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_SHIFT   0U
+#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_WIDTH   1U
+#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuMonSts
+ */
+#define XSYSMONPSU_MON_STS_OFFSET   0x00000050U
+#define XSYSMONPSU_MON_STS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MON_STS_JTAG_LCKD_SHIFT   23U
+#define XSYSMONPSU_MON_STS_JTAG_LCKD_WIDTH   1U
+#define XSYSMONPSU_MON_STS_JTAG_LCKD_MASK    0x00800000U
+
+#define XSYSMONPSU_MON_STS_BSY_SHIFT   22U
+#define XSYSMONPSU_MON_STS_BSY_WIDTH   1U
+#define XSYSMONPSU_MON_STS_BSY_MASK    0x00400000U
+
+#define XSYSMONPSU_MON_STS_CH_SHIFT   16U
+#define XSYSMONPSU_MON_STS_CH_WIDTH   6U
+#define XSYSMONPSU_MON_STS_CH_MASK    0x003f0000U
+
+#define XSYSMONPSU_MON_STS_DATA_SHIFT   0U
+#define XSYSMONPSU_MON_STS_DATA_WIDTH   16U
+#define XSYSMONPSU_MON_STS_DATA_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll0
+ */
+#define XSYSMONPSU_VCC_PSPLL0_OFFSET   0x00000060U
+#define XSYSMONPSU_VCC_PSPLL0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL0_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL0_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL0_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll1
+ */
+#define XSYSMONPSU_VCC_PSPLL1_OFFSET   0x00000064U
+#define XSYSMONPSU_VCC_PSPLL1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL1_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL1_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll2
+ */
+#define XSYSMONPSU_VCC_PSPLL2_OFFSET   0x00000068U
+#define XSYSMONPSU_VCC_PSPLL2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL2_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL2_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL2_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll3
+ */
+#define XSYSMONPSU_VCC_PSPLL3_OFFSET   0x0000006CU
+#define XSYSMONPSU_VCC_PSPLL3_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL3_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL3_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL3_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll4
+ */
+#define XSYSMONPSU_VCC_PSPLL4_OFFSET   0x00000070U
+#define XSYSMONPSU_VCC_PSPLL4_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL4_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL4_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL4_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPsbatt
+ */
+#define XSYSMONPSU_VCC_PSBATT_OFFSET   0x00000074U
+#define XSYSMONPSU_VCC_PSBATT_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSBATT_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSBATT_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSBATT_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccint
+ */
+#define XSYSMONPSU_VCCINT_OFFSET   0x00000078U
+#define XSYSMONPSU_VCCINT_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCINT_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCINT_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCINT_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccbram
+ */
+#define XSYSMONPSU_VCCBRAM_OFFSET   0x0000007CU
+#define XSYSMONPSU_VCCBRAM_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCBRAM_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCBRAM_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCBRAM_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccaux
+ */
+#define XSYSMONPSU_VCCAUX_OFFSET   0x00000080U
+#define XSYSMONPSU_VCCAUX_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPsddrpll
+ */
+#define XSYSMONPSU_VCC_PSDDRPLL_OFFSET   0x00000084U
+#define XSYSMONPSU_VCC_PSDDRPLL_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSDDRPLL_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSDDRPLL_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSDDRPLL_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuDdrphyVref
+ */
+#define XSYSMONPSU_DDRPHY_VREF_OFFSET   0x00000088U
+#define XSYSMONPSU_DDRPHY_VREF_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_DDRPHY_VREF_VAL_SHIFT   0U
+#define XSYSMONPSU_DDRPHY_VREF_VAL_WIDTH   16U
+#define XSYSMONPSU_DDRPHY_VREF_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuDdrphyAto
+ */
+#define XSYSMONPSU_DDRPHY_ATO_OFFSET   0x0000008CU
+#define XSYSMONPSU_DDRPHY_ATO_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_DDRPHY_ATO_VAL_SHIFT   0U
+#define XSYSMONPSU_DDRPHY_ATO_VAL_WIDTH   16U
+#define XSYSMONPSU_DDRPHY_ATO_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuPsgtAt0
+ */
+#define XSYSMONPSU_PSGT_AT0_OFFSET   0x00000090U
+#define XSYSMONPSU_PSGT_AT0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PSGT_AT0_VAL_SHIFT   0U
+#define XSYSMONPSU_PSGT_AT0_VAL_WIDTH   16U
+#define XSYSMONPSU_PSGT_AT0_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuPsgtAt1
+ */
+#define XSYSMONPSU_PSGT_AT1_OFFSET   0x00000094U
+#define XSYSMONPSU_PSGT_AT1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PSGT_AT1_VAL_SHIFT   0U
+#define XSYSMONPSU_PSGT_AT1_VAL_WIDTH   16U
+#define XSYSMONPSU_PSGT_AT1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuReserve0
+ */
+#define XSYSMONPSU_RESERVE0_OFFSET   0x00000098U
+#define XSYSMONPSU_RESERVE0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_RESERVE0_VAL_SHIFT   0U
+#define XSYSMONPSU_RESERVE0_VAL_WIDTH   16U
+#define XSYSMONPSU_RESERVE0_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuReserve1
+ */
+#define XSYSMONPSU_RESERVE1_OFFSET   0x0000009CU
+#define XSYSMONPSU_RESERVE1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_RESERVE1_VAL_SHIFT   0U
+#define XSYSMONPSU_RESERVE1_VAL_WIDTH   16U
+#define XSYSMONPSU_RESERVE1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuTemp
+ */
+#define XSYSMONPSU_TEMP_OFFSET   0x00000000U
+#define XSYSMONPSU_TEMP_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_TEMP_SHIFT   0U
+#define XSYSMONPSU_TEMP_WIDTH   16U
+#define XSYSMONPSU_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup1
+ */
+#define XSYSMONPSU_SUP1_OFFSET   0x00000004U
+#define XSYSMONPSU_SUP1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP1_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP1_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP1_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup2
+ */
+#define XSYSMONPSU_SUP2_OFFSET   0x00000008U
+#define XSYSMONPSU_SUP2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP2_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP2_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP2_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVpVn
+ */
+#define XSYSMONPSU_VP_VN_OFFSET   0x0000000CU
+#define XSYSMONPSU_VP_VN_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VP_VN_SHIFT   0U
+#define XSYSMONPSU_VP_VN_WIDTH   16U
+#define XSYSMONPSU_VP_VN_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVrefp
+ */
+#define XSYSMONPSU_VREFP_OFFSET   0x00000010U
+#define XSYSMONPSU_VREFP_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VREFP_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_VREFP_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_VREFP_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVrefn
+ */
+#define XSYSMONPSU_VREFN_OFFSET   0x00000014U
+#define XSYSMONPSU_VREFN_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VREFN_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_VREFN_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_VREFN_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup3
+ */
+#define XSYSMONPSU_SUP3_OFFSET   0x00000018U
+#define XSYSMONPSU_SUP3_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP3_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP3_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP3_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuCalSupOff
+ */
+#define XSYSMONPSU_CAL_SUP_OFF_OFFSET   0x00000020U
+#define XSYSMONPSU_CAL_SUP_OFF_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CAL_SUP_OFF_VAL_SHIFT   0U
+#define XSYSMONPSU_CAL_SUP_OFF_VAL_WIDTH   16U
+#define XSYSMONPSU_CAL_SUP_OFF_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuCalAdcBiplrOff
+ */
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_OFFSET   0x00000024U
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_SHIFT   0U
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_WIDTH   16U
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuCalGainErr
+ */
+#define XSYSMONPSU_CAL_GAIN_ERR_OFFSET   0x00000028U
+#define XSYSMONPSU_CAL_GAIN_ERR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CAL_GAIN_ERR_VAL_SHIFT   0U
+#define XSYSMONPSU_CAL_GAIN_ERR_VAL_WIDTH   16U
+#define XSYSMONPSU_CAL_GAIN_ERR_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup4
+ */
+#define XSYSMONPSU_SUP4_OFFSET   0x00000034U
+#define XSYSMONPSU_SUP4_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP4_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP4_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP4_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup5
+ */
+#define XSYSMONPSU_SUP5_OFFSET   0x00000038U
+#define XSYSMONPSU_SUP5_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP5_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP5_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP5_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup6
+ */
+#define XSYSMONPSU_SUP6_OFFSET   0x0000003CU
+#define XSYSMONPSU_SUP6_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP6_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP6_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP6_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux00
+ */
+#define XSYSMONPSU_VAUX00_OFFSET   0x00000040U
+#define XSYSMONPSU_VAUX00_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX00_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX00_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX00_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux01
+ */
+#define XSYSMONPSU_VAUX01_OFFSET   0x00000044U
+#define XSYSMONPSU_VAUX01_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX01_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX01_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX01_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux02
+ */
+#define XSYSMONPSU_VAUX02_OFFSET   0x00000048U
+#define XSYSMONPSU_VAUX02_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX02_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX02_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX02_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux03
+ */
+#define XSYSMONPSU_VAUX03_OFFSET   0x0000004CU
+#define XSYSMONPSU_VAUX03_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX03_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX03_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX03_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux04
+ */
+#define XSYSMONPSU_VAUX04_OFFSET   0x00000050U
+#define XSYSMONPSU_VAUX04_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX04_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX04_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX04_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux05
+ */
+#define XSYSMONPSU_VAUX05_OFFSET   0x00000054U
+#define XSYSMONPSU_VAUX05_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX05_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX05_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX05_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux06
+ */
+#define XSYSMONPSU_VAUX06_OFFSET   0x00000058U
+#define XSYSMONPSU_VAUX06_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX06_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX06_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX06_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux07
+ */
+#define XSYSMONPSU_VAUX07_OFFSET   0x0000005CU
+#define XSYSMONPSU_VAUX07_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX07_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX07_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX07_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux08
+ */
+#define XSYSMONPSU_VAUX08_OFFSET   0x00000060U
+#define XSYSMONPSU_VAUX08_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX08_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX08_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX08_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux09
+ */
+#define XSYSMONPSU_VAUX09_OFFSET   0x00000064U
+#define XSYSMONPSU_VAUX09_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX09_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX09_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX09_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0a
+ */
+#define XSYSMONPSU_VAUX0A_OFFSET   0x00000068U
+#define XSYSMONPSU_VAUX0A_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0A_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0A_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0A_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0b
+ */
+#define XSYSMONPSU_VAUX0B_OFFSET   0x0000006CU
+#define XSYSMONPSU_VAUX0B_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0B_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0B_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0B_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0c
+ */
+#define XSYSMONPSU_VAUX0C_OFFSET   0x00000070U
+#define XSYSMONPSU_VAUX0C_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0C_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0C_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0C_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0d
+ */
+#define XSYSMONPSU_VAUX0D_OFFSET   0x00000074U
+#define XSYSMONPSU_VAUX0D_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0D_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0D_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0D_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0e
+ */
+#define XSYSMONPSU_VAUX0E_OFFSET   0x00000078U
+#define XSYSMONPSU_VAUX0E_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0E_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0E_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0E_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0f
+ */
+#define XSYSMONPSU_VAUX0F_OFFSET   0x0000007CU
+#define XSYSMONPSU_VAUX0F_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0F_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0F_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0F_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxTemp
+ */
+#define XSYSMONPSU_MAX_TEMP_OFFSET   0x00000080U
+#define XSYSMONPSU_MAX_TEMP_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_TEMP_SHIFT   0U
+#define XSYSMONPSU_MAX_TEMP_WIDTH   16U
+#define XSYSMONPSU_MAX_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup1
+ */
+#define XSYSMONPSU_MAX_SUP1_OFFSET   0x00000084U
+#define XSYSMONPSU_MAX_SUP1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP1_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP1_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup2
+ */
+#define XSYSMONPSU_MAX_SUP2_OFFSET   0x00000088U
+#define XSYSMONPSU_MAX_SUP2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP2_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP2_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP2_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup3
+ */
+#define XSYSMONPSU_MAX_SUP3_OFFSET   0x0000008CU
+#define XSYSMONPSU_MAX_SUP3_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP3_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP3_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP3_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinTemp
+ */
+#define XSYSMONPSU_MIN_TEMP_OFFSET   0x00000090U
+#define XSYSMONPSU_MIN_TEMP_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_TEMP_SHIFT   0U
+#define XSYSMONPSU_MIN_TEMP_WIDTH   16U
+#define XSYSMONPSU_MIN_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup1
+ */
+#define XSYSMONPSU_MIN_SUP1_OFFSET   0x00000094U
+#define XSYSMONPSU_MIN_SUP1_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP1_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP1_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup2
+ */
+#define XSYSMONPSU_MIN_SUP2_OFFSET   0x00000098U
+#define XSYSMONPSU_MIN_SUP2_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP2_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP2_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP2_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup3
+ */
+#define XSYSMONPSU_MIN_SUP3_OFFSET   0x0000009CU
+#define XSYSMONPSU_MIN_SUP3_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP3_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP3_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP3_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup4
+ */
+#define XSYSMONPSU_MAX_SUP4_OFFSET   0x000000A0U
+#define XSYSMONPSU_MAX_SUP4_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP4_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP4_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP4_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup5
+ */
+#define XSYSMONPSU_MAX_SUP5_OFFSET   0x000000A4U
+#define XSYSMONPSU_MAX_SUP5_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP5_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP5_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP5_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup6
+ */
+#define XSYSMONPSU_MAX_SUP6_OFFSET   0x000000A8U
+#define XSYSMONPSU_MAX_SUP6_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP6_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP6_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP6_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup4
+ */
+#define XSYSMONPSU_MIN_SUP4_OFFSET   0x000000B0U
+#define XSYSMONPSU_MIN_SUP4_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP4_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP4_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP4_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup5
+ */
+#define XSYSMONPSU_MIN_SUP5_OFFSET   0x000000B4U
+#define XSYSMONPSU_MIN_SUP5_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP5_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP5_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP5_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup6
+ */
+#define XSYSMONPSU_MIN_SUP6_OFFSET   0x000000B8U
+#define XSYSMONPSU_MIN_SUP6_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP6_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP6_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP6_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuStsFlag
+ */
+#define XSYSMONPSU_STS_FLAG_OFFSET   0x000000FCU
+#define XSYSMONPSU_STS_FLAG_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_SHIFT   15U
+#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_MASK    0x00008000U
+
+#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_SHIFT   14U
+#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_MASK    0x00004000U
+
+#define XSYSMONPSU_STS_FLAG_JTAG_DISD_SHIFT   11U
+#define XSYSMONPSU_STS_FLAG_JTAG_DISD_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_JTAG_DISD_MASK    0x00000800U
+
+#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_SHIFT   10U
+#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_MASK    0x00000400U
+
+#define XSYSMONPSU_STS_FLAG_INTRNL_REF_SHIFT   9U
+#define XSYSMONPSU_STS_FLAG_INTRNL_REF_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_INTRNL_REF_MASK    0x00000200U
+
+#define XSYSMONPSU_STS_FLAG_DISD_SHIFT   8U
+#define XSYSMONPSU_STS_FLAG_DISD_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_DISD_MASK    0x00000100U
+
+#define XSYSMONPSU_STS_FLAG_ALM_6_3_SHIFT   4U
+#define XSYSMONPSU_STS_FLAG_ALM_6_3_WIDTH   4U
+#define XSYSMONPSU_STS_FLAG_ALM_6_3_MASK    0x000000f0U
+
+#define XSYSMONPSU_STS_FLAG_OT_SHIFT   3U
+#define XSYSMONPSU_STS_FLAG_OT_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_OT_MASK    0x00000008U
+
+#define XSYSMONPSU_STS_FLAG_ALM_2_0_SHIFT   0U
+#define XSYSMONPSU_STS_FLAG_ALM_2_0_WIDTH   3U
+#define XSYSMONPSU_STS_FLAG_ALM_2_0_MASK    0x00000007U
+
+/**
+ * Register: XSysmonPsuCfgReg0
+ */
+#define XSYSMONPSU_CFG_REG0_OFFSET   0x00000100U
+#define XSYSMONPSU_CFG_REG0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT   12U
+#define XSYSMONPSU_CFG_REG0_AVRGNG_WIDTH   2U
+#define XSYSMONPSU_CFG_REG0_AVRGNG_MASK    0x00003000U
+
+#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_SHIFT   11U
+#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK    0x00000800U
+
+#define XSYSMONPSU_CFG_REG0_BU_SHIFT   10U
+#define XSYSMONPSU_CFG_REG0_BU_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_BU_MASK    0x00000400U
+
+#define XSYSMONPSU_CFG_REG0_EC_SHIFT   9U
+#define XSYSMONPSU_CFG_REG0_EC_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_EC_MASK    0x00000200U
+
+#define XSYSMONPSU_EVENT_MODE	1
+#define XSYSMONPSU_CONTINUOUS_MODE 2
+
+#define XSYSMONPSU_CFG_REG0_ACQ_SHIFT   8U
+#define XSYSMONPSU_CFG_REG0_ACQ_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_ACQ_MASK    0x00000100U
+
+#define XSYSMONPSU_CFG_REG0_MUX_CH_SHIFT   0U
+#define XSYSMONPSU_CFG_REG0_MUX_CH_WIDTH   6U
+#define XSYSMONPSU_CFG_REG0_MUX_CH_MASK    0x0000003fU
+
+/**
+ * Register: XSysmonPsuCfgReg1
+ */
+#define XSYSMONPSU_CFG_REG1_OFFSET   0x00000104U
+#define XSYSMONPSU_CFG_REG1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT   12U
+#define XSYSMONPSU_CFG_REG1_SEQ_MDE_WIDTH   4U
+#define XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK    0x0000f000U
+
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_SHIFT   8U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_WIDTH   4U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_MASK    0x00000f00U
+
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_SHIFT   1U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_WIDTH   3U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_MASK    0x0000000eU
+
+#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_SHIFT   0U
+#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_WIDTH   1U
+#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_MASK    0x00000001U
+
+#define XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK 0x00000f0fU
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP6_MASK		0x0800U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP5_MASK		0x0400U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP4_MASK		0x0200U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP3_MASK		0x0100U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP2_MASK		0x0008U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP1_MASK		0x0004U
+#define XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK		0x0002U
+#define XSYSMONPSU_CFR_REG1_ALRM_OT_MASK		0x0001U
+
+/**
+ * Register: XSysmonPsuCfgReg2
+ */
+#define XSYSMONPSU_CFG_REG2_OFFSET   0x00000108U
+#define XSYSMONPSU_CFG_REG2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT   8U
+#define XSYSMONPSU_CFG_REG2_CLK_DVDR_WIDTH   8U
+#define XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK    0x0000ff00U
+
+#define XSYSMONPSU_CLK_DVDR_MIN_VAL			0U
+#define XSYSMONPSU_CLK_DVDR_MAX_VAL			255U
+
+#define XSYSMONPSU_CFG_REG2_PWR_DOWN_SHIFT   4U
+#define XSYSMONPSU_CFG_REG2_PWR_DOWN_WIDTH   4U
+#define XSYSMONPSU_CFG_REG2_PWR_DOWN_MASK    0x000000f0U
+
+#define XSYSMONPSU_CFG_REG2_TST_CH_EN_SHIFT   2U
+#define XSYSMONPSU_CFG_REG2_TST_CH_EN_WIDTH   1U
+#define XSYSMONPSU_CFG_REG2_TST_CH_EN_MASK    0x00000004U
+
+#define XSYSMONPSU_CFG_REG2_TST_MDE_SHIFT   0U
+#define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH   2U
+#define XSYSMONPSU_CFG_REG2_TST_MDE_MASK    0x00000003U
+
+/* Register: XSysmonPsuCfgReg3 */
+#define XSYSMONPSU_CFG_REG3_OFFSET		0x0000010CU
+#define XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK	0x0000003FU
+
+#define XSM_CFG_ALARM_SHIFT			16U
+
+/* Register: XSysmonPsuSeqCh2 */
+#define XSYSMONPSU_SEQ_CH2_OFFSET   0x00000118U
+
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_SHIFT	5U
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_MASK	0x00000020U
+
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_SHIFT		4U
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_MASK		0x00000010U
+
+#define XSYSMONPSU_SEQ_CH2_SUP10_SHIFT		3U
+#define XSYSMONPSU_SEQ_CH2_SUP10_MASK		0x00000008U
+
+#define XSYSMONPSU_SEQ_CH2_SUP9_SHIFT		2U
+#define XSYSMONPSU_SEQ_CH2_SUP9_MASK		0x00000004U
+
+#define XSYSMONPSU_SEQ_CH2_SUP8_SHIFT		1U
+#define XSYSMONPSU_SEQ_CH2_SUP8_MASK		0x00000002U
+
+#define XSYSMONPSU_SEQ_CH2_SUP7_SHIFT		0U
+#define XSYSMONPSU_SEQ_CH2_SUP7_MASK		0x00000001U
+
+#define XSYSMONPSU_SEQ_CH2_VALID_MASK     	0x0000003FU
+
+/* Register: XSysmonPsuSeqAverage0 */
+#define XSYSMONPSU_SEQ_AVERAGE2_OFFSET  0x0000011CU
+#define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL  0x00000000U
+#define XSYSMONPSU_SEQ_AVERAGE2_MASK	0x0000003FU
+
+/**
+ * Register: XSysmonPsuSeqCh0
+ */
+#define XSYSMONPSU_SEQ_CH0_OFFSET   0x00000120U
+#define XSYSMONPSU_SEQ_CH0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_CH0_CUR_MON_SHIFT   15U
+#define XSYSMONPSU_SEQ_CH0_CUR_MON_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_CUR_MON_MASK    0x00008000U
+
+#define XSYSMONPSU_SEQ_CH0_SUP3_SHIFT   14U
+#define XSYSMONPSU_SEQ_CH0_SUP3_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP3_MASK    0x00004000U
+
+#define XSYSMONPSU_SEQ_CH0_VREFN_SHIFT   13U
+#define XSYSMONPSU_SEQ_CH0_VREFN_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_VREFN_MASK    0x00002000U
+
+#define XSYSMONPSU_SEQ_CH0_VREFP_SHIFT   12U
+#define XSYSMONPSU_SEQ_CH0_VREFP_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_VREFP_MASK    0x00001000U
+
+#define XSYSMONPSU_SEQ_CH0_VP_VN_SHIFT   11U
+#define XSYSMONPSU_SEQ_CH0_VP_VN_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_VP_VN_MASK    0x00000800U
+
+#define XSYSMONPSU_SEQ_CH0_SUP2_SHIFT   10U
+#define XSYSMONPSU_SEQ_CH0_SUP2_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP2_MASK    0x00000400U
+
+#define XSYSMONPSU_SEQ_CH0_SUP1_SHIFT   9U
+#define XSYSMONPSU_SEQ_CH0_SUP1_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP1_MASK    0x00000200U
+
+#define XSYSMONPSU_SEQ_CH0_TEMP_SHIFT   8U
+#define XSYSMONPSU_SEQ_CH0_TEMP_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_TEMP_MASK    0x00000100U
+
+#define XSYSMONPSU_SEQ_CH0_SUP6_SHIFT   7U
+#define XSYSMONPSU_SEQ_CH0_SUP6_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP6_MASK    0x00000080U
+
+#define XSYSMONPSU_SEQ_CH0_SUP5_SHIFT   6U
+#define XSYSMONPSU_SEQ_CH0_SUP5_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP5_MASK    0x00000040U
+
+#define XSYSMONPSU_SEQ_CH0_SUP4_SHIFT   5U
+#define XSYSMONPSU_SEQ_CH0_SUP4_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP4_MASK    0x00000020U
+
+#define XSYSMONPSU_SEQ_CH0_TST_CH_SHIFT   3U
+#define XSYSMONPSU_SEQ_CH0_TST_CH_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_TST_CH_MASK    0x00000008U
+
+#define XSYSMONPSU_SEQ_CH0_CALIBRTN_SHIFT   0U
+#define XSYSMONPSU_SEQ_CH0_CALIBRTN_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_CALIBRTN_MASK    0x00000001U
+
+#define XSYSMONPSU_SEQ_CH0_VALID_MASK     0x0000FFE9U
+
+/**
+ * Register: XSysmonPsuSeqCh1
+ */
+#define XSYSMONPSU_SEQ_CH1_OFFSET         0x00000124U
+#define XSYSMONPSU_SEQ_CH1_VALID_MASK     0x0000FFFFU
+#define XSYSMONPSU_SEQ_CH1_RSTVAL         0x00000000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0F_SHIFT   15U
+#define XSYSMONPSU_SEQ_CH1_VAUX0F_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0F_MASK    0x00008000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0E_SHIFT   14U
+#define XSYSMONPSU_SEQ_CH1_VAUX0E_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0E_MASK    0x00004000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0D_SHIFT   13U
+#define XSYSMONPSU_SEQ_CH1_VAUX0D_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0D_MASK    0x00002000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0C_SHIFT   12U
+#define XSYSMONPSU_SEQ_CH1_VAUX0C_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0C_MASK    0x00001000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0B_SHIFT   11U
+#define XSYSMONPSU_SEQ_CH1_VAUX0B_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0B_MASK    0x00000800U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0A_SHIFT   10U
+#define XSYSMONPSU_SEQ_CH1_VAUX0A_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0A_MASK    0x00000400U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX09_SHIFT   9U
+#define XSYSMONPSU_SEQ_CH1_VAUX09_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX09_MASK    0x00000200U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX08_SHIFT   8U
+#define XSYSMONPSU_SEQ_CH1_VAUX08_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX08_MASK    0x00000100U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX07_SHIFT   7U
+#define XSYSMONPSU_SEQ_CH1_VAUX07_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX07_MASK    0x00000080U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX06_SHIFT   6U
+#define XSYSMONPSU_SEQ_CH1_VAUX06_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX06_MASK    0x00000040U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX05_SHIFT   5U
+#define XSYSMONPSU_SEQ_CH1_VAUX05_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX05_MASK    0x00000020U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX04_SHIFT   4U
+#define XSYSMONPSU_SEQ_CH1_VAUX04_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX04_MASK    0x00000010U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX03_SHIFT   3U
+#define XSYSMONPSU_SEQ_CH1_VAUX03_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX03_MASK    0x00000008U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX02_SHIFT   2U
+#define XSYSMONPSU_SEQ_CH1_VAUX02_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX02_MASK    0x00000004U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX01_SHIFT   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX01_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX01_MASK    0x00000002U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX00_SHIFT   0U
+#define XSYSMONPSU_SEQ_CH1_VAUX00_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX00_MASK    0x00000001U
+
+#define XSM_SEQ_CH_SHIFT                  16U
+#define XSM_SEQ_CH2_SHIFT                 32U
+
+/**
+ * Register: XSysmonPsuSeqAverage0
+ */
+#define XSYSMONPSU_SEQ_AVERAGE0_OFFSET   0x00000128U
+#define XSYSMONPSU_SEQ_AVERAGE0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_AVERAGE0_SHIFT   0U
+#define XSYSMONPSU_SEQ_AVERAGE0_WIDTH   16U
+#define XSYSMONPSU_SEQ_AVERAGE0_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqAverage1
+ */
+#define XSYSMONPSU_SEQ_AVERAGE1_OFFSET   0x0000012CU
+#define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_AVERAGE1_SHIFT   0U
+#define XSYSMONPSU_SEQ_AVERAGE1_WIDTH   16U
+#define XSYSMONPSU_SEQ_AVERAGE1_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqInputMde0
+ */
+#define XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET   0x00000130U
+#define XSYSMONPSU_SEQ_INPUT_MDE0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE0_SHIFT   0U
+#define XSYSMONPSU_SEQ_INPUT_MDE0_WIDTH   16U
+#define XSYSMONPSU_SEQ_INPUT_MDE0_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqInputMde1
+ */
+#define XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET   0x00000134U
+#define XSYSMONPSU_SEQ_INPUT_MDE1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE1_SHIFT   0U
+#define XSYSMONPSU_SEQ_INPUT_MDE1_WIDTH   16U
+#define XSYSMONPSU_SEQ_INPUT_MDE1_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqAcq0
+ */
+#define XSYSMONPSU_SEQ_ACQ0_OFFSET   0x00000138U
+#define XSYSMONPSU_SEQ_ACQ0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ0_SHIFT   0U
+#define XSYSMONPSU_SEQ_ACQ0_WIDTH   16U
+#define XSYSMONPSU_SEQ_ACQ0_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqAcq1
+ */
+#define XSYSMONPSU_SEQ_ACQ1_OFFSET   0x0000013CU
+#define XSYSMONPSU_SEQ_ACQ1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ1_SHIFT   0U
+#define XSYSMONPSU_SEQ_ACQ1_WIDTH   16U
+#define XSYSMONPSU_SEQ_ACQ1_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTempUpr
+ */
+#define XSYSMONPSU_ALRM_TEMP_UPR_OFFSET   0x00000140U
+#define XSYSMONPSU_ALRM_TEMP_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TEMP_UPR_SHIFT   0U
+#define XSYSMONPSU_ALRM_TEMP_UPR_WIDTH   16U
+#define XSYSMONPSU_ALRM_TEMP_UPR_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup1Upr
+ */
+#define XSYSMONPSU_ALRM_SUP1_UPR_OFFSET   0x00000144U
+#define XSYSMONPSU_ALRM_SUP1_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup2Upr
+ */
+#define XSYSMONPSU_ALRM_SUP2_UPR_OFFSET   0x00000148U
+#define XSYSMONPSU_ALRM_SUP2_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmOtUpr
+ */
+#define XSYSMONPSU_ALRM_OT_UPR_OFFSET   0x0000014CU
+#define XSYSMONPSU_ALRM_OT_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_OT_UPR_TEMP_SHIFT   0U
+#define XSYSMONPSU_ALRM_OT_UPR_TEMP_WIDTH   16U
+#define XSYSMONPSU_ALRM_OT_UPR_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTempLwr
+ */
+#define XSYSMONPSU_ALRM_TEMP_LWR_OFFSET   0x00000150U
+#define XSYSMONPSU_ALRM_TEMP_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TEMP_LWR_SHIFT   1U
+#define XSYSMONPSU_ALRM_TEMP_LWR_WIDTH   15U
+#define XSYSMONPSU_ALRM_TEMP_LWR_MASK    0x0000fffeU
+
+#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_SHIFT   0U
+#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_WIDTH   1U
+#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuAlrmSup1Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP1_LWR_OFFSET   0x00000154U
+#define XSYSMONPSU_ALRM_SUP1_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup2Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP2_LWR_OFFSET   0x00000158U
+#define XSYSMONPSU_ALRM_SUP2_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmOtLwr
+ */
+#define XSYSMONPSU_ALRM_OT_LWR_OFFSET   0x0000015CU
+#define XSYSMONPSU_ALRM_OT_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_OT_LWR_TEMP_SHIFT   1U
+#define XSYSMONPSU_ALRM_OT_LWR_TEMP_WIDTH   15U
+#define XSYSMONPSU_ALRM_OT_LWR_TEMP_MASK    0x0000fffeU
+
+#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_SHIFT   0U
+#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_WIDTH   1U
+#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuAlrmSup3Upr
+ */
+#define XSYSMONPSU_ALRM_SUP3_UPR_OFFSET   0x00000160U
+#define XSYSMONPSU_ALRM_SUP3_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup4Upr
+ */
+#define XSYSMONPSU_ALRM_SUP4_UPR_OFFSET   0x00000164U
+#define XSYSMONPSU_ALRM_SUP4_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup5Upr
+ */
+#define XSYSMONPSU_ALRM_SUP5_UPR_OFFSET   0x00000168U
+#define XSYSMONPSU_ALRM_SUP5_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup6Upr
+ */
+#define XSYSMONPSU_ALRM_SUP6_UPR_OFFSET   0x0000016CU
+#define XSYSMONPSU_ALRM_SUP6_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup3Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP3_LWR_OFFSET   0x00000170U
+#define XSYSMONPSU_ALRM_SUP3_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup4Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP4_LWR_OFFSET   0x00000174U
+#define XSYSMONPSU_ALRM_SUP4_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup5Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP5_LWR_OFFSET   0x00000178U
+#define XSYSMONPSU_ALRM_SUP5_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup6Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP6_LWR_OFFSET   0x0000017CU
+#define XSYSMONPSU_ALRM_SUP6_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup7Upr
+ */
+#define XSYSMONPSU_ALRM_SUP7_UPR_OFFSET   0x00000180U
+#define XSYSMONPSU_ALRM_SUP7_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup8Upr
+ */
+#define XSYSMONPSU_ALRM_SUP8_UPR_OFFSET   0x00000184U
+#define XSYSMONPSU_ALRM_SUP8_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup9Upr
+ */
+#define XSYSMONPSU_ALRM_SUP9_UPR_OFFSET   0x00000188U
+#define XSYSMONPSU_ALRM_SUP9_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup10Upr
+ */
+#define XSYSMONPSU_ALRM_SUP10_UPR_OFFSET   0x0000018CU
+#define XSYSMONPSU_ALRM_SUP10_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmVccamsUpr
+ */
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_OFFSET   0x00000190U
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTremoteUpr
+ */
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_OFFSET   0x00000194U
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_SHIFT   0U
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_WIDTH   16U
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup7Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP7_LWR_OFFSET   0x000001A0U
+#define XSYSMONPSU_ALRM_SUP7_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup8Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP8_LWR_OFFSET   0x000001A4U
+#define XSYSMONPSU_ALRM_SUP8_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup9Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP9_LWR_OFFSET   0x000001A8U
+#define XSYSMONPSU_ALRM_SUP9_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup10Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP10_LWR_OFFSET   0x000001ACU
+#define XSYSMONPSU_ALRM_SUP10_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmVccamsLwr
+ */
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_OFFSET   0x000001B0U
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTremoteLwr
+ */
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_OFFSET   0x000001B4U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_SHIFT   1U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_WIDTH   15U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_MASK    0x0000fffeU
+
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_SHIFT   0U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH   1U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK    0x00000001U
+
+/* Register: XSysmonPsuSeqInputMde2 */
+#define XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET	0x000001E0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_RSTVAL	0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE2_SHIFT		0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_MASK		0x0000003FU
+
+/**
+ * Register: XSysmonPsuSeqAcq2
+ */
+#define XSYSMONPSU_SEQ_ACQ2_OFFSET		0x000001E4U
+#define XSYSMONPSU_SEQ_ACQ2_RSTVAL		0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ2_SHIFT		0U
+#define XSYSMONPSU_SEQ_ACQ2_MASK		0x0000003FU
+
+/**
+ * Register: XSysmonPsuSup7
+ */
+#define XSYSMONPSU_SUP7_OFFSET   0x00000200U
+#define XSYSMONPSU_SUP7_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP7_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP7_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP7_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup8
+ */
+#define XSYSMONPSU_SUP8_OFFSET   0x00000204U
+#define XSYSMONPSU_SUP8_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP8_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP8_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP8_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup9
+ */
+#define XSYSMONPSU_SUP9_OFFSET   0x00000208U
+#define XSYSMONPSU_SUP9_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP9_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP9_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP9_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup10
+ */
+#define XSYSMONPSU_SUP10_OFFSET   0x0000020CU
+#define XSYSMONPSU_SUP10_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP10_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP10_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP10_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccams
+ */
+#define XSYSMONPSU_VCCAMS_OFFSET   0x00000210U
+#define XSYSMONPSU_VCCAMS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCAMS_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCAMS_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCAMS_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuTempRemte
+ */
+#define XSYSMONPSU_TEMP_REMTE_OFFSET   0x00000214U
+#define XSYSMONPSU_TEMP_REMTE_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_TEMP_REMTE_SHIFT   0U
+#define XSYSMONPSU_TEMP_REMTE_WIDTH   16U
+#define XSYSMONPSU_TEMP_REMTE_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup7
+ */
+#define XSYSMONPSU_MAX_SUP7_OFFSET   0x00000280U
+#define XSYSMONPSU_MAX_SUP7_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP7_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP7_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP7_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup8
+ */
+#define XSYSMONPSU_MAX_SUP8_OFFSET   0x00000284U
+#define XSYSMONPSU_MAX_SUP8_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP8_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP8_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP8_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup9
+ */
+#define XSYSMONPSU_MAX_SUP9_OFFSET   0x00000288U
+#define XSYSMONPSU_MAX_SUP9_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP9_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP9_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP9_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup10
+ */
+#define XSYSMONPSU_MAX_SUP10_OFFSET   0x0000028CU
+#define XSYSMONPSU_MAX_SUP10_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP10_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP10_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP10_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxVccams
+ */
+#define XSYSMONPSU_MAX_VCCAMS_OFFSET   0x00000290U
+#define XSYSMONPSU_MAX_VCCAMS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxTempRemte
+ */
+#define XSYSMONPSU_MAX_TEMP_REMTE_OFFSET   0x00000294U
+#define XSYSMONPSU_MAX_TEMP_REMTE_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_TEMP_REMTE_SHIFT   0U
+#define XSYSMONPSU_MAX_TEMP_REMTE_WIDTH   16U
+#define XSYSMONPSU_MAX_TEMP_REMTE_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup7
+ */
+#define XSYSMONPSU_MIN_SUP7_OFFSET   0x000002A0U
+#define XSYSMONPSU_MIN_SUP7_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP7_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP7_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP7_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup8
+ */
+#define XSYSMONPSU_MIN_SUP8_OFFSET   0x000002A4U
+#define XSYSMONPSU_MIN_SUP8_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP8_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP8_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP8_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup9
+ */
+#define XSYSMONPSU_MIN_SUP9_OFFSET   0x000002A8U
+#define XSYSMONPSU_MIN_SUP9_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP9_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP9_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP9_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup10
+ */
+#define XSYSMONPSU_MIN_SUP10_OFFSET   0x000002ACU
+#define XSYSMONPSU_MIN_SUP10_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP10_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP10_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP10_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinVccams
+ */
+#define XSYSMONPSU_MIN_VCCAMS_OFFSET   0x000002B0U
+#define XSYSMONPSU_MIN_VCCAMS_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinTempRemte
+ */
+#define XSYSMONPSU_MIN_TEMP_REMTE_OFFSET   0x000002B4U
+#define XSYSMONPSU_MIN_TEMP_REMTE_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_TEMP_REMTE_SHIFT   0U
+#define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH   16U
+#define XSYSMONPSU_MIN_TEMP_REMTE_MASK    0x0000ffffU
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the SYSMONPSU device.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XSysmonPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the SYSMONPSU device.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XSysmonPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XSYSMONPSU_HW_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
new file mode 100644
index 000000000..b178c2e11
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu_intr.c
+*
+* This file contains functions related to SYSMONPSU interrupt handling.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn    12/15/15 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsysmonpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Mask is the 64 bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* bits defined in
+*		xsysmonpsu_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask)
+{
+	u32 RegValue;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Enable the specified interrupts in the AMS Interrupt Enable Register. */
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IER_0_OFFSET);
+	RegValue |= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_0_OFFSET,
+			  RegValue);
+
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IER_1_OFFSET);
+	RegValue |= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_1_OFFSET,
+			  RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Mask is the 64 bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XSYSMONPSU_IDR_0_* and XSYSMONPSU_IDR_1_* bits defined in
+*		xsysmonpsu_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_IntrDisable(XSysMonPsu *InstancePtr, u64 Mask)
+{
+	u32 RegValue;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable the specified interrupts in the AMS Interrupt Disable Register. */
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IDR_0_OFFSET);
+	RegValue |= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IDR_0_OFFSET,
+			  RegValue);
+
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IDR_1_OFFSET);
+	RegValue |= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IDR_1_OFFSET,
+			  RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Enable
+* Register (IER). Use the XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* constants
+* defined in xsysmonpsu_hw.h to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	A 64-bit value representing the contents of the Interrupt Mask
+* 			Registers (IMR1 IMR0).
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr)
+{
+	u64 MaskedInterrupts;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Return the value read from the AMS Interrupt Mask Register. */
+	MaskedInterrupts = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                         XSYSMONPSU_IMR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
+	MaskedInterrupts |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                         XSYSMONPSU_IMR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
+                          << XSYSMONPSU_IXR_1_SHIFT;
+
+	return (~MaskedInterrupts);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(ISR). Use the XSYSMONPSU_ISR_0_* and XSYSMONPSU_ISR_1_ constants
+* defined in xsysmonpsu_hw.h to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	A 64-bit value representing the contents of the Interrupt Status
+* 			Registers (ISR1 ISR0).
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_IntrGetStatus(XSysMonPsu *InstancePtr)
+{
+	u64 IntrStatusRegister;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Return the value read from the AMS ISR. */
+	IntrStatusRegister = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                           XSYSMONPSU_ISR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
+	IntrStatusRegister |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                           XSYSMONPSU_ISR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
+                           << XSYSMONPSU_IXR_1_SHIFT;
+
+	return IntrStatusRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (ISR).
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Mask is the 64 bit-mask of the interrupts to be cleared.
+*		Bit positions of 1 will be cleared. Bit positions of 0 will not
+* 		change the previous interrupt status. This mask is formed by
+* 		OR'ing the XSYSMONPSU_ISR_0_* and XSYSMONPSU_ISR_1_* bits
+* 		which are defined in xsysmonpsu_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask)
+{
+	u32 RegValue;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Clear the specified interrupts in the Interrupt Status register. */
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_ISR_0_OFFSET);
+	RegValue &= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_0_OFFSET,
+			  RegValue);
+
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_ISR_1_OFFSET);
+	RegValue &= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_1_OFFSET,
+			  RegValue);
+}
+
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
new file mode 100644
index 000000000..5b709be14
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmon_selftest.c
+*
+* This file contains a diagnostic self test function for the XSysMon driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xsysmonpsu.h for more information.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   kvn   12/15/15  First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xsysmonpsu.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XSM_ATR_TEST_VALUE 		0x55U
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Resets the device,
+*	- Writes a value into the Alarm Threshold register and reads it back
+*	for comparison.
+*	- Resets the device again.
+*
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the Alarm Threshold
+*		register is the same as the value written.
+*		- XST_FAILURE Otherwise
+*
+* @note		This is a destructive test in that resets of the device are
+*		performed. Refer to the device specification for the
+*		device status after the reset operation.
+*
+******************************************************************************/
+s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr)
+{
+	s32 Status;
+	u32 RegValue;
+
+	/* Assert the argument */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Reset the device to get it back to its default state */
+	XSysMonPsu_Reset(InstancePtr);
+
+	/*
+	 * Write a value into the Alarm Threshold registers, read it back, and
+	 * do the comparison
+	 */
+	XSysMonPsu_SetAlarmThreshold(InstancePtr, XSM_ATR_SUP1_UPPER,
+				  XSM_ATR_TEST_VALUE, XSYSMON_PS);
+	RegValue = (u32)XSysMonPsu_GetAlarmThreshold(InstancePtr,
+					XSM_ATR_SUP1_UPPER, XSYSMON_PS);
+
+	if (RegValue == XSM_ATR_TEST_VALUE) {
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	/* Reset the device again to its default state. */
+	XSysMonPsu_Reset(InstancePtr);
+
+	/* Return the test result. */
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
new file mode 100644
index 000000000..34249a209
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu_sinit.c
+*
+* This file contains the implementation of the XSysMonPsu driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	    Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn    12/15/15 First release.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsysmonpsu.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XSysMonPsu_Config XSysMonPsu_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XSysmonPsu_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId)
+{
+	XSysMonPsu_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSYSMONPSU_NUM_INSTANCES; Index++) {
+		if (XSysMonPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSysMonPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile
deleted file mode 100644
index 35c277dde..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner ttcps_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling ttcps"
-
-ttcps_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: ttcps_includes
-
-ttcps_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c
deleted file mode 100644
index 4534553f6..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps.c
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file contains the implementation of the XTtcPs driver. This driver
-* controls the operation of one timer counter in the Triple Timer Counter (TTC)
-* module in the Ps block. Refer to xttcps.h for more detailed description
-* of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- -------------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.01	pkp	   01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
-*						to stop the timer before configuring
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XTtcPs instance such that the driver is ready to use.
-* This function initializes a single timer counter in the triple timer counter
-* function block.
-*
-* The state of the device after initialization is:
-*  - Overflow Mode
-*  - Internal (pclk) selected
-*  - Counter disabled
-*  - All Interrupts disabled
-*  - Output waveforms disabled
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	ConfigPtr is a reference to a structure containing information
-*		about a specific TTC device.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the address
-*		mapping from EffectiveAddr to the device physical base address
-*		unchanged once this function is invoked. Unexpected errors may
-*		occur if the address mapping changes after this function is
-*		called. If address translation is not used, then use
-*		ConfigPtr->BaseAddress for this parameter, passing the physical
-*		address instead.
-*
-* @return
-*
-* 		- XST_SUCCESS if the initialization is successful.
-*		- XST_DEVICE_IS_STARTED if the device is started. It must be
-*		  stopped to re-initialize.
-*
-* @note		Device has to be stopped first to call this function to
-*		initialize it.
-*
-******************************************************************************/
-s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
-			      u32 EffectiveAddr)
-{
-	s32 Status;
-	u32 IsStartResult;
-	/*
-	 * Assert to validate input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-
-	/*
-	 * Set some default values
-	 */
-	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
-
-	IsStartResult = XTtcPs_IsStarted(InstancePtr);
-	/*
-	 * If the timer counter has already started, return an error
-	 * Device should be stopped first.
-	 */
-	if(IsStartResult == (u32)TRUE) {
-		Status = XST_DEVICE_IS_STARTED;
-	} else {
-
-		/*
-		 * stop the timer before configuring
-		 */
-		XTtcPs_Stop(InstancePtr);
-		/*
-		 * Reset the count control register to it's default value.
-		 */
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_CNT_CNTRL_OFFSET,
-				  XTTCPS_CNT_CNTRL_RESET_VALUE);
-
-		/*
-		 * Reset the rest of the registers to the default values.
-		 */
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_MATCH_1_OFFSET, 0x00U);
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_MATCH_2_OFFSET, 0x00U);
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_MATCH_2_OFFSET, 0x00U);
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_IER_OFFSET, 0x00U);
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
-
-		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-		/*
-		 * Reset the counter value
-		 */
-		XTtcPs_ResetCounterValue(InstancePtr);
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function is used to set the match registers. There are three match
-* registers.
-*
-* The match 0 register is special. If the waveform output mode is enabled, the
-* waveform will change polarity when the count matches the value in the match 0
-* register. The polarity of the waveform output can also be set using the
-* XTtcPs_SetOptions() function.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	MatchIndex is the index to the match register to be set.
-*		Valid values are 0, 1, or 2.
-* @param	Value is the 16-bit value to be set in the match register.
-*
-* @return	None
-*
-* @note		None
-*
-****************************************************************************/
-void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
-{
-	/*
-	 * Assert to validate input arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
-
-	/*
-	 * Write the value to the correct match register with MatchIndex
-	 */
-	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XTtcPs_Match_N_Offset(MatchIndex), Value);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function is used to get the value of the match registers. There are
-* three match registers.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	MatchIndex is the index to the match register to be set.
-*		Valid values are 0, 1, or 2.
-*
-* @return	None
-*
-* @note		None
-*
-****************************************************************************/
-u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
-{
-	u32 MatchReg;
-
-	/*
-	 * Assert to validate input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
-
-	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
-			    XTtcPs_Match_N_Offset(MatchIndex));
-
-	return (u16) MatchReg;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the prescaler enable bit and if needed sets the prescaler
-* bits in the control register.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	PrescalerValue is a number from 0-16 that sets the prescaler
-*		to use.
-*		If the parameter is 0 - 15, use a prescaler on the clock of
-*		2^(PrescalerValue+1), or 2-65536.
-*		If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
-*		prescaler.
-*
-* @return	None
-*
-* @note		None
-*
-****************************************************************************/
-void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
-{
-	u32 ClockReg;
-
-	/*
-	 * Assert to validate input arguments.
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
-
-	/*
-	 * Read the clock control register
-	 */
-	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
-			   XTTCPS_CLK_CNTRL_OFFSET);
-
-	/*
-	 * Clear all of the prescaler control bits in the register
-	 */
-	ClockReg &=
-		~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
-
-	if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
-		/*
-		 * Set the prescaler value and enable prescaler
-		 */
-		ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
-			(u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
-		ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
-	}
-
-	/*
-	 * Write the register with the new values.
-	 */
-	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the input clock prescaler
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* <pre>
-* @return	The value(n) from which the prescalar value is calculated
-*		as 2^(n+1). Some example values are given below :
-*
-* 	Value		Prescaler
-* 	0		2
-* 	1		4
-* 	N		2^(n+1)
-* 	15		65536
-* 	16		1
-* </pre>
-*
-* @note		None.
-*
-****************************************************************************/
-u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
-{
-	u8 Status;
-	u32 ClockReg;
-
-	/*
-	 * Assert to validate input arguments.
-	 */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read the clock control register
-	 */
-	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    XTTCPS_CLK_CNTRL_OFFSET);
-
-	if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
-		/*
-		 * Prescaler is disabled. Return the correct flag value
-		 */
-		Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
-	}
-	else {
-
-		Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
-			(u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
-	}
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function calculates the interval value as well as the prescaler value
-* for a given frequency.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	Freq is the requested output frequency for the device.
-* @param	Interval is the interval value for the given frequency,
-*		it is the output value for this function.
-* @param	Prescaler is the prescaler value for the given frequency,
-*		it is the output value for this function.
-*
-* @return	None.
-*
-* @note
-*  Upon successful calculation for the given frequency, Interval and Prescaler
-*  carry the settings for the timer counter; Upon unsuccessful calculation,
-*  Interval and Prescaler are set to 0xFF(FF) for their maximum values to
-*  signal the caller of failure. Therefore, caller needs to check the return
-*  interval or prescaler values for whether the function has succeeded.
-*
-****************************************************************************/
-void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
-        u16 *Interval, u8 *Prescaler)
-{
-	u8 TmpPrescaler;
-	u32 TempValue;
-	u32 InputClock;
-
-	InputClock = InstancePtr->Config.InputClockHz;
-	/*
-	 * Find the smallest prescaler that will work for a given frequency. The
-	 * smaller the prescaler, the larger the count and the more accurate the
-	 *  PWM setting.
-	 */
-	TempValue = InputClock/ Freq;
-
-	if (TempValue < 4U) {
-		/*
-		 * The frequency is too high, it is too close to the input
-		 * clock value. Use maximum values to signal caller.
-		 */
-		*Interval = 0xFFFFU;
-		*Prescaler = 0xFFU;
-		return;
-	}
-
-	/*
-	 * First, do we need a prescaler or not?
-	 */
-	if (((u32)65536U) > TempValue) {
-		/*
-		 * We do not need a prescaler, so set the values appropriately
-		 */
-		*Interval = (u16)TempValue;
-		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
-		return;
-	}
-
-
-	for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
-	     TmpPrescaler++) {
-		TempValue =	InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
-
-		/*
-		 * The first value less than 2^16 is the best bet
-		 */
-		if (((u32)65536U) > TempValue) {
-			/*
-			 * Set the values appropriately
-			 */
-			*Interval = (u16)TempValue;
-			*Prescaler = TmpPrescaler;
-			return;
-		}
-	}
-
-	/* Can not find interval values that work for the given frequency.
-	 * Return maximum values to signal caller.
-	 */
-	*Interval = 0XFFFFU;
-	*Prescaler = 0XFFU;
-	return;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h
deleted file mode 100644
index 646d24db5..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps.h
-* @addtogroup ttcps_v3_0
-* @{
-* @details
-*
-* This is the driver for one 16-bit timer counter in the Triple Timer Counter
-* (TTC) module in the Ps block.
-*
-* The TTC module provides three independent timer/counter modules that can each
-* be clocked using either the system clock (pclk) or an externally driven
-* clock (ext_clk). In addition, each counter can independently prescale its
-* selected clock input (divided by 2 to 65536). Counters can be set to
-* decrement or increment.
-*
-* Each of the counters can be programmed to generate interrupt pulses:
-*	. At a regular, predefined period, that is on a timed interval
-*	. When the counter registers overflow
-* 	. When the count matches any one of the three 'match' registers
-*
-* Therefore, up to six different events can trigger a timer interrupt: three
-* match interrupts, an overflow interrupt, an interval interrupt and an event
-* timer interrupt. Note that the overflow interrupt and the interval interrupt
-* are mutually exclusive.
-*
-* <b>Initialization & Configuration</b>
-*
-* An XTtcPs_Config structure is used to configure a driver instance.
-* Information in the XTtcPs_Config structure is the hardware properties
-* about the device.
-*
-* A driver instance is initialized through
-* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
-* is a pointer to the XTtcPs_Config structure, it can be looked up statically
-* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
-* EffectiveAddr can be the static base address of the device or virtual
-* mapped address if address translation is supported.
-*
-* <b>Interrupts</b>
-*
-* Interrupt handler is not provided by the driver, as handling of interrupt
-* is application specific.
-*
-* @note
-* The default setting for a timer/counter is:
-*  - Overflow Mode
-*  - Internal clock (pclk) selected
-*  - Counter disabled
-*  - All Interrupts disabled
-*  - Output waveforms disabled
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- -----------------------------------------------------
-* 1.00a drg/jz 01/20/10 First release..
-* 2.0   adk    12/10/13 Updated as per the New Tcl API's
-* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
-*			modified for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTTCPS_H		/* prevent circular inclusions */
-#define XTTCPS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xttcps_hw.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * Options for the device. Each of the options is bit field, so more than one
- * options can be specified.
- *
- * @{
- */
-#define XTTCPS_OPTION_EXTERNAL_CLK	0x00000001U 	/**< External clock source */
-#define XTTCPS_OPTION_CLK_EDGE_NEG	0x00000002U	/**< Clock on trailing edge for
-						     external clock*/
-#define XTTCPS_OPTION_INTERVAL_MODE	0x00000004U	/**< Interval mode */
-#define XTTCPS_OPTION_DECREMENT		0x00000008U	/**< Decrement the counter */
-#define XTTCPS_OPTION_MATCH_MODE	0x00000010U	/**< Match mode */
-#define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
-#define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;	  /**< Unique ID for device */
-	u32 BaseAddress;  /**< Base address for device */
-	u32 InputClockHz; /**< Input clock frequency */
-} XTtcPs_Config;
-
-/**
- * The XTtcPs driver instance data. The user is required to allocate a
- * variable of this type for each PS timer/counter device in the system. A
- * pointer to a variable of this type is then passed to various driver API
- * functions.
- */
-typedef struct {
-	XTtcPs_Config Config;	/**< Configuration structure */
-	u32 IsReady;		/**< Device is initialized and ready */
-} XTtcPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * Internal helper macros
- */
-#define InstReadReg(InstancePtr, RegOffset) \
-    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
-
-#define InstWriteReg(InstancePtr, RegOffset, Data) \
-    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
-
-/*****************************************************************************/
-/**
-*
-* This function starts the counter/timer without resetting the counter value.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return	None
-*
-* @note		C-style signature:
-*		void XTtcPs_Start(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_Start(InstancePtr)	\
-		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
-		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
-		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function stops the counter/timer. This macro may be called at any time
-* to stop the counter. The counter holds the last value until it is reset,
-* restarted or enabled.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return	None
-*
-* @note		C-style signature:
-*		void XTtcPs_Stop(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_Stop(InstancePtr)		\
-		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
-		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
-		 XTTCPS_CNT_CNTRL_DIS_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function checks whether the timer counter has already started.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance
-*
-* @return	Non-zero if the device has started, '0' otherwise.
-*
-* @note		C-style signature:
-*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_IsStarted(InstancePtr) \
-     ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
-       XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current 16-bit counter value. It may be called at
-* any time.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return	16-bit counter value.
-*
-* @note		C-style signature:
-*		u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_GetCounterValue(InstancePtr) \
-		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function sets the interval value to be used in interval mode.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	Value is the 16-bit value to be set in the interval register.
-*
-* @return	None
-*
-* @note		C-style signature:
-*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
-*
-****************************************************************************/
-#define XTtcPs_SetInterval(InstancePtr, Value)	\
-		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
-
-/*****************************************************************************/
-/**
-*
-* This function gets the interval value from the interval register.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return	16-bit interval value
-*
-* @note		C-style signature:
-*		u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_GetInterval(InstancePtr) \
-		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This macro resets the count register. It may be called at any time. The
-* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
-* the increment/decrement mode. The state of the counter, as started or
-* stopped, is not affected by calling reset.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return	None
-*
-* @note		C-style signature:
-*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_ResetCounterValue(InstancePtr) \
-		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
-		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
-		 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function enables the interrupts.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	InterruptMask defines which interrupt should be enabled.
-*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-*		This is a bit mask, all set bits will be enabled, cleared bits
-*		will not be disabled.
-*
-* @return	None.
-*
-* @note
-* C-style signature:
-*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
-		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
-		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
-		 (InterruptMask)))
-
-/*****************************************************************************/
-/**
-*
-* This function disables the interrupts.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	InterruptMask defines which interrupt should be disabled.
-*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-*		This is a bit mask, all set bits will be disabled, cleared bits
-*		will not be disabled.
-*
-* @return	None.
-*
-* @note
-* C-style signature:
-*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
-		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
-		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
-		 ~(InterruptMask)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
-*
-******************************************************************************/
-#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
-		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	InterruptMask defines which interrupt should be cleared.
-*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-*		This is a bit mask, all set bits will be cleared, cleared bits
-*		will not be cleared.
-*
-* @return	None.
-*
-* @note
-* C-style signature:
-*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
-		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
-		 (InterruptMask))
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization functions in xttcps_sinit.c
- */
-XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
-
-/*
- * Required functions, in xttcps.c
- */
-s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
-         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
-
-void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
-u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
-
-void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
-u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
-
-void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
-        u16 *Interval, u8 *Prescaler);
-
-/*
- * Functions for options, in file xttcps_options.c
- */
-s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
-u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
-
-/*
- * Function for self-test, in file xttcps_selftest.c
- */
-s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c
deleted file mode 100644
index 10c16eb02..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c
+++ /dev/null
@@ -1,111 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xttcps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XTtcPs_Config XTtcPs_ConfigTable[] =
-{
-	{
-		XPAR_PSU_TTC_0_DEVICE_ID,
-		XPAR_PSU_TTC_0_BASEADDR,
-		XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_1_DEVICE_ID,
-		XPAR_PSU_TTC_1_BASEADDR,
-		XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_2_DEVICE_ID,
-		XPAR_PSU_TTC_2_BASEADDR,
-		XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_3_DEVICE_ID,
-		XPAR_PSU_TTC_3_BASEADDR,
-		XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_4_DEVICE_ID,
-		XPAR_PSU_TTC_4_BASEADDR,
-		XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_5_DEVICE_ID,
-		XPAR_PSU_TTC_5_BASEADDR,
-		XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_6_DEVICE_ID,
-		XPAR_PSU_TTC_6_BASEADDR,
-		XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_7_DEVICE_ID,
-		XPAR_PSU_TTC_7_BASEADDR,
-		XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_8_DEVICE_ID,
-		XPAR_PSU_TTC_8_BASEADDR,
-		XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_9_DEVICE_ID,
-		XPAR_PSU_TTC_9_BASEADDR,
-		XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_10_DEVICE_ID,
-		XPAR_PSU_TTC_10_BASEADDR,
-		XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ
-	},
-	{
-		XPAR_PSU_TTC_11_DEVICE_ID,
-		XPAR_PSU_TTC_11_BASEADDR,
-		XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h
deleted file mode 100644
index af78bcd67..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_hw.h
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file defines the hardware interface to one of the three timer counters
-* in the Ps block.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- -------------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
-#define XTTCPS_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of the device.
- *
- * @{
- */
-#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000U  /**< Clock Control Register */
-#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000CU  /**< Counter Control Register*/
-#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018U  /**< Current Counter Value */
-#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024U  /**< Interval Count Value */
-#define XTTCPS_MATCH_0_OFFSET		0x00000030U  /**< Match 1 value */
-#define XTTCPS_MATCH_1_OFFSET		0x0000003CU  /**< Match 2 value */
-#define XTTCPS_MATCH_2_OFFSET		0x00000048U  /**< Match 3 value */
-#define XTTCPS_ISR_OFFSET			0x00000054U  /**< Interrupt Status Register */
-#define XTTCPS_IER_OFFSET			0x00000060U  /**< Interrupt Enable Register */
-/* @} */
-
-/** @name Clock Control Register
- * Clock Control Register definitions
- * @{
- */
-#define XTTCPS_CLK_CNTRL_PS_EN_MASK		0x00000001U  /**< Prescale enable */
-#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001EU  /**< Prescale value */
-#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT			 1U  /**< Prescale shift */
-#define XTTCPS_CLK_CNTRL_PS_DISABLE				16U  /**< Prescale disable */
-#define XTTCPS_CLK_CNTRL_SRC_MASK		0x00000020U  /**< Clock source */
-#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040U  /**< External Clock edge */
-/* @} */
-
-/** @name Counter Control Register
- * Counter Control Register definitions
- * @{
- */
-#define XTTCPS_CNT_CNTRL_DIS_MASK		0x00000001U /**< Disable the counter */
-#define XTTCPS_CNT_CNTRL_INT_MASK		0x00000002U /**< Interval mode */
-#define XTTCPS_CNT_CNTRL_DECR_MASK		0x00000004U /**< Decrement mode */
-#define XTTCPS_CNT_CNTRL_MATCH_MASK		0x00000008U /**< Match mode */
-#define XTTCPS_CNT_CNTRL_RST_MASK		0x00000010U /**< Reset counter */
-#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020U /**< Enable waveform */
-#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040U /**< Waveform polarity */
-#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021U /**< Reset value */
-/* @} */
-
-/** @name Current Counter Value Register
- * Current Counter Value Register definitions
- * @{
- */
-#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
-/* @} */
-
-/** @name Interval Value Register
- * Interval Value Register is the maximum value the counter will count up or
- * down to.
- * @{
- */
-#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
-/* @} */
-
-/** @name Match Registers
- * Definitions for Match registers, each timer counter has three match
- * registers.
- * @{
- */
-#define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
-#define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
-/* @} */
-
-/** @name Interrupt Registers
- * Following register bit mask is for all interrupt registers.
- *
- * @{
- */
-#define XTTCPS_IXR_INTERVAL_MASK	0x00000001U  /**< Interval Interrupt */
-#define XTTCPS_IXR_MATCH_0_MASK		0x00000002U  /**< Match 1 Interrupt */
-#define XTTCPS_IXR_MATCH_1_MASK		0x00000004U  /**< Match 2 Interrupt */
-#define XTTCPS_IXR_MATCH_2_MASK		0x00000008U  /**< Match 3 Interrupt */
-#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010U  /**< Counter Overflow */
-#define XTTCPS_IXR_ALL_MASK			0x0000001FU  /**< All valid Interrupts */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given Timer Counter register.
-*
-* @param	BaseAddress is the base address of the timer counter device.
-* @param	RegOffset is the register offset to be read
-*
-* @return	The 32-bit value of the register
-*
-* @note		C-style signature:
-*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
-    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Timer Counter register.
-*
-* @param	BaseAddress is the base address of the timer counter device.
-* @param	RegOffset is the register offset to be written
-* @param	Data is the 32-bit value to write to the register
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
-*		u32 Data)
-*
-*****************************************************************************/
-#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
-    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
-
-/****************************************************************************/
-/**
-*
-* Calculate a match register offset using the Match Register index.
-*
-* @param	MatchIndex is the 0-2 value of the match register
-*
-* @return	MATCH_N_OFFSET.
-*
-* @note		C-style signature:
-*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
-*
-*****************************************************************************/
-#define XTtcPs_Match_N_Offset(MatchIndex) \
-		((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c
deleted file mode 100644
index 532b235c5..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_options.c
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file contains functions to get or set option features for the device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 1.01a nm     03/05/2012 Removed break statement after return to remove
-*                         compilation warnings.
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
-	u32 Option;
-	u32 Mask;
-	u32 Register;
-} OptionsMap;
-
-static OptionsMap TmrCtrOptionsTable[] = {
-	{XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
-	 XTTCPS_CLK_CNTRL_OFFSET},
-	{XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
-	 XTTCPS_CLK_CNTRL_OFFSET},
-	{XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
-	 XTTCPS_CNT_CNTRL_OFFSET},
-	{XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
-	 XTTCPS_CNT_CNTRL_OFFSET},
-	{XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
-	 XTTCPS_CNT_CNTRL_OFFSET},
-	{XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
-	 XTTCPS_CNT_CNTRL_OFFSET},
-	{XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
-	 XTTCPS_CNT_CNTRL_OFFSET},
-};
-
-#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
-				sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the TTC device.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-* @param	Options contains the specified options to be set. This is a bit
-*		mask where a 1 means to turn the option on, and a 0 means to
-*		turn the option off. One or more bit values may be contained
-*		in the mask. See the bit definitions named XTTCPS_*_OPTION in
-*		the file xttcps.h.
-*
-* @return
-*		- XST_SUCCESS if options are successfully set.
-*		- XST_FAILURE if any of the options are unknown.
-*
-* @note		None
-*
-******************************************************************************/
-s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
-{
-	u32 CountReg;
-	u32 ClockReg;
-	u32 Index;
-	s32 Status = XST_SUCCESS;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    XTTCPS_CLK_CNTRL_OFFSET);
-	CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    XTTCPS_CNT_CNTRL_OFFSET);
-
-	/*
-	 * Loop through the options table, turning the option on or off
-	 * depending on whether the bit is set in the incoming options flag.
-	 */
-	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
-		if(Status != (s32)XST_FAILURE) {
-			if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
-
-			switch (TmrCtrOptionsTable[Index].Register) {
-
-			case XTTCPS_CLK_CNTRL_OFFSET:
-				/* Add option */
-				ClockReg |= TmrCtrOptionsTable[Index].Mask;
-				break;
-
-			case XTTCPS_CNT_CNTRL_OFFSET:
-				/* Add option */
-				CountReg |= TmrCtrOptionsTable[Index].Mask;
-				break;
-
-			default:
-				Status = XST_FAILURE;
-				break;
-			}
-		}
-		else {
-			switch (TmrCtrOptionsTable[Index].Register) {
-
-			case XTTCPS_CLK_CNTRL_OFFSET:
-				/* Remove option*/
-				ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
-				break;
-
-			case XTTCPS_CNT_CNTRL_OFFSET:
-				/* Remove option*/
-				CountReg &= ~TmrCtrOptionsTable[Index].Mask;
-				break;
-
-			default:
-				Status = XST_FAILURE;
-				break;
-				}
-			}
-		}
-	}
-
-	/*
-	 * Now write the registers. Leave it to the upper layers to restart the
-	 * device.
-	 */
-	if (Status != (s32)XST_FAILURE ) {
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
-		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
-				  XTTCPS_CNT_CNTRL_OFFSET, CountReg);
-	}
-
-	return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the settings for the options for the TTC device.
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return
-*
-* The return u32 contains the specified options that are set. This is a bit
-* mask where a '1' means the option is on, and a'0' means the option is off.
-* One or more bit values may be contained in the mask. See the bit definitions
-* named XTTCPS_*_OPTION in the file xttcps.h.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
-{
-	u32 OptionsFlag = 0U;
-	u32 Register;
-	u32 Index;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
-	/*
-	 * Loop through the options table to determine which options are set
-	 */
-	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
-		/*
-		 * Get the control register to determine which options are
-		 * currently set.
-		 */
-		Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
-					      TmrCtrOptionsTable[Index].
-					      Register);
-
-		if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
-			OptionsFlag |= TmrCtrOptionsTable[Index].Option;
-		}
-	}
-
-	return OptionsFlag;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c
deleted file mode 100644
index 4923df667..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_selftest.c
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file contains the implementation of self test function for the
-* XTtcPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device.
-*
-*
-* @param	InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return
-*
-*	- XST_SUCCESS if successful
-*	- XST_FAILURE indicates a register did not read or write correctly
-*
-* @note		This test fails if it is not called right after initialization.
-*
-******************************************************************************/
-s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
-{
-	s32 Status;
-	u32 TempReg;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * All the TTC registers should be in their default state right now.
-	 */
-	TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XTTCPS_CNT_CNTRL_OFFSET);
-	if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
-		Status = XST_FAILURE;
-	}
-	else {
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
deleted file mode 100644
index ef3c6ea6b..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_sinit.c
-* @addtogroup ttcps_v3_0
-* @{
-*
-* The implementation of the XTtcPs driver's static initialization functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param	DeviceId contains the unique ID of the device
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xttcps.h for the definition of XTtcPs_Config.
-*
-* @note		None.
-*
-******************************************************************************/
-XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
-{
-	XTtcPs_Config *CfgPtr = NULL;
-	u32 Index;
-
-	for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
-		if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XTtcPs_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XTtcPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile
new file mode 100644
index 000000000..35c277dde
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner ttcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ttcps"
+
+ttcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: ttcps_includes
+
+ttcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c
new file mode 100644
index 000000000..394262868
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c
@@ -0,0 +1,443 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	   01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
+*						to stop the timer before configuring
+* 3.2   mus    10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+*                       32 bit interval count for zynq ultrascale+mpsoc
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+*  - Overflow Mode
+*  - Internal (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific TTC device.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, then use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return
+*
+* 		- XST_SUCCESS if the initialization is successful.
+*		- XST_DEVICE_IS_STARTED if the device is started. It must be
+*		  stopped to re-initialize.
+*
+* @note		Device has to be stopped first to call this function to
+*		initialize it.
+*
+******************************************************************************/
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+			      u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 IsStartResult;
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+
+	IsStartResult = XTtcPs_IsStarted(InstancePtr);
+	/*
+	 * If the timer counter has already started, return an error
+	 * Device should be stopped first.
+	 */
+	if(IsStartResult == (u32)TRUE) {
+		Status = XST_DEVICE_IS_STARTED;
+	} else {
+
+		/*
+		 * stop the timer before configuring
+		 */
+		XTtcPs_Stop(InstancePtr);
+		/*
+		 * Reset the count control register to it's default value.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET,
+				  XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+		/*
+		 * Reset the rest of the registers to the default values.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_1_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_IER_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		/*
+		 * Reset the counter value
+		 */
+		XTtcPs_ResetCounterValue(InstancePtr);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+* @param	Value is the 16-bit value to be set in the match register.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
+{
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
+
+	/*
+	 * Write the value to the correct match register with MatchIndex
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+	u32 MatchReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XTtcPs_Match_N_Offset(MatchIndex));
+
+	return (u16) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	PrescalerValue is a number from 0-16 that sets the prescaler
+*		to use.
+*		If the parameter is 0 - 15, use a prescaler on the clock of
+*		2^(PrescalerValue+1), or 2-65536.
+*		If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+*		prescaler.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			   XTTCPS_CLK_CNTRL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register
+	 */
+	ClockReg &=
+		~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+	if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+		/*
+		 * Set the prescaler value and enable prescaler
+		 */
+		ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
+		ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
+	}
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* <pre>
+* @return	The value(n) from which the prescalar value is calculated
+*		as 2^(n+1). Some example values are given below :
+*
+* 	Value		Prescaler
+* 	0		2
+* 	1		4
+* 	N		2^(n+1)
+* 	15		65536
+* 	16		1
+* </pre>
+*
+* @note		None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+	u8 Status;
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+
+	if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+		/*
+		 * Prescaler is disabled. Return the correct flag value
+		 */
+		Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
+	}
+	else {
+
+		Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Freq is the requested output frequency for the device.
+* @param	Interval is the interval value for the given frequency,
+*		it is the output value for this function.
+* @param	Prescaler is the prescaler value for the given frequency,
+*		it is the output value for this function.
+*
+* @return	None.
+*
+* @note
+*  Upon successful calculation for the given frequency, Interval and Prescaler
+*  carry the settings for the timer counter; Upon unsuccessful calculation,
+*  Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+*  signal the caller of failure. Therefore, caller needs to check the return
+*  interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        XInterval *Interval, u8 *Prescaler)
+{
+	u8 TmpPrescaler;
+	u32 TempValue;
+	u32 InputClock;
+
+	InputClock = InstancePtr->Config.InputClockHz;
+	/*
+	 * Find the smallest prescaler that will work for a given frequency. The
+	 * smaller the prescaler, the larger the count and the more accurate the
+	 *  PWM setting.
+	 */
+	TempValue = InputClock/ Freq;
+
+	if (TempValue < 4U) {
+		/*
+		 * The frequency is too high, it is too close to the input
+		 * clock value. Use maximum values to signal caller.
+		 */
+		*Interval = XTTCPS_MAX_INTERVAL_COUNT;
+		*Prescaler = 0xFFU;
+		return;
+	}
+
+	/*
+	 * First, do we need a prescaler or not?
+	 */
+	if (((u32)65536U) > TempValue) {
+		/*
+		 * We do not need a prescaler, so set the values appropriately
+		 */
+		*Interval = (XInterval)TempValue;
+		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+		return;
+	}
+
+
+	for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+	     TmpPrescaler++) {
+		TempValue =	InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
+
+		/*
+		 * The first value less than 2^16 is the best bet
+		 */
+		if (((u32)65536U) > TempValue) {
+			/*
+			 * Set the values appropriately
+			 */
+			*Interval = (XInterval)TempValue;
+			*Prescaler = TmpPrescaler;
+			return;
+		}
+	}
+
+	/* Can not find interval values that work for the given frequency.
+	 * Return maximum values to signal caller.
+	 */
+	*Interval = XTTCPS_MAX_INTERVAL_COUNT;
+	*Prescaler = 0XFFU;
+	return;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
new file mode 100644
index 000000000..be266d9b3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
@@ -0,0 +1,460 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_0
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+*	. At a regular, predefined period, that is on a timed interval
+*	. When the counter registers overflow
+* 	. When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* <b>Initialization & Configuration</b>
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* <b>Interrupts</b>
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+*  - Overflow Mode
+*  - Internal clock (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.2   mus    10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+*                       macros to return 32 bit values for zynq ultrascale+mpsoc
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H		/* prevent circular inclusions */
+#define XTTCPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK	0x00000001U 	/**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG	0x00000002U	/**< Clock on trailing edge for
+						     external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE	0x00000004U	/**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT		0x00000008U	/**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE	0x00000010U	/**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	  /**< Unique ID for device */
+	u32 BaseAddress;  /**< Base address for device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+	XTtcPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+#else
+typedef u32 XInterval;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr)	\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
+		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr)		\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
+		 XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance
+*
+* @return	Non-zero if the device has started, '0' otherwise.
+*
+* @note		C-style signature:
+*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+     ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+       XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit counter value.
+*           zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+               InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Value is the 16-bit value to be set in the interval register.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value)	\
+		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit interval value.
+*           zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+		 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be enabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be enabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
+		 (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be disabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be disabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
+		 ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
+		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be cleared.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be cleared, cleared bits
+*		will not be cleared.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+		 (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c
new file mode 100644
index 000000000..28d356092
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c
@@ -0,0 +1,111 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_TTC_0_DEVICE_ID,
+		XPAR_PSU_TTC_0_BASEADDR,
+		XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_1_DEVICE_ID,
+		XPAR_PSU_TTC_1_BASEADDR,
+		XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_2_DEVICE_ID,
+		XPAR_PSU_TTC_2_BASEADDR,
+		XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_3_DEVICE_ID,
+		XPAR_PSU_TTC_3_BASEADDR,
+		XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_4_DEVICE_ID,
+		XPAR_PSU_TTC_4_BASEADDR,
+		XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_5_DEVICE_ID,
+		XPAR_PSU_TTC_5_BASEADDR,
+		XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_6_DEVICE_ID,
+		XPAR_PSU_TTC_6_BASEADDR,
+		XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_7_DEVICE_ID,
+		XPAR_PSU_TTC_7_BASEADDR,
+		XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_8_DEVICE_ID,
+		XPAR_PSU_TTC_8_BASEADDR,
+		XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_9_DEVICE_ID,
+		XPAR_PSU_TTC_9_BASEADDR,
+		XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_10_DEVICE_ID,
+		XPAR_PSU_TTC_10_BASEADDR,
+		XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_11_DEVICE_ID,
+		XPAR_PSU_TTC_11_BASEADDR,
+		XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
new file mode 100644
index 000000000..af78bcd67
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
@@ -0,0 +1,212 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
+#define XTTCPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000U  /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000CU  /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018U  /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024U  /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET		0x00000030U  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET		0x0000003CU  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET		0x00000048U  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET			0x00000054U  /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET			0x00000060U  /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK		0x00000001U  /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001EU  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT			 1U  /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE				16U  /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK		0x00000020U  /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040U  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK		0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK		0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK		0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK		0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK		0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
+#define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK	0x00000001U  /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK		0x00000002U  /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK		0x00000004U  /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK		0x00000008U  /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010U  /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK			0x0000001FU  /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param	MatchIndex is the 0-2 value of the match register
+*
+* @return	MATCH_N_OFFSET.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+		((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
new file mode 100644
index 000000000..532b235c5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
@@ -0,0 +1,243 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains functions to get or set option features for the device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm     03/05/2012 Removed break statement after return to remove
+*                         compilation warnings.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+	u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+	{XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+				sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained
+*		in the mask. See the bit definitions named XTTCPS_*_OPTION in
+*		the file xttcps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_FAILURE if any of the options are unknown.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+	u32 CountReg;
+	u32 ClockReg;
+	u32 Index;
+	s32 Status = XST_SUCCESS;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+	CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CNT_CNTRL_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		if(Status != (s32)XST_FAILURE) {
+			if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
+
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Add option */
+				ClockReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Add option */
+				CountReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+			}
+		}
+		else {
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Remove option*/
+				ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Remove option*/
+				CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Now write the registers. Leave it to the upper layers to restart the
+	 * device.
+	 */
+	if (Status != (s32)XST_FAILURE ) {
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 Register;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		/*
+		 * Get the control register to determine which options are
+		 * currently set.
+		 */
+		Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+					      TmrCtrOptionsTable[Index].
+					      Register);
+
+		if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
+			OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
new file mode 100644
index 000000000..4923df667
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+*	- XST_SUCCESS if successful
+*	- XST_FAILURE indicates a register did not read or write correctly
+*
+* @note		This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+	s32 Status;
+	u32 TempReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the TTC registers should be in their default state right now.
+	 */
+	TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XTTCPS_CNT_CNTRL_OFFSET);
+	if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
+		Status = XST_FAILURE;
+	}
+	else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
new file mode 100644
index 000000000..ef3c6ea6b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+	XTtcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+		if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XTtcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XTtcPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile
deleted file mode 100644
index 88b1e625c..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xuartps_libs clean
-
-%.o: %.c
-	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
-	echo "Compiling uartps"
-
-xuartps_libs: ${OBJECTS}
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xuartps_includes
-
-xuartps_includes:
-	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
-	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c
deleted file mode 100644
index a338d1f09..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c
+++ /dev/null
@@ -1,644 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps.c
-* @addtogroup uartps_v3_1
-* @{
-*
-* This file contains the implementation of the interface functions for XUartPs
-* driver. Refer to the header file xuartps.h for more detailed information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	 Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00	drg/jz 01/13/10 First Release
-* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
-*                       baud rate. CR# 804281.
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-/* The following constant defines the amount of error that is allowed for
- * a specified baud rate. This error is the difference between the actual
- * baud rate that will be generated using the specified clock and the
- * desired baud rate.
- */
-#define XUARTPS_MAX_BAUD_ERROR_RATE		 3U	/* max % error allowed */
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
-				 u32 ByteCount);
-
-u32  XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-u32  XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* Initializes a specific XUartPs instance such that it is ready to be used.
-* The data format of the device is setup for 8 data bits, 1 stop bit, and no
-* parity by default. The baud rate is set to a default value specified by
-* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
-* receive FIFO threshold is set for 8 bytes. The default operating mode of the
-* driver is polled mode.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	Config is a reference to a structure containing information
-*		about a specific XUartPs driver.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the address
-*		mapping from EffectiveAddr to the device physical base address
-*		unchanged once this function is invoked. Unexpected errors may
-*		occur if the address mapping changes after this function is
-*		called. If address translation is not used, pass in the physical
-*		address instead.
-*
-* @return
-*
-*		- XST_SUCCESS if initialization was successful
-*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
-*		  the inputclock frequency is not divisible with an acceptable
-*		  amount of error
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-*   All interrupts are disabled.
-*
-*****************************************************************************/
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
-				   XUartPs_Config * Config, u32 EffectiveAddr)
-{
-	s32 Status;
-	u32 ModeRegister;
-	u32 BaudRate;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(Config != NULL);
-
-	/* Setup the driver instance using passed in parameters */
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-	InstancePtr->Config.InputClockHz = Config->InputClockHz;
-	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
-
-	/* Initialize other instance data to default values */
-	InstancePtr->Handler = XUartPs_StubHandler;
-
-	InstancePtr->SendBuffer.NextBytePtr = NULL;
-	InstancePtr->SendBuffer.RemainingBytes = 0U;
-	InstancePtr->SendBuffer.RequestedBytes = 0U;
-
-	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
-	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
-	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
-
-	/* Initialize the platform data */
-	InstancePtr->Platform = XGetPlatform_Info();
-
-	InstancePtr->is_rxbs_error = 0U;
-
-	/* Flag that the driver instance is ready to use */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-	/*
-	 * Set the default baud rate here, can be changed prior to
-	 * starting the device
-	 */
-	BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
-	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
-	if (Status != (s32)XST_SUCCESS) {
-		InstancePtr->IsReady = 0U;
-	} else {
-
-		/*
-		 * Set up the default data format: 8 bit data, 1 stop bit, no
-		 * parity
-		 */
-		ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XUARTPS_MR_OFFSET);
-
-		/* Mask off what's already there */
-		ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
-						 (u32)XUARTPS_MR_STOPMODE_MASK |
-						 (u32)XUARTPS_MR_PARITY_MASK));
-
-		/* Set the register value to the desired data format */
-		ModeRegister |=	((u32)XUARTPS_MR_CHARLEN_8_BIT |
-						 (u32)XUARTPS_MR_STOPMODE_1_BIT |
-						 (u32)XUARTPS_MR_PARITY_NONE);
-
-		/* Write the mode register out */
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
-				   ModeRegister);
-
-		/* Set the RX FIFO trigger at 8 data bytes. */
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XUARTPS_RXWM_OFFSET, 0x08U);
-
-		/* Set the RX timeout to 1, which will be 4 character time */
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XUARTPS_RXTOUT_OFFSET, 0x01U);
-
-		/* Disable all interrupts, polled mode is the default */
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
-				   XUARTPS_IXR_MASK);
-
-		Status = XST_SUCCESS;
-	}
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sends the specified buffer using the device in either
-* polled or interrupt driven mode. This function is non-blocking, if the device
-* is busy sending data, it will return and indicate zero bytes were sent.
-* Otherwise, it fills the TX FIFO as much as it can, and return the number of
-* bytes sent.
-*
-* In a polled mode, this function will only send as much data as TX FIFO can
-* buffer. The application may need to call it repeatedly to send the entire
-* buffer.
-*
-* In interrupt mode, this function will start sending the specified buffer,
-* then the interrupt handler will continue sending data until the entire
-* buffer has been sent. A callback function, as specified by the application,
-* will be called to indicate the completion of sending.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	BufferPtr is pointer to a buffer of data to be sent.
-* @param  	NumBytes contains the number of bytes to be sent. A value of
-*		zero will stop a previous send operation that is in progress
-*		in interrupt mode. Any data that was already put into the
-*		transmit FIFO will be sent.
-*
-* @return	The number of bytes actually sent.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called with
-* a value of zero to stop an operation that is already in progress.
-* <br><br>
-*
-*****************************************************************************/
-u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
-			   u32 NumBytes)
-{
-	u32 BytesSent;
-
-	/* Asserts validate the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(BufferPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Disable the UART transmit interrupts to allow this call to stop a
-	 * previous operation that may be interrupt driven.
-	 */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
-					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
-
-	/* Setup the buffer parameters */
-	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
-	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
-	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
-
-	/*
-	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
-	 * filling the TX FIFO.
-	 */
-	BytesSent = XUartPs_SendBuffer(InstancePtr);
-
-	return BytesSent;
-}
-
-/****************************************************************************/
-/**
-*
-* This function attempts to receive a specified number of bytes of data
-* from the device and store it into the specified buffer. This function works
-* for both polled or interrupt driven modes. It is non-blocking.
-*
-* In a polled mode, this function will only receive the data already in the
-* RX FIFO. The application may need to call it repeatedly to receive the
-* entire buffer. Polled mode is the default mode of operation for the device.
-*
-* In interrupt mode, this function will start the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue receiving data
-* until the entire buffer has been received. A callback function, as specified
-* by the application, will be called to indicate the completion of the
-* receiving or error conditions.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-* @param	BufferPtr is pointer to buffer for data to be received into
-* @param	NumBytes is the number of bytes to be received. A value of zero
-*		will stop a previous receive operation that is in progress in
-*		interrupt mode.
-*
-* @return	The number of bytes received.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called
-* with a value of zero to stop an operation that is already in progress.
-*
-*****************************************************************************/
-u32 XUartPs_Recv(XUartPs *InstancePtr,
-			  u8 *BufferPtr, u32 NumBytes)
-{
-	u32 ReceivedCount;
-	u32 ImrRegister;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(BufferPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Disable all the interrupts.
-	 * This stops a previous operation that may be interrupt driven
-	 */
-	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XUARTPS_IMR_OFFSET);
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
-		XUARTPS_IXR_MASK);
-
-	/* Setup the buffer parameters */
-	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
-	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
-	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
-
-	/* Receive the data from the device */
-	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
-
-	/* Restore the interrupt state */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
-		ImrRegister);
-
-	return ReceivedCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function sends a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function for the XUartPs driver such that it may be called from a shell
-* function that sets up the buffer or from an interrupt handler.
-*
-* This function sends the specified buffer in either polled or interrupt
-* driven modes. This function is non-blocking.
-*
-* In a polled mode, this function only sends as much data as the TX FIFO
-* can buffer. The application may need to call it repeatedly to send the
-* entire buffer.
-*
-* In interrupt mode, this function starts the sending of the buffer, if not
-* the entire buffer has been sent, then the interrupt handler continues the
-* sending until the entire buffer has been sent. A callback function, as
-* specified by the application, will be called to indicate the completion of
-* sending.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-*
-* @return	The number of bytes actually sent
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
-{
-	u32 SentCount = 0U;
-	u32 ImrRegister;
-
-	/*
-	 * If the TX FIFO is full, send nothing.
-	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
-	 * data has been put into the FIFO.
-	 */
-	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
-		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
-
-		/* Fill the FIFO from the buffer */
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XUARTPS_FIFO_OFFSET,
-				   ((u32)InstancePtr->SendBuffer.
-				   NextBytePtr[SentCount]));
-
-		/* Increment the send count. */
-		SentCount++;
-	}
-
-	/* Update the buffer to reflect the bytes that were sent from it */
-	InstancePtr->SendBuffer.NextBytePtr += SentCount;
-	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
-
-	/*
-	 * If interrupts are enabled as indicated by the receive interrupt, then
-	 * enable the TX FIFO empty interrupt, so further action can be taken
-	 * for this sending.
-	 */
-	ImrRegister =
-		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XUARTPS_IMR_OFFSET);
-	if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
-		((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
-		((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
-
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-					   XUARTPS_IER_OFFSET,
-					   ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
-	}
-
-	return SentCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function receives a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function, and it may be called from a shell function that sets up the buffer
-* or from an interrupt handler.
-*
-* This function attempts to receive a specified number of bytes from the
-* device and store it into the specified buffer. This function works for
-* either polled or interrupt driven modes. It is non-blocking.
-*
-* In polled mode, this function only receives as much data as in the RX FIFO.
-* The application may need to call it repeatedly to receive the entire buffer.
-* Polled mode is the default mode for the driver.
-*
-* In interrupt mode, this function starts the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue until the
-* entire buffer has been received. A callback function, as specified by the
-* application, will be called to indicate the completion of the receiving or
-* error conditions.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-*
-* @return	The number of bytes received.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
-{
-	u32 CsrRegister;
-	u32 ReceivedCount = 0U;
-	u32 ByteStatusValue, EventData;
-	u32 Event;
-
-	/*
-	 * Read the Channel Status Register to determine if there is any data in
-	 * the RX FIFO
-	 */
-	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XUARTPS_SR_OFFSET);
-
-	/*
-	 * Loop until there is no more data in RX FIFO or the specified
-	 * number of bytes has been received
-	 */
-	while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&&
-		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
-
-		if (InstancePtr->is_rxbs_error) {
-			ByteStatusValue = XUartPs_ReadReg(
-						InstancePtr->Config.BaseAddress,
-						XUARTPS_RXBS_OFFSET);
-			if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
-				EventData = ByteStatusValue;
-				Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
-				/*
-				 * Call the application handler to indicate that there is a receive
-				 * error or a break interrupt, if the application cares about the
-				 * error it call a function to get the last errors.
-				 */
-				InstancePtr->Handler(InstancePtr->CallBackRef,
-							Event, EventData);
-			}
-		}
-
-		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
-			XUartPs_ReadReg(InstancePtr->Config.
-				  BaseAddress,
-				  XUARTPS_FIFO_OFFSET);
-
-		ReceivedCount++;
-
-		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-								XUARTPS_SR_OFFSET);
-	}
-	InstancePtr->is_rxbs_error = 0;
-	/*
-	 * Update the receive buffer to reflect the number of bytes just
-	 * received
-	 */
-	if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
-		InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
-	}
-	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
-
-	return ReceivedCount;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the baud rate for the device. Checks the input value for
-* validity and also verifies that the requested rate can be configured to
-* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
-* If the provided rate is not possible, the current setting is unchanged.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-* @param	BaudRate to be set
-*
-* @return
-*		- XST_SUCCESS if everything configured as expected
-*		- XST_UART_BAUD_ERROR if the requested rate is not available
-*		  because there was too much error
-*
-* @note		None.
-*
-*****************************************************************************/
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
-{
-	u32 IterBAUDDIV;	/* Iterator for available baud divisor values */
-	u32 BRGR_Value;		/* Calculated value for baud rate generator */
-	u32 CalcBaudRate;	/* Calculated baud rate */
-	u32 BaudError;		/* Diff between calculated and requested baud rate */
-	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
-	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
-	u32 Best_Error = 0xFFFFFFFFU;
-	u32 PercentError;
-	u32 ModeReg;
-	u32 InputClk;
-
-	/* Asserts validate the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
-	Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
-
-	/*
-	 * Make sure the baud rate is not impossilby large.
-	 * Fastest possible baud rate is Input Clock / 2.
-	 */
-	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
-		return XST_UART_BAUD_ERROR;
-	}
-	/* Check whether the input clock is divided by 8 */
-	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
-				 XUARTPS_MR_OFFSET);
-
-	InputClk = InstancePtr->Config.InputClockHz;
-	if(ModeReg & XUARTPS_MR_CLKSEL) {
-		InputClk = InstancePtr->Config.InputClockHz / 8;
-	}
-
-	/*
-	 * Determine the Baud divider. It can be 4to 254.
-	 * Loop through all possible combinations
-	 */
-	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
-
-		/* Calculate the value for BRGR register */
-		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
-
-		/* Calculate the baud rate from the BRGR value */
-		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
-
-		/* Avoid unsigned integer underflow */
-		if (BaudRate > CalcBaudRate) {
-			BaudError = BaudRate - CalcBaudRate;
-		}
-		else {
-			BaudError = CalcBaudRate - BaudRate;
-		}
-
-		/* Find the calculated baud rate closest to requested baud rate. */
-		if (Best_Error > BaudError) {
-
-			Best_BRGR = BRGR_Value;
-			Best_BAUDDIV = IterBAUDDIV;
-			Best_Error = BaudError;
-		}
-	}
-
-	/* Make sure the best error is not too large. */
-	PercentError = (Best_Error * 100) / BaudRate;
-	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
-		return XST_UART_BAUD_ERROR;
-	}
-
-	/* Disable TX and RX to avoid glitches when setting the baud rate. */
-	XUartPs_DisableUart(InstancePtr);
-
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
-
-	/* RX and TX SW reset */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
-				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
-
-	/* Enable device */
-	XUartPs_EnableUart(InstancePtr);
-
-	InstancePtr->BaudRate = BaudRate;
-
-	return XST_SUCCESS;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function is a stub handler that is the default handler such that if the
-* application has not set the handler when interrupts are enabled, this
-* function will be called.
-*
-* @param	CallBackRef is unused by this function.
-* @param	Event is unused by this function.
-* @param	ByteCount is unused by this function.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
-				 u32 ByteCount)
-{
-	(void *) CallBackRef;
-	(void) Event;
-	(void) ByteCount;
-	/* Assert occurs always since this is a stub and should never be called */
-	Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h
deleted file mode 100644
index 6bd42b21c..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_1
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* <b>Initialization & Configuration</b>
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-*	 configuration structure provided by the caller. If running in a system
-*	 with address translation, the parameter EffectiveAddr should be the
-* 	  virtual address.
-*
-* <b>Baud Rate</b>
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. Ther input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-* <pre>
-*	baud_rate = input_clock / (bgen * (bdiv + 1)
-* </pre>
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* <b>Interrupts</b>
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* <b>Data Transfer</b>
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a	drg/jz 01/12/10 First Release
-* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
-*		        in XUartPs_SetFlowDelay where the value was not
-*			being written to the register.
-* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
-*			instance structure and the driver is updated to use
-*			InputClockHz parameter from the XUartPs_Config config
-*			structure.
-*			Added a parameter to XUartPs_Config structure which
-*			specifies whether the user has selected Modem pins
-*			to be connected to MIO or FMIO.
-*			Added the tcl file to generate the xparameters.h
-* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-*			with the correct values for CR 666724
-* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
-*			and XUARTPS_IXR_TTRIG.
-*			Modified the name of these defines
-*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk     08/22/13 Added API for uart reset and related
-*			constant definitions.
-* 2.0   hk      03/07/14 Version number revised.
-* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
-*                       baud rate. CR# 804281.
-* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
-*			Support for Zynq Ultrascale Mp added.
-* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
-*						platform variable in driver instance structure.
-* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
-*			uart is connected to a valid interrupt controller CR#946803.
-*
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H		/* prevent circular inclusions */
-#define XUARTPS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE	 921600U
-#define XUARTPS_MIN_RATE	 110U
-
-#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified.  These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
-											 *	error detected */
-#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;	 /**< Unique ID  of device */
-	u32 BaseAddress; /**< Base address of device (IPIF) */
-	u32 InputClockHz;/**< Input clock frequency */
-	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
-				 *  to MIO or FMIO */
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
-	u8 *NextBytePtr;
-	u32 RequestedBytes;
-	u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
-	u32 BaudRate;	/**< In bps, ie 1200 */
-	u32 DataBits;	/**< Number of data bits */
-	u32 Parity;		/**< Parity */
-	u8 StopBits;	/**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the handler, and is passed back to the upper layer
- *		when the handler is called. It is used to find the device driver
- *		instance.
- * @param	Event contains one of the event constants indicating events that
- *		have occurred.
- * @param	EventData contains the number of bytes sent or received at the
- *		time of the call for send and receive events and contains the
- *		modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
-				  u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
-	XUartPs_Config Config;	/* Configuration data structure */
-	u32 InputClockHz;	/* Input clock frequency */
-	u32 IsReady;		/* Device is initialized and ready */
-	u32 BaudRate;		/* Current baud rate */
-
-	XUartPsBuffer SendBuffer;
-	XUartPsBuffer ReceiveBuffer;
-
-	XUartPs_Handler Handler;
-	void *CallBackRef;	/* Callback reference for event handler */
-	u32 Platform;
-	u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr)   \
-	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr)  \
-	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
-   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
-			(u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
-   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
-	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
-	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
-   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
-	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
-	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*		- TRUE if a byte can be sent
-*		- FALSE if the Transmitter Fifo is not empty
-*
-* @note		C-Style signature:
-*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr)				\
-	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
-	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
-				  XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
-			   u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
-			   u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
-			 void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
deleted file mode 100644
index 94aaf5b2e..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
+++ /dev/null
@@ -1,63 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xuartps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XUartPs_Config XUartPs_ConfigTable[] =
-{
-	{
-		XPAR_PSU_UART_0_DEVICE_ID,
-		XPAR_PSU_UART_0_BASEADDR,
-		XPAR_PSU_UART_0_UART_CLK_FREQ_HZ,
-		XPAR_PSU_UART_0_HAS_MODEM
-	},
-	{
-		XPAR_PSU_UART_1_DEVICE_ID,
-		XPAR_PSU_UART_1_BASEADDR,
-		XPAR_PSU_UART_1_UART_CLK_FREQ_HZ,
-		XPAR_PSU_UART_1_HAS_MODEM
-	}
-};
-
-
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c
deleted file mode 100644
index 299dd35ae..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_hw.c
-* @addtogroup uartps_v3_1
-* @{
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00	drg/jz 01/12/10 First Release
-* 1.05a hk     08/22/13 Added reset function
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xuartps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* This function sends one byte using the device. This function operates in
-* polled mode and blocks until the data has been put into the TX FIFO register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	Data contains the byte to be sent.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_SendByte(u32 BaseAddress, u8 Data)
-{
-	/* Wait until there is space in TX FIFO */
-	while (XUartPs_IsTransmitFull(BaseAddress)) {
-		;
-	}
-
-	/* Write the byte into the TX FIFO */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
-}
-
-/****************************************************************************/
-/**
-*
-* This function receives a byte from the device. It operates in polled mode
-* and blocks until a byte has received.
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @return	The data byte received.
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XUartPs_RecvByte(u32 BaseAddress)
-{
-	u32 RecievedByte;
-	/* Wait until there is data */
-	while (!XUartPs_IsReceiveData(BaseAddress)) {
-		;
-	}
-	RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
-	/* Return the byte received */
-	return (u8)RecievedByte;
-}
-
-/****************************************************************************/
-/**
-*
-* This function resets UART
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @return	None
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_ResetHw(u32 BaseAddress)
-{
-
-	/* Disable interrupts */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
-
-	/* Disable receive and transmit */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
-				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
-
-	/*
-	 * Software reset of receive and transmit
-	 * This clears the FIFO.
-	 */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
-				((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
-
-	/* Clear status flags - SW reset wont clear sticky flags. */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
-
-	/*
-	 * Mode register reset value : All zeroes
-	 * Normal mode, even parity, 1 stop bit
-	 */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
-				XUARTPS_MR_CHMODE_NORM);
-
-	/* Rx and TX trigger register reset values */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
-				XUARTPS_RXWM_RESET_VAL);
-	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
-				XUARTPS_TXWM_RESET_VAL);
-
-	/* Rx timeout disabled by default */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
-				XUARTPS_RXTOUT_DISABLE);
-
-	/* Baud rate generator and dividor reset values */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
-				XUARTPS_BAUDGEN_RESET_VAL);
-	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
-				XUARTPS_BAUDDIV_RESET_VAL);
-
-	/*
-	 * Control register reset value -
-	 * RX and TX are disable by default
-	 */
-	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
-				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
-						(u32)XUARTPS_CR_STOPBRK));
-
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h
deleted file mode 100644
index 9f5f0b700..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h
+++ /dev/null
@@ -1,449 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xuartps_hw.h
-* @addtogroup uartps_v3_1
-* @{
-*
-* This header file contains the hardware interface of an XUartPs device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00	drg/jz 01/12/10 First Release
-* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
-*			and XUARTPS_IXR_TTRIG.
-*			Modified the names of these defines
-*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk     08/22/13 Added prototype for uart reset and related
-*			constant definitions.
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
-#define XUARTPS_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the UART.
- * @{
- */
-#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET		0x0048U  /**< RX FIFO Byte Status [11:0] */
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
-#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
-#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
-#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
-#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
-#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
-/* @}*/
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
-#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
-/* @} */
-
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
-#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
-#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
-#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
-/* @} */
-
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
-#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
-#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
-#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
-/* @} */
-
-/** @name Transmit FIFO Trigger Level Register
- *
- * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
- * which the TX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
-#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define XUARTPS_MODEMCR_FCM	0x00000010U  /**< Flow control mode */
-#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
-#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
-#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
-#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
-#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
-#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
-#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
-#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
-#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
-#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
-/* @} */
-
-/** @name Receiver FIFO Byte Status Register
- *
- * The Receiver FIFO Status register is used to have a continuous
- * monitoring of the raw unmasked byte status information. The register
- * contains frame, parity and break status information for the top
- * four bytes in the RX FIFO.
- *
- * Receiver FIFO Byte Status Register Bit Definition
- * @{
- */
-#define XUARTPS_RXBS_BYTE3_BRKE		0x00000800U /**< Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME		0x00000400U /**< Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE		0x00000200U /**< Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE		0x00000100U /**< Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME		0x00000080U /**< Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE		0x00000040U /**< Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE		0x00000020U /**< Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME		0x00000010U /**< Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE		0x00000008U /**< Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE		0x00000004U /**< Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME		0x00000002U /**< Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE		0x00000001U /**< Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK		0x00000007U /**< 3 bit RX byte status mask */
-/* @} */
-
-
-/*
- * Defines for backwards compatabilty, will be removed
- * in the next version of the driver
- */
-#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
-#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
-#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
-#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-* Read a UART register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the base address of the
-*		device.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
-*
-******************************************************************************/
-#define XUartPs_ReadReg(BaseAddress, RegOffset) \
-	Xil_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write a UART register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the base address of the
-*		device.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
-*						   u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
-	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @return	TRUE if there is receive data, FALSE otherwise.
-*
-* @note		C-Style signature:
-*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsReceiveData(BaseAddress)			 \
-	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
-	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param	BaseAddress contains the base address of the device.
-*
-* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-*		FIFO.
-*
-* @note		C-Style signature:
-*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitFull(BaseAddress)			 \
-	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
-	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
-
-/************************** Function Prototypes ******************************/
-
-void XUartPs_SendByte(u32 BaseAddress, u8 Data);
-
-u8 XUartPs_RecvByte(u32 BaseAddress);
-
-void XUartPs_ResetHw(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c
deleted file mode 100644
index 849cb48db..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_intr.c
-* @addtogroup uartps_v3_1
-* @{
-*
-* This file contains the functions for interrupt handling
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00  drg/jz 01/13/10 First Release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-static void ReceiveDataHandler(XUartPs *InstancePtr);
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
-static void ModemHandler(XUartPs *InstancePtr);
-
-
-/* Internal function prototypes implemented in xuartps.c */
-extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-typedef void (*Handler)(XUartPs *InstancePtr);
-
-/****************************************************************************/
-/**
-*
-* This function gets the interrupt mask
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*		The current interrupt mask. The mask indicates which interupts
-*		are enabled.
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
-{
-	/* Assert validates the input argument */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-
-	/* Read the Interrupt Mask register */
-	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-			 XUARTPS_IMR_OFFSET));
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the interrupt mask.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-* @param	Mask contains the interrupts to be enabled or disabled.
-*		A '1' enables an interupt, and a '0' disables.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
-{
-	u32 TempMask = Mask;
-	/* Assert validates the input arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-
-	TempMask &= (u32)XUARTPS_IXR_MASK;
-
-	/* Write the mask to the IER Register */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-		 XUARTPS_IER_OFFSET, TempMask);
-
-	/* Write the inverse of the Mask to the IDR register */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-		 XUARTPS_IDR_OFFSET, (~TempMask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-* @param	FuncPtr is the pointer to the callback function.
-* @param	CallBackRef is the upper layer callback reference passed back
-*		when the callback function is invoked.
-*
-* @return	None.
-*
-* @note
-*
-* There is no assert on the CallBackRef since the driver doesn't know what it
-* is (nor should it)
-*
-*****************************************************************************/
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
-		 void *CallBackRef)
-{
-	/*
-	 * Asserts validate the input arguments
-	 * CallBackRef not checked, no way to know what is valid
-	 */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(FuncPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	InstancePtr->Handler = FuncPtr;
-	InstancePtr->CallBackRef = CallBackRef;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is the interrupt handler for the driver.
-* It must be connected to an interrupt system by the application such that it
-* can be called when an interrupt occurs.
-*
-* @param	InstancePtr contains a pointer to the driver instance
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void XUartPs_InterruptHandler(XUartPs *InstancePtr)
-{
-	u32 IsrStatus;
-
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read the interrupt ID register to determine which
-	 * interrupt is active
-	 */
-	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XUARTPS_IMR_OFFSET);
-
-	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XUARTPS_ISR_OFFSET);
-
-	/* Dispatch an appropriate handler. */
-	if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
-			(u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
-		/* Received data interrupt */
-		ReceiveDataHandler(InstancePtr);
-	}
-
-	if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
-									 != (u32)0) {
-		/* Transmit data interrupt */
-		SendDataHandler(InstancePtr, IsrStatus);
-	}
-
-	/* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
-	if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
-			(u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
-		/* Received Error Status interrupt */
-		ReceiveErrorHandler(InstancePtr, IsrStatus);
-	}
-
-	if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
-		/* Received Timeout interrupt */
-		ReceiveTimeoutHandler(InstancePtr);
-	}
-
-	if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
-		/* Modem status interrupt */
-		ModemHandler(InstancePtr);
-	}
-
-	/* Clear the interrupt status. */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
-		IsrStatus);
-
-}
-
-/****************************************************************************/
-/*
-*
-* This function handles interrupts for receive errors which include
-* overrun errors, framing errors, parity errors, and the break interrupt.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
-	u32 ByteStatusValue, EventData;
-	u32 Event;
-
-	InstancePtr->is_rxbs_error = 0;
-
-	if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
-		(IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
-					| (u32)XUARTPS_IXR_FRAMING))) {
-		InstancePtr->is_rxbs_error = 1;
-	}
-	/*
-	 * If there are bytes still to be received in the specified buffer
-	 * go ahead and receive them. Removing bytes from the RX FIFO will
-	 * clear the interrupt.
-	 */
-
-	(void)XUartPs_ReceiveBuffer(InstancePtr);
-
-	if (!(InstancePtr->is_rxbs_error)) {
-		Event = XUARTPS_EVENT_RECV_ERROR;
-		EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
-			InstancePtr->ReceiveBuffer.RemainingBytes;
-
-		/*
-		 * Call the application handler to indicate that there is a receive
-		 * error or a break interrupt, if the application cares about the
-		 * error it call a function to get the last errors.
-		 */
-		InstancePtr->Handler(InstancePtr->CallBackRef,
-					Event,
-					EventData);
-	}
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the receive timeout interrupt. This interrupt occurs
-* whenever a number of bytes have been present in the RX FIFO and the receive
-* data line has been idle for at lease 4 or more character times, (the timeout
-* is set using XUartPs_SetrecvTimeout() function).
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
-{
-	u32 Event;
-
-	/*
-	 * If there are bytes still to be received in the specified buffer
-	 * go ahead and receive them. Removing bytes from the RX FIFO will
-	 * clear the interrupt.
-	 */
-	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
-		(void)XUartPs_ReceiveBuffer(InstancePtr);
-	}
-
-	/*
-	 * If there are no more bytes to receive then indicate that this is
-	 * not a receive timeout but the end of the buffer reached, a timeout
-	 * normally occurs if # of bytes is not divisible by FIFO threshold,
-	 * don't rely on previous test of remaining bytes since receive
-	 * function updates it
-	 */
-	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
-		Event = XUARTPS_EVENT_RECV_TOUT;
-	} else {
-		Event = XUARTPS_EVENT_RECV_DATA;
-	}
-
-	/*
-	 * Call the application handler to indicate that there is a receive
-	 * timeout or data event
-	 */
-	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
-				 InstancePtr->ReceiveBuffer.RequestedBytes -
-				 InstancePtr->ReceiveBuffer.RemainingBytes);
-
-}
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data is in RX FIFO.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void ReceiveDataHandler(XUartPs *InstancePtr)
-{
-	/*
-	 * If there are bytes still to be received in the specified buffer
-	 * go ahead and receive them. Removing bytes from the RX FIFO will
-	 * clear the interrupt.
-	 */
-	 if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
-		(void)XUartPs_ReceiveBuffer(InstancePtr);
-	}
-
-	 /* If the last byte of a message was received then call the application
-	 * handler, this code should not use an else from the previous check of
-	 * the number of bytes to receive because the call to receive the buffer
-	 * updates the bytes ramained
-	 */
-	if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
-		InstancePtr->Handler(InstancePtr->CallBackRef,
-				XUARTPS_EVENT_RECV_DATA,
-				(InstancePtr->ReceiveBuffer.RequestedBytes -
-				InstancePtr->ReceiveBuffer.RemainingBytes));
-	}
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data has been sent, the transmit
-* FIFO is empty (transmitter holding register).
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-* @param	IsrStatus is the register value for channel status register
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
-
-	/*
-	 * If there are not bytes to be sent from the specified buffer then disable
-	 * the transmit interrupt so it will stop interrupting as it interrupts
-	 * any time the FIFO is empty
-	 */
-	if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XUARTPS_IDR_OFFSET,
-				((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
-
-		/* Call the application handler to indicate the sending is done */
-		InstancePtr->Handler(InstancePtr->CallBackRef,
-					XUARTPS_EVENT_SENT_DATA,
-					InstancePtr->SendBuffer.RequestedBytes -
-					InstancePtr->SendBuffer.RemainingBytes);
-	}
-
-	/* If TX FIFO is empty, send more. */
-	else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
-		(void)XUartPs_SendBuffer(InstancePtr);
-	}
-	else {
-		/* Else with dummy entry for MISRA-C Compliance.*/
-		;
-	}
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles modem interrupts.  It does not do any processing
-* except to call the application handler to indicate a modem event.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-static void ModemHandler(XUartPs *InstancePtr)
-{
-	u32 MsrRegister;
-
-	/*
-	 * Read the modem status register so that the interrupt is acknowledged
-	 * and it can be passed to the callback handler with the event
-	 */
-	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-			  XUARTPS_MODEMSR_OFFSET);
-
-	/*
-	 * Call the application handler to indicate the modem status changed,
-	 * passing the modem status and the event data in the call
-	 */
-	InstancePtr->Handler(InstancePtr->CallBackRef,
-				  XUARTPS_EVENT_MODEM,
-				  MsrRegister);
-
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c
deleted file mode 100644
index 7051d07ec..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c
+++ /dev/null
@@ -1,761 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_options.c
-* @addtogroup uartps_v3_1
-* @{
-*
-* The implementation of the options functions for the XUartPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00  drg/jz 01/13/10 First Release
-* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
-*			value was not being written to the register.
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-/*
- * The following data type is a map from an option to the offset in the
- * register to which it belongs as well as its bit mask in that register.
- */
-typedef struct {
-	u16 Option;
-	u16 RegisterOffset;
-	u32 Mask;
-} Mapping;
-
-/*
- * Create the table which contains options which are to be processed to get/set
- * the options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-
-static Mapping OptionsTable[] = {
-	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
-	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
-	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
-	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
-	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
-	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
-	 XUARTPS_MODEMCR_RTS},
-	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
-	 XUARTPS_MODEMCR_DTR},
-	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
-};
-
-/* Create a constant for the number of entries in the table */
-
-#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Gets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simulataneously.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The current options for the UART. The optionss are bit masks that are
-* contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @note		None.
-*
-*****************************************************************************/
-u16 XUartPs_GetOptions(XUartPs *InstancePtr)
-{
-	u16 Options = 0U;
-	u32 Register;
-	u32 Index;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Loop thru the options table to map the physical options in the
-	 * registers of the UART to the logical options to be returned
-	 */
-	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
-		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-						 OptionsTable[Index].
-						 RegisterOffset);
-
-		/*
-		 * If the bit in the register which correlates to the option
-		 * is set, then set the corresponding bit in the options,
-		 * ignoring any bits which are zero since the options variable
-		 * is initialized to zero
-		 */
-		if ((Register & OptionsTable[Index].Mask) != (u32)0) {
-			Options |= OptionsTable[Index].Option;
-		}
-	}
-
-	return Options;
-}
-
-/****************************************************************************/
-/**
-*
-* Sets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simultaneously.
-*
-* The GetOptions function may be called to retrieve the currently enabled
-* options. The result is ORed in the desired new settings to be enabled and
-* ANDed with the inverse to clear the settings to be disabled. The resulting
-* value is then used as the options for the SetOption function call.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	Options contains the options to be set which are bit masks
-*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
-{
-	u32 Index;
-	u32 Register;
-
-	/* Assert validates the input arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Loop thru the options table to map the logical options to the
-	 * physical options in the registers of the UART.
-	 */
-	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
-
-		/*
-		 * Read the register which contains option so that the register
-		 * can be changed without destoying any other bits of the
-		 * register.
-		 */
-		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-						 OptionsTable[Index].
-						 RegisterOffset);
-
-		/*
-		 * If the option is set in the input, then set the corresponding
-		 * bit in the specified register, otherwise clear the bit in
-		 * the register.
-		 */
-		if ((Options & OptionsTable[Index].Option) != (u16)0) {
-			Register |= OptionsTable[Index].Mask;
-		}
-		else {
-			Register &= ~OptionsTable[Index].Mask;
-		}
-
-		/* Write the new value to the register to set the option */
-		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   OptionsTable[Index].RegisterOffset,
-				   Register);
-	}
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the receive FIFO trigger level. The receive trigger
-* level indicates the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	The current receive FIFO trigger level. This is a value
-*		from 0-31.
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
-{
-	u8 RtrigRegister;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read the value of the FIFO control register so that the threshold
-	 * can be retrieved, this read takes special register processing
-	 */
-	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-						   XUARTPS_RXWM_OFFSET);
-
-	/* Return only the trigger level from the register value */
-
-	RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
-	return RtrigRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the receive FIFO trigger level. The receive trigger
-* level specifies the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	TriggerLevel contains the trigger level to set.
-*
-* @return	None
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
-{
-	u32 RtrigRegister;
-
-	/* Assert validates the input arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
-
-	/*
-	 * Write the new value for the FIFO control register to it such that the
-	 * threshold is changed
-	 */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XUARTPS_RXWM_OFFSET, RtrigRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the modem status from the specified UART. The modem
-* status indicates any changes of the modem signals. This function allows
-* the modem status to be read in a polled mode. The modem status is updated
-* whenever it is read such that reading it twice may not yield the same
-* results.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The modem status which are bit masks that are contained in the file
-* xuartps.h and named XUARTPS_MODEM_*.
-*
-* @note
-*
-* The bit masks used for the modem status are the exact bits of the modem
-* status register with no abstraction.
-*
-*****************************************************************************/
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
-{
-	u32 ModemStatusRegister;
-	u16 TmpRegister;
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Read the modem status register to return
-	 */
-	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-						XUARTPS_MODEMSR_OFFSET);
-	TmpRegister = (u16)ModemStatusRegister;
-	return TmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function determines if the specified UART is sending data.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*		- TRUE if the UART is sending data
-*		- FALSE if UART is not sending data
-*
-* @note		None.
-*
-*****************************************************************************/
-u32 XUartPs_IsSending(XUartPs *InstancePtr)
-{
-	u32 ChanStatRegister;
-	u32 ChanTmpSRegister;
-	u32 ActiveResult;
-	u32 EmptyResult;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Read the channel status register to determine if the transmitter is
-	 * active
-	 */
-	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-						 XUARTPS_SR_OFFSET);
-
-	/*
-	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
-	 * that the UART is still sending some data
-	 */
-	ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
-	EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
-	ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
-		(((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
-
-	return ChanTmpSRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The operational mode is specified by constants defined in xuartps.h. The
-* constants are named XUARTPS_OPER_MODE_*
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
-{
-	u32 ModeRegister;
-	u8 OperMode;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Read the Mode register. */
-	ModeRegister =
-		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XUARTPS_MR_OFFSET);
-
-	ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
-	/* Return the constant */
-	switch (ModeRegister) {
-	case XUARTPS_MR_CHMODE_NORM:
-		OperMode = XUARTPS_OPER_MODE_NORMAL;
-		break;
-	case XUARTPS_MR_CHMODE_ECHO:
-		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
-		break;
-	case XUARTPS_MR_CHMODE_L_LOOP:
-		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
-		break;
-	case XUARTPS_MR_CHMODE_R_LOOP:
-		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
-		break;
-	default:
-		OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
-			XUARTPS_MR_CHMODE_SHIFT);
-		break;
-	}
-
-	return OperMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	OperationMode is the mode of the UART.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
-{
-	u32 ModeRegister;
-
-	/* Assert validates the input arguments. */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
-
-	/* Read the Mode register. */
-	ModeRegister =
-		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XUARTPS_MR_OFFSET);
-
-	/* Set the correct value by masking the bits, then ORing the const. */
-	ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
-
-	switch (OperationMode) {
-		case XUARTPS_OPER_MODE_NORMAL:
-			ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
-			break;
-		case XUARTPS_OPER_MODE_AUTO_ECHO:
-			ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
-			break;
-		case XUARTPS_OPER_MODE_LOCAL_LOOP:
-			ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
-			break;
-		case XUARTPS_OPER_MODE_REMOTE_LOOP:
-			ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
-			break;
-		default:
-			/* Default case made for MISRA-C Compliance. */
-			break;
-	}
-
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
-			   ModeRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The Flow Delay is specified by constants defined in xuartps_hw.h. The
-* constants are named XUARTPS_FLOWDEL*
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
-{
-	u32 FdelTmpRegister;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Read the Mode register. */
-	FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-					 XUARTPS_FLOWDEL_OFFSET);
-
-	/* Return the contents of the flow delay register */
-	FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
-	return  FdelTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	FlowDelayValue is the Setting for the flow delay.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
-{
-	u32 FdelRegister;
-
-	/* Assert validates the input arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Set the correct value by shifting the input constant, then masking
-	 * the bits
-	 */
-	FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
-
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Receive Timeout of the UART.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	The current setting for receive time out.
-*
-* @note		None.
-*
-*****************************************************************************/
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
-{
-	u32 RtoRegister;
-	u8 RtoRTmpRegister;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Read the Receive Timeout register. */
-	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XUARTPS_RXTOUT_OFFSET);
-
-	/* Return the contents of the mode register shifted appropriately */
-	RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
-	return RtoRTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Receive Timeout of the UART.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	RecvTimeout setting allows the UART to detect an idle connection
-*		on the reciever data line.
-*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
-*		timeout function.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
-{
-	u32 RtoRegister;
-
-	/* Assert validates the input arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Set the correct value by masking the bits */
-	RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
-
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
-
-	/* Configure CR to restart the receiver timeout counter */
-	RtoRegister =
-		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XUARTPS_CR_OFFSET);
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
-			   (RtoRegister | XUARTPS_CR_TORST));
-
-}
-/****************************************************************************/
-/**
-*
-* Sets the data format for the device. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity. It is the
-* caller's responsibility to ensure that the UART is not sending or receiving
-* data when this function is called.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	FormatPtr is a pointer to a format structure containing the data
-*		format to be set.
-*
-* @return
-*		- XST_SUCCESS if the data format was successfully set.
-*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
-*		set because of the amount of error with the baud rate and
-*		the input clock frequency.
-*		- XST_INVALID_PARAM if one of the parameters was not valid.
-*
-* @note
-*
-* The data types in the format type, data bits and parity, are 32 bit fields
-* to prevent a compiler warning.
-* The asserts in this function will cause a warning if these fields are
-* bytes.
-* <br><br>
-*
-*****************************************************************************/
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
-			XUartPsFormat * FormatPtr)
-{
-	s32 Status;
-	u32 ModeRegister;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(FormatPtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Verify the inputs specified are valid */
-	if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
-		(FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
-		(FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
-		Status = XST_INVALID_PARAM;
-	} else {
-
-		/*
-		 * Try to set the baud rate and if it's not successful then don't
-		 * continue altering the data format, this is done first to avoid the
-		 * format from being altered when an error occurs
-		 */
-		Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
-		if (Status != (s32)XST_SUCCESS) {
-			;
-		} else {
-
-			ModeRegister =
-				XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-						  XUARTPS_MR_OFFSET);
-
-			/*
-			 * Set the length of data (8,7,6) by first clearing out the bits
-			 * that control it in the register, then set the length in the register
-			 */
-			ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
-			ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
-
-			/*
-			 * Set the number of stop bits in the mode register by first clearing
-			 * out the bits that control it in the register, then set the number
-			 * of stop bits in the register.
-			 */
-			ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
-			ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
-
-			/*
-			 * Set the parity by first clearing out the bits that control it in the
-			 * register, then set the bits in the register, the default is no parity
-			 * after clearing the register bits
-			 */
-			ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
-			ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
-
-			/* Update the mode register */
-			XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
-					   ModeRegister);
-
-			Status = XST_SUCCESS;
-		}
-	}
-	return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Gets the data format for the specified UART. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	FormatPtr is a pointer to a format structure that will contain
-*		the data format after this call completes.
-*
-* @return	None.
-*
-* @note		None.
-*
-*
-*****************************************************************************/
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
-{
-	u32 ModeRegister;
-
-
-	/* Assert validates the input arguments */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(FormatPtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/*
-	 * Get the baud rate from the instance, this is not retrieved from the
-	 * hardware because it is only kept as a divisor such that it is more
-	 * difficult to get back to the baud rate
-	 */
-	FormatPtr->BaudRate = InstancePtr->BaudRate;
-
-	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				  XUARTPS_MR_OFFSET);
-
-	/* Get the length of data (8,7,6,5) */
-	FormatPtr->DataBits =
-		((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
-		XUARTPS_MR_CHARLEN_SHIFT);
-
-	/* Get the number of stop bits */
-	FormatPtr->StopBits =
-		(u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
-		XUARTPS_MR_STOPMODE_SHIFT);
-
-	/* Determine what parity is */
-	FormatPtr->Parity =
-		(u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
-		XUARTPS_MR_PARITY_SHIFT);
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c
deleted file mode 100644
index a1a7dd366..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_selftest.c
-* @addtogroup uartps_v3_1
-* @{
-*
-* This file contains the self-test functions for the XUartPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00	drg/jz 01/13/10 First Release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XUARTPS_TOTAL_BYTES (u8)32
-
-/************************** Variable Definitions *****************************/
-
-static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
-static u8 ReturnString[XUARTPS_TOTAL_BYTES];
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test performs a local loopback and verifies data can be sent and received.
-*
-* The time for this test is proportional to the baud rate that has been set
-* prior to calling this function.
-*
-* The mode and control registers are restored before return.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance
-*
-* @return
-*		 - XST_SUCCESS if the test was successful
-*		- XST_UART_TEST_FAIL if the test failed looping back the data
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-s32 XUartPs_SelfTest(XUartPs *InstancePtr)
-{
-	s32 Status = XST_SUCCESS;
-	u32 IntrRegister;
-	u32 ModeRegister;
-	u8 Index;
-	u32 ReceiveDataResult;
-
-	/* Assert validates the input arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-	/* Disable all interrupts in the interrupt disable register */
-	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XUARTPS_IMR_OFFSET);
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
-		XUARTPS_IXR_MASK);
-
-	/* Setup for local loopback */
-	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XUARTPS_MR_OFFSET);
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
-			   ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
-				(u32)XUARTPS_MR_CHMODE_L_LOOP));
-
-	/* Send a number of bytes and receive them, one at a time. */
-	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
-		/*
-		 * Send out the byte and if it was not sent then the failure
-		 * will be caught in the comparison at the end
-		 */
-		(void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
-
-		/*
-		 * Wait until the byte is received. This can hang if the HW
-		 * is broken. Watch for the FIFO empty flag to be false.
-		 */
-		ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
-				XUARTPS_SR_RXEMPTY;
-		while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
-			ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
-					XUARTPS_SR_RXEMPTY;
-		}
-
-		/* Receive the byte */
-		(void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
-	}
-
-	/*
-	 * Compare the bytes received to the bytes sent to verify the exact data
-	 * was received
-	 */
-	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
-		if (TestString[Index] != ReturnString[Index]) {
-			Status = XST_UART_TEST_FAIL;
-		}
-	}
-
-	/*
-	 * Restore the registers which were altered to put into polling and
-	 * loopback modes so that this test is not destructive
-	 */
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
-			   IntrRegister);
-	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
-			   ModeRegister);
-
-	return Status;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c
deleted file mode 100644
index 8dc87dae3..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_sinit.c
-* @addtogroup uartps_v3_1
-* @{
-*
-* The implementation of the XUartPs driver's static initialzation
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00  drg/jz 01/13/10 First Release
-* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param	DeviceId contains the ID of the device
-*
-* @return	A pointer to the configuration structure or NULL if the
-*		specified device is not in the system.
-*
-* @note		None.
-*
-******************************************************************************/
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
-{
-	XUartPs_Config *CfgPtr = NULL;
-
-	u32 Index;
-
-	for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
-		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XUartPs_ConfigTable[Index];
-			break;
-		}
-	}
-
-	return (XUartPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile
new file mode 100644
index 000000000..88b1e625c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
new file mode 100644
index 000000000..a338d1f09
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
@@ -0,0 +1,644 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	 Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3U	/* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount);
+
+u32  XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32  XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XUartPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, pass in the physical
+*		address instead.
+*
+* @return
+*
+*		- XST_SUCCESS if initialization was successful
+*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
+*		  the inputclock frequency is not divisible with an acceptable
+*		  amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*   All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ModeRegister;
+	u32 BaudRate;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/* Setup the driver instance using passed in parameters */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = Config->InputClockHz;
+	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+	/* Initialize other instance data to default values */
+	InstancePtr->Handler = XUartPs_StubHandler;
+
+	InstancePtr->SendBuffer.NextBytePtr = NULL;
+	InstancePtr->SendBuffer.RemainingBytes = 0U;
+	InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+	/* Initialize the platform data */
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	InstancePtr->is_rxbs_error = 0U;
+
+	/* Flag that the driver instance is ready to use */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Set the default baud rate here, can be changed prior to
+	 * starting the device
+	 */
+	BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+	if (Status != (s32)XST_SUCCESS) {
+		InstancePtr->IsReady = 0U;
+	} else {
+
+		/*
+		 * Set up the default data format: 8 bit data, 1 stop bit, no
+		 * parity
+		 */
+		ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XUARTPS_MR_OFFSET);
+
+		/* Mask off what's already there */
+		ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+						 (u32)XUARTPS_MR_STOPMODE_MASK |
+						 (u32)XUARTPS_MR_PARITY_MASK));
+
+		/* Set the register value to the desired data format */
+		ModeRegister |=	((u32)XUARTPS_MR_CHARLEN_8_BIT |
+						 (u32)XUARTPS_MR_STOPMODE_1_BIT |
+						 (u32)XUARTPS_MR_PARITY_NONE);
+
+		/* Write the mode register out */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+				   ModeRegister);
+
+		/* Set the RX FIFO trigger at 8 data bytes. */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXWM_OFFSET, 0x08U);
+
+		/* Set the RX timeout to 1, which will be 4 character time */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+		/* Disable all interrupts, polled mode is the default */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+				   XUARTPS_IXR_MASK);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	BufferPtr is pointer to a buffer of data to be sent.
+* @param  	NumBytes contains the number of bytes to be sent. A value of
+*		zero will stop a previous send operation that is in progress
+*		in interrupt mode. Any data that was already put into the
+*		transmit FIFO will be sent.
+*
+* @return	The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* <br><br>
+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   u32 NumBytes)
+{
+	u32 BytesSent;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the UART transmit interrupts to allow this call to stop a
+	 * previous operation that may be interrupt driven.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+	/* Setup the buffer parameters */
+	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+	 * filling the TX FIFO.
+	 */
+	BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+	return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BufferPtr is pointer to buffer for data to be received into
+* @param	NumBytes is the number of bytes to be received. A value of zero
+*		will stop a previous receive operation that is in progress in
+*		interrupt mode.
+*
+* @return	The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+			  u8 *BufferPtr, u32 NumBytes)
+{
+	u32 ReceivedCount;
+	u32 ImrRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all the interrupts.
+	 * This stops a previous operation that may be interrupt driven
+	 */
+	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup the buffer parameters */
+	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+	/* Receive the data from the device */
+	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+	/* Restore the interrupt state */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+		ImrRegister);
+
+	return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes actually sent
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+	u32 SentCount = 0U;
+	u32 ImrRegister;
+
+	/*
+	 * If the TX FIFO is full, send nothing.
+	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+	 * data has been put into the FIFO.
+	 */
+	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+		/* Fill the FIFO from the buffer */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_FIFO_OFFSET,
+				   ((u32)InstancePtr->SendBuffer.
+				   NextBytePtr[SentCount]));
+
+		/* Increment the send count. */
+		SentCount++;
+	}
+
+	/* Update the buffer to reflect the bytes that were sent from it */
+	InstancePtr->SendBuffer.NextBytePtr += SentCount;
+	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+	/*
+	 * If interrupts are enabled as indicated by the receive interrupt, then
+	 * enable the TX FIFO empty interrupt, so further action can be taken
+	 * for this sending.
+	 */
+	ImrRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+		((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+		((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XUARTPS_IER_OFFSET,
+					   ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+	}
+
+	return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+	u32 CsrRegister;
+	u32 ReceivedCount = 0U;
+	u32 ByteStatusValue, EventData;
+	u32 Event;
+
+	/*
+	 * Read the Channel Status Register to determine if there is any data in
+	 * the RX FIFO
+	 */
+	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_SR_OFFSET);
+
+	/*
+	 * Loop until there is no more data in RX FIFO or the specified
+	 * number of bytes has been received
+	 */
+	while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&&
+		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+		if (InstancePtr->is_rxbs_error) {
+			ByteStatusValue = XUartPs_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						XUARTPS_RXBS_OFFSET);
+			if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+				EventData = ByteStatusValue;
+				Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+				/*
+				 * Call the application handler to indicate that there is a receive
+				 * error or a break interrupt, if the application cares about the
+				 * error it call a function to get the last errors.
+				 */
+				InstancePtr->Handler(InstancePtr->CallBackRef,
+							Event, EventData);
+			}
+		}
+
+		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+			XUartPs_ReadReg(InstancePtr->Config.
+				  BaseAddress,
+				  XUARTPS_FIFO_OFFSET);
+
+		ReceivedCount++;
+
+		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+								XUARTPS_SR_OFFSET);
+	}
+	InstancePtr->is_rxbs_error = 0;
+	/*
+	 * Update the receive buffer to reflect the number of bytes just
+	 * received
+	 */
+	if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+		InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+	}
+	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+	return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BaudRate to be set
+*
+* @return
+*		- XST_SUCCESS if everything configured as expected
+*		- XST_UART_BAUD_ERROR if the requested rate is not available
+*		  because there was too much error
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u32 IterBAUDDIV;	/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/* Check whether the input clock is divided by 8 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/* Calculate the value for BRGR register */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/* Calculate the baud rate from the BRGR value */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/* Avoid unsigned integer underflow */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/* Find the calculated baud rate closest to requested baud rate. */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/* Make sure the best error is not too large. */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/* Disable TX and RX to avoid glitches when setting the baud rate. */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/* RX and TX SW reset */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+	/* Enable device */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+* @param	ByteCount is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount)
+{
+	(void *) CallBackRef;
+	(void) Event;
+	(void) ByteCount;
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h
new file mode 100644
index 000000000..d915917bb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h
@@ -0,0 +1,512 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_1
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* <b>Initialization & Configuration</b>
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* <b>Baud Rate</b>
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* <pre>
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* </pre>
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* <b>Interrupts</b>
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* <b>Data Transfer</b>
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600U
+#define XUARTPS_MIN_RATE	 110U
+
+#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
+											 *	error detected */
+#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+	u8 *NextBytePtr;
+	u32 RequestedBytes;
+	u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;		/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+	u32 Platform;
+	u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				  XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c
new file mode 100644
index 000000000..d4a8e5ab9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c
@@ -0,0 +1,63 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_UART_0_DEVICE_ID,
+		XPAR_PSU_UART_0_BASEADDR,
+		XPAR_PSU_UART_0_UART_CLK_FREQ_HZ,
+		XPAR_PSU_UART_0_HAS_MODEM
+	},
+	{
+		XPAR_PSU_UART_1_DEVICE_ID,
+		XPAR_PSU_UART_1_BASEADDR,
+		XPAR_PSU_UART_1_UART_CLK_FREQ_HZ,
+		XPAR_PSU_UART_1_HAS_MODEM
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c
new file mode 100644
index 000000000..299dd35ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c
@@ -0,0 +1,180 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_1
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.05a hk     08/22/13 Added reset function
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	Data contains the byte to be sent.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+	/* Wait until there is space in TX FIFO */
+	while (XUartPs_IsTransmitFull(BaseAddress)) {
+		;
+	}
+
+	/* Write the byte into the TX FIFO */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	The data byte received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+	u32 RecievedByte;
+	/* Wait until there is data */
+	while (!XUartPs_IsReceiveData(BaseAddress)) {
+		;
+	}
+	RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+	/* Return the byte received */
+	return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+	/* Disable interrupts */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+	/* Disable receive and transmit */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+	/*
+	 * Software reset of receive and transmit
+	 * This clears the FIFO.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+	/* Clear status flags - SW reset wont clear sticky flags. */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Mode register reset value : All zeroes
+	 * Normal mode, even parity, 1 stop bit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+				XUARTPS_MR_CHMODE_NORM);
+
+	/* Rx and TX trigger register reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+				XUARTPS_RXWM_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+				XUARTPS_TXWM_RESET_VAL);
+
+	/* Rx timeout disabled by default */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+				XUARTPS_RXTOUT_DISABLE);
+
+	/* Baud rate generator and dividor reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+				XUARTPS_BAUDGEN_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+				XUARTPS_BAUDDIV_RESET_VAL);
+
+	/*
+	 * Control register reset value -
+	 * RX and TX are disable by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+						(u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h
new file mode 100644
index 000000000..9f5f0b700
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h
@@ -0,0 +1,449 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_1
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET		0x0048U  /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000010U  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE		0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME		0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE		0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE		0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME		0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE		0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE		0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME		0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE		0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE		0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME		0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE		0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK		0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c
new file mode 100644
index 000000000..3068ee795
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c
@@ -0,0 +1,450 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		The current interrupt mask. The mask indicates which interupts
+*		are enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+	/* Assert validates the input argument */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Read the Interrupt Mask register */
+	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	Mask contains the interrupts to be enabled or disabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+	u32 TempMask = Mask;
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	TempMask &= (u32)XUARTPS_IXR_MASK;
+
+	/* Write the mask to the IER Register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IER_OFFSET, TempMask);
+
+	/* Write the inverse of the Mask to the IDR register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active
+	 */
+	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+
+	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_ISR_OFFSET);
+
+	/* Dispatch an appropriate handler. */
+	if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+			(u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+		/* Received data interrupt */
+		ReceiveDataHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+									 != (u32)0) {
+		/* Transmit data interrupt */
+		SendDataHandler(InstancePtr, IsrStatus);
+	}
+
+	/* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+	if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+			(u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+		/* Received Error Status interrupt */
+		ReceiveErrorHandler(InstancePtr, IsrStatus);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+		/* Received Timeout interrupt */
+		ReceiveTimeoutHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+		/* Modem status interrupt */
+		ModemHandler(InstancePtr);
+	}
+
+	/* Clear the interrupt status. */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+		IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+	u32 EventData;
+	u32 Event;
+
+	InstancePtr->is_rxbs_error = 0;
+
+	if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+		(IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+					| (u32)XUARTPS_IXR_FRAMING))) {
+		InstancePtr->is_rxbs_error = 1;
+	}
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+
+	(void)XUartPs_ReceiveBuffer(InstancePtr);
+
+	if (!(InstancePtr->is_rxbs_error)) {
+		Event = XUARTPS_EVENT_RECV_ERROR;
+		EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+			InstancePtr->ReceiveBuffer.RemainingBytes;
+
+		/*
+		 * Call the application handler to indicate that there is a receive
+		 * error or a break interrupt, if the application cares about the
+		 * error it call a function to get the last errors.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					Event,
+					EventData);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+	u32 Event;
+
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * If there are no more bytes to receive then indicate that this is
+	 * not a receive timeout but the end of the buffer reached, a timeout
+	 * normally occurs if # of bytes is not divisible by FIFO threshold,
+	 * don't rely on previous test of remaining bytes since receive
+	 * function updates it
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		Event = XUARTPS_EVENT_RECV_TOUT;
+	} else {
+		Event = XUARTPS_EVENT_RECV_DATA;
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * timeout or data event
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+				 InstancePtr->ReceiveBuffer.RequestedBytes -
+				 InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	 if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	 /* If the last byte of a message was received then call the application
+	 * handler, this code should not use an else from the previous check of
+	 * the number of bytes to receive because the call to receive the buffer
+	 * updates the bytes ramained
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_DATA,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	IsrStatus is the register value for channel status register
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+	/*
+	 * If there are not bytes to be sent from the specified buffer then disable
+	 * the transmit interrupt so it will stop interrupting as it interrupts
+	 * any time the FIFO is empty
+	 */
+	if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_IDR_OFFSET,
+				((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+		/* Call the application handler to indicate the sending is done */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XUARTPS_EVENT_SENT_DATA,
+					InstancePtr->SendBuffer.RequestedBytes -
+					InstancePtr->SendBuffer.RemainingBytes);
+	}
+
+	/* If TX FIFO is empty, send more. */
+	else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+		(void)XUartPs_SendBuffer(InstancePtr);
+	}
+	else {
+		/* Else with dummy entry for MISRA-C Compliance.*/
+		;
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts.  It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+	u32 MsrRegister;
+
+	/*
+	 * Read the modem status register so that the interrupt is acknowledged
+	 * and it can be passed to the callback handler with the event
+	 */
+	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			  XUARTPS_MODEMSR_OFFSET);
+
+	/*
+	 * Call the application handler to indicate the modem status changed,
+	 * passing the modem status and the event data in the call
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				  XUARTPS_EVENT_MODEM,
+				  MsrRegister);
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c
new file mode 100644
index 000000000..9a699afa1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c
@@ -0,0 +1,764 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+*			value was not being written to the register.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+	u16 Option;
+	u16 RegisterOffset;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_RTS},
+	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_DTR},
+	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+	u16 Options = 0U;
+	u32 Register;
+	u32 Index;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the physical options in the
+	 * registers of the UART to the logical options to be returned
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the bit in the register which correlates to the option
+		 * is set, then set the corresponding bit in the options,
+		 * ignoring any bits which are zero since the options variable
+		 * is initialized to zero
+		 */
+		if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+			Options |= OptionsTable[Index].Option;
+		}
+	}
+
+	return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Options contains the options to be set which are bit masks
+*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+	u32 Index;
+	u32 Register;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the logical options to the
+	 * physical options in the registers of the UART.
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+		/*
+		 * Read the register which contains option so that the register
+		 * can be changed without destoying any other bits of the
+		 * register.
+		 */
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the option is set in the input, then set the corresponding
+		 * bit in the specified register, otherwise clear the bit in
+		 * the register.
+		 */
+		if ((Options & OptionsTable[Index].Option) != (u16)0) {
+			if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+				Register &= ~XUARTPS_CR_STOPBRK;
+			Register |= OptionsTable[Index].Mask;
+		}
+		else {
+			Register &= ~OptionsTable[Index].Mask;
+		}
+
+		/* Write the new value to the register to set the option */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   OptionsTable[Index].RegisterOffset,
+				   Register);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current receive FIFO trigger level. This is a value
+*		from 0-31.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+	u8 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the value of the FIFO control register so that the threshold
+	 * can be retrieved, this read takes special register processing
+	 */
+	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XUARTPS_RXWM_OFFSET);
+
+	/* Return only the trigger level from the register value */
+
+	RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+	return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	TriggerLevel contains the trigger level to set.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+	u32 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+	/*
+	 * Write the new value for the FIFO control register to it such that the
+	 * threshold is changed
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+	u32 ModemStatusRegister;
+	u16 TmpRegister;
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the modem status register to return
+	 */
+	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUARTPS_MODEMSR_OFFSET);
+	TmpRegister = (u16)ModemStatusRegister;
+	return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if the UART is sending data
+*		- FALSE if UART is not sending data
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+	u32 ChanStatRegister;
+	u32 ChanTmpSRegister;
+	u32 ActiveResult;
+	u32 EmptyResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel status register to determine if the transmitter is
+	 * active
+	 */
+	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XUARTPS_SR_OFFSET);
+
+	/*
+	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
+	 * that the UART is still sending some data
+	 */
+	ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+	EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+	ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+		(((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+	return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+	u32 ModeRegister;
+	u8 OperMode;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+	/* Return the constant */
+	switch (ModeRegister) {
+	case XUARTPS_MR_CHMODE_NORM:
+		OperMode = XUARTPS_OPER_MODE_NORMAL;
+		break;
+	case XUARTPS_MR_CHMODE_ECHO:
+		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+		break;
+	case XUARTPS_MR_CHMODE_L_LOOP:
+		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+		break;
+	case XUARTPS_MR_CHMODE_R_LOOP:
+		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+		break;
+	default:
+		OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+			XUARTPS_MR_CHMODE_SHIFT);
+		break;
+	}
+
+	return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	OperationMode is the mode of the UART.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+	u32 ModeRegister;
+
+	/* Assert validates the input arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Set the correct value by masking the bits, then ORing the const. */
+	ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+	switch (OperationMode) {
+		case XUARTPS_OPER_MODE_NORMAL:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+			break;
+		case XUARTPS_OPER_MODE_AUTO_ECHO:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+			break;
+		case XUARTPS_OPER_MODE_LOCAL_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+			break;
+		case XUARTPS_OPER_MODE_REMOTE_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+			break;
+		default:
+			/* Default case made for MISRA-C Compliance. */
+			break;
+	}
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+	u32 FdelTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XUARTPS_FLOWDEL_OFFSET);
+
+	/* Return the contents of the flow delay register */
+	FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+	return  FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FlowDelayValue is the Setting for the flow delay.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+	u32 FdelRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by shifting the input constant, then masking
+	 * the bits
+	 */
+	FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current setting for receive time out.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+	u32 RtoRegister;
+	u8 RtoRTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Receive Timeout register. */
+	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUARTPS_RXTOUT_OFFSET);
+
+	/* Return the contents of the mode register shifted appropriately */
+	RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+	return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RecvTimeout setting allows the UART to detect an idle connection
+*		on the reciever data line.
+*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+*		timeout function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+	u32 RtoRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Set the correct value by masking the bits */
+	RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+	/* Configure CR to restart the receiver timeout counter */
+	RtoRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_CR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+			   (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure containing the data
+*		format to be set.
+*
+* @return
+*		- XST_SUCCESS if the data format was successfully set.
+*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
+*		set because of the amount of error with the baud rate and
+*		the input clock frequency.
+*		- XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* <br><br>
+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+			XUartPsFormat * FormatPtr)
+{
+	s32 Status;
+	u32 ModeRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FormatPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Verify the inputs specified are valid */
+	if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+		(FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+		(FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+		Status = XST_INVALID_PARAM;
+	} else {
+
+		/*
+		 * Try to set the baud rate and if it's not successful then don't
+		 * continue altering the data format, this is done first to avoid the
+		 * format from being altered when an error occurs
+		 */
+		Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+		if (Status != (s32)XST_SUCCESS) {
+			;
+		} else {
+
+			ModeRegister =
+				XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						  XUARTPS_MR_OFFSET);
+
+			/*
+			 * Set the length of data (8,7,6) by first clearing out the bits
+			 * that control it in the register, then set the length in the register
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+			ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+			/*
+			 * Set the number of stop bits in the mode register by first clearing
+			 * out the bits that control it in the register, then set the number
+			 * of stop bits in the register.
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+			ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+			/*
+			 * Set the parity by first clearing out the bits that control it in the
+			 * register, then set the bits in the register, the default is no parity
+			 * after clearing the register bits
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+			ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+			/* Update the mode register */
+			XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+					   ModeRegister);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure that will contain
+*		the data format after this call completes.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+	u32 ModeRegister;
+
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FormatPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the baud rate from the instance, this is not retrieved from the
+	 * hardware because it is only kept as a divisor such that it is more
+	 * difficult to get back to the baud rate
+	 */
+	FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Get the length of data (8,7,6,5) */
+	FormatPtr->DataBits =
+		((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+		XUARTPS_MR_CHARLEN_SHIFT);
+
+	/* Get the number of stop bits */
+	FormatPtr->StopBits =
+		(u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+		XUARTPS_MR_STOPMODE_SHIFT);
+
+	/* Determine what parity is */
+	FormatPtr->Parity =
+		(u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+		XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
new file mode 100644
index 000000000..a1a7dd366
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*		- XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrRegister;
+	u32 ModeRegister;
+	u8 Index;
+	u32 ReceiveDataResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable all interrupts in the interrupt disable register */
+	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup for local loopback */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_MR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+				(u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+	/* Send a number of bytes and receive them, one at a time. */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		/*
+		 * Send out the byte and if it was not sent then the failure
+		 * will be caught in the comparison at the end
+		 */
+		(void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+		/*
+		 * Wait until the byte is received. This can hang if the HW
+		 * is broken. Watch for the FIFO empty flag to be false.
+		 */
+		ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+				XUARTPS_SR_RXEMPTY;
+		while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+			ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+					XUARTPS_SR_RXEMPTY;
+		}
+
+		/* Receive the byte */
+		(void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+	}
+
+	/*
+	 * Compare the bytes received to the bytes sent to verify the exact data
+	 * was received
+	 */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		if (TestString[Index] != ReturnString[Index]) {
+			Status = XST_UART_TEST_FAIL;
+		}
+	}
+
+	/*
+	 * Restore the registers which were altered to put into polling and
+	 * loopback modes so that this test is not destructive
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+			   IntrRegister);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
new file mode 100644
index 000000000..8dc87dae3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device
+*
+* @return	A pointer to the configuration structure or NULL if the
+*		specified device is not in the system.
+*
+* @note		None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+	XUartPs_Config *CfgPtr = NULL;
+
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XUartPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile
new file mode 100644
index 000000000..d30648814
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling usbpsu"
+
+xusbps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
new file mode 100644
index 000000000..c39d11a2f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
@@ -0,0 +1,906 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   sg    06/16/16 First release
+* 1.1   sg    10/24/16 Added new function XUsbPsu_IsSuperSpeed
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is cleared or timeout occurs
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Offset is register offset.
+* @param	BitMask is bit mask of required bit to be checked.
+* @param	Timeout is the time to wait specified in micro seconds.
+*
+* @return
+*			- XST_SUCCESS when bit is cleared.
+*			- XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout)
+{
+	u32 RegVal;
+	u32 LocalTimeout = Timeout;
+
+	do {
+		RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+		if ((RegVal & BitMask) == 0U) {
+			break;
+		}
+		LocalTimeout--;
+		if (LocalTimeout == 0U) {
+			return XST_FAILURE;
+		}
+		XUsbSleep(1U);
+	} while (1);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is set or timeout occurs
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Offset is register offset.
+* @param	BitMask is bit mask of required bit to be checked.
+* @param	Timeout is the time to wait specified in micro seconds.
+*
+* @return
+*			- XST_SUCCESS when bit is set.
+*			- XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout)
+{
+	u32 RegVal;
+	u32 LocalTimeout = Timeout;
+
+	do {
+		RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+		if ((RegVal & BitMask) != 0U) {
+			break;
+		}
+		LocalTimeout--;
+		if (LocalTimeout == 0U) {
+			return XST_FAILURE;
+		}
+		XUsbSleep(1U);
+	} while (1);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Sets mode of Core to USB Device/Host/OTG.
+*
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Mode is mode to set
+*			- XUSBPSU_GCTL_PRTCAP_OTG
+*			- XUSBPSU_GCTL_PRTCAP_HOST
+*			- XUSBPSU_GCTL_PRTCAP_DEVICE
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+	u32 RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Mode <= XUSBPSU_GCTL_PRTCAP_OTG) &&
+					(Mode >= XUSBPSU_GCTL_PRTCAP_HOST));
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
+	RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Issues core PHY reset.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Before Resetting PHY, put Core in Reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+	/* Assert USB3 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+	RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+	/* Assert USB2 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+	RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+	XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+	/* Clear USB3 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+	RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+	/* Clear USB2 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+	RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+	XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+	/* Take Core out of reset state after PHYS are stable*/
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Sets up Event buffers so that events are written by Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
+{
+    struct XUsbPsu_EvtBuffer *Evt;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	Evt = &InstancePtr->Evt;
+	Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0),
+						(UINTPTR)InstancePtr->EventBuffer);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0),
+						((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
+					XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer)));
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
+}
+
+/*****************************************************************************/
+/**
+* Resets Event buffer Registers to zero so that events are not written by Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U), 0U);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U), 0U);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
+			(u32)XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0U));
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
+}
+
+/*****************************************************************************/
+/**
+* Reads data from Hardware Params Registers of Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	RegIndex is Register number to read
+*			- XUSBPSU_GHWPARAMS0
+*			- XUSBPSU_GHWPARAMS1
+*			- XUSBPSU_GHWPARAMS2
+*			- XUSBPSU_GHWPARAMS3
+*			- XUSBPSU_GHWPARAMS4
+*			- XUSBPSU_GHWPARAMS5
+*			- XUSBPSU_GHWPARAMS6
+*			- XUSBPSU_GHWPARAMS7
+*
+* @return	One of the GHWPARAMS RegValister contents.
+*
+******************************************************************************/
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(RegIndex <= (u8)XUSBPSU_GHWPARAMS7);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, ((u32)XUSBPSU_GHWPARAMS0_OFFSET +
+							((u32)RegIndex * (u32)4)));
+	return RegVal;
+}
+
+/*****************************************************************************/
+/**
+* Initializes Core.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return
+*	 	- XST_SUCCESS if initialization was successful
+*		- XST_FAILURE if initialization was not successful
+*
+******************************************************************************/
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+	u32		Hwparams1;
+
+	/* issue device SoftReset too */
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DCTL,
+			XUSBPSU_DCTL_CSFTRST, 500U) == XST_FAILURE) {
+		/* timed out return failure */
+		return XST_FAILURE;
+	}
+
+	XUsbPsu_PhyReset(InstancePtr);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+    RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
+    RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
+    RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS;
+
+	Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U);
+
+	switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
+		case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
+			RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
+			break;
+
+		case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
+		/* enable hibernation here */
+			break;
+
+		default:
+			/* Made for Misra-C Compliance. */
+			break;
+	}
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Enables an interrupt in Event Enable RegValister.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on
+* @param  Mask is the OR of any Interrupt Enable Masks:
+*		- XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+*		- XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+*		- XUSBPSU_DEVTEN_CMDCMPLTEN
+*		- XUSBPSU_DEVTEN_ERRTICERREN
+*		- XUSBPSU_DEVTEN_SOFEN
+*		- XUSBPSU_DEVTEN_EOPFEN
+*		- XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+*		- XUSBPSU_DEVTEN_WKUPEVTEN
+*		- XUSBPSU_DEVTEN_ULSTCNGEN
+*		- XUSBPSU_DEVTEN_CONNECTDONEEN
+*		- XUSBPSU_DEVTEN_USBRSTEN
+*		- XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return  None
+*
+******************************************************************************/
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+    u32	RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+    RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+    RegVal |= Mask;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Disables an interrupt in Event Enable RegValister.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param  Mask is the OR of Interrupt Enable Masks
+*		- XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+*		- XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+*		- XUSBPSU_DEVTEN_CMDCMPLTEN
+*		- XUSBPSU_DEVTEN_ERRTICERREN
+*		- XUSBPSU_DEVTEN_SOFEN
+*		- XUSBPSU_DEVTEN_EOPFEN
+*		- XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+*		- XUSBPSU_DEVTEN_WKUPEVTEN
+*		- XUSBPSU_DEVTEN_ULSTCNGEN
+*		- XUSBPSU_DEVTEN_CONNECTDONEEN
+*		- XUSBPSU_DEVTEN_USBRSTEN
+*		- XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return  None
+*
+******************************************************************************/
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+	u32 RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+	RegVal &= ~Mask;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/****************************************************************************/
+/**
+*
+* This function does the following:
+*	- initializes a specific XUsbPsu instance.
+*	- sets up Event Buffer for Core to write events.
+*	- Core Reset and PHY Reset.
+*	- Sets core in Device Mode.
+*	- Sets default speed as HIGH_SPEED.
+*	- Sets Device Address to 0.
+*	- Enables interrupts.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	ConfigPtr points to the XUsbPsu device configuration structure.
+* @param	BaseAddress is the device base address in the virtual memory
+*			address space. If the address translation is not used then the
+*			physical address is passed.
+*			Unexpected errors may occur if the address mapping is changed
+*			after this function is invoked.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+			XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
+{
+	int Status;
+	u32 RegVal;
+
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr   != NULL);
+	Xil_AssertNonvoid(BaseAddress != 0U)
+
+	InstancePtr->ConfigPtr = ConfigPtr;
+
+	Status = XUsbPsu_CoreInit(InstancePtr);
+	if (Status != XST_SUCCESS) {
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Core initialization failed\r\n");
+#endif
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
+	InstancePtr->NumInEps = (u8)XUSBPSU_NUM_IN_EPS(RegVal);
+	InstancePtr->NumOutEps = (u8)(XUSBPSU_NUM_EPS(RegVal) -
+			InstancePtr->NumInEps);
+
+	/* Map USB and Physical Endpoints */
+	XUsbPsu_InitializeEps(InstancePtr);
+
+	XUsbPsu_EventBuffersSetup(InstancePtr);
+
+	XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
+
+    /*
+     * Setting to max speed to support SS and HS
+     */
+    XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED);
+
+	(void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Starts the controller so that Host can detect this device.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr)
+{
+	u32			RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+
+	RegVal |= XUSBPSU_DCTL_RUN_STOP;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Stops the controller so that Device disconnects from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
+{
+	u32	RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	if (XUsbPsu_Wait_Set_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+ * Enables USB2 Test Modes
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ * @param	Mode is Test mode to set.
+ *
+ * @return	XST_SUCCESS else XST_FAILURE
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+	u32	RegVal;
+	s32 Status = XST_SUCCESS;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Mode >= XUSBPSU_TEST_J)
+			&& (Mode <= XUSBPSU_TEST_FORCE_ENABLE));
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+
+	switch (Mode) {
+		case XUSBPSU_TEST_J:
+		case XUSBPSU_TEST_K:
+		case XUSBPSU_TEST_SE0_NAK:
+		case XUSBPSU_TEST_PACKET:
+		case XUSBPSU_TEST_FORCE_ENABLE:
+			RegVal |= (u32)Mode << 1;
+			break;
+
+		default:
+			Status = (s32)XST_FAILURE;
+			break;
+	}
+
+	if (Status != (s32)XST_FAILURE) {
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+ * Gets current State of USB Link
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ *
+ * @return	Link State
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+
+	return XUSBPSU_DSTS_USBLNKST(RegVal);
+}
+
+/****************************************************************************/
+/**
+ * Sets USB Link to a particular State
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ * @param	State is State of Link to set.
+ *
+ * @return	XST_SUCCESS else XST_FAILURE
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+		XusbPsuLinkStateChange State)
+{
+	u32		RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	 /* Wait until device controller is ready. */
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DCNRD, 500U) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
+
+	RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Speed is required speed
+*				- XUSBPSU_DCFG_HIGHSPEED
+*				- XUSBPSU_DCFG_FULLSPEED2
+*				- XUSBPSU_DCFG_LOWSPEED
+*				- XUSBPSU_DCFG_FULLSPEED1
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
+{
+	u32	RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Speed <= (u32)XUSBPSU_DCFG_SUPERSPEED);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
+	RegVal |= Speed;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Sets Device Address of the Core
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Addr is address to set.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Addr <= 127U);
+
+	if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) {
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+	RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+
+	if (Addr) {
+		InstancePtr->State = XUSBPSU_STATE_ADDRESS;
+	}
+	else {
+		InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr)
+{
+	if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U1 sleep timeout
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Sleep is time in microseconds
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+	RegVal &= ~XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK;
+	RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U2 sleep timeout
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Sleep is time in microseconds
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+	RegVal &= ~XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK;
+	RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+	return XST_SUCCESS;
+}
+/****************************************************************************/
+/**
+* Enable Accept U1 and U2 sleep enable
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal |= XUSBPSU_DCTL_ACCEPTU2ENA | XUSBPSU_DCTL_ACCEPTU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 enable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal |= XUSBPSU_DCTL_INITU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 enable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal |= XUSBPSU_DCTL_INITU2ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 disable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 disable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
new file mode 100644
index 000000000..a1366487b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
@@ -0,0 +1,608 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.h
+* @addtogroup usbpsu_v1_0
+* @{
+* @details
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   sg    06/06/16 First release
+* 1.1   sg    10/24/16 Update for backward compatability
+*                      Added XUsbPsu_IsSuperSpeed function in xusbpsu.c
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XUSBPSU_H  /* Prevent circular inclusions */
+#define XUSBPSU_H  /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xusbpsu_hw.h"
+#include "xil_io.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#if defined (__arm__) || defined (__aarch64__)
+#include "sleep.h"
+#endif
+
+#ifdef __MICROBLAZE__
+#include "microblaze_sleep.h"
+#endif
+#include "xil_cache.h"
+
+/************************** Constant Definitions ****************************/
+
+#define ALIGNMENT_CACHELINE		__attribute__ ((aligned(64)))
+
+#define	XUSBPSU_PHY_TIMEOUT		5000U /* in micro seconds */
+
+#define XUSBPSU_EP_DIR_IN				1U
+#define XUSBPSU_EP_DIR_OUT				0U
+
+#define XUSBPSU_ENDPOINT_NUMBER_MASK        0x0f    /* in bEndpointAddress */
+#define XUSBPSU_ENDPOINT_DIR_MASK           0x80
+
+#define XUSBPSU_ENDPOINT_XFERTYPE_MASK      0x03    /* in bmAttributes */
+#define XUSBPSU_ENDPOINT_XFER_CONTROL       0U
+#define XUSBPSU_ENDPOINT_XFER_ISOC          1U
+#define XUSBPSU_ENDPOINT_XFER_BULK          2U
+#define XUSBPSU_ENDPOINT_XFER_INT           3U
+#define XUSBPSU_ENDPOINT_MAX_ADJUSTABLE     0x80
+
+#define	XUSBPSU_TEST_J							1U
+#define	XUSBPSU_TEST_K							2U
+#define	XUSBPSU_TEST_SE0_NAK					3U
+#define	XUSBPSU_TEST_PACKET						4U
+#define	XUSBPSU_TEST_FORCE_ENABLE				5U
+
+#define XUSBPSU_NUM_TRBS				8
+
+#define XUSBPSU_EVENT_PENDING		(0x00000001U << 0)
+
+#define XUSBPSU_EP_ENABLED			(0x00000001U << 0)
+#define XUSBPSU_EP_STALL			(0x00000001U << 1)
+#define XUSBPSU_EP_WEDGE			(0x00000001U << 2)
+#define XUSBPSU_EP_BUSY				((u32)0x00000001U << 4)
+#define XUSBPSU_EP_PENDING_REQUEST	(0x00000001U << 5)
+#define XUSBPSU_EP_MISSED_ISOC		(0x00000001U << 6)
+
+#define	XUSBPSU_GHWPARAMS0				0U
+#define	XUSBPSU_GHWPARAMS1				1U
+#define	XUSBPSU_GHWPARAMS2				2U
+#define	XUSBPSU_GHWPARAMS3				3U
+#define	XUSBPSU_GHWPARAMS4				4U
+#define	XUSBPSU_GHWPARAMS5				5U
+#define	XUSBPSU_GHWPARAMS6				6U
+#define	XUSBPSU_GHWPARAMS7				7U
+
+/* HWPARAMS0 */
+#define XUSBPSU_MODE(n)					((n) & 0x7)
+#define XUSBPSU_MDWIDTH(n)				(((n) & 0xff00) >> 8)
+
+/* HWPARAMS1 */
+#define XUSBPSU_NUM_INT(n)				(((n) & (0x3f << 15)) >> 15)
+
+/* HWPARAMS3 */
+#define XUSBPSU_NUM_IN_EPS_MASK		((u32)0x0000001fU << (u32)18)
+#define XUSBPSU_NUM_EPS_MASK		((u32)0x0000003fU << (u32)12)
+#define XUSBPSU_NUM_EPS(p)			(((u32)(p) &		\
+									(XUSBPSU_NUM_EPS_MASK)) >> (u32)12)
+#define XUSBPSU_NUM_IN_EPS(p)		(((u32)(p) &		\
+									(XUSBPSU_NUM_IN_EPS_MASK)) >> (u32)18)
+
+/* HWPARAMS7 */
+#define XUSBPSU_RAM1_DEPTH(n)			((n) & 0xffff)
+
+#define XUSBPSU_DEPEVT_XFERCOMPLETE		0x01U
+#define XUSBPSU_DEPEVT_XFERINPROGRESS	0x02U
+#define XUSBPSU_DEPEVT_XFERNOTREADY		0x03U
+#define XUSBPSU_DEPEVT_STREAMEVT		0x06U
+#define XUSBPSU_DEPEVT_EPCMDCMPLT		0x07U
+
+/* Within XferNotReady */
+#define DEPEVT_STATUS_TRANSFER_ACTIVE	(1 << 3)
+
+/* Within XferComplete */
+#define DEPEVT_STATUS_BUSERR			(1 << 0)
+#define DEPEVT_STATUS_SHORT				(1 << 1)
+#define DEPEVT_STATUS_IOC				(1 << 2)
+#define DEPEVT_STATUS_LST				(1 << 3)
+
+/* Stream event only */
+#define DEPEVT_STREAMEVT_FOUND		1U
+#define DEPEVT_STREAMEVT_NOTFOUND	2U
+
+/* Control-only Status */
+#define DEPEVT_STATUS_CONTROL_DATA				1U
+#define DEPEVT_STATUS_CONTROL_STATUS			2U
+#define DEPEVT_STATUS_CONTROL_DATA_INVALTRB		9
+#define DEPEVT_STATUS_CONTROL_STATUS_INVALTRB	0xA
+
+#define XUSBPSU_ENDPOINTS_NUM			12U
+
+#define XUSBPSU_EVENT_SIZE				4U       /* bytes */
+#define XUSBPSU_EVENT_MAX_NUM			64U      /* 2 events/endpoint */
+#define XUSBPSU_EVENT_BUFFERS_SIZE		(XUSBPSU_EVENT_SIZE * \
+										XUSBPSU_EVENT_MAX_NUM)
+
+#define XUSBPSU_EVENT_TYPE_MASK                 0x000000feU
+
+#define XUSBPSU_EVENT_TYPE_DEV                  0U
+#define XUSBPSU_EVENT_TYPE_CARKIT               3U
+#define XUSBPSU_EVENT_TYPE_I2C                  4U
+
+#define XUSBPSU_DEVICE_EVENT_DISCONNECT         0U
+#define XUSBPSU_DEVICE_EVENT_RESET              1U
+#define XUSBPSU_DEVICE_EVENT_CONNECT_DONE       2U
+#define XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE 3U
+#define XUSBPSU_DEVICE_EVENT_WAKEUP             4U
+#define XUSBPSU_DEVICE_EVENT_HIBER_REQ          5U
+#define XUSBPSU_DEVICE_EVENT_EOPF               6U
+#define XUSBPSU_DEVICE_EVENT_SOF                7U
+#define XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR      9U
+#define XUSBPSU_DEVICE_EVENT_CMD_CMPL           10U
+#define XUSBPSU_DEVICE_EVENT_OVERFLOW           11U
+
+#define XUSBPSU_GEVNTCOUNT_MASK                 0x0000fffcU
+
+/*
+ * Control Endpoint state
+ */
+#define	XUSBPSU_EP0_SETUP_PHASE				1U	/**< Setup Phase */
+#define	XUSBPSU_EP0_DATA_PHASE				2U	/**< Data Phase */
+#define	XUSBPSU_EP0_STATUS_PHASE			3U	/**< Status Pahse */
+
+/*
+ * Link State
+ */
+#define		XUSBPSU_LINK_STATE_MASK			0x0FU
+
+typedef enum {
+	XUSBPSU_LINK_STATE_U0 = 0x00U, /**< in HS - ON */
+	XUSBPSU_LINK_STATE_U1 =	0x01U,
+	XUSBPSU_LINK_STATE_U2 =	0x02U, /**< in HS - SLEEP */
+	XUSBPSU_LINK_STATE_U3 =	0x03U, /**< in HS - SUSPEND */
+	XUSBPSU_LINK_STATE_SS_DIS =	0x04U,
+	XUSBPSU_LINK_STATE_RX_DET =	0x05U,
+	XUSBPSU_LINK_STATE_SS_INACT = 0x06U,
+	XUSBPSU_LINK_STATE_POLL	=	0x07U,
+	XUSBPSU_LINK_STATE_RECOV =	0x08U,
+	XUSBPSU_LINK_STATE_HRESET =	0x09U,
+	XUSBPSU_LINK_STATE_CMPLY =	0x0AU,
+	XUSBPSU_LINK_STATE_LPBK	=	0x0BU,
+	XUSBPSU_LINK_STATE_RESET = 	0x0EU,
+	XUSBPSU_LINK_STATE_RESUME =	0x0FU,
+}XusbPsuLinkState;
+
+typedef enum {
+	XUSBPSU_LINK_STATE_CHANGE_U0 = 0x00U, /**< in HS - ON */
+	XUSBPSU_LINK_STATE_CHANGE_SS_DIS =	0x04U,
+	XUSBPSU_LINK_STATE_CHANGE_RX_DET =	0x05U,
+	XUSBPSU_LINK_STATE_CHANGE_SS_INACT = 0x06U,
+	XUSBPSU_LINK_STATE_CHANGE_RECOV =	0x08U,
+	XUSBPSU_LINK_STATE_CHANGE_CMPLY =	0x0AU,
+}XusbPsuLinkStateChange;
+
+/*
+ * Device States
+ */
+#define		XUSBPSU_STATE_ATTACHED			0U
+#define		XUSBPSU_STATE_POWERED			1U
+#define		XUSBPSU_STATE_DEFAULT			2U
+#define		XUSBPSU_STATE_ADDRESS			3U
+#define		XUSBPSU_STATE_CONFIGURED		4U
+#define		XUSBPSU_STATE_SUSPENDED			5U
+
+/*
+ * Device Speeds
+ */
+#define		XUSBPSU_SPEED_UNKNOWN			0U
+#define		XUSBPSU_SPEED_LOW				1U
+#define		XUSBPSU_SPEED_FULL				2U
+#define		XUSBPSU_SPEED_HIGH				3U
+#define		XUSBPSU_SPEED_SUPER				4U
+
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XUSBPSU
+ * device.
+ */
+typedef struct {
+        u16 DeviceId;           /**< Unique ID of controller */
+        u32 BaseAddress;        /**< Core register base address */
+} XUsbPsu_Config;
+
+/**
+ * Software Event buffer representation
+ */
+struct XUsbPsu_EvtBuffer {
+	void	*BuffAddr;
+	u32		Offset;
+	u32		Count;
+	u32		Flags;
+};
+
+/**
+ * Transfer Request Block - Hardware format
+ */
+struct XUsbPsu_Trb {
+	u32		BufferPtrLow;
+	u32		BufferPtrHigh;
+	u32		Size;
+	u32		Ctrl;
+} __attribute__((packed));
+
+
+/*
+ * Endpoint Parameters
+ */
+struct XUsbPsu_EpParams {
+	u32	Param2;		/**< Parameter 2 */
+	u32	Param1;		/**< Parameter 1 */
+	u32	Param0;		/**< Parameter 0 */
+};
+
+/**
+ * USB Standard Control Request
+ */
+typedef struct {
+        u8  bRequestType;
+        u8  bRequest;
+        u16 wValue;
+        u16 wIndex;
+        u16 wLength;
+} __attribute__ ((packed)) SetupPacket;
+
+/**
+ * Endpoint representation
+ */
+struct XUsbPsu_Ep {
+	void (*Handler)(void *, u32, u32);
+						/** < User handler called
+						 *   when data is sent for IN Ep
+						 *   and received for OUT Ep
+						 */
+	struct XUsbPsu_Trb	EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */
+	u32	EpStatus;		/**< Flags to represent Endpoint status */
+	u32	RequestedBytes;	/**< RequestedBytes for transfer */
+	u32	BytesTxed;		/**< Actual Bytes transferred */
+	u16	MaxSize;		/**< Size of endpoint */
+	u8	*BufferPtr;		/**< Buffer location */
+	u8	ResourceIndex;	/**< Resource Index assigned to
+						 *  Endpoint by core
+						 */
+	u8	PhyEpNum;		/**< Physical Endpoint Number in core */
+	u8	UsbEpNum;		/**< USB Endpoint Number */
+	u8	Type;			/**< Type of Endpoint -
+						 *	 Control/BULK/INTERRUPT/ISOC
+						 */
+	u8	Direction;		/**< Direction - EP_DIR_OUT/EP_DIR_IN */
+	u8	UnalignedTx;
+};
+
+/**
+ * USB Device Controller representation
+ */
+struct XUsbPsu {
+	SetupPacket SetupData ALIGNMENT_CACHELINE;
+					/**< Setup Packet buffer */
+	struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE;
+					/**< TRB for control transfers */
+	XUsbPsu_Config *ConfigPtr;	/**< Configuration info pointer */
+	struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */
+	struct XUsbPsu_EvtBuffer Evt;
+	struct XUsbPsu_EpParams EpParams;
+	u32 BaseAddress;	/**< Core register base address */
+	u32 DevDescSize;
+	u32 ConfigDescSize;
+	void (*Chapter9)(struct XUsbPsu *, SetupPacket *);
+	void (*ClassHandler)(struct XUsbPsu *, SetupPacket *);
+	void *DevDesc;
+	void *ConfigDesc;
+	u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]
+						__attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE)));
+	u8 NumOutEps;
+	u8 NumInEps;
+	u8 ControlDir;
+	u8 IsInTestMode;
+	u8 TestMode;
+	u8 Speed;
+	u8 State;
+	u8 Ep0State;
+	u8 LinkState;
+	u8 UnalignedTx;
+	u8 IsConfigDone;
+	u8 IsThreeStage;
+};
+
+struct XUsbPsu_Event_Type {
+	u32	Is_DevEvt:1;
+	u32	Type:7;
+	u32	Reserved8_31:24;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_depvt - Device Endpoint Events
+ * @Is_EpEvt: indicates this is an endpoint event
+ * @endpoint_number: number of the endpoint
+ * @endpoint_event: The event we have:
+ *	0x00	- Reserved
+ *	0x01	- XferComplete
+ *	0x02	- XferInProgress
+ *	0x03	- XferNotReady
+ *	0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)
+ *	0x05	- Reserved
+ *	0x06	- StreamEvt
+ *	0x07	- EPCmdCmplt
+ * @Reserved11_10: Reserved, don't use.
+ * @Status: Indicates the status of the event. Refer to databook for
+ *	more information.
+ * @Parameters: Parameters of the current event. Refer to databook for
+ *	more information.
+ */
+struct XUsbPsu_Event_Epevt {
+	u32	Is_EpEvt:1;
+	u32	Epnumber:5;
+	u32	Endpoint_Event:4;
+	u32	Reserved11_10:2;
+	u32	Status:4;
+	u32	Parameters:16;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_devt - Device Events
+ * @Is_DevEvt: indicates this is a non-endpoint event
+ * @Device_Event: indicates it's a device event. Should read as 0x00
+ * @Type: indicates the type of device event.
+ *	0	- DisconnEvt
+ *	1	- USBRst
+ *	2	- ConnectDone
+ *	3	- ULStChng
+ *	4	- WkUpEvt
+ *	5	- Reserved
+ *	6	- EOPF
+ *	7	- SOF
+ *	8	- Reserved
+ *	9	- ErrticErr
+ *	10	- CmdCmplt
+ *	11	- EvntOverflow
+ *	12	- VndrDevTstRcved
+ * @Reserved15_12: Reserved, not used
+ * @Event_Info: Information about this event
+ * @Reserved31_25: Reserved, not used
+ */
+struct XUsbPsu_Event_Devt {
+	u32	Is_DevEvt:1;
+	u32	Device_Event:7;
+	u32	Type:4;
+	u32	Reserved15_12:4;
+	u32	Event_Info:9;
+	u32	Reserved31_25:7;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_gevt - Other Core Events
+ * @one_bit: indicates this is a non-endpoint event (not used)
+ * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
+ * @phy_port_number: self-explanatory
+ * @reserved31_12: Reserved, not used.
+ */
+struct XUsbPsu_Event_Gevt {
+	u32	Is_GlobalEvt:1;
+	u32	Device_Event:7;
+	u32	Phy_Port_Number:4;
+	u32	Reserved31_12:20;
+} __attribute__((packed));
+
+/**
+ * union XUsbPsu_event - representation of Event Buffer contents
+ * @raw: raw 32-bit event
+ * @type: the type of the event
+ * @depevt: Device Endpoint Event
+ * @devt: Device Event
+ * @gevt: Global Event
+ */
+union XUsbPsu_Event {
+	u32				Raw;
+	struct XUsbPsu_Event_Type	Type;
+	struct XUsbPsu_Event_Epevt	Epevt;
+	struct XUsbPsu_Event_Devt	Devt;
+	struct XUsbPsu_Event_Gevt	Gevt;
+};
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define IS_ALIGNED(x, a)	(((x) & ((typeof(x))(a) - 1)) == 0U)
+
+#define roundup(x, y) (                                 \
+{                                                       \
+        const typeof(y) y__ = (y);                        \
+        (((x) + (u32)(y__ - 1)) / (u32)y__) * (u32)y__;                \
+}                                                       \
+)
+
+#define DECLARE_DEV_DESC(Instance, desc)			\
+	(Instance).DevDesc = &(desc); 					\
+	(Instance).DevDescSize = sizeof((desc))
+
+#define DECLARE_CONFIG_DESC(Instance, desc) 		\
+	(Instance).ConfigDesc = &(desc); 				\
+	(Instance).ConfigDescSize = sizeof((desc))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xusbpsu.c
+ */
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout);
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout);
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode);
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_CoreNumEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_cache_hwparams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex);
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+			XUsbPsu_Config *ConfigPtr, u32 BaseAddress);
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode);
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+		XusbPsuLinkStateChange State);
+s32 XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr,
+					s32 Cmd, u32 Param);
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed);
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr);
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr);
+
+/*
+ * Functions in xusbpsu_endpoint.c
+ */
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+				u8 Dir);
+const char *XUsbPsu_EpCmdString(u8 Cmd);
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+			u32 Cmd, struct XUsbPsu_EpParams *Params);
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum,
+				u8 Dir);
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+				u16 Size, u8 Type);
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+			u16 Maxsize, u8 Type);
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size);
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+			u8 *BufferPtr, u32 BufferLen);
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+				u8 *BufferPtr, u32 Length);
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+			u8 Dir, void (*Handler)(void *, u32, u32));
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+							const struct XUsbPsu_Event_Epevt *Event);
+
+/*
+ * Functions in xusbpsu_controltransfers.c
+ */
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr,
+				SetupPacket *Ctrl);
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+			const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+				const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+					struct XUsbPsu_Ep *Ept);
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr,
+			u32 BufferLen);
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length);
+void XUsbSleep(u32 USeconds);
+
+/*
+ * Functions in xusbpsu_intr.c
+ */
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr,
+				u32 EvtInfo);
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Devt *Event);
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+                const union XUsbPsu_Event *Event);
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr);
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr);
+
+/*
+ * Functions in xusbpsu_sinit.c
+ */
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
new file mode 100644
index 000000000..b3a93dc63
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
@@ -0,0 +1,681 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_controltransfers.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg  06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+#define USB_DIR_OUT				0U		/* to device */
+#define USB_DIR_IN				0x80U	/* to host */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Initiates DMA on Control Endpoint 0 to receive Setup packet.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep	*Ept;
+	s32	Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	/* Setup packet always on EP0 */
+	Ept = &InstancePtr->eps[0];
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+	TrbPtr->Size = 8U;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_SETUP;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+				XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+						Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls Control Endpoint and restarts to receive Setup packet.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_Ep		*Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* reinitialize physical ep1 */
+	Ept = &InstancePtr->eps[1];
+	Ept->EpStatus = XUSBPSU_EP_ENABLED;
+
+	/* stall is always issued on EP0 */
+	XUsbPsu_EpSetStall(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT);
+
+	Ept = &InstancePtr->eps[0];
+	Ept->EpStatus = XUSBPSU_EP_ENABLED;
+	InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+	(void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+						 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32	Status;
+	u32	Length;
+	u32	Epnum;
+	u8	Dir;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Epnum = Event->Epnumber;
+	Dir = (u8)(!!Epnum);
+	Ept = &InstancePtr->eps[Epnum];
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
+	if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) {
+		return;
+	}
+
+	Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+	if (Length == 0U) {
+		Ept->BytesTxed = Ept->RequestedBytes;
+	} else {
+		if (Dir == XUSBPSU_EP_DIR_IN) {
+			Ept->BytesTxed = Ept->RequestedBytes - Length;
+		} else if (Dir == XUSBPSU_EP_DIR_OUT) {
+			if (Ept->UnalignedTx == 1U) {
+				Ept->BytesTxed = Ept->RequestedBytes;
+				Ept->UnalignedTx = 0U;
+			}
+		}
+	}
+
+	if (Dir == XUSBPSU_EP_DIR_OUT) {
+		/* Invalidate Cache */
+		Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+	}
+
+	if (Ept->Handler != NULL) {
+		Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+	}
+}
+
+/****************************************************************************/
+/**
+* Checks the Status Phase and starts next Control transfer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Trb	*TrbPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	if (InstancePtr->IsInTestMode != 0U) {
+		s32 Ret;
+
+		Ret = XUsbPsu_SetTestMode(InstancePtr,
+					InstancePtr->TestMode);
+		if (Ret < 0) {
+			XUsbPsu_Ep0StallRestart(InstancePtr);
+			return;
+		}
+	}
+	Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	(void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer complete event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+							 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+	SetupPacket *Ctrl;
+	u16 Length;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+	Ctrl = &InstancePtr->SetupData;
+
+	Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = 0U;
+
+	switch (InstancePtr->Ep0State) {
+	case XUSBPSU_EP0_SETUP_PHASE:
+		Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData,
+					sizeof(InstancePtr->SetupData));
+		Length = Ctrl->wLength;
+		if (Length == 0U) {
+			InstancePtr->IsThreeStage = 0U;
+			InstancePtr->ControlDir = XUSBPSU_EP_DIR_OUT;
+		} else {
+			InstancePtr->IsThreeStage = 1U;
+			InstancePtr->ControlDir = !!(Ctrl->bRequestType &
+							USB_DIR_IN);
+		}
+
+		Xil_AssertVoid(InstancePtr->Chapter9 != NULL);
+
+		InstancePtr->Chapter9(InstancePtr,
+									&InstancePtr->SetupData);
+		break;
+
+	case XUSBPSU_EP0_DATA_PHASE:
+		XUsbPsu_Ep0DataDone(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_EP0_STATUS_PHASE:
+		XUsbPsu_Ep0StatusDone(InstancePtr, Event);
+		break;
+
+	default:
+		/* Default case is a required MISRA-C guideline. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Starts Status Phase of Control Transfer
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+				const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep  *Ept;
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Trb *TrbPtr;
+	u32 Type;
+	s32 Ret;
+	u8 Dir;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	Type = (InstancePtr->IsThreeStage != 0U) ? XUSBPSU_TRBCTL_CONTROL_STATUS3
+					: XUSBPSU_TRBCTL_CONTROL_STATUS2;
+	TrbPtr = &InstancePtr->Ep0_Trb;
+	/* we use same TrbPtr for setup packet */
+	TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+	TrbPtr->Size = 0U;
+	TrbPtr->Ctrl = Type;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_STATUS_PHASE;
+
+	/*
+	 * Control OUT transfer - Status stage happens on EP0 IN - EP1
+	 * Control IN transfer - Status stage happens on EP0 OUT - EP0
+	 */
+	Dir = !InstancePtr->ControlDir;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir,
+							XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+							Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Ends Data Phase - used incase of error.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Dep is a pointer to the Endpoint structure.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+								struct XUsbPsu_Ep *Ept)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32	Cmd;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Ept != NULL);
+
+	if (Ept->ResourceIndex == 0U) {
+		return;
+	}
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
+						Cmd, Params);
+	Ept->ResourceIndex = 0U;
+	XUsbSleep(200U);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer Not Ready event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+							 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+
+	switch (Event->Status) {
+	case DEPEVT_STATUS_CONTROL_DATA:
+		/*
+		 * We already have a DATA transfer in the controller's cache,
+		 * if we receive a XferNotReady(DATA) we will ignore it, unless
+		 * it's for the wrong direction.
+		 *
+		 * In that case, we must issue END_TRANSFER command to the Data
+		 * Phase we already have started and issue SetStall on the
+		 * control endpoint.
+		 */
+		if (Event->Epnumber != InstancePtr->ControlDir) {
+			XUsbPsu_Ep0_EndControlData(InstancePtr, Ept);
+			XUsbPsu_Ep0StallRestart(InstancePtr);
+		}
+		break;
+
+	case DEPEVT_STATUS_CONTROL_STATUS:
+		(void)XUsbPsu_Ep0StartStatus(InstancePtr, Event);
+		break;
+
+	default:
+		/* Default case is a required MIRSA-C guideline. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Handles Interrupts of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	switch (Event->Endpoint_Event) {
+	case XUSBPSU_DEPEVT_XFERCOMPLETE:
+		XUsbPsu_Ep0XferComplete(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_DEPEVT_XFERNOTREADY:
+		XUsbPsu_Ep0XferNotReady(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_DEPEVT_XFERINPROGRESS:
+	case XUSBPSU_DEPEVT_STREAMEVT:
+	case XUSBPSU_DEPEVT_EPCMDCMPLT:
+		break;
+
+	default:
+		/* Default case is a required MIRSA-C guideline. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on Control Endpoint EP0 IN to Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	BufferPtr is pointer to data.
+* @param	BufferLen is Length of data buffer.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen)
+{
+	/* Control IN - EP1 */
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Ep 	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	s32 Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	Ept = &InstancePtr->eps[1];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = BufferLen;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh  = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = BufferLen;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN,
+							XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+						Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Control Endpoint EP0 OUT from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	BufferPtr is pointer to data.
+* @param	Length is Length of data to be received.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length)
+{
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Ep 	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32 Size;
+	s32 Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	Ept = &InstancePtr->eps[0];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = Length;
+	Size = Length;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	/*
+	 * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+	 * must be a multiple of MaxPacketSize even if software is expecting a
+	 * fixed non-multiple of MaxPacketSize transfer from the Host.
+	 */
+	if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+		Size = (u32)roundup(Length, Ept->MaxSize);
+		InstancePtr->UnalignedTx = 1U;
+	}
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = Size;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+				XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+							Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* API for Sleep routine.
+*
+* @param	USeconds is time in MicroSeconds.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUsbSleep(u32 USeconds) {
+	(void)usleep(USeconds);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
new file mode 100644
index 000000000..41368e526
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
@@ -0,0 +1,927 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_endpoint.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg  06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* return Physical EP number as dwc3 mapping */
+#define PhysicalEp(epnum, direction)	(((epnum) << 1 ) | (direction))
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Returns zeroed parameters to be used by Endpoint commands
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	Zeroed Params structure pointer.
+*
+* @note		None.
+*
+*****************************************************************************/
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr)
+{
+	if (InstancePtr == NULL) {
+		return NULL;
+	}
+
+	InstancePtr->EpParams.Param0 = 0x00U;
+	InstancePtr->EpParams.Param1 = 0x00U;
+	InstancePtr->EpParams.Param2 = 0x00U;
+
+	return &InstancePtr->EpParams;
+}
+
+/****************************************************************************/
+/**
+* Returns Transfer Index assigned by Core for an Endpoint transfer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT
+*
+* @return	Transfer Resource Index.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+								u8 Dir)
+{
+	u8 PhyEpNum;
+	u32 ResourceIndex;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = (u8)PhysicalEp(UsbEpNum, Dir);
+	ResourceIndex = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum));
+
+	return (u32)XUSBPSU_DEPCMD_GET_RSC_IDX(ResourceIndex);
+}
+
+/****************************************************************************/
+/**
+* Sends Endpoint command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+* @param	Cmd is Endpoint command.
+* @param	Params is Endpoint command parameters.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+					  u32 Cmd, struct XUsbPsu_EpParams *Params)
+{
+	u32	PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR0(PhyEpNum),
+					 Params->Param0);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR1(PhyEpNum),
+					 Params->Param1);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR2(PhyEpNum),
+					 Params->Param2);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+			Cmd | XUSBPSU_DEPCMD_CMDACT);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+			XUSBPSU_DEPCMD_CMDACT, 500U) == (s32)XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Start New Configuration command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note
+* 			As per data book this command should be issued by software
+*			under these conditions:
+*				1. After power-on-reset with XferRscIdx=0 before starting
+*				   to configure Physical Endpoints 0 and 1.
+*				2. With XferRscIdx=2 before starting to configure
+*				   Physical Endpoints > 1
+*				3. This command should always be issued to
+*				   Endpoint 0 (DEPCMD0).
+*
+*****************************************************************************/
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32	Cmd;
+	u8 PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u32)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = (u8)PhysicalEp(UsbEpNum, (u32)Dir);
+	Params =  XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	if (PhyEpNum != 1U) {
+		Cmd = XUSBPSU_DEPCMD_DEPSTARTCFG;
+		/* XferRscIdx == 0 for EP0 and 2 for the remaining */
+		if (PhyEpNum > 1U) {
+			if (InstancePtr->IsConfigDone != 0U) {
+				return XST_SUCCESS;
+			}
+			InstancePtr->IsConfigDone = 1U;
+			Cmd |= XUSBPSU_DEPCMD_PARAM(2);
+		}
+
+		return XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+								 Cmd, Params);
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Set Endpoint Configuration command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Size is size of Endpoint size.
+* @param	Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+						u16 Size, u8 Type)
+{
+	struct XUsbPsu_EpParams *Params;
+	u8 PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+	Xil_AssertNonvoid((Size >= 64U) && (Size <= 1024U));
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+
+	Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type)
+		| XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size);
+
+	/*
+	 * Set burst size to 1 as recommended
+	 */
+	Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1);
+
+	Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN
+		| XUSBPSU_DEPCFG_XFER_NOT_READY_EN;
+
+	/*
+	 * We are doing 1:1 mapping for endpoints, meaning
+	 * Physical Endpoints 2 maps to Logical Endpoint 2 and
+	 * so on. We consider the direction bit as part of the physical
+	 * endpoint number. So USB endpoint 0x81 is 0x03.
+	 */
+	Params->Param1 |= XUSBPSU_DEPCFG_EP_NUMBER(PhyEpNum);
+
+	if (Dir != XUSBPSU_EP_DIR_OUT) {
+		 Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >> 1);
+	}
+
+	return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+							 XUSBPSU_DEPCMD_SETEPCONFIG, Params);
+}
+
+/****************************************************************************/
+/**
+* Sends Set Transfer Resource command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/
+*											XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_EpParams *Params;
+
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	Params->Param0 = XUSBPSU_DEPXFERCFG_NUM_XFER_RES(1);
+
+	return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+							 XUSBPSU_DEPCMD_SETTRANSFRESOURCE, Params);
+}
+
+/****************************************************************************/
+/**
+* Enables Endpoint for sending/receiving data.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Maxsize is size of Endpoint size.
+* @param	Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+			u16 Maxsize, u8 Type)
+{
+	struct XUsbPsu_Ep *Ept;
+	u32 RegVal;
+	s32 Ret = (s32)XST_FAILURE;
+	u32 PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+	Xil_AssertNonvoid((Maxsize >= 64U) && (Maxsize <= 1024U));
+
+	PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	Ept->UsbEpNum	= UsbEpNum;
+	Ept->Direction	= Dir;
+	Ept->Type	= Type;
+	Ept->MaxSize	= Maxsize;
+	Ept->PhyEpNum	= (u8)PhyEpNum;
+
+	if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+		Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir);
+		if (Ret != 0) {
+			return Ret;
+		}
+	}
+
+	Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type);
+	if (Ret != 0) {
+		return Ret;
+	}
+
+	if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+		Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir);
+		if (Ret != 0) {
+			return Ret;
+		}
+
+		Ept->EpStatus |= XUSBPSU_EP_ENABLED;
+
+		RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+		RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum);
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Disables Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	u32	RegVal;
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+	RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+
+	Ept->Type = 0U;
+	Ept->EpStatus = 0U;
+	Ept->MaxSize = 0U;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enables USB Control Endpoint i.e., EP0OUT and EP0IN of Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Size is control endpoint size.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size)
+{
+	s32 RetVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U));
+
+	RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size,
+				XUSBPSU_ENDPOINT_XFER_CONTROL);
+	if (RetVal != 0) {
+		return XST_FAILURE;
+	}
+
+	RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size,
+				XUSBPSU_ENDPOINT_XFER_CONTROL);
+	if (RetVal != 0) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initializes Endpoints. All OUT endpoints are even numbered and all IN
+* endpoints are odd numbered. EP0 is for Control OUT and EP1 is for
+* Control IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr)
+{
+	u8  i;
+	u8 Epnum;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	for (i = 0U; i < InstancePtr->NumOutEps; i++) {
+		Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT;
+		InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+		InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT;
+	}
+	for (i = 0U; i < InstancePtr->NumInEps; i++) {
+		Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN;
+		InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+		InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN;
+	}
+}
+
+/****************************************************************************/
+/**
+* Stops transfer on Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+	u8 PhyEpNum;
+	u32 Cmd;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(UsbEpNum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->ResourceIndex == 0U) {
+		return;
+	}
+
+	/*
+	 * - Issue EndTransfer WITH CMDIOC bit set
+	 * - Wait 100us
+	 */
+	Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	Cmd |= XUSBPSU_DEPCMD_CMDIOC;
+	Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							Cmd, Params);
+	Ept->ResourceIndex = 0U;
+	Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+	XUsbSleep(100U);
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on all endpoints.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32 Epnum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	for (Epnum = 1U; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) {
+
+		Ept = &InstancePtr->eps[Epnum];
+		if (Ept == NULL) {
+			continue;
+		}
+
+		if ((Ept->EpStatus & XUSBPSU_EP_STALL) == 0U) {
+			continue;
+		}
+
+		Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+
+		(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum,
+						  Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL,
+						  Params);
+	}
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on endpoint to Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEp is USB endpoint number.
+* @param	BufferPtr is pointer to data.
+* @param	BufferLen is length of data buffer.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+						 u8 *BufferPtr, u32 BufferLen)
+{
+	u8	PhyEpNum;
+	s32	RetVal;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEp <= (u8)16U);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_IN);
+	if (PhyEpNum == 1U) {
+		RetVal = XUsbPsu_Ep0Send(InstancePtr, BufferPtr, BufferLen);
+		return RetVal;
+	}
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->Direction != XUSBPSU_EP_DIR_IN) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = BufferLen;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	TrbPtr = &Ept->EpTrb;
+	Xil_AssertNonvoid(TrbPtr != NULL);
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh  = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+					| XUSBPSU_TRB_CTRL_LST
+					| XUSBPSU_TRB_CTRL_IOC
+					| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+								XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (RetVal != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+													Ept->UsbEpNum,
+													Ept->Direction);
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Endpoint from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	BufferPtr is pointer to data.
+* @param	Length is length of data to be received.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+						 u8 *BufferPtr, u32 Length)
+{
+	u8	PhyEpNum;
+	u32 Size;
+	s32	RetVal;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEp <= (u8)16U);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_OUT);
+	if (PhyEpNum == 0U) {
+		RetVal = XUsbPsu_Ep0Recv(InstancePtr, BufferPtr, Length);
+		return RetVal;
+	}
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->Direction != XUSBPSU_EP_DIR_OUT) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = Length;
+	Size = Length;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	/*
+	 * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+	 * must be a multiple of MaxPacketSize even if software is expecting a
+	 * fixed non-multiple of MaxPacketSize transfer from the Host.
+	 */
+	if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+		Size = (u32)roundup(Length, Ept->MaxSize);
+		Ept->UnalignedTx = 1U;
+	}
+
+	TrbPtr = &Ept->EpTrb;
+	Xil_AssertNonvoid(TrbPtr != NULL);
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = Size;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+					| XUSBPSU_TRB_CTRL_LST
+					| XUSBPSU_TRB_CTRL_IOC
+					| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+								XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (RetVal != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+													Ept->UsbEpNum,
+													Ept->Direction);
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls an Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir	is direction.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept = NULL;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							XUSBPSU_DEPCMD_SETSTALL, Params);
+
+	Ept->EpStatus |= XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on an Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir	is direction.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept = NULL;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							XUSBPSU_DEPCMD_CLEARSTALL, Params);
+
+	Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Sets an user handler to be called after data is sent/received by an Endpoint
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Handler is user handler to be called.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+			u8 Dir, void (*Handler)(void *, u32, u32))
+{
+	u8 PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+	Ept->Handler = Handler;
+}
+
+/****************************************************************************/
+/**
+* Returns status of endpoint - Stalled or not
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return
+*			1 - if stalled
+*			0 - if not stalled
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8 PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Epnum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	return (s32)(!!(Ept->EpStatus & XUSBPSU_EP_STALL));
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+							const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32	Length;
+	u32	Epnum;
+	u8	Dir;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Epnum = Event->Epnumber;
+	Ept = &InstancePtr->eps[Epnum];
+	Dir = Ept->Direction;
+	TrbPtr = &Ept->EpTrb;
+	Xil_AssertVoid(TrbPtr != NULL);
+
+	Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+	if (Length == 0U) {
+		Ept->BytesTxed = Ept->RequestedBytes;
+	} else {
+		if (Dir == XUSBPSU_EP_DIR_IN) {
+			Ept->BytesTxed = Ept->RequestedBytes - Length;
+		} else if (Dir == XUSBPSU_EP_DIR_OUT) {
+			if (Ept->UnalignedTx == 1U) {
+				Ept->BytesTxed = Ept->RequestedBytes;
+				Ept->UnalignedTx = 0U;
+			}
+		}
+	}
+
+	if (Dir == XUSBPSU_EP_DIR_OUT) {
+		/* Invalidate Cache */
+		Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+	}
+
+	if (Ept->Handler != NULL) {
+		Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+	}
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
new file mode 100644
index 000000000..299837862
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbpsu_v1_0
+* @{
+ *
+ * This is an internal file containing the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.0   sg  06/06/16  First release
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPSU_ENDPOINT_H
+#define XUSBPSU_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbpsu.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Device Generic Command Register */
+#define XUSBPSU_DGCMD_SET_LMP                   0x00000001U
+#define XUSBPSU_DGCMD_SET_PERIODIC_PAR          0x00000002U
+#define XUSBPSU_DGCMD_XMIT_FUNCTION             0x00000003U
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO    0x00000004U
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI    0x00000005U
+
+#define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH       0x00000009U
+#define XUSBPSU_DGCMD_ALL_FIFO_FLUSH            0x0000000aU
+#define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY         0x0000000cU
+#define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK      0x00000010U
+
+#define XUSBPSU_DGCMD_STATUS(n)                 (((u32)(n) >> 15) & 1)
+#define XUSBPSU_DGCMD_CMDACT                    (0x00000001U << 10)
+#define XUSBPSU_DGCMD_CMDIOC                    (0x00000001U << 8)
+
+/* Device Generic Command Parameter Register */
+#define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT    (0x00000001U << 0)
+#define XUSBPSU_DGCMDPAR_FIFO_NUM(n)            ((u32)(n) << 0)
+#define XUSBPSU_DGCMDPAR_RX_FIFO                (0x00000000U << 5)
+#define XUSBPSU_DGCMDPAR_TX_FIFO                (0x00000001U << 5)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_DIS           (0x00000000U << 0)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_ENA           (0x00000001U << 0)
+
+/* Device Endpoint Command Register */
+#define XUSBPSU_DEPCMD_PARAM_SHIFT              16U
+#define XUSBPSU_DEPCMD_PARAM(x)         ((u32)(x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
+#define XUSBPSU_DEPCMD_GET_RSC_IDX(x)  (((u32)(x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
+                                        (u32)0x0000007fU)
+#define XUSBPSU_DEPCMD_STATUS(x)                (((u32)(x) >> 12) & (u32)0xF)
+#define XUSBPSU_DEPCMD_HIPRI_FORCERM            (0x00000001U << 11)
+#define XUSBPSU_DEPCMD_CMDACT                   (0x00000001U << 10)
+#define XUSBPSU_DEPCMD_CMDIOC                   (0x00000001U << 8)
+
+#define XUSBPSU_DEPCMD_DEPSTARTCFG              0x00000009U
+#define XUSBPSU_DEPCMD_ENDTRANSFER              0x00000008U
+#define XUSBPSU_DEPCMD_UPDATETRANSFER           0x00000007U
+#define XUSBPSU_DEPCMD_STARTTRANSFER            0x00000006U
+#define XUSBPSU_DEPCMD_CLEARSTALL               0x00000005U
+#define XUSBPSU_DEPCMD_SETSTALL                 0x00000004U
+#define XUSBPSU_DEPCMD_GETEPSTATE               0x00000003U
+#define XUSBPSU_DEPCMD_SETTRANSFRESOURCE        0x00000002U
+#define XUSBPSU_DEPCMD_SETEPCONFIG              0x00000001U
+
+/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
+#define XUSBPSU_DALEPENA_EP(n)                  (0x00000001U << (n))
+
+#define XUSBPSU_DEPCFG_INT_NUM(n)               ((u32)(n) << 0)
+#define XUSBPSU_DEPCFG_XFER_COMPLETE_EN         (0x00000001U << 8)
+#define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN      (0x00000001U << 9)
+#define XUSBPSU_DEPCFG_XFER_NOT_READY_EN        (0x00000001U << 10)
+#define XUSBPSU_DEPCFG_FIFO_ERROR_EN            (0x00000001U << 11)
+#define XUSBPSU_DEPCFG_STREAM_EVENT_EN          (0x00000001U << 13)
+#define XUSBPSU_DEPCFG_BINTERVAL_M1(n)          ((u32)(n) << 16)
+#define XUSBPSU_DEPCFG_STREAM_CAPABLE           (0x00000001U << 24)
+#define XUSBPSU_DEPCFG_EP_NUMBER(n)             ((u32)(n) << 25)
+#define XUSBPSU_DEPCFG_BULK_BASED               (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_FIFO_BASED               (0x00000001U << 31)
+
+/* DEPCFG parameter 0 */
+#define XUSBPSU_DEPCFG_EP_TYPE(n)               ((u32)(n) << 1)
+#define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n)       ((u32)(n) << 3)
+#define XUSBPSU_DEPCFG_FIFO_NUMBER(n)           ((u32)(n) << 17)
+#define XUSBPSU_DEPCFG_BURST_SIZE(n)            ((u32)(n) << 22)
+#define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n)          ((u32)(n) << 26)
+/* This applies for core versions earlier than 1.94a */
+#define XUSBPSU_DEPCFG_IGN_SEQ_NUM              (0x00000001U << 31)
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DEPCFG_ACTION_INIT              (0x00000000U << 30)
+#define XUSBPSU_DEPCFG_ACTION_RESTORE           (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_ACTION_MODIFY            (0x00000002U << 30)
+
+/* DEPXFERCFG parameter 0 */
+#define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((u32)(n) & (u32)0xffff)
+
+#define XUSBPSU_DEPCMD_TYPE_BULK                2U
+#define XUSBPSU_DEPCMD_TYPE_INTR                3U
+
+/* TRB Length, PCM and Status */
+#define XUSBPSU_TRB_SIZE_MASK           (0x00ffffffU)
+#define XUSBPSU_TRB_SIZE_LENGTH(n)      ((u32)(n) & XUSBPSU_TRB_SIZE_MASK)
+#define XUSBPSU_TRB_SIZE_PCM1(n)        (((u32)(n) & (u32)0x03) << 24)
+#define XUSBPSU_TRB_SIZE_TRBSTS(n)      (((u32)(n) & ((u32)0x0f << 28)) >> 28)
+
+#define XUSBPSU_TRBSTS_OK               0U
+#define XUSBPSU_TRBSTS_MISSED_ISOC      1U
+#define XUSBPSU_TRBSTS_SETUP_PENDING    2U
+#define XUSBPSU_TRB_STS_XFER_IN_PROG    4U
+
+/* TRB Control */
+#define XUSBPSU_TRB_CTRL_HWO            ((u32)0x00000001U << 0)
+#define XUSBPSU_TRB_CTRL_LST            ((u32)0x00000001U << 1)
+#define XUSBPSU_TRB_CTRL_CHN            ((u32)0x00000001U << 2)
+#define XUSBPSU_TRB_CTRL_CSP            ((u32)0x00000001U << 3)
+#define XUSBPSU_TRB_CTRL_TRBCTL(n)      (((u32)(n) & (u32)0x3f) << 4)
+#define XUSBPSU_TRB_CTRL_ISP_IMI        (0x00000001U << 10)
+#define XUSBPSU_TRB_CTRL_IOC            (0x00000001U << 11)
+#define XUSBPSU_TRB_CTRL_SID_SOFN(n)    (((u32)(n) & (u32)0xffff) << 14)
+
+#define XUSBPSU_TRBCTL_NORMAL                   XUSBPSU_TRB_CTRL_TRBCTL(1)
+#define XUSBPSU_TRBCTL_CONTROL_SETUP            XUSBPSU_TRB_CTRL_TRBCTL(2)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS2          XUSBPSU_TRB_CTRL_TRBCTL(3)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS3          XUSBPSU_TRB_CTRL_TRBCTL(4)
+#define XUSBPSU_TRBCTL_CONTROL_DATA             XUSBPSU_TRB_CTRL_TRBCTL(5)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST        XUSBPSU_TRB_CTRL_TRBCTL(6)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS              XUSBPSU_TRB_CTRL_TRBCTL(7)
+#define XUSBPSU_TRBCTL_LINK_TRB                 XUSBPSU_TRB_CTRL_TRBCTL(8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPSU_ENDPOINT_H */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
new file mode 100644
index 000000000..41a9b8c7a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPsu_Config XUsbPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_USB_0_DEVICE_ID,
+		XPAR_PSU_USB_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
new file mode 100644
index 000000000..db612b00f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
@@ -0,0 +1,363 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_hw.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   sg    06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUSBPSU_HW_H	/* Prevent circular inclusions */
+#define XUSBPSU_HW_H	/* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+/************************** Constant Definitions ****************************/
+
+/**@name Register offsets
+ *
+ * The following constants provide access to each of the registers of the
+ * USBPSU device.
+ * @{
+ */
+
+/**/
+#define XUSBPSU_PORTSC_30						0x430
+#define XUSBPSU_PORTMSC_30						0x434
+
+/* XUSBPSU registers memory space boundries */
+#define XUSBPSU_GLOBALS_REGS_START              0xc100
+#define XUSBPSU_GLOBALS_REGS_END                0xc6ff
+#define XUSBPSU_DEVICE_REGS_START               0xc700
+#define XUSBPSU_DEVICE_REGS_END                 0xcbff
+#define XUSBPSU_OTG_REGS_START                  0xcc00
+#define XUSBPSU_OTG_REGS_END                    0xccff
+
+/* Global Registers */
+#define XUSBPSU_GSBUSCFG0                       0xc100
+#define XUSBPSU_GSBUSCFG1                       0xc104
+#define XUSBPSU_GTXTHRCFG                       0xc108
+#define XUSBPSU_GRXTHRCFG                       0xc10c
+#define XUSBPSU_GCTL                            0xc110
+#define XUSBPSU_GEVTEN                          0xc114
+#define XUSBPSU_GSTS                            0xc118
+#define XUSBPSU_GSNPSID                         0xc120
+#define XUSBPSU_GGPIO                           0xc124
+#define XUSBPSU_GUID                            0xc128
+#define XUSBPSU_GUCTL                           0xc12c
+#define XUSBPSU_GBUSERRADDR0                    0xc130
+#define XUSBPSU_GBUSERRADDR1                    0xc134
+#define XUSBPSU_GPRTBIMAP0                      0xc138
+#define XUSBPSU_GPRTBIMAP1                      0xc13c
+#define XUSBPSU_GHWPARAMS0_OFFSET               0xc140U
+#define XUSBPSU_GHWPARAMS1_OFFSET               0xc144U
+#define XUSBPSU_GHWPARAMS2_OFFSET               0xc148U
+#define XUSBPSU_GHWPARAMS3_OFFSET               0xc14cU
+#define XUSBPSU_GHWPARAMS4_OFFSET               0xc150U
+#define XUSBPSU_GHWPARAMS5_OFFSET               0xc154U
+#define XUSBPSU_GHWPARAMS6_OFFSET               0xc158U
+#define XUSBPSU_GHWPARAMS7_OFFSET               0xc15cU
+#define XUSBPSU_GDBGFIFOSPACE                   0xc160
+#define XUSBPSU_GDBGLTSSM                       0xc164
+#define XUSBPSU_GPRTBIMAP_HS0                   0xc180
+#define XUSBPSU_GPRTBIMAP_HS1                   0xc184
+#define XUSBPSU_GPRTBIMAP_FS0                   0xc188
+#define XUSBPSU_GPRTBIMAP_FS1                   0xc18c
+
+#define XUSBPSU_GUSB2PHYCFG(n)                  ((u32)0xc200 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GUSB2I2CCTL(n)                  ((u32)0xc240 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB2PHYACC(n)                  ((u32)0xc280 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB3PIPECTL(n)                 ((u32)0xc2c0 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GTXFIFOSIZ(n)                   ((u32)0xc300 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GRXFIFOSIZ(n)                   ((u32)0xc380 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GEVNTADRLO(n)                   ((u32)0xc400 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTADRHI(n)                   ((u32)0xc404 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTSIZ(n)                     ((u32)0xc408 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTCOUNT(n)                   ((u32)0xc40c + ((u32)(n) * (u32)0x10))
+
+#define XUSBPSU_GHWPARAMS8                      0x0000c600U
+
+/* Device Registers */
+#define XUSBPSU_DCFG                            0x0000c700U
+#define XUSBPSU_DCTL                            0x0000c704U
+#define XUSBPSU_DEVTEN                          0x0000c708U
+#define XUSBPSU_DSTS                            0x0000c70cU
+#define XUSBPSU_DGCMDPAR                        0x0000c710U
+#define XUSBPSU_DGCMD                           0x0000c714U
+#define XUSBPSU_DALEPENA                        0x0000c720U
+#define XUSBPSU_DEPCMDPAR2(n)                   ((u32)0xc800 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR1(n)                   ((u32)0xc804 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR0(n)                   ((u32)0xc808 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMD(n)                       ((u32)0xc80c + ((u32)n * (u32)0x10))
+
+/* OTG Registers */
+#define XUSBPSU_OCFG                            0x0000cc00U
+#define XUSBPSU_OCTL                            0x0000cc04U
+#define XUSBPSU_OEVT                            0xcc08U
+#define XUSBPSU_OEVTEN                          0xcc0CU
+#define XUSBPSU_OSTS                            0xcc10U
+
+/* Bit fields */
+
+/* Global Configuration Register */
+#define XUSBPSU_GCTL_PWRDNSCALE(n)              ((n) << 19)
+#define XUSBPSU_GCTL_U2RSTECN                   (1 << 16)
+#define XUSBPSU_GCTL_RAMCLKSEL(x)       (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
+#define XUSBPSU_GCTL_CLK_BUS                    (0U)
+#define XUSBPSU_GCTL_CLK_PIPE                   (1U)
+#define XUSBPSU_GCTL_CLK_PIPEHALF               (2U)
+#define XUSBPSU_GCTL_CLK_MASK                   (3U)
+
+#define XUSBPSU_GCTL_PRTCAP(n)                  (((n) & (3 << 12)) >> 12)
+#define XUSBPSU_GCTL_PRTCAPDIR(n)               ((n) << 12)
+#define XUSBPSU_GCTL_PRTCAP_HOST                1U
+#define XUSBPSU_GCTL_PRTCAP_DEVICE              2U
+#define XUSBPSU_GCTL_PRTCAP_OTG                 3U
+
+#define XUSBPSU_GCTL_CORESOFTRESET              (0x00000001U << 11)
+#define XUSBPSU_GCTL_SOFITPSYNC                 (0x00000001U << 10)
+#define XUSBPSU_GCTL_SCALEDOWN(n)               ((u32)(n) << 4)
+#define XUSBPSU_GCTL_SCALEDOWN_MASK             XUSBPSU_GCTL_SCALEDOWN(3)
+#define XUSBPSU_GCTL_DISSCRAMBLE                (0x00000001U << 3)
+#define XUSBPSU_GCTL_U2EXIT_LFPS                (0x00000001U << 2)
+#define XUSBPSU_GCTL_GBLHIBERNATIONEN           (0x00000001U << 1)
+#define XUSBPSU_GCTL_DSBLCLKGTNG                (0x00000001U << 0)
+
+/* Global Status Register Device Interrupt Mask */
+#define XUSBPSU_GSTS_DEVICE_IP_MASK 			0x00000040
+
+/* Global USB2 PHY Configuration Register */
+#define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST          (0x00000001U << 31)
+#define XUSBPSU_GUSB2PHYCFG_SUSPHY              (0x00000001U << 6)
+
+/* Global USB3 PIPE Control Register */
+#define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST         (0x00000001U << 31)
+#define XUSBPSU_GUSB3PIPECTL_SUSPHY             (0x00000001U << 17)
+
+/* Global TX Fifo Size Register */
+#define XUSBPSU_GTXFIFOSIZ_TXFDEF(n)            ((u32)(n) & (u32)0xffffU)
+#define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n)         ((u32)(n) & 0xffff0000U)
+
+/* Global Event Size Registers */
+#define XUSBPSU_GEVNTSIZ_INTMASK                ((u32)0x00000001U << 31U)
+#define XUSBPSU_GEVNTSIZ_SIZE(n)                ((u32)(n) & (u32)0xffffU)
+
+/* Global HWPARAMS1 Register */
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT(n)         (((u32)(n) & ((u32)3 << 24)) >> 24)
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO         0U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK        1U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB        2U
+#define XUSBPSU_GHWPARAMS1_PWROPT(n)            ((u32)(n) << 24)
+#define XUSBPSU_GHWPARAMS1_PWROPT_MASK          XUSBPSU_GHWPARAMS1_PWROPT(3)
+
+/* Global HWPARAMS4 Register */
+#define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((u32)(n) & ((u32)0x0f << 13)) >> 13)
+#define XUSBPSU_MAX_HIBER_SCRATCHBUFS           15U
+
+/* Device Configuration Register */
+#define XUSBPSU_DCFG_DEVADDR(addr)              ((u32)(addr) << 3)
+#define XUSBPSU_DCFG_DEVADDR_MASK               XUSBPSU_DCFG_DEVADDR(0x7f)
+
+#define XUSBPSU_DCFG_SPEED_MASK					7U
+#define XUSBPSU_DCFG_SUPERSPEED					4U
+#define XUSBPSU_DCFG_HIGHSPEED					0U
+#define XUSBPSU_DCFG_FULLSPEED2					1U
+#define XUSBPSU_DCFG_LOWSPEED					2U
+#define XUSBPSU_DCFG_FULLSPEED1					3U
+
+#define XUSBPSU_DCFG_LPM_CAP                    (0x00000001U << 22U)
+
+/* Device Control Register */
+#define XUSBPSU_DCTL_RUN_STOP                   (0x00000001U << 31U)
+#define XUSBPSU_DCTL_CSFTRST                    ((u32)0x00000001U << 30U)
+#define XUSBPSU_DCTL_LSFTRST                    (0x00000001U << 29U)
+
+#define XUSBPSU_DCTL_HIRD_THRES_MASK            (0x0000001fU << 24U)
+#define XUSBPSU_DCTL_HIRD_THRES(n)              ((u32)(n) << 24)
+
+#define XUSBPSU_DCTL_APPL1RES                   (0x00000001U << 23)
+
+/* These apply for core versions 1.87a and earlier */
+#define XUSBPSU_DCTL_TRGTULST_MASK              (0x0000000fU << 17)
+#define XUSBPSU_DCTL_TRGTULST(n)                ((u32)(n) << 17)
+#define XUSBPSU_DCTL_TRGTULST_U2                (XUSBPSU_DCTL_TRGTULST(2))
+#define XUSBPSU_DCTL_TRGTULST_U3                (XUSBPSU_DCTL_TRGTULST(3))
+#define XUSBPSU_DCTL_TRGTULST_SS_DIS            (XUSBPSU_DCTL_TRGTULST(4))
+#define XUSBPSU_DCTL_TRGTULST_RX_DET            (XUSBPSU_DCTL_TRGTULST(5))
+#define XUSBPSU_DCTL_TRGTULST_SS_INACT          (XUSBPSU_DCTL_TRGTULST(6))
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DCTL_KEEP_CONNECT               (0x00000001U << 19)
+#define XUSBPSU_DCTL_L1_HIBER_EN                (0x00000001U << 18)
+#define XUSBPSU_DCTL_CRS                        (0x00000001U << 17)
+#define XUSBPSU_DCTL_CSS                        (0x00000001U << 16)
+
+#define XUSBPSU_DCTL_INITU2ENA                  (0x00000001U << 12)
+#define XUSBPSU_DCTL_ACCEPTU2ENA                (0x00000001U << 11)
+#define XUSBPSU_DCTL_INITU1ENA                  (0x00000001U << 10)
+#define XUSBPSU_DCTL_ACCEPTU1ENA                (0x00000001U << 9)
+#define XUSBPSU_DCTL_TSTCTRL_MASK               (0x0000000fU << 1)
+
+#define XUSBPSU_DCTL_ULSTCHNGREQ_MASK           (0x0000000fU << 5)
+#define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((u32)(n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
+
+#define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION         (XUSBPSU_DCTL_ULSTCHNGREQ(0))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED       (XUSBPSU_DCTL_ULSTCHNGREQ(4))
+#define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT         (XUSBPSU_DCTL_ULSTCHNGREQ(5))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE       (XUSBPSU_DCTL_ULSTCHNGREQ(6))
+#define XUSBPSU_DCTL_ULSTCHNG_RECOVERY          (XUSBPSU_DCTL_ULSTCHNGREQ(8))
+#define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE        (XUSBPSU_DCTL_ULSTCHNGREQ(10))
+#define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK          (XUSBPSU_DCTL_ULSTCHNGREQ(11))
+
+/* Device Event Enable Register */
+#define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN        ((u32)0x00000001 << 12)
+#define XUSBPSU_DEVTEN_EVNTOVERFLOWEN           ((u32)0x00000001 << 11)
+#define XUSBPSU_DEVTEN_CMDCMPLTEN               ((u32)0x00000001 << 10)
+#define XUSBPSU_DEVTEN_ERRTICERREN              ((u32)0x00000001 << 9)
+#define XUSBPSU_DEVTEN_SOFEN                    ((u32)0x00000001 << 7)
+#define XUSBPSU_DEVTEN_EOPFEN                   ((u32)0x00000001 << 6)
+#define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN      ((u32)0x00000001 << 5)
+#define XUSBPSU_DEVTEN_WKUPEVTEN                ((u32)0x00000001 << 4)
+#define XUSBPSU_DEVTEN_ULSTCNGEN                ((u32)0x00000001 << 3)
+#define XUSBPSU_DEVTEN_CONNECTDONEEN            ((u32)0x00000001 << 2)
+#define XUSBPSU_DEVTEN_USBRSTEN                 ((u32)0x00000001 << 1)
+#define XUSBPSU_DEVTEN_DISCONNEVTEN             ((u32)0x00000001 << 0)
+
+/* Device Status Register */
+#define XUSBPSU_DSTS_DCNRD                      (0x00000001U << 29)
+
+/* This applies for core versions 1.87a and earlier */
+#define XUSBPSU_DSTS_PWRUPREQ                   (0x00000001U << 24)
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DSTS_RSS                        (0x00000001U << 25)
+#define XUSBPSU_DSTS_SSS                        (0x00000001U << 24)
+
+#define XUSBPSU_DSTS_COREIDLE                   (0x00000001U << 23)
+#define XUSBPSU_DSTS_DEVCTRLHLT                 (0x00000001U << 22)
+
+#define XUSBPSU_DSTS_USBLNKST_MASK              (0x0000000fU << 18)
+#define XUSBPSU_DSTS_USBLNKST(n) (((u32)(n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
+
+#define XUSBPSU_DSTS_RXFIFOEMPTY                (0x00000001U << 17)
+
+#define XUSBPSU_DSTS_SOFFN_MASK                 (0x00003fffU << 3)
+#define XUSBPSU_DSTS_SOFFN(n)           (((u32)(n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
+
+#define XUSBPSU_DSTS_CONNECTSPD                 (0x00000007U << 0)
+
+#define XUSBPSU_DSTS_SUPERSPEED                 (4U << 0)
+#define XUSBPSU_DSTS_HIGHSPEED                  (0U << 0)
+#define XUSBPSU_DSTS_FULLSPEED2                 (1U << 0)
+#define XUSBPSU_DSTS_LOWSPEED                   (2U << 0)
+#define XUSBPSU_DSTS_FULLSPEED1                 (3U << 0)
+
+/*Portpmsc 3.0 bit field*/
+#define XUSBPSU_PORTMSC_30_FLA_MASK				(1U << 16)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK		(0xffU << 8)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT		(8U)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK		(0xffU << 0)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT		(0U)
+
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the USBPS8 device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Offset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
+*
+******************************************************************************/
+#define XUsbPsu_ReadReg(InstancePtr, Offset) \
+	Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the USBPS8 device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
+*								u32 Offset,u32 Data)
+*
+******************************************************************************/
+#define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
+	Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
new file mode 100644
index 000000000..85baab0f8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
@@ -0,0 +1,434 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_intr.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg  06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+* Endpoint interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is endpoint Event occured in the core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+	u32 Epnum;
+
+	Epnum = Event->Epnumber;
+	Ept = &InstancePtr->eps[Epnum];
+
+	if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
+		return;
+	}
+
+	if ((Epnum == (u32)0) || (Epnum == (u32)1)) {
+		XUsbPsu_Ep0Intr(InstancePtr, Event);
+		return;
+	}
+
+	/* Handle other end point events */
+	switch (Event->Endpoint_Event) {
+		case XUSBPSU_DEPEVT_XFERCOMPLETE:
+			XUsbPsu_EpXferComplete(InstancePtr, Event);
+			break;
+
+		case XUSBPSU_DEPEVT_XFERNOTREADY:
+			break;
+
+		default:
+			/* Made for Misra-C Compliance. */
+			break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Disconnect Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	InstancePtr->IsConfigDone = 0U;
+	InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN;
+}
+
+/****************************************************************************/
+/**
+* Reset Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr)
+{
+	u32	RegVal;
+	u32	Index;
+
+	InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+	InstancePtr->TestMode = 0U;
+
+	for (Index = 0U; Index < (InstancePtr->NumInEps + InstancePtr->NumOutEps);
+			Index++)
+	{
+		InstancePtr->eps[Index].EpStatus = 0U;
+	}
+
+	InstancePtr->IsConfigDone = 0U;
+
+	/* Reset device address to zero */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Connection Done Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr)
+{
+	u32			RegVal;
+	u16			Size;
+	u8			Speed;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+	Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD);
+	InstancePtr->Speed = Speed;
+
+	switch (Speed) {
+	case XUSBPSU_DCFG_SUPERSPEED:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Super Speed\r\n");
+#endif
+		Size = 512U;
+		InstancePtr->Speed = XUSBPSU_SPEED_SUPER;
+		break;
+
+	case XUSBPSU_DCFG_HIGHSPEED:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("High Speed\r\n");
+#endif
+		Size = 64U;
+		InstancePtr->Speed = XUSBPSU_SPEED_HIGH;
+		break;
+
+	case XUSBPSU_DCFG_FULLSPEED2:
+	case XUSBPSU_DCFG_FULLSPEED1:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Full Speed\r\n");
+#endif
+		Size = 64U;
+		InstancePtr->Speed = XUSBPSU_SPEED_FULL;
+		break;
+
+	case XUSBPSU_DCFG_LOWSPEED:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Low Speed\r\n");
+#endif
+		Size = 64U;
+		InstancePtr->Speed = XUSBPSU_SPEED_LOW;
+		break;
+	default :
+		Size = 64U;
+		break;
+	}
+
+	(void)XUsbPsu_EnableControlEp(InstancePtr, Size);
+	(void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Link Status Change Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EvtInfo is Event information.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr, u32 EvtInfo)
+{
+	u32	State = EvtInfo & (u32)XUSBPSU_LINK_STATE_MASK;
+	InstancePtr->LinkState = (u8)State;
+}
+
+/****************************************************************************/
+/**
+* Interrupt handler for device specific events.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is the Device Event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Devt *Event)
+{
+
+	switch (Event->Type) {
+		case XUSBPSU_DEVICE_EVENT_DISCONNECT:
+			XUsbPsu_DisconnectIntr(InstancePtr);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_RESET:
+			XUsbPsu_ResetIntr(InstancePtr);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_CONNECT_DONE:
+			XUsbPsu_ConnDoneIntr(InstancePtr);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_WAKEUP:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_HIBER_REQ:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE:
+			XUsbPsu_LinkStsChangeIntr(InstancePtr,
+					Event->Event_Info);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_EOPF:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_SOF:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_CMD_CMPL:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_OVERFLOW:
+			break;
+
+		default:
+			/* Made for Misra-C Compliance. */
+			break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Processes an Event entry in Event Buffer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is the Event entry.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+			const union XUsbPsu_Event *Event)
+{
+
+	if (Event->Type.Is_DevEvt == 0U) {
+		/* End point Specific Event */
+		XUsbPsu_EpInterrupt(InstancePtr, &Event->Epevt);
+		return;
+	}
+
+	switch (Event->Type.Type) {
+	case XUSBPSU_EVENT_TYPE_DEV:
+		/* Device Specific Event */
+		XUsbPsu_DevInterrupt(InstancePtr, &Event->Devt);
+		break;
+	/* Carkit and I2C events not supported now */
+	default:
+		/* Made for Misra-C Compliance. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Processes events in an Event Buffer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @bus		Event buffer number.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EvtBuffer *Evt;
+	union XUsbPsu_Event Event = {0};
+
+	Evt = &InstancePtr->Evt;
+
+	Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr,
+                              (u32)XUSBPSU_EVENT_BUFFERS_SIZE);
+
+	while (Evt->Count > 0) {
+		Event.Raw = *(UINTPTR *)(Evt->BuffAddr + Evt->Offset);
+
+		/*
+         * Process the event received
+         */
+        XUsbPsu_EventHandler(InstancePtr, &Event);
+
+		Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE;
+		Evt->Count -= 4;
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U);
+	}
+
+	Evt->Flags &= ~XUSBPSU_EVENT_PENDING;
+}
+
+/****************************************************************************/
+/**
+* Main Interrupt Handler.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr)
+{
+	struct XUsbPsu	*InstancePtr;
+	struct XUsbPsu_EvtBuffer *Evt;
+	u32 Count;
+	u32 RegVal;
+
+	InstancePtr = XUsbPsuInstancePtr;
+
+	Evt = &InstancePtr->Evt;
+
+	Count = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0));
+	Count &= XUSBPSU_GEVNTCOUNT_MASK;
+	/*
+	 * As per data book software should only process Events if Event count
+	 * is greater than zero.
+	 */
+	if (Count == 0U) {
+		return;
+	}
+
+	Evt->Count = Count;
+	Evt->Flags |= XUSBPSU_EVENT_PENDING;
+
+	/* Mask event interrupt */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+	RegVal |= XUSBPSU_GEVNTSIZ_INTMASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+
+	/* Processes events in an Event Buffer */
+	XUsbPsu_EventBufferHandler(InstancePtr);
+
+	/* Unmask event interrupt */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+	RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+}
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
new file mode 100644
index 000000000..c172c5d69
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_sinit.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg   06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern XUsbPsu_Config XUsbPsu_ConfigTable[];
+
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId)
+{
+	XUsbPsu_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XUSBPSU_NUM_INSTANCES; i++) {
+			if (XUsbPsu_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XUsbPsu_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XUsbPsu_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
index 5147be676..6ea6b192b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
index 33202264d..194aac12e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
index 5a742ad93..76354534a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
@@ -4,7 +4,7 @@
 
 BEGIN OS
  PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 5.4
+ PARAMETER OS_VER = 6.1
  PARAMETER PROC_INSTANCE = psu_cortexr5_0
  PARAMETER stdin = psu_uart_0
  PARAMETER stdout = psu_uart_0
@@ -15,13 +15,12 @@ BEGIN PROCESSOR
  PARAMETER DRIVER_NAME = cpu_cortexr5
  PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_cortexr5_0
- PARAMETER extra_compiler_flags = -g -DARMR5 -mfpu=vfpv3-d16
 END
 
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
  PARAMETER HW_INSTANCE = psu_acpu_gic
 END
 
@@ -117,31 +116,31 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = sysmonpsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 2.0
  PARAMETER HW_INSTANCE = psu_ams
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_1
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_2
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_5
 END
 
@@ -151,15 +150,9 @@ BEGIN DRIVER
  PARAMETER HW_INSTANCE = psu_apu
 END
 
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_bbram_0
-END
-
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = canps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_can_1
 END
 
@@ -177,7 +170,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = coresightps_dcc
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
  PARAMETER HW_INSTANCE = psu_coresight_0
 END
 
@@ -201,7 +194,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = csudma
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_csudma
 END
 
@@ -254,8 +247,8 @@ BEGIN DRIVER
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = ddrcpsu
+ PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_ddrc_0
 END
 
@@ -279,7 +272,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.3
  PARAMETER HW_INSTANCE = psu_ethernet_3
 END
 
@@ -375,22 +368,16 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
  PARAMETER HW_INSTANCE = psu_i2c_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
  PARAMETER HW_INSTANCE = psu_i2c_1
 END
 
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_iou_s
-END
-
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
@@ -417,13 +404,13 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ipipsu
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_VER = 2.1
  PARAMETER HW_INSTANCE = psu_ipi_1
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ipipsu
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_VER = 2.1
  PARAMETER HW_INSTANCE = psu_ipi_2
 END
 
@@ -469,12 +456,6 @@ BEGIN DRIVER
  PARAMETER HW_INSTANCE = psu_ocm_ram_0
 END
 
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_ocm_ram_1
-END
-
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
@@ -502,24 +483,24 @@ END
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_global_0
+ PARAMETER HW_INSTANCE = psu_pcie_low
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_iomodule
+ PARAMETER HW_INSTANCE = psu_pmu_global_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_ram
+ PARAMETER HW_INSTANCE = psu_pmu_iomodule
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = qspipsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.3
  PARAMETER HW_INSTANCE = psu_qspi_0
 END
 
@@ -535,36 +516,12 @@ BEGIN DRIVER
  PARAMETER HW_INSTANCE = psu_r5_0_atcm
 END
 
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_0_atcm_lockstep
-END
-
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
  PARAMETER HW_INSTANCE = psu_r5_0_btcm
 END
 
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_0_btcm_lockstep
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_1_atcm
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_1_btcm
-END
-
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
@@ -579,7 +536,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
  PARAMETER HW_INSTANCE = psu_rcpu_gic
 END
 
@@ -597,7 +554,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = rtcpsu
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
  PARAMETER HW_INSTANCE = psu_rtc
 END
 
@@ -609,7 +566,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 2.7
+ PARAMETER DRIVER_VER = 3.1
  PARAMETER HW_INSTANCE = psu_sd_1
 END
 
@@ -639,43 +596,43 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_1
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_2
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_3
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
  PARAMETER HW_INSTANCE = psu_uart_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
  PARAMETER HW_INSTANCE = psu_uart_1
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = usbpsu
+ PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_usb_0
 END
 
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
index aa923f4f9..e9d647916 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
index a082ce0fd..b478e5d05 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
index 219b80d7f..0c8b226fc 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
index 85c993d2d..f44563f9f 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
index 4dd178f04..8671e3fbe 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
index fb9e56339..17fa89370 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
index 51801c5eb..0c9c7875d 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
index 9f75b9763..464f2099e 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
index 1edd414e3..90a346f75 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
index dc2b71035..cd548fd9f 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
@@ -116,7 +116,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata|src/platform.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/printf-stdarg.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata|src/platform.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
index 9fb066b6b..04040ffb0 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
@@ -129,7 +129,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044021</id>
+			<id>1484796638366</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -138,7 +138,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044028</id>
+			<id>1484796638369</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -147,7 +147,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044037</id>
+			<id>1484796638372</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -156,7 +156,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044046</id>
+			<id>1484796638376</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -165,7 +165,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044057</id>
+			<id>1484796638381</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -174,7 +174,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044063</id>
+			<id>1484796638385</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -183,7 +183,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044071</id>
+			<id>1484796638389</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -192,7 +192,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044076</id>
+			<id>1484796638392</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -201,7 +201,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044081</id>
+			<id>1484796638396</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -210,7 +210,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044088</id>
+			<id>1484796638399</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -219,7 +219,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044094</id>
+			<id>1484796638402</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -228,7 +228,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044098</id>
+			<id>1484796638406</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -237,7 +237,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044103</id>
+			<id>1484796638409</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -246,7 +246,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044107</id>
+			<id>1484796638413</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -254,6 +254,15 @@
 				<arguments>1.0-name-matches-false-false-blocktim.c</arguments>
 			</matcher>
 		</filter>
+		<filter>
+			<id>1484796638416</id>
+			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-AbortDelay.c</arguments>
+			</matcher>
+		</filter>
 		<filter>
 			<id>1426008787023</id>
 			<name>src/lwIP_Demo/lwIP-1.4.0/src/core</name>
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
index 21130bdad..546d99ff0 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
@@ -161,6 +161,8 @@ referenced anyway. */
 #define INCLUDE_xTaskGetSchedulerState			0
 #define INCLUDE_xSemaphoreGetMutexHolder		0
 #define INCLUDE_xTimerPendFunctionCall			1
+#define INCLUDE_xTaskAbortDelay					1
+#define INCLUDE_xTaskGetHandle					1
 
 /* This demo does not make use of example stats formatting functions.  These
 format the raw data provided by the uxTaskGetSystemState() function in to human
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
index 6964298f2..d4562fae6 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
@@ -140,6 +140,7 @@
 #include "EventGroupsDemo.h"
 #include "TaskNotify.h"
 #include "IntSemTest.h"
+#include "AbortDelay.h"
 
 /* Priorities for the demo application tasks. */
 #define mainSEM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1UL )
@@ -251,6 +252,7 @@ void main_full( void )
 	vStartEventGroupTasks();
 	vStartTaskNotifyTask();
 	vStartInterruptSemaphoreTasks();
+	vCreateAbortDelayTasks();
 
 	/* Note - the set of standard demo tasks contains two versions of
 	vStartMathTasks.c.  One is defined in flop.c, and uses double precision
@@ -371,17 +373,22 @@ unsigned long ulErrorFound = pdFALSE;
 			ulErrorFound |= 1UL << 14UL;
 		}
 
+		if( xAreAbortDelayTestTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 15UL;
+		}
+
 		/* Check that the register test 1 task is still running. */
 		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
 		{
-			ulErrorFound |= 1UL << 15UL;
+			ulErrorFound |= 1UL << 16UL;
 		}
 		ulLastRegTest1Value = ulRegTest1LoopCounter;
 
 		/* Check that the register test 2 task is still running. */
 		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
 		{
-			ulErrorFound |= 1UL << 16UL;
+			ulErrorFound |= 1UL << 17UL;
 		}
 		ulLastRegTest2Value = ulRegTest2LoopCounter;
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
index 51c750825..0b780d6ff 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -136,12 +136,18 @@ context. */
 #define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portEL3							( ( StackType_t ) 0x0c )
 #define portSP_ELx						( ( StackType_t ) 0x01 )
 #define portSP_EL0						( ( StackType_t ) 0x00 )
 
-/* At the time of writing, the BSP only supports EL3. */
-#define portINITIAL_PSTATE				( portEL3 | portSP_EL0 )
+#if GUEST
+	#define portEL1						( ( StackType_t ) 0x04 )
+	#define portINITIAL_PSTATE				( portEL1 | portSP_EL0 )
+#else
+	#define portEL3						( ( StackType_t ) 0x0c )
+	/* At the time of writing, the BSP only supports EL3. */
+	#define portINITIAL_PSTATE			( portEL3 | portSP_EL0 )
+#endif
+
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
 point is zero. */
@@ -329,7 +335,9 @@ uint32_t ulAPSR;
 
 		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
 		value. */
-		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+		configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+
 
 		/* Restore the clobbered interrupt priority register to its original
 		value. */
@@ -341,9 +349,13 @@ uint32_t ulAPSR;
 	/* At the time of writing, the BSP only supports EL3. */
 	__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
 	ulAPSR &= portAPSR_MODE_BITS_MASK;
+#if GUEST
+	configASSERT( ulAPSR == portEL1 );
+	if( ulAPSR == portEL1 )
+#else
 	configASSERT( ulAPSR == portEL3 );
-
 	if( ulAPSR == portEL3 )
+#endif
 	{
 		/* Only continue if the binary point value is set to its lowest possible
 		setting.  See the comments in vPortValidateInterruptPriority() below for
@@ -423,7 +435,11 @@ void vPortExitCritical( void )
 void FreeRTOS_Tick_Handler( void )
 {
 	/* Must be the lowest possible priority. */
-	configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	#if( !QEMU )
+	{
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	}
+	#endif
 
 	/* Interrupts should not be enabled before this point. */
 	#if( configASSERT_DEFINED == 1 )
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
index ad12a68a8..c55aff563 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
@@ -111,10 +111,14 @@
 	STP 	X30, XZR, [SP, #-0x10]!
 
 	/* Save the SPSR. */
+#if GUEST
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
 	MRS		X3, SPSR_EL3
-
 	/* Save the ELR. */
 	MRS		X2, ELR_EL3
+#endif
 
 	STP 	X2, X3, [SP, #-0x10]!
 
@@ -217,11 +221,17 @@
 1:
 	LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
 
+#if GUEST
+	/* Restore the SPSR. */
+	MSR		SPSR_EL1, X3
+	/* Restore the ELR. */
+	MSR		ELR_EL1, X2
+#else
 	/* Restore the SPSR. */
 	MSR		SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
-
 	/* Restore the ELR. */
 	MSR		ELR_EL3, X2
+#endif
 
 	LDP 	X30, XZR, [SP], #0x10
 	LDP 	X28, X29, [SP], #0x10
@@ -256,10 +266,19 @@
 FreeRTOS_SWI_Handler:
 	/* Save the context of the current task and select a new task to run. */
 	portSAVE_CONTEXT
-
+#if GUEST
+	MRS		X0, ESR_EL1
+#else
 	MRS		X0, ESR_EL3
+#endif
+
 	LSR		X1, X0, #26
-	CMP		X1, #0x17 /* 0x17 = SMC instruction. */
+
+#if GUEST
+	CMP		X1, #0x15 	/* 0x15 = SVC instruction. */
+#else
+	CMP		X1, #0x17 	/* 0x17 = SMC instruction. */
+#endif
 	B.NE	FreeRTOS_Abort
 	BL 		vTaskSwitchContext
 
@@ -279,7 +298,11 @@ vPortRestoreTaskContext:
 
 	/* Install the FreeRTOS interrupt handlers. */
 	LDR		X1, =freertos_vector_base
+#if GUEST
+	MSR		VBAR_EL1, X1
+#else
 	MSR		VBAR_EL3, X1
+#endif
 	DSB		SY
 	ISB		SY
 
@@ -307,8 +330,13 @@ FreeRTOS_IRQ_Handler:
 	STP		X29, X30, [SP, #-0x10]!
 
 	/* Save the SPSR and ELR. */
+#if GUEST
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
 	MRS		X3, SPSR_EL3
 	MRS		X2, ELR_EL3
+#endif
 	STP 	X2, X3, [SP, #-0x10]!
 
 	/* Increment the interrupt nesting counter. */
@@ -365,8 +393,13 @@ FreeRTOS_IRQ_Handler:
 
 	/* Restore volatile registers. */
 	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if GUEST
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
 	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
 	MSR		ELR_EL3, X4
+#endif
 	DSB		SY
 	ISB		SY
 
@@ -390,8 +423,13 @@ FreeRTOS_IRQ_Handler:
 Exit_IRQ_No_Context_Switch:
 	/* Restore volatile registers. */
 	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if GUEST
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
 	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
 	MSR		ELR_EL3, X4
+#endif
 	DSB		SY
 	ISB		SY
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index a617b829b..3fe8cf645 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -128,8 +128,11 @@ extern uint64_t ullPortYieldRequired;			\
 }
 
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SMC 0" )
-
+#if GUEST
+	#define portYIELD() __asm volatile ( "SVC 0" )
+#else
+	#define portYIELD() __asm volatile ( "SMC 0" )
+#endif
 /*-----------------------------------------------------------
  * Critical section control
  *----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
index ff0abc740..856ff0d29 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -475,7 +475,7 @@ void xPortSysTickHandler( void )
 
 	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
 	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
 	TickType_t xModifiableIdleTime;
 
 		/* Make sure the SysTick reload value does not overflow the counter. */
@@ -551,18 +551,21 @@ void xPortSysTickHandler( void )
 			}
 			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
 
-			/* Stop SysTick.  Again, the time the SysTick is stopped for is
-			accounted for as best it can be, but using the tickless mode will
-			inevitably result in some tiny drift of the time maintained by the
-			kernel with respect to calendar time. */
-			ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
-			portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
-
 			/* Re-enable interrupts - see comments above the cpsid instruction()
 			above. */
 			__asm volatile( "cpsie i" );
-
-			if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			
+			/* Disable the SysTick clock without reading the 
+			portNVIC_SYSTICK_CTRL_REG register to ensure the 
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
 			{
 				uint32_t ulCalculatedLoadValue;
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
index 13b971342..50380967e 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
@@ -230,16 +230,17 @@ FreeRTOS_IRQ_Handler:
 	LDR		r0, [r2]
 
 	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	future use. */
+	future use.  _RB_ Is this ever needed provided the start of the stack is
+	alligned on an 8-byte boundary? */
 	MOV		r2, sp
 	AND		r2, r2, #4
 	SUB		sp, sp, r2
 
 	/* Call the interrupt handler. */
-	PUSH	{r0-r3, lr}
+	PUSH	{r0-r4, lr}
 	LDR		r1, vApplicationIRQHandlerConst
 	BLX		r1
-	POP		{r0-r3, lr}
+	POP		{r0-r4, lr}
 	ADD		sp, sp, r2
 
 	CPSID	i
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
index cc9a2c721..918d0f960 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
@@ -128,16 +128,16 @@ FreeRTOS_IRQ_Handler
 	LDR		r0, [r2]
 
 	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	; future use.
+	; future use.  _RB_ Is this ever necessary if start of stack is 8-byte aligned?
 	MOV		r2, sp
 	AND		r2, r2, #4
 	SUB		sp, sp, r2
 
-	; Call the interrupt handler
-	PUSH	{r0-r3, lr}
+	; Call the interrupt handler.  r4 is pushed to maintain alignment.
+	PUSH	{r0-r4, lr}
 	LDR		r1, =vApplicationIRQHandler
 	BLX		r1
-	POP		{r0-r3, lr}
+	POP		{r0-r4, lr}
 	ADD		sp, sp, r2
 
 	CPSID	i