From: Stephen Warren Date: Fri, 21 Mar 2014 18:28:53 +0000 (-0600) Subject: ARM: tegra: use apb_misc.h in more places X-Git-Tag: v2014.07-rc1~2^2~4^2~12 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=19ed7b4ecf6bdcf991d0a63aac3faa80b6df43cb;p=u-boot ARM: tegra: use apb_misc.h in more places Tegra's "APB misc" register region contains various miscellaneous registers and the Tegra pinmux registers. Some code that touches the misc registers currently uses struct pmux_tri_ctlr, which is intended to be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl, which is intended to be a definition of the miscellaneous registers. Convert all such code to use struct apb_misc_pp_ctrl, since struct pmux_tri_ctlr goes away in the next patch. This requires adding a missing field definition to struct apb_misc_pp_ctrl, and moving the header into a more common location. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 5171a8f907..3479541020 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -13,16 +13,18 @@ #include #include #include +#include #include #include #include "cpu.h" void spl_board_init(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; /* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); + writel(0xC0, &apb_misc->cfg_ctl); board_init_uart_f(); diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c index 934e395955..ed2462ab0f 100644 --- a/arch/arm/cpu/tegra20-common/emc.c +++ b/arch/arm/cpu/tegra20-common/emc.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c index 8beba53fc3..5fdc4bbb50 100644 --- a/arch/arm/cpu/tegra20-common/warmboot.c +++ b/arch/arm/cpu/tegra20-common/warmboot.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void) { u32 ram_code; struct sdram_params sdram; - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct apb_misc_gp_ctlr *gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; @@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void) union fbio_spare_reg fbio_spare; /* get ram code that is used as index to array sdram_params in BCT */ - ram_code = (readl(&pmt->pmt_strap_opt_a) >> - STRAP_OPT_A_RAM_CODE_SHIFT) & 3; + ram_code = (readl(&apb_misc->strapping_opt_a) >> + STRAP_OPT_A_RAM_CODE_SHIFT) & 3; memcpy(&sdram, (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), sizeof(sdram)); diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index b910f7844b..27ce5f480f 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,7 +22,8 @@ void wb_start(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct clk_rst_ctlr *clkrst = @@ -33,7 +35,7 @@ void wb_start(void) u32 reg; /* enable JTAG & TBE */ - writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl); + writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl); /* Are we running where we're supposed to be? */ asm volatile ( diff --git a/arch/arm/include/asm/arch-tegra/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h new file mode 100644 index 0000000000..a5bc092ffd --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/apb_misc.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GP_PADCTRL_H_ +#define _GP_PADCTRL_H_ + +/* APB_MISC_PP registers */ +struct apb_misc_pp_ctlr { + u32 reserved0[2]; + u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ + u32 reserved1[6]; /* 0x0c .. 0x20 */ + u32 cfg_ctl; /* 0x24 */ +}; + +/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ +#define RAM_CODE_SHIFT 4 +#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) + +#endif diff --git a/arch/arm/include/asm/arch-tegra20/apb_misc.h b/arch/arm/include/asm/arch-tegra20/apb_misc.h deleted file mode 100644 index f314f5acc3..0000000000 --- a/arch/arm/include/asm/arch-tegra20/apb_misc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ - -/* APB_MISC_PP registers */ -struct apb_misc_pp_ctlr { - u32 reserved0[2]; - u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ -}; - -/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ -#define RAM_CODE_SHIFT 4 -#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) - -#endif