From: Andre Przywara <andre.przywara@arm.com>
Date: Thu, 16 Feb 2017 01:20:18 +0000 (+0000)
Subject: sunxi: fix ACTLR.SMP assembly routine
X-Git-Tag: v2017.05-rc2~81^2~11
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1afd0f6f17db1625a50b69a1edc40f5163db7c31;p=u-boot

sunxi: fix ACTLR.SMP assembly routine

If we take the liberty to use register r0 to perform our bit set, we
should be nice enough to tell the compiler about it.
Add r0 to the clobber list to avoid potential mayhem.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Jagan Teki <jagan@openedev.com>
---

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 52be5b0551..58fbacb774 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -188,7 +188,8 @@ void s_init(void)
 	asm volatile(
 		"mrc p15, 0, r0, c1, c0, 1\n"
 		"orr r0, r0, #1 << 6\n"
-		"mcr p15, 0, r0, c1, c0, 1\n");
+		"mcr p15, 0, r0, c1, c0, 1\n"
+		::: "r0");
 #endif
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
 	/* Enable non-secure access to some peripherals */