From: Chunhe Lan <Chunhe.Lan@freescale.com>
Date: Mon, 20 Oct 2014 08:03:15 +0000 (+0800)
Subject: powerpc/t4rdb: Fix CPLD timing
X-Git-Tag: v2015.01-rc3~52^2~5
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1b5c2b51337bb360555f2fb2f6e671fd8662a8d2;p=u-boot

powerpc/t4rdb: Fix CPLD timing

This fixes CPLD timing from previous commit
ab06b236f76cfa42f264ee161be190b3e479298f.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: This is the difference between v2 and v1 patch]
Reviewed-by: York Sun <yorksun@freescale.com>
---

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index e639e1d57a..48b8dc7fd7 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -533,7 +533,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0