From: mifi <mifi@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Mon, 16 Jun 2008 19:54:15 +0000 (+0000)
Subject: - added target and event script for the eir-sam7se512 target
X-Git-Tag: v0.1.0~577
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1c429d9ce7d54be12645addabe15cf81dda94737;p=openocd

- added target and event script for the eir-sam7se512 target

git-svn-id: svn://svn.berlios.de/openocd/trunk@712 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/src/target/event/eir-sam7se512_reset.script b/src/target/event/eir-sam7se512_reset.script
new file mode 100644
index 00000000..8a78532a
--- /dev/null
+++ b/src/target/event/eir-sam7se512_reset.script
@@ -0,0 +1,87 @@
+# WDT_MR, disable watchdog 
+mww 0xFFFFFD44 0x00008000
+
+# RSTC_MR, enable user reset
+mww 0xfffffd08 0xa5000001
+
+# CKGR_MOR
+mww 0xFFFFFC20 0x00000601
+sleep 10
+
+# CKGR_PLLR
+mww 0xFFFFFC2C 0x00481c0e
+sleep 10
+
+# PMC_MCKR
+mww 0xFFFFFC30 0x00000007
+sleep 10
+
+# PMC_IER
+mww 0xFFFFFF60 0x00480100
+
+#
+# Enable SDRAM interface.
+#
+
+# Enable SDRAM control at PIO A.
+mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
+mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+
+# Enable address bus (A0, A2-A11, A13-A17) at PIO B
+mww 0xfffff674 0x0003effd # PIO_BSR_OFF
+mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+
+# Enable 16 bit data bus at PIO C
+mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
+mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+
+# Enable SDRAM chip select
+mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+
+# Set SDRAM characteristics in configuration register.
+# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+sleep 10
+
+# Issue 16 bit SDRAM command: NOP
+mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+
+# Issue 16 bit SDRAM command: Precharge all
+mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+
+# Issue 8 auto-refresh cycles
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000000 
+
+# Issue 16 bit SDRAM command: Set mode register  
+mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+mww 0x20000014 0xcafedede
+
+# Set refresh rate count ???
+mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+
+# Issue 16 bit SDRAM command: Normal mode
+mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+mww 0x20000000 0x00000180
+
+#
+# Enable external reset key.
+#
+mww 0xfffffd08 0xa5000001
+
diff --git a/src/target/target/eir-sam7se512.cfg b/src/target/target/eir-sam7se512.cfg
new file mode 100644
index 00000000..4c517bea
--- /dev/null
+++ b/src/target/target/eir-sam7se512.cfg
@@ -0,0 +1,24 @@
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+
+#target configuration
+daemon_startup reset
+
+#target <type> <startup mode>
+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
+target arm7tdmi little run_and_init 0 arm7tdmi
+run_and_halt_time 0 30
+
+target_script 0 reset event/eir-sam7se512_reset.script
+
+working_area 0 0x00200000 0x4000 nobackup
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank at91sam7 0 0 0 0 0
+
+# For more information about the configuration files, take a 
+# look at the "Open On-Chip Debugger (openocd)" documentation.