From: Tang Yuantian Date: Wed, 16 Dec 2015 05:50:57 +0000 (+0800) Subject: arm: ls1021a: Adjust sata register default values X-Git-Tag: v2016.03-rc1~45^2~36 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1ef7ac70e24c40553307d5246cfa6ebd7394f2f1;p=u-boot arm: ls1021a: Adjust sata register default values Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c index deeb674c69..144f2c368d 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -11,11 +11,11 @@ /* port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28183411 -#define AHCI_PORT_PHY_3_CFG 0x0e081004 -#define AHCI_PORT_PHY_4_CFG 0x00480811 -#define AHCI_PORT_PHY_5_CFG 0x192c96a4 -#define AHCI_PORT_TRANS_CFG 0x08000025 +#define AHCI_PORT_PHY_2_CFG 0x28183414 +#define AHCI_PORT_PHY_3_CFG 0x0e080e06 +#define AHCI_PORT_PHY_4_CFG 0x064a080b +#define AHCI_PORT_PHY_5_CFG 0x2aa86470 +#define AHCI_PORT_TRANS_CFG 0x08000029 #define SATA_ECC_REG_ADDR 0x20220520 #define SATA_ECC_DISABLE 0x00020000