From: Lokesh Vutla Date: Thu, 11 Aug 2016 07:30:59 +0000 (+0530) Subject: drivers: net: cpsw: always flush cache of size aligned to PKTALIGN X-Git-Tag: v2016.09-rc2~67 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1f01962e0fde9d3e57318e9f6e05c45d8ef2a783;p=u-boot drivers: net: cpsw: always flush cache of size aligned to PKTALIGN cpsw tries to flush dcache which is not in the range of PKTALIGN. Because of this the following warning comes while flushing: CACHE: Misaligned operation at range [dffecec0, dffed016] Fix it by flushing cache of size aligned to PKTALIGN. Signed-off-by: Lokesh Vutla --- diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 774b021e35..511a965c9b 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -908,7 +908,7 @@ static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) int timeout = CPDMA_TIMEOUT; flush_dcache_range((unsigned long)packet, - (unsigned long)packet + length); + (unsigned long)packet + ALIGN(length, PKTALIGN)); /* first reap completed packets */ while (timeout-- &&