From: richardbarry Date: Wed, 24 Nov 2010 20:53:02 +0000 (+0000) Subject: Update the CMSIS files included in the Red Suite LPC17xx demo. X-Git-Tag: V6.1.1~92 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=20c5c56178dc524f13a44ee1cda921e18b35c3e2;p=freertos Update the CMSIS files included in the Red Suite LPC17xx demo. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1165 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/LPC17xx.h b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/LPC17xx.h index 09572d30b..8c4050b3a 100644 --- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/LPC17xx.h +++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/LPC17xx.h @@ -1,160 +1,20 @@ -#ifndef __LPC17xx_H -#define __LPC17xx_H - -/* System Control Block (SCB) includes: - Flash Accelerator Module, Clocking and Power Control, External Interrupts, - Reset, System Control and Status -*/ -#define SCB_BASE_ADDR 0x400FC000 - -#define PCONP_PCTIM0 0x00000002 -#define PCONP_PCTIM1 0x00000004 -#define PCONP_PCUART0 0x00000008 -#define PCONP_PCUART1 0x00000010 -#define PCONP_PCPWM1 0x00000040 -#define PCONP_PCI2C0 0x00000080 -#define PCONP_PCSPI 0x00000100 -#define PCONP_PCRTC 0x00000200 -#define PCONP_PCSSP1 0x00000400 -#define PCONP_PCAD 0x00001000 -#define PCONP_PCCAN1 0x00002000 -#define PCONP_PCCAN2 0x00004000 -#define PCONP_PCGPIO 0x00008000 -#define PCONP_PCRIT 0x00010000 -#define PCONP_PCMCPWM 0x00020000 -#define PCONP_PCQEI 0x00040000 -#define PCONP_PCI2C1 0x00080000 -#define PCONP_PCSSP0 0x00200000 -#define PCONP_PCTIM2 0x00400000 -#define PCONP_PCTIM3 0x00800000 -#define PCONP_PCUART2 0x01000000 -#define PCONP_PCUART3 0x02000000 -#define PCONP_PCI2C2 0x04000000 -#define PCONP_PCI2S 0x08000000 -#define PCONP_PCGPDMA 0x20000000 -#define PCONP_PCENET 0x40000000 -#define PCONP_PCUSB 0x80000000 - -#define PLLCON_PLLE 0x00000001 -#define PLLCON_PLLC 0x00000002 -#define PLLCON_MASK 0x00000003 - -#define PLLCFG_MUL1 0x00000000 -#define PLLCFG_MUL2 0x00000001 -#define PLLCFG_MUL3 0x00000002 -#define PLLCFG_MUL4 0x00000003 -#define PLLCFG_MUL5 0x00000004 -#define PLLCFG_MUL6 0x00000005 -#define PLLCFG_MUL7 0x00000006 -#define PLLCFG_MUL8 0x00000007 -#define PLLCFG_MUL9 0x00000008 -#define PLLCFG_MUL10 0x00000009 -#define PLLCFG_MUL11 0x0000000A -#define PLLCFG_MUL12 0x0000000B -#define PLLCFG_MUL13 0x0000000C -#define PLLCFG_MUL14 0x0000000D -#define PLLCFG_MUL15 0x0000000E -#define PLLCFG_MUL16 0x0000000F -#define PLLCFG_MUL17 0x00000010 -#define PLLCFG_MUL18 0x00000011 -#define PLLCFG_MUL19 0x00000012 -#define PLLCFG_MUL20 0x00000013 -#define PLLCFG_MUL21 0x00000014 -#define PLLCFG_MUL22 0x00000015 -#define PLLCFG_MUL23 0x00000016 -#define PLLCFG_MUL24 0x00000017 -#define PLLCFG_MUL25 0x00000018 -#define PLLCFG_MUL26 0x00000019 -#define PLLCFG_MUL27 0x0000001A -#define PLLCFG_MUL28 0x0000001B -#define PLLCFG_MUL29 0x0000001C -#define PLLCFG_MUL30 0x0000001D -#define PLLCFG_MUL31 0x0000001E -#define PLLCFG_MUL32 0x0000001F -#define PLLCFG_MUL33 0x00000020 -#define PLLCFG_MUL34 0x00000021 -#define PLLCFG_MUL35 0x00000022 -#define PLLCFG_MUL36 0x00000023 - -#define PLLCFG_DIV1 0x00000000 -#define PLLCFG_DIV2 0x00010000 -#define PLLCFG_DIV3 0x00020000 -#define PLLCFG_DIV4 0x00030000 -#define PLLCFG_DIV5 0x00040000 -#define PLLCFG_DIV6 0x00050000 -#define PLLCFG_DIV7 0x00060000 -#define PLLCFG_DIV8 0x00070000 -#define PLLCFG_DIV9 0x00080000 -#define PLLCFG_DIV10 0x00090000 -#define PLLCFG_MASK 0x00FF7FFF - -#define PLLSTAT_MSEL_MASK 0x00007FFF -#define PLLSTAT_NSEL_MASK 0x00FF0000 - -#define PLLSTAT_PLLE (1 << 24) -#define PLLSTAT_PLLC (1 << 25) -#define PLLSTAT_PLOCK (1 << 26) - -#define PLLFEED_FEED1 0x000000AA -#define PLLFEED_FEED2 0x00000055 - -#define NVIC_IRQ_WDT 0u // IRQ0, exception number 16 -#define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17 -#define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18 -#define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19 -#define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20 -#define NVIC_IRQ_UART0 5u // IRQ5, exception number 21 -#define NVIC_IRQ_UART1 6u // IRQ6, exception number 22 -#define NVIC_IRQ_UART2 7u // IRQ7, exception number 23 -#define NVIC_IRQ_UART3 8u // IRQ8, exception number 24 -#define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25 -#define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26 -#define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27 -#define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28 -#define NVIC_IRQ_SPI 13u // IRQ13, exception number 29 -#define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30 -#define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31 -#define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32 -#define NVIC_IRQ_RTC 17u // IRQ17, exception number 33 -#define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34 -#define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35 -#define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36 -#define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37 -#define NVIC_IRQ_ADC 22u // IRQ22, exception number 38 -#define NVIC_IRQ_BOD 23u // IRQ23, exception number 39 -#define NVIC_IRQ_USB 24u // IRQ24, exception number 40 -#define NVIC_IRQ_CAN 25u // IRQ25, exception number 41 -#define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42 -#define NVIC_IRQ_I2S 27u // IRQ27, exception number 43 -#define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44 -#define NVIC_IRQ_RIT 29u // IRQ29, exception number 45 -#define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46 -#define NVIC_IRQ_QE 31u // IRQ31, exception number 47 -#define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48 -#define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49 -#define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50 - - -#endif // __LPC17xx_H - - -#ifndef CMSIS_17xx_H -#define CMSIS_17xx_H - -/****************************************************************************** - * @file: LPC17xx.h - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for +/**************************************************************************//** + * @file LPC17xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for * NXP LPC17xx Device Series - * @version: V1.1 - * @date: 14th May 2009 - *---------------------------------------------------------------------------- + * @version: V1.09 + * @date: 17. March 2010 + * - * Copyright (C) 2008 ARM Limited. All rights reserved. + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. * - * ARM Limited (ARM) is supplying this software for use with Cortex-M3 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * + * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. @@ -219,6 +79,8 @@ typedef enum IRQn MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ + USBActivity_IRQn = 33, /* USB Activity interrupt */ + CANActivity_IRQn = 34, /* CAN Activity interrupt */ } IRQn_Type; @@ -234,28 +96,18 @@ typedef enum IRQn #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -//#include "..\core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "core_cm3.h" +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ #include "system_LPC17xx.h" /* System Header */ - -/** - * Initialize the system clock - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemFrequency variable. - */ -extern void SystemInit (void); - - /******************************************************************************/ /* Device Specific Peripheral registers structures */ /******************************************************************************/ +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + /*------------- System Control (SC) ------------------------------------------*/ typedef struct { @@ -277,7 +129,9 @@ typedef struct __IO uint32_t CCLKCFG; __IO uint32_t USBCLKCFG; __IO uint32_t CLKSRCSEL; - uint32_t RESERVED4[12]; + __IO uint32_t CANSLEEPCLR; + __IO uint32_t CANWAKEFLAGS; + uint32_t RESERVED4[10]; __IO uint32_t EXTINT; /* External Interrupts */ uint32_t RESERVED5; __IO uint32_t EXTMODE; @@ -291,9 +145,9 @@ typedef struct __IO uint32_t PCLKSEL1; uint32_t RESERVED8[4]; __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ - uint32_t RESERVED9; + __IO uint32_t DMAREQSEL; __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ - } SC_TypeDef; + } LPC_SC_TypeDef; /*------------- Pin Connect Block (PINCON) -----------------------------------*/ typedef struct @@ -325,18 +179,79 @@ typedef struct __IO uint32_t PINMODE_OD2; __IO uint32_t PINMODE_OD3; __IO uint32_t PINMODE_OD4; -} PINCON_TypeDef; + __IO uint32_t I2CPADCFG; +} LPC_PINCON_TypeDef; /*------------- General Purpose Input/Output (GPIO) --------------------------*/ typedef struct { - __IO uint32_t FIODIR; - uint32_t RESERVED0[3]; - __IO uint32_t FIOMASK; - __IO uint32_t FIOPIN; - __IO uint32_t FIOSET; - __O uint32_t FIOCLR; -} GPIO_TypeDef; + union { + __IO uint32_t FIODIR; + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; typedef struct { @@ -352,7 +267,7 @@ typedef struct __O uint32_t IO2IntClr; __IO uint32_t IO2IntEnR; __IO uint32_t IO2IntEnF; -} GPIOINT_TypeDef; +} LPC_GPIOINT_TypeDef; /*------------- Timer (TIM) --------------------------------------------------*/ typedef struct @@ -372,9 +287,9 @@ typedef struct __I uint32_t CR1; uint32_t RESERVED0[2]; __IO uint32_t EMR; - uint32_t RESERVED1[24]; + uint32_t RESERVED1[12]; __IO uint32_t CTCR; -} TIM_TypeDef; +} LPC_TIM_TypeDef; /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ typedef struct @@ -394,14 +309,15 @@ typedef struct __I uint32_t CR1; __I uint32_t CR2; __I uint32_t CR3; + uint32_t RESERVED0; __IO uint32_t MR4; __IO uint32_t MR5; __IO uint32_t MR6; __IO uint32_t PCR; __IO uint32_t LER; - uint32_t RESERVED0[7]; + uint32_t RESERVED1[7]; __IO uint32_t CTCR; -} PWM_TypeDef; +} LPC_PWM_TypeDef; /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ typedef struct @@ -422,7 +338,7 @@ typedef struct }; __IO uint8_t LCR; uint8_t RESERVED1[7]; - __IO uint8_t LSR; + __I uint8_t LSR; uint8_t RESERVED2[7]; __IO uint8_t SCR; uint8_t RESERVED3[3]; @@ -432,11 +348,41 @@ typedef struct __IO uint8_t FDR; uint8_t RESERVED5[7]; __IO uint8_t TER; - uint8_t RESERVED6[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED7[3]; - __IO uint8_t ADRMATCH; -} UART_TypeDef; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART0_TypeDef; typedef struct { @@ -458,9 +404,9 @@ typedef struct uint8_t RESERVED1[3]; __IO uint8_t MCR; uint8_t RESERVED2[3]; - __IO uint8_t LSR; + __I uint8_t LSR; uint8_t RESERVED3[3]; - __IO uint8_t MSR; + __I uint8_t MSR; uint8_t RESERVED4[3]; __IO uint8_t SCR; uint8_t RESERVED5[3]; @@ -475,7 +421,9 @@ typedef struct __IO uint8_t ADRMATCH; uint8_t RESERVED10[3]; __IO uint8_t RS485DLY; -} UART1_TypeDef; + uint8_t RESERVED11[3]; + __IO uint32_t FIFOLVL; +} LPC_UART1_TypeDef; /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ typedef struct @@ -486,7 +434,7 @@ typedef struct __IO uint32_t SPCCR; uint32_t RESERVED0[3]; __IO uint32_t SPINT; -} SPI_TypeDef; +} LPC_SPI_TypeDef; /*------------- Synchronous Serial Communication (SSP) -----------------------*/ typedef struct @@ -501,7 +449,7 @@ typedef struct __IO uint32_t MIS; __IO uint32_t ICR; __IO uint32_t DMACR; -} SSP_TypeDef; +} LPC_SSP_TypeDef; /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ typedef struct @@ -522,13 +470,13 @@ typedef struct __IO uint32_t I2MASK1; __IO uint32_t I2MASK2; __IO uint32_t I2MASK3; -} I2C_TypeDef; +} LPC_I2C_TypeDef; /*------------- Inter IC Sound (I2S) -----------------------------------------*/ typedef struct { __IO uint32_t I2SDAO; - __IO uint32_t I2SDAI; + __IO uint32_t I2SDAI; __O uint32_t I2STXFIFO; __I uint32_t I2SRXFIFO; __I uint32_t I2SSTATE; @@ -541,7 +489,7 @@ typedef struct __IO uint32_t I2SRXBITRATE; __IO uint32_t I2STXMODE; __IO uint32_t I2SRXMODE; -} I2S_TypeDef; +} LPC_I2S_TypeDef; /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ typedef struct @@ -551,13 +499,13 @@ typedef struct __IO uint8_t RICTRL; uint8_t RESERVED0[3]; __IO uint32_t RICOUNTER; -} RIT_TypeDef; +} LPC_RIT_TypeDef; /*------------- Real-Time Clock (RTC) ----------------------------------------*/ typedef struct { __IO uint8_t ILR; - uint8_t RESERVED0[3]; + uint8_t RESERVED0[7]; __IO uint8_t CCR; uint8_t RESERVED1[3]; __IO uint8_t CIIR; @@ -589,9 +537,9 @@ typedef struct __IO uint32_t GPREG2; __IO uint32_t GPREG3; __IO uint32_t GPREG4; - __IO uint8_t WAKEUPDIS; + __IO uint8_t RTC_AUXEN; uint8_t RESERVED12[3]; - __IO uint8_t PWRCTRL; + __IO uint8_t RTC_AUX; uint8_t RESERVED13[3]; __IO uint8_t ALSEC; uint8_t RESERVED14[3]; @@ -609,7 +557,7 @@ typedef struct uint8_t RESERVED20[3]; __IO uint16_t ALYEAR; uint16_t RESERVED21; -} RTC_TypeDef; +} LPC_RTC_TypeDef; /*------------- Watchdog Timer (WDT) -----------------------------------------*/ typedef struct @@ -621,7 +569,7 @@ typedef struct uint8_t RESERVED1[3]; __I uint32_t WDTV; __IO uint32_t WDCLKSEL; -} WDT_TypeDef; +} LPC_WDT_TypeDef; /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ typedef struct @@ -640,7 +588,7 @@ typedef struct __I uint32_t ADDR7; __I uint32_t ADSTAT; __IO uint32_t ADTRM; -} ADC_TypeDef; +} LPC_ADC_TypeDef; /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ typedef struct @@ -648,7 +596,7 @@ typedef struct __IO uint32_t DACR; __IO uint32_t DACCTRL; __IO uint16_t DACCNTVAL; -} DAC_TypeDef; +} LPC_DAC_TypeDef; /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ typedef struct @@ -683,7 +631,7 @@ typedef struct __O uint32_t MCINTFLAG_SET; __O uint32_t MCINTFLAG_CLR; __O uint32_t MCCAP_CLR; -} MCPWM_TypeDef; +} LPC_MCPWM_TypeDef; /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ typedef struct @@ -711,13 +659,13 @@ typedef struct __I uint32_t QEIIE; __O uint32_t QEICLR; __O uint32_t QEISET; -} QEI_TypeDef; +} LPC_QEI_TypeDef; /*------------- Controller Area Network (CAN) --------------------------------*/ typedef struct { __IO uint32_t mask[512]; /* ID Masks */ -} CANAF_RAM_TypeDef; +} LPC_CANAF_RAM_TypeDef; typedef struct /* Acceptance Filter Registers */ { @@ -729,14 +677,17 @@ typedef struct /* Acceptance Filter Registers */ __IO uint32_t ENDofTable; __I uint32_t LUTerrAd; __I uint32_t LUTerr; -} CANAF_TypeDef; + __IO uint32_t FCANIE; + __IO uint32_t FCANIC0; + __IO uint32_t FCANIC1; +} LPC_CANAF_TypeDef; typedef struct /* Central Registers */ { __I uint32_t CANTxSR; __I uint32_t CANRxSR; __I uint32_t CANMSR; -} CANCR_TypeDef; +} LPC_CANCR_TypeDef; typedef struct /* Controller Registers */ { @@ -764,7 +715,7 @@ typedef struct /* Controller Registers */ __IO uint32_t TID3; __IO uint32_t TDA3; __IO uint32_t TDB3; -} CAN_TypeDef; +} LPC_CAN_TypeDef; /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ typedef struct /* Common Registers */ @@ -783,7 +734,7 @@ typedef struct /* Common Registers */ __IO uint32_t DMACSoftLSReq; __IO uint32_t DMACConfig; __IO uint32_t DMACSync; -} GPDMA_TypeDef; +} LPC_GPDMA_TypeDef; typedef struct /* Channel Registers */ { @@ -792,7 +743,7 @@ typedef struct /* Channel Registers */ __IO uint32_t DMACCLLI; __IO uint32_t DMACCControl; __IO uint32_t DMACCConfig; -} GPDMACH_TypeDef; +} LPC_GPDMACH_TypeDef; /*------------- Universal Serial Bus (USB) -----------------------------------*/ typedef struct @@ -878,23 +829,25 @@ typedef struct __O uint32_t USBSysErrIntSet; uint32_t RESERVED4[15]; + union { __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_WO; + __O uint32_t I2C_TX; + }; __I uint32_t I2C_STS; __IO uint32_t I2C_CTL; __IO uint32_t I2C_CLKHI; __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[823]; + uint32_t RESERVED5[824]; union { __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ __IO uint32_t OTGClkCtrl; - } ; + }; union { __I uint32_t USBClkSt; __I uint32_t OTGClkSt; }; -} USB_TypeDef; +} LPC_USB_TypeDef; /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ typedef struct @@ -953,128 +906,130 @@ typedef struct __IO uint32_t PowerDown; uint32_t RESERVED8; __IO uint32_t Module_ID; -} EMAC_TypeDef; +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + /******************************************************************************/ /* Peripheral memory map */ /******************************************************************************/ /* Base addresses */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x10000000UL) -#define GPIO_BASE (0x2009C000UL) -#define APB0_BASE (0x40000000UL) -#define APB1_BASE (0x40080000UL) -#define AHB_BASE (0x50000000UL) -#define CM3_BASE (0xE0000000UL) +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) /* APB0 peripherals */ -#define WDT_BASE (APB0_BASE + 0x00000) -#define TIM0_BASE (APB0_BASE + 0x04000) -#define TIM1_BASE (APB0_BASE + 0x08000) -#define UART0_BASE (APB0_BASE + 0x0C000) -#define UART1_BASE (APB0_BASE + 0x10000) -#define PWM1_BASE (APB0_BASE + 0x18000) -#define I2C0_BASE (APB0_BASE + 0x1C000) -#define SPI_BASE (APB0_BASE + 0x20000) -#define RTC_BASE (APB0_BASE + 0x24000) -#define GPIOINT_BASE (APB0_BASE + 0x28080) -#define PINCON_BASE (APB0_BASE + 0x2C000) -#define SSP1_BASE (APB0_BASE + 0x30000) -#define ADC_BASE (APB0_BASE + 0x34000) -#define CANAF_RAM_BASE (APB0_BASE + 0x38000) -#define CANAF_BASE (APB0_BASE + 0x3C000) -#define CANCR_BASE (APB0_BASE + 0x40000) -#define CAN1_BASE (APB0_BASE + 0x44000) -#define CAN2_BASE (APB0_BASE + 0x48000) -#define I2C1_BASE (APB0_BASE + 0x5C000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) /* APB1 peripherals */ -#define SSP0_BASE (APB1_BASE + 0x08000) -#define DAC_BASE (APB1_BASE + 0x0C000) -#define TIM2_BASE (APB1_BASE + 0x10000) -#define TIM3_BASE (APB1_BASE + 0x14000) -#define UART2_BASE (APB1_BASE + 0x18000) -#define UART3_BASE (APB1_BASE + 0x1C000) -#define I2C2_BASE (APB1_BASE + 0x20000) -#define I2S_BASE (APB1_BASE + 0x28000) -#define RIT_BASE (APB1_BASE + 0x30000) -#define MCPWM_BASE (APB1_BASE + 0x38000) -#define QEI_BASE (APB1_BASE + 0x3C000) -#define SC_BASE (APB1_BASE + 0x7C000) +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) /* AHB peripherals */ -#define EMAC_BASE (AHB_BASE + 0x00000) -#define GPDMA_BASE (AHB_BASE + 0x04000) -#define GPDMACH0_BASE (AHB_BASE + 0x04100) -#define GPDMACH1_BASE (AHB_BASE + 0x04120) -#define GPDMACH2_BASE (AHB_BASE + 0x04140) -#define GPDMACH3_BASE (AHB_BASE + 0x04160) -#define GPDMACH4_BASE (AHB_BASE + 0x04180) -#define GPDMACH5_BASE (AHB_BASE + 0x041A0) -#define GPDMACH6_BASE (AHB_BASE + 0x041C0) -#define GPDMACH7_BASE (AHB_BASE + 0x041E0) -#define USB_BASE (AHB_BASE + 0x0C000) +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) /* GPIOs */ -#define GPIO0_BASE (GPIO_BASE + 0x00000) -#define GPIO1_BASE (GPIO_BASE + 0x00020) -#define GPIO2_BASE (GPIO_BASE + 0x00040) -#define GPIO3_BASE (GPIO_BASE + 0x00060) -#define GPIO4_BASE (GPIO_BASE + 0x00080) +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) /******************************************************************************/ /* Peripheral declaration */ /******************************************************************************/ -#define SC (( SC_TypeDef *) SC_BASE) -#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE) -#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE) -#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE) -#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE) -#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE) -#define WDT (( WDT_TypeDef *) WDT_BASE) -#define TIM0 (( TIM_TypeDef *) TIM0_BASE) -#define TIM1 (( TIM_TypeDef *) TIM1_BASE) -#define TIM2 (( TIM_TypeDef *) TIM2_BASE) -#define TIM3 (( TIM_TypeDef *) TIM3_BASE) -#define RIT (( RIT_TypeDef *) RIT_BASE) -#define UART0 (( UART_TypeDef *) UART0_BASE) -#define UART1 (( UART1_TypeDef *) UART1_BASE) -#define UART2 (( UART_TypeDef *) UART2_BASE) -#define UART3 (( UART_TypeDef *) UART3_BASE) -#define PWM1 (( PWM_TypeDef *) PWM1_BASE) -#define I2C0 (( I2C_TypeDef *) I2C0_BASE) -#define I2C1 (( I2C_TypeDef *) I2C1_BASE) -#define I2C2 (( I2C_TypeDef *) I2C2_BASE) -#define I2S (( I2S_TypeDef *) I2S_BASE) -#define SPI (( SPI_TypeDef *) SPI_BASE) -#define RTC (( RTC_TypeDef *) RTC_BASE) -#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE) -#define PINCON (( PINCON_TypeDef *) PINCON_BASE) -#define SSP0 (( SSP_TypeDef *) SSP0_BASE) -#define SSP1 (( SSP_TypeDef *) SSP1_BASE) -#define ADC (( ADC_TypeDef *) ADC_BASE) -#define DAC (( DAC_TypeDef *) DAC_BASE) -#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE) -#define CANAF (( CANAF_TypeDef *) CANAF_BASE) -#define CANCR (( CANCR_TypeDef *) CANCR_BASE) -#define CAN1 (( CAN_TypeDef *) CAN1_BASE) -#define CAN2 (( CAN_TypeDef *) CAN2_BASE) -#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE) -#define QEI (( QEI_TypeDef *) QEI_BASE) -#define EMAC (( EMAC_TypeDef *) EMAC_BASE) -#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE) -#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE) -#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE) -#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE) -#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE) -#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE) -#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE) -#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE) -#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE) -#define USB (( USB_TypeDef *) USB_BASE) +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) #endif // __LPC17xx_H__ - - -#endif diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/core_cm3.h b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/core_cm3.h index b6f9696bf..2b6b51a7d 100644 --- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/core_cm3.h +++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/core_cm3.h @@ -1,16 +1,18 @@ -/****************************************************************************** - * @file: core_cm3.h - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version: V1.20 - * @date: 22. May 2009 - *---------------------------------------------------------------------------- +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 * + * @note * Copyright (C) 2009 ARM Limited. All rights reserved. * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * + * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. @@ -22,53 +24,38 @@ #ifndef __CM3_CORE_H__ #define __CM3_CORE_H__ -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -/** - * Lint configuration \n - * ----------------------- \n - * - * The following Lint messages will be suppressed and not shown: \n - * \n - * --- Error 10: --- \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' \n - * \n - * --- Error 530: --- \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n - * \n - * --- Error 550: --- \n - * __regBasePri = (basePri & 0x1ff); \n - * } \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n - * \n - * --- Error 754: --- \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n - * \n - * --- Error 750: --- \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n - * \n - * --- Error 528: --- \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n - * \n - * --- Error 751: --- \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n - * \n - * \n - * Note: To re-enable a Message, insert a space before 'lint' * \n +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * * */ @@ -82,6 +69,24 @@ /*lint -e751 */ +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + #include /* Include standard types */ #if defined (__ICCARM__) @@ -103,9 +108,9 @@ */ #ifdef __cplusplus -#define __I volatile /*!< defines 'read only' permissions */ + #define __I volatile /*!< defines 'read only' permissions */ #else -#define __I volatile const /*!< defines 'read only' permissions */ + #define __I volatile const /*!< defines 'read only' permissions */ #endif #define __O volatile /*!< defines 'write only' permissions */ #define __IO volatile /*!< defines 'read / write' permissions */ @@ -115,188 +120,630 @@ /******************************************************************************* * Register Abstraction ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ -/* System Reset */ -#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ -#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ -#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ -#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; -/* Core Debug */ -#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ -#define ITM_TCR_ITMENA 1 /*!< ITM enable */ +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ -/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Software Trigger Interrupt Register */ -} NVIC_Type; - - -/* memory mapping struct for System Control Block */ -typedef struct -{ - __I uint32_t CPUID; /*!< CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< System Control Register */ - __IO uint32_t CCR; /*!< Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Processor Feature Register */ - __I uint32_t DFR; /*!< Debug Feature Register */ - __I uint32_t ADR; /*!< Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< ISA Feature Register */ -} SCB_Type; - - -/* memory mapping struct for SysTick */ +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ typedef struct { - __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< SysTick Current Value Register */ - __I uint32_t CALIB; /*!< SysTick Calibration Register */ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ } SysTick_Type; +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -/* memory mapping structur for ITM */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ typedef struct { __O union { - __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< ITM Integration Write Register */ - __IO uint32_t IRR; /*!< ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< ITM Lock Access Register */ - __IO uint32_t LSR; /*!< ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< ITM Product ID Registers */ - __I uint32_t PID5; - __I uint32_t PID6; - __I uint32_t PID7; - __I uint32_t PID0; - __I uint32_t PID1; - __I uint32_t PID2; - __I uint32_t PID3; - __I uint32_t CID0; - __I uint32_t CID1; - __I uint32_t CID2; - __I uint32_t CID3; -} ITM_Type; - - -/* memory mapped struct for Interrupt Type */ + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ typedef struct { uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Interrupt Control Type Register */ + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Auxiliary Control Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ #else uint32_t RESERVED1; #endif } InterruptType_Type; +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + -/* Memory Protection Unit */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ typedef struct { - __I uint32_t TYPE; /*!< MPU Type Register */ - __IO uint32_t CTRL; /*!< MPU Control Register */ - __IO uint32_t RNR; /*!< MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ #endif -/* Core Debug Register */ +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ typedef struct { - __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ } CoreDebug_Type; +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + /* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ #endif +/*@}*/ /* end of group CMSIS_CM3_core_register */ /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ - #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined ( __GNUC__ ) @@ -304,8 +751,8 @@ typedef struct #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif @@ -344,8 +791,7 @@ typedef struct /** * @brief Return the Process Stack Pointer * - * @param none - * @return uint32_t ProcessStackPointer + * @return ProcessStackPointer * * Return the actual process stack pointer */ @@ -354,8 +800,7 @@ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * - * @param uint32_t Process Stack Pointer - * @return none + * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register @@ -365,8 +810,7 @@ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * - * @param none - * @return uint32_t Main Stack Pointer + * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register @@ -376,8 +820,7 @@ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * - * @param uint32_t Main Stack Pointer - * @return none + * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register @@ -387,18 +830,18 @@ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Reverse byte order in unsigned short value * - * @param uint16_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); -/* +/** * @brief Reverse byte order in signed short value with sign extension to integer * - * @param int16_t value to reverse - * @return int32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ @@ -410,9 +853,6 @@ extern int32_t __REVSH(int16_t value); /** * @brief Remove the exclusive lock created by ldrex * - * @param none - * @return none - * * Removes the exclusive lock which is created by ldrex. */ extern void __CLREX(void); @@ -420,8 +860,7 @@ extern void __CLREX(void); /** * @brief Return the Base Priority value * - * @param none - * @return uint32_t BasePriority + * @return BasePriority * * Return the content of the base priority register */ @@ -430,8 +869,7 @@ extern uint32_t __get_BASEPRI(void); /** * @brief Set the Base Priority value * - * @param uint32_t BasePriority - * @return none + * @param basePri BasePriority * * Set the base priority register */ @@ -440,19 +878,16 @@ extern void __set_BASEPRI(uint32_t basePri); /** * @brief Return the Priority Mask value * - * @param none - * @return uint32_t PriMask + * @return PriMask * - * Return the state of the priority mask bit from the priority mask - * register + * Return state of the priority mask bit from the priority mask register */ extern uint32_t __get_PRIMASK(void); /** * @brief Set the Priority Mask value * - * @param uint32_t PriMask - * @return none + * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ @@ -461,8 +896,7 @@ extern void __set_PRIMASK(uint32_t priMask); /** * @brief Return the Fault Mask value * - * @param none - * @return uint32_t FaultMask + * @return FaultMask * * Return the content of the fault mask register */ @@ -471,8 +905,7 @@ extern uint32_t __get_FAULTMASK(void); /** * @brief Set the Fault Mask value * - * @param uint32_t faultMask value - * @return none + * @param faultMask faultMask value * * Set the fault mask register */ @@ -481,8 +914,7 @@ extern void __set_FAULTMASK(uint32_t faultMask); /** * @brief Return the Control Register value * - * @param none - * @return uint32_t Control value + * @return Control value * * Return the content of the control register */ @@ -491,8 +923,7 @@ extern uint32_t __get_CONTROL(void); /** * @brief Set the Control Register value * - * @param uint32_t Control value - * @return none + * @param control Control value * * Set the control register */ @@ -500,13 +931,9 @@ extern void __set_CONTROL(uint32_t control); #else /* (__ARMCC_VERSION >= 400000) */ - /** * @brief Remove the exclusive lock created by ldrex * - * @param none - * @return none - * * Removes the exclusive lock which is created by ldrex. */ #define __CLREX __clrex @@ -514,8 +941,7 @@ extern void __set_CONTROL(uint32_t control); /** * @brief Return the Base Priority value * - * @param none - * @return uint32_t BasePriority + * @return BasePriority * * Return the content of the base priority register */ @@ -528,25 +954,22 @@ static __INLINE uint32_t __get_BASEPRI(void) /** * @brief Set the Base Priority value * - * @param uint32_t BasePriority - * @return none + * @param basePri BasePriority * * Set the base priority register */ static __INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0x1ff); + __regBasePri = (basePri & 0xff); } /** * @brief Return the Priority Mask value * - * @param none - * @return uint32_t PriMask + * @return PriMask * - * Return the state of the priority mask bit from the priority mask - * register + * Return state of the priority mask bit from the priority mask register */ static __INLINE uint32_t __get_PRIMASK(void) { @@ -557,8 +980,7 @@ static __INLINE uint32_t __get_PRIMASK(void) /** * @brief Set the Priority Mask value * - * @param uint32_t PriMask - * @return none + * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ @@ -571,8 +993,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask) /** * @brief Return the Fault Mask value * - * @param none - * @return uint32_t FaultMask + * @return FaultMask * * Return the content of the fault mask register */ @@ -585,8 +1006,7 @@ static __INLINE uint32_t __get_FAULTMASK(void) /** * @brief Set the Fault Mask value * - * @param uint32_t faultMask value - * @return none + * @param faultMask faultMask value * * Set the fault mask register */ @@ -599,8 +1019,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask) /** * @brief Return the Control Register value * - * @param none - * @return uint32_t Control value + * @return Control value * * Return the content of the control register */ @@ -613,8 +1032,7 @@ static __INLINE uint32_t __get_CONTROL(void) /** * @brief Set the Control Register value * - * @param uint32_t Control value - * @return none + * @param control Control value * * Set the control register */ @@ -637,7 +1055,7 @@ static __INLINE void __set_CONTROL(uint32_t control) static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } -#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ static __INLINE void __WFI() { __ASM ("wfi"); } static __INLINE void __WFE() { __ASM ("wfe"); } static __INLINE void __SEV() { __ASM ("sev"); } @@ -659,8 +1077,7 @@ static __INLINE void __CLREX() { __ASM ("clrex"); } /** * @brief Return the Process Stack Pointer * - * @param none - * @return uint32_t ProcessStackPointer + * @return ProcessStackPointer * * Return the actual process stack pointer */ @@ -669,8 +1086,7 @@ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * - * @param uint32_t Process Stack Pointer - * @return none + * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register @@ -680,8 +1096,7 @@ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * - * @param none - * @return uint32_t Main Stack Pointer + * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register @@ -691,8 +1106,7 @@ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * - * @param uint32_t Main Stack Pointer - * @return none + * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register @@ -702,8 +1116,8 @@ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Reverse byte order in unsigned short value * - * @param uint16_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in unsigned short value */ @@ -712,73 +1126,73 @@ extern uint32_t __REV16(uint16_t value); /** * @brief Reverse bit order of value * - * @param uint32_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse bit order of value */ extern uint32_t __RBIT(uint32_t value); /** - * @brief LDR Exclusive + * @brief LDR Exclusive (8 bit) * - * @param uint8_t* address - * @return uint8_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 8 bit values) */ extern uint8_t __LDREXB(uint8_t *addr); /** - * @brief LDR Exclusive + * @brief LDR Exclusive (16 bit) * - * @param uint16_t* address - * @return uint16_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 16 bit values */ extern uint16_t __LDREXH(uint16_t *addr); /** - * @brief LDR Exclusive + * @brief LDR Exclusive (32 bit) * - * @param uint32_t* address - * @return uint32_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 32 bit values */ extern uint32_t __LDREXW(uint32_t *addr); /** - * @brief STR Exclusive + * @brief STR Exclusive (8 bit) * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 8 bit values */ extern uint32_t __STREXB(uint8_t value, uint8_t *addr); /** - * @brief STR Exclusive + * @brief STR Exclusive (16 bit) * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 16 bit values */ extern uint32_t __STREXH(uint16_t value, uint16_t *addr); /** - * @brief STR Exclusive + * @brief STR Exclusive (32 bit) * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 32 bit values */ extern uint32_t __STREXW(uint32_t value, uint32_t *addr); @@ -806,8 +1220,7 @@ static __INLINE void __CLREX() { __ASM volatile ("clrex"); } /** * @brief Return the Process Stack Pointer * - * @param none - * @return uint32_t ProcessStackPointer + * @return ProcessStackPointer * * Return the actual process stack pointer */ @@ -816,8 +1229,7 @@ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * - * @param uint32_t Process Stack Pointer - * @return none + * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register @@ -827,8 +1239,7 @@ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * - * @param none - * @return uint32_t Main Stack Pointer + * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register @@ -838,8 +1249,7 @@ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * - * @param uint32_t Main Stack Pointer - * @return none + * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register @@ -849,8 +1259,7 @@ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Return the Base Priority value * - * @param none - * @return uint32_t BasePriority + * @return BasePriority * * Return the content of the base priority register */ @@ -859,8 +1268,7 @@ extern uint32_t __get_BASEPRI(void); /** * @brief Set the Base Priority value * - * @param uint32_t BasePriority - * @return none + * @param basePri BasePriority * * Set the base priority register */ @@ -869,19 +1277,16 @@ extern void __set_BASEPRI(uint32_t basePri); /** * @brief Return the Priority Mask value * - * @param none - * @return uint32_t PriMask + * @return PriMask * - * Return the state of the priority mask bit from the priority mask - * register + * Return state of the priority mask bit from the priority mask register */ extern uint32_t __get_PRIMASK(void); /** * @brief Set the Priority Mask value * - * @param uint32_t PriMask - * @return none + * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ @@ -890,8 +1295,7 @@ extern void __set_PRIMASK(uint32_t priMask); /** * @brief Return the Fault Mask value * - * @param none - * @return uint32_t FaultMask + * @return FaultMask * * Return the content of the fault mask register */ @@ -900,8 +1304,7 @@ extern uint32_t __get_FAULTMASK(void); /** * @brief Set the Fault Mask value * - * @param uint32_t faultMask value - * @return none + * @param faultMask faultMask value * * Set the fault mask register */ @@ -910,8 +1313,7 @@ extern void __set_FAULTMASK(uint32_t faultMask); /** * @brief Return the Control Register value * -* @param none -* @return uint32_t Control value +* @return Control value * * Return the content of the control register */ @@ -920,8 +1322,7 @@ extern uint32_t __get_CONTROL(void); /** * @brief Set the Control Register value * - * @param uint32_t Control value - * @return none + * @param control Control value * * Set the control register */ @@ -930,8 +1331,8 @@ extern void __set_CONTROL(uint32_t control); /** * @brief Reverse byte order in integer value * - * @param uint32_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in integer value */ @@ -940,93 +1341,93 @@ extern uint32_t __REV(uint32_t value); /** * @brief Reverse byte order in unsigned short value * - * @param uint16_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); -/* - * Reverse byte order in signed short value with sign extension to integer +/** + * @brief Reverse byte order in signed short value with sign extension to integer * - * @param int16_t value to reverse - * @return int32_t reversed value + * @param value value to reverse + * @return reversed value * - * @brief Reverse byte order in signed short value with sign extension to integer + * Reverse byte order in signed short value with sign extension to integer */ extern int32_t __REVSH(int16_t value); /** * @brief Reverse bit order of value * - * @param uint32_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse bit order of value */ extern uint32_t __RBIT(uint32_t value); /** - * @brief LDR Exclusive + * @brief LDR Exclusive (8 bit) * - * @param uint8_t* address - * @return uint8_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 8 bit value */ extern uint8_t __LDREXB(uint8_t *addr); /** - * @brief LDR Exclusive + * @brief LDR Exclusive (16 bit) * - * @param uint16_t* address - * @return uint16_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 16 bit values */ extern uint16_t __LDREXH(uint16_t *addr); /** - * @brief LDR Exclusive + * @brief LDR Exclusive (32 bit) * - * @param uint32_t* address - * @return uint32_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 32 bit values */ extern uint32_t __LDREXW(uint32_t *addr); /** - * @brief STR Exclusive + * @brief STR Exclusive (8 bit) * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 8 bit values */ extern uint32_t __STREXB(uint8_t value, uint8_t *addr); /** - * @brief STR Exclusive + * @brief STR Exclusive (16 bit) * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 16 bit values */ extern uint32_t __STREXH(uint16_t value, uint16_t *addr); /** - * @brief STR Exclusive + * @brief STR Exclusive (32 bit) * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 32 bit values */ extern uint32_t __STREXW(uint32_t value, uint32_t *addr); @@ -1043,15 +1444,20 @@ extern uint32_t __STREXW(uint32_t value, uint32_t *addr); #endif +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ /* ########################## NVIC functions #################################### */ - /** * @brief Set the Priority Grouping in NVIC Interrupt Controller * - * @param uint32_t priority_grouping is priority grouping field - * @return none + * @param PriorityGroup is priority grouping field * * Set the priority grouping field using the required unlock sequence. * The parameter priority_grouping is assigned to the field @@ -1064,31 +1470,31 @@ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ - reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; } /** * @brief Get the Priority Grouping from NVIC Interrupt Controller * - * @param none - * @return uint32_t priority grouping field + * @return priority grouping field * * Get the priority grouping from NVIC Interrupt Controller. * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. */ static __INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } /** * @brief Enable Interrupt in NVIC Interrupt Controller * - * @param IRQn_Type IRQn specifies the interrupt number - * @return none + * @param IRQn The positive number of the external interrupt to enable * * Enable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. @@ -1101,8 +1507,7 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) /** * @brief Disable the interrupt line for external interrupt specified * - * @param IRQn_Type IRQn is the positive number of the external interrupt - * @return none + * @param IRQn The positive number of the external interrupt to disable * * Disable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. @@ -1115,8 +1520,8 @@ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) /** * @brief Read the interrupt pending bit for a device specific interrupt source * - * @param IRQn_Type IRQn is the number of the device specifc interrupt - * @return uint32_t 1 if pending interrupt else 0 + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending * * Read the pending register in NVIC and return 1 if its status is pending, * otherwise it returns 0 @@ -1129,8 +1534,7 @@ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) /** * @brief Set the pending bit for an external interrupt * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none + * @param IRQn The number of the interrupt for set pending * * Set the pending bit for the specified interrupt. * The interrupt number cannot be a negative value. @@ -1143,8 +1547,7 @@ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) /** * @brief Clear the pending bit for an external interrupt * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none + * @param IRQn The number of the interrupt for clear pending * * Clear the pending bit for the specified interrupt. * The interrupt number cannot be a negative value. @@ -1157,8 +1560,8 @@ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** * @brief Read the active bit for an external interrupt * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return uint32_t 1 if active else 0 + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active * * Read the active register in NVIC and returns 1 if its status is active, * otherwise it returns 0. @@ -1171,13 +1574,12 @@ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) /** * @brief Set the priority for an interrupt * - * @param IRQn_Type IRQn is the Number of the interrupt - * @param priority is the priority for the interrupt - * @return none + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set * * Set the priority for the specified interrupt. The interrupt * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. \n + * interrupt, or negative to specify an internal (core) interrupt. * * Note: The priority cannot be set for every core interrupt. */ @@ -1186,14 +1588,14 @@ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } /** * @brief Read the priority for an interrupt * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return uint32_t priority is the priority for the interrupt + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt * * Read the priority for the specified interrupt. The interrupt * number can be positive to specify an external (device specific) @@ -1217,10 +1619,10 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) /** * @brief Encode the priority for an interrupt * - * @param uint32_t PriorityGroup is the used priority group - * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0) - * @param uint32_t SubPriority is the sub priority value (starting from 0) - * @return uint32_t the priority for the interrupt + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt * * Encode the priority for an interrupt with the given priority group, * preemptive priority value and sub priority value. @@ -1231,7 +1633,7 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) */ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; @@ -1248,11 +1650,10 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P /** * @brief Decode the priority of an interrupt * - * @param uint32_t Priority the priority for the interrupt - * @param uint32_t PrioGroup is the used priority group - * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0) - * @param uint32_t* pSubPrio is the sub priority value (starting from 0) - * @return none + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) * * Decode an interrupt priority value with the given priority group to * preemptive priority value and sub priority value. @@ -1263,7 +1664,7 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P */ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; @@ -1280,17 +1681,11 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) -/* SysTick constants */ -#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ -#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ -#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ -#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ - /** * @brief Initialize and start the SysTick counter and its interrupt. * - * @param uint32_t ticks is the number of ticks between two interrupts - * @return none + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful * * Initialise the system tick timer and its interrupt and start the * system tick timer / counter in free running mode to generate @@ -1298,13 +1693,15 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { - if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ - SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1< SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ } #endif @@ -1312,33 +1709,45 @@ static __INLINE uint32_t SysTick_Config(uint32_t ticks) - /* ################################## Reset function ############################################ */ /** * @brief Initiate a system reset request. * - * @param none - * @return none - * - * Initialize a system reset request to reset the MCU + * Initiate a system reset request to reset the MCU */ static __INLINE void NVIC_SystemReset(void) { - SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ } +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ -/* ################################## Debug Output function ############################################ */ +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ /** * @brief Outputs a character via the ITM channel 0 * - * @param uint32_t character to output - * @return uint32_t input character + * @param ch character to output + * @return character to output * * The function outputs a character via the ITM channel 0. * The function returns when no debugger is connected that has booked the output. @@ -1346,11 +1755,9 @@ static __INLINE void NVIC_SystemReset(void) */ static __INLINE uint32_t ITM_SendChar (uint32_t ch) { - if (ch == '\n') ITM_SendChar('\r'); - - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && - (ITM->TCR & ITM_TCR_ITMENA) && - (ITM->TER & (1UL << 0)) ) + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; @@ -1358,10 +1765,54 @@ static __INLINE uint32_t ITM_SendChar (uint32_t ch) return (ch); } + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + #ifdef __cplusplus } #endif +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + #endif /* __CM3_CORE_H__ */ /*lint -restore */ diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/cr_startup_lpc17.c b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/cr_startup_lpc17.c index 5b923637d..92a2af743 100644 --- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/cr_startup_lpc17.c +++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/cr_startup_lpc17.c @@ -5,7 +5,7 @@ // | | // +-+--+ | // | +--+--+ -// +----+ Copyright (c) 2009 Code Red Technologies Ltd. +// +----+ Copyright (c) 2009-10 Code Red Technologies Ltd. // // Microcontroller Startup code for use with Red Suite // @@ -25,22 +25,53 @@ // CODE RED TECHNOLOGIES LTD. // //***************************************************************************** +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + #define WEAK __attribute__ ((weak)) #define ALIAS(f) __attribute__ ((weak, alias (#f))) +// Code Red - if CMSIS is being used, then SystemInit() routine +// will be called by startup code rather than in application's main() +#if defined (__USE_CMSIS) +#include "system_LPC17xx.h" +#endif + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + //***************************************************************************** // -// Forward declaration of the default handlers. +// Forward declaration of the default handlers. These are aliased. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions // //***************************************************************************** -void Reset_Handler(void); -void ResetISR(void) ALIAS(Reset_Handler); -static void NMI_Handler(void); -static void HardFault_Handler(void); -static void MemManage_Handler(void); -static void BusFault_Handler(void); -static void UsageFault_Handler(void); -static void DebugMon_Handler(void); + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SVCall_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); //***************************************************************************** // @@ -83,48 +114,49 @@ void RIT_IRQHandler(void) ALIAS(IntDefaultHandler); void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler); void QEI_IRQHandler(void) ALIAS(IntDefaultHandler); void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler); +void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler); +void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler); extern void xPortSysTickHandler(void); extern void xPortPendSVHandler(void); extern void vPortSVCHandler( void ); extern void vEMAC_ISR( void ); - -//***************************************************************************** -// -// The entry point for the C++ library startup -// -//***************************************************************************** -extern WEAK void __libc_init_array(void); - //***************************************************************************** // // The entry point for the application. -// __main() is the entry point for redlib based applications -// main() is the entry point for newlib based applications +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications // //***************************************************************************** -extern WEAK void __main(void); -extern WEAK void main(void); +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); //***************************************************************************** // // External declaration for the pointer to the stack top from the Linker Script // //***************************************************************************** -extern void _vStackTop; +extern void _vStackTop(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif //***************************************************************************** // // The vector table. // This relies on the linker script to place at correct location in memory. // //***************************************************************************** +extern void (* const g_pfnVectors[])(void); __attribute__ ((section(".isr_vector"))) void (* const g_pfnVectors[])(void) = { // Core Level - CM3 (void *)&_vStackTop, // The initial stack pointer - Reset_Handler, // The reset handler + ResetISR, // The reset handler NMI_Handler, // The NMI handler HardFault_Handler, // The hard fault handler MemManage_Handler, // The MPU fault handler @@ -174,6 +206,8 @@ void (* const g_pfnVectors[])(void) = MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL) + USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup + CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup }; //***************************************************************************** @@ -196,7 +230,7 @@ extern unsigned long _ebss; // //***************************************************************************** void Reset_Handler(void) -{ +ResetISR(void) { unsigned long *pulSrc, *pulDest; // @@ -222,21 +256,23 @@ void Reset_Handler(void) " strlt r2, [r0], #4\n" " blt zero_loop"); - // - // Call C++ library initilisation, if present - // - if (__libc_init_array) - __libc_init_array() ; +#ifdef __USE_CMSIS + SystemInit(); +#endif +#if defined (__cplusplus) // - // Call the application's entry point. - // __main() is the entry point for redlib based applications (which calls main()) - // main() is the entry point for newlib based applications + // Call C++ library initialisation // - if (__main) - __main() ; - else - main() ; + __libc_init_array(); +#endif + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main() ; +#else + main(); +#endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop @@ -253,42 +289,43 @@ void Reset_Handler(void) // by a debugger. // //***************************************************************************** -static void NMI_Handler(void) +void NMI_Handler(void) { while(1) { } } -static void HardFault_Handler(void) +void HardFault_Handler(void) { while(1) { } } -static void MemManage_Handler(void) +void MemManage_Handler(void) { while(1) { } } -static void BusFault_Handler(void) +void BusFault_Handler(void) { while(1) { } } -static void UsageFault_Handler(void) +void UsageFault_Handler(void) { while(1) { } } -static void DebugMon_Handler(void) + +void DebugMon_Handler(void) { while(1) { @@ -301,7 +338,7 @@ static void DebugMon_Handler(void) // is not present in the application code. // //***************************************************************************** -static void IntDefaultHandler(void) +void IntDefaultHandler(void) { // // Go into an infinite loop. diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/system_LPC17xx.h b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/system_LPC17xx.h index a5c9727d4..e58767e9c 100644 --- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/system_LPC17xx.h +++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/system_LPC17xx.h @@ -1,17 +1,19 @@ -/****************************************************************************** - * @file: system_LPC17xx.h - * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC17xx Device Series - * @version: V1.0 - * @date: 25. Nov. 2008 - *---------------------------------------------------------------------------- +/**************************************************************************//** + * @file system_LPC17xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC17xx Device Series + * @version V1.02 + * @date 08. September 2009 * - * Copyright (C) 2008 ARM Limited. All rights reserved. + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. * - * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * + * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. @@ -24,7 +26,13 @@ #ifndef __SYSTEM_LPC17xx_H #define __SYSTEM_LPC17xx_H -extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */ +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** @@ -34,7 +42,23 @@ extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */ * @return none * * @brief Setup the microcontroller system. - * Initialize the System and update the SystemFrequency variable. + * Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} #endif + +#endif /* __SYSTEM_LPC17xx_H */