From: Jens Gehrlein <jens.gehrlein@tqs.de>
Date: Wed, 26 Sep 2007 15:55:54 +0000 (+0200)
Subject: TQM885D: Exchanged SDRAM timing by a more relaxed timing.
X-Git-Tag: v1.3.2-rc1~105^2~3
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=22d1a56cbfb0bff34f477b4db6a55d076d829b83;p=u-boot

TQM885D: Exchanged SDRAM timing by a more relaxed timing.

CAS-Latency=2, Write Recovery Time tWR=2
The max. supported bus frequency is 66 MHz. Therefore, changed
threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.

Signed-off-by: Martin Krause <martin.krause@tqs.de>
---

diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index cebdcc0764..06bf5f8ee2 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFFFFF
 
+/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
 const uint sdram_table[] =
 {
 	/*
@@ -63,14 +64,14 @@ const uint sdram_table[] =
 	/*
 	 * Single Write. (Offset 18 in UPMA RAM)
 	 */
-	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
+	0x1FF5FC47, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	/*
 	 * Burst Write. (Offset 20 in UPMA RAM)
 	 */
 	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
-	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
-					    _NOT_USED_,
+	0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	/*
@@ -83,7 +84,7 @@ const uint sdram_table[] =
 	/*
 	 * Exception. (Offset 3c in UPMA RAM)
 	 */
-	0x7FFFFC07, /* last */
+	0xFFFFFC07, /* last */
 		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
 };
 
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 101d5f9cb3..11b089330b 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -259,11 +259,8 @@ int get_clocks_866 (void)
 	 */
 	sccr_reg = immr->im_clkrst.car_sccr;
 	sccr_reg &= ~SCCR_EBDF11;
-#if defined(CONFIG_TQM885D)
-	if (gd->cpu_clk <= 80000000) {
-#else
+
 	if (gd->cpu_clk <= 66000000) {
-#endif
 		sccr_reg |= SCCR_EBDF00;	/* bus division factor = 1 */
 		gd->bus_clk = gd->cpu_clk;
 	} else {
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index dd26d54262..e0c69652bb 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -42,7 +42,7 @@
 #define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
 #define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
 #define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
-#define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  50 MHz - CPU default clock	*/
+#define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  66 MHz - CPU default clock	*/
 						/* (it will be used if there is no	*/
 						/* 'cpuclk' variable with valid value)	*/