From: Akshay Saraswat <akshay.s@samsung.com>
Date: Fri, 22 Mar 2013 02:26:36 +0000 (+0000)
Subject: Exynos5: clock: Update the equation to calculate PLL output frequency
X-Git-Tag: v2013.07-rc2~60^2~10^2~17
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=234370cab4b2f096e095fe8f3284fd39740a4023;p=u-boot

Exynos5: clock: Update the equation to calculate PLL output frequency

According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
---

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 223660aab6..1203adaad9 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -116,10 +116,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
 		fout = (m + k / 1024) * (freq / (p * (1 << s)));
 	} else {
-		if (s < 1)
-			s = 1;
-		/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-		fout = m * (freq / (p * (1 << (s - 1))));
+		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+		fout = m * (freq / (p * (1 << s)));
 	}
 
 	return fout;