From: Paul Fertser <fercerpav@gmail.com>
Date: Fri, 2 Dec 2016 17:15:46 +0000 (+0300)
Subject: target: arm: disassembler: decode v6T2 ARM ISB instruction
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2420aa00a458c6847faca2d6b7f9d99718d693f2;p=openocd

target: arm: disassembler: decode v6T2 ARM ISB instruction

Change-Id: Iaaa54aee6a74f0b250b83c53e7a3fb7c17718920
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3895
Tested-by: jenkins
---

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 15366793..f432f57c 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -170,6 +170,18 @@ static int evaluate_pld(uint32_t opcode,
 
 		return ERROR_OK;
 	}
+	/* ISB */
+	if ((opcode & 0x07f000f0) == 0x05700060) {
+		instruction->type = ARM_ISB;
+
+		snprintf(instruction->text,
+				128,
+				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB %s",
+				address, opcode,
+				((opcode & 0x0000000f) == 0xf) ? "SY" : "UNK");
+
+		return ERROR_OK;
+	}
 	return evaluate_unknown(opcode, address, instruction);
 }
 
diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index b73f24a8..e9f4d44c 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -107,6 +107,7 @@ enum arm_instruction_type {
 	ARM_MRRC,
 	ARM_PLD,
 	ARM_DSB,
+	ARM_ISB,
 	ARM_QADD,
 	ARM_QDADD,
 	ARM_QSUB,