From: Anton Staaf <robotboy@chromium.org>
Date: Mon, 17 Oct 2011 23:46:07 +0000 (-0700)
Subject: sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
X-Git-Tag: v2011.12-rc1~470
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2482e3c836a9342a6aa1a9885331aa60dbd1f8f8;p=u-boot

sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
index 2cfc0a7944..6ffab4d374 100644
--- a/arch/sh/include/asm/cache.h
+++ b/arch/sh/include/asm/cache.h
@@ -6,6 +6,7 @@
 int cache_control(unsigned int cmd);
 
 #define L1_CACHE_BYTES 32
+
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
@@ -30,6 +31,22 @@ void dcache_invalid_range(u32 start, u32 end)
 			      : "m" (__m(v)));
 	}
 }
+#else
+
+/*
+ * 32-bytes is the largest L1 data cache line size for SH the architecture.  So
+ * it is a safe default for DMA alignment.
+ */
+#define ARCH_DMA_MINALIGN	32
+
 #endif /* CONFIG_SH4 || CONFIG_SH4A */
 
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on SH.
+ */
+#ifndef ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+#endif
+
 #endif	/* __ASM_SH_CACHE_H */