From: Ben Gardiner Date: Wed, 20 Apr 2011 20:25:06 +0000 (-0400) Subject: da850evm: fix NAND WSTROBE and TA timings X-Git-Tag: v2011.06-rc1~66^2~10 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=24a514c44557601de52df3c8bc0ee789bef8714c;p=u-boot da850evm: fix NAND WSTROBE and TA timings The current NAND timings, introduced in commit a3f88293ddd13facd734769c1664d35ab4ed681f da850evm: setup the NAND flash timings , incorrectly set WSTROBE and TA to 0. A more recent inspection of the values set by the Linux kernel indicates that these should be set to 1. Set the WSTROBE and TA field of the EMIFA cycle-count timings configuration to 1 to match the values set by linux. Signed-off-by: Ben Gardiner CC: Stefano Babic CC: Sandeep Paulraj CC: Scott Wood Signed-off-by: Sandeep Paulraj --- diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index b088c9c3e3..73eaa48b0b 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -179,12 +179,12 @@ int board_init(void) * Linux kernel @ 25MHz EMIFA */ writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(0) | + DAVINCI_ABCR_WSTROBE(1) | DAVINCI_ABCR_WHOLD(0) | DAVINCI_ABCR_RSETUP(0) | DAVINCI_ABCR_RSTROBE(1) | DAVINCI_ABCR_RHOLD(0) | - DAVINCI_ABCR_TA(0) | + DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT), &davinci_emif_regs->ab2cr); /* CS3 */ #endif