From: Álvaro Fernández Rojas Date: Sun, 7 May 2017 18:09:31 +0000 (+0200) Subject: mips: bmips: add bcm6345-gpio driver support for BCM6358 X-Git-Tag: v2017.07-rc1~357^2~25 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2507f69c41d8b4f9140e3668f3a4c76a43bb76d1;p=u-boot mips: bmips: add bcm6345-gpio driver support for BCM6358 This SoC has one gpio bank divided into two 32 bit registers, with a total of 40 GPIOs. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 48322fb143..4c94555204 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -73,6 +73,25 @@ mask = <0x1>; }; + gpio1: gpio-controller@fffe0080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + gpio0: gpio-controller@fffe0084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + uart0: serial@fffe0100 { compatible = "brcm,bcm6345-uart"; reg = <0xfffe0100 0x18>;