From: York Sun Date: Sat, 18 Nov 2017 19:09:08 +0000 (-0800) Subject: mtd: cfi: Fix checking status register feature X-Git-Tag: v2018.01-rc1~2^2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2544f47078635958bacb106684a2f81f57a4ed80;p=u-boot mtd: cfi: Fix checking status register feature Commit 72443c7f7d21 ("mtd: cfi: Add support for status register polling") added a feature check to determine if status register is available for certain flash chips. The "lower software bits" register used to determine this feature is not backward compati- ble. Older flash chips without this feature has reserved value 0xff. Instead of checking "lower software bits" register, use CFI primary vendor-specific extended query. Since CFI version 1.4, software features can be read from offset 0x53 according to document AN201168 from Cypress. Signed-off-by: York Sun CC: Marek Vasut Tested-by: Marek Vasut Signed-off-by: Stefan Roese --- diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 8a5babea7b..f096e039cb 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1694,7 +1694,7 @@ static void cmdset_amd_read_jedec_ids(flash_info_t *info) { ushort bankId = 0; uchar manuId; - uchar lsbits; + uchar feature; flash_write_cmd(info, 0, 0, AMD_CMD_RESET); flash_unlock_seq(info, 0); @@ -1710,8 +1710,14 @@ static void cmdset_amd_read_jedec_ids(flash_info_t *info) } info->manufacturer_id = manuId; - lsbits = flash_read_uchar(info, FLASH_OFFSET_LOWER_SW_BITS); - info->sr_supported = lsbits & BIT(0); + debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n", + info->ext_addr, info->cfi_version); + if (info->ext_addr && info->cfi_version >= 0x3134) { + /* read software feature (at 0x53) */ + feature = flash_read_uchar(info, info->ext_addr + 0x13); + debug("feature = 0x%x\n", feature); + info->sr_supported = feature & 0x1; + } switch (info->chipwidth){ case FLASH_CFI_8BIT: