From: Hannes Petermaier <oe5hpm@oevsv.at>
Date: Wed, 4 Jun 2014 08:19:26 +0000 (+0200)
Subject: arch-am33xx: Add defines for timer0-7
X-Git-Tag: v2014.07-rc3~4^2^2~9
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=25b0a729aa5f771edb277f2ef9cfd9b737ec0e9e;p=u-boot

arch-am33xx: Add defines for timer0-7

For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.

Also the 'Timer register bits' are expanded.

By the way we add defines for all timers within AM335x SoC.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
---

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index d9f0306b0a..aa10fab4dd 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -26,7 +26,17 @@
 #define TCLR_PRE			BIT(5)	/* Pre-scaler enable */
 #define TCLR_PTV_SHIFT			(2)	/* Pre-scaler shift value */
 #define TCLR_PRE_DISABLE		CL_BIT(5) /* Pre-scalar disable */
-
+#define TCLR_CE				BIT(6)	/* compare mode enable */
+#define TCLR_SCPWM			BIT(7)	/* pwm outpin behaviour */
+#define TCLR_TCM			BIT(8)	/* edge detection of input pin*/
+#define TCLR_TRG_SHIFT			(10)	/* trigmode on pwm outpin */
+#define TCLR_PT				BIT(12)	/* pulse/toggle mode of outpin*/
+#define TCLR_CAPTMODE			BIT(13) /* capture mode */
+#define TCLR_GPOCFG			BIT(14)	/* 0=output,1=input */
+
+#define TCFG_RESET			BIT(0)	/* software reset */
+#define TCFG_EMUFREE			BIT(1)	/* behaviour of tmr on debug */
+#define TCFG_IDLEMOD_SHIFT		(2)	/* power management */
 /* device type */
 #define DEVICE_MASK			(BIT(8) | BIT(9) | BIT(10))
 #define TST_DEVICE			0x0
@@ -87,7 +97,8 @@ struct cm_wkuppll {
 	unsigned int wkctrlclkctrl;	/* offset 0x04 */
 	unsigned int wkgpio0clkctrl;	/* offset 0x08 */
 	unsigned int wkl4wkclkctrl;	/* offset 0x0c */
-	unsigned int resv2[4];
+	unsigned int timer0clkctrl;	/* offset 0x10 */
+	unsigned int resv2[3];
 	unsigned int idlestdpllmpu;	/* offset 0x20 */
 	unsigned int resv3[2];
 	unsigned int clkseldpllmpu;	/* offset 0x2c */
@@ -121,7 +132,9 @@ struct cm_wkuppll {
 	unsigned int wkup_uart0ctrl;	/* offset 0xB4 */
 	unsigned int wkup_i2c0ctrl;	/* offset 0xB8 */
 	unsigned int wkup_adctscctrl;	/* offset 0xBC */
-	unsigned int resv12[6];
+	unsigned int resv12;
+	unsigned int timer1clkctrl;	/* offset 0xC4 */
+	unsigned int resv13[4];
 	unsigned int divm6dpllcore;	/* offset 0xD8 */
 };
 
@@ -178,7 +191,9 @@ struct cm_perpll {
 	unsigned int epwmss2clkctrl;	/* offset 0xD8 */
 	unsigned int l3instrclkctrl;	/* offset 0xDC */
 	unsigned int l3clkctrl;		/* Offset 0xE0 */
-	unsigned int resv8[4];
+	unsigned int resv8[2];
+	unsigned int timer5clkctrl;	/* offset 0xEC */
+	unsigned int timer6clkctrl;	/* offset 0xF0 */
 	unsigned int mmc1clkctrl;	/* offset 0xF4 */
 	unsigned int mmc2clkctrl;	/* offset 0xF8 */
 	unsigned int resv9[8];
@@ -191,9 +206,17 @@ struct cm_perpll {
 
 /* Encapsulating Display pll registers */
 struct cm_dpll {
-	unsigned int resv1[2];
+	unsigned int resv1;
+	unsigned int clktimer7clk;	/* offset 0x04 */
 	unsigned int clktimer2clk;	/* offset 0x08 */
-	unsigned int resv2[10];
+	unsigned int clktimer3clk;	/* offset 0x0C */
+	unsigned int clktimer4clk;	/* offset 0x10 */
+	unsigned int resv2;
+	unsigned int clktimer5clk;	/* offset 0x18 */
+	unsigned int clktimer6clk;	/* offset 0x1C */
+	unsigned int resv3[2];
+	unsigned int clktimer1clk;	/* offset 0x28 */
+	unsigned int resv4[2];
 	unsigned int clklcdcpixelclk;	/* offset 0x34 */
 };
 #else