From: Larry Johnson Date: Tue, 22 Jan 2008 13:51:59 +0000 (-0500) Subject: ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code X-Git-Tag: v1.3.2-rc1~7^2^2^2~1 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=29e3500cbc43c89eff6e720ca83e375deeecd9b3;p=u-boot ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code Signed-off-by: Larry Johnson --- diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 825bc2139c..60f89c97fc 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -3,7 +3,7 @@ * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core * DDR2 controller, specifically the 440EPx/GRx. * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org. * * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... @@ -77,10 +77,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#if defined(CFG_ENABLE_SDRAM_CACHE) +#if defined(CONFIG_4xx_DCACHE) #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */