From: Hans de Goede Date: Sat, 15 Aug 2015 10:32:24 +0000 (+0200) Subject: sunxi_nand_spl: Add proper cache flusing X-Git-Tag: v2015.10-rc3~40^2~18 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2a43973f64bce7dba1a5aabd18f2268f062aa0ef;p=u-boot sunxi_nand_spl: Add proper cache flusing We are using dma, so we should flush the cache before starting the dma, and invalidate it once the dma is done. Things are working without this by mostly luck, but lets not rely on that. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 147d47638f..663c03ec4f 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -266,6 +266,10 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst, writel(oob_offset, SUNXI_NFC_BASE + NFC_SPARE_AREA); } + flush_dcache_range(dst, + ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE, + ARCH_DMA_MINALIGN)); + /* SUNXI_DMA */ writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */ /* read from REG_IO_DATA */ @@ -311,6 +315,10 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst, return; } + invalidate_dcache_range(dst, + ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE, + ARCH_DMA_MINALIGN)); + if (readl(SUNXI_NFC_BASE + NFC_ECC_ST)) (*ecc_errors)++; }