From: Stefan Agner Date: Tue, 2 Aug 2016 06:55:18 +0000 (-0700) Subject: mtd: nand: mxs: fix cache alignment for cache lines >32 X-Git-Tag: v2016.09~7^2~17 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2a83c95fdb9c2f735d1c30c71bc52f6fd8aa0f97;p=u-boot mtd: nand: mxs: fix cache alignment for cache lines >32 Currently the command buffer gets allocated with a size of 32 bytes. This causes warning messages on systems with cache lines bigger than 32 bytes: CACHE: Misaligned operation at range [9df17a00, 9df17a20] Define command buffer to be at least 32 bytes, but more if cache line is bigger. Signed-off-by: Stefan Agner Reviewed-by: Stefano Babic --- diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 94fc5c18a0..4bf564e4f5 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -37,7 +37,12 @@ #endif #define MXS_NAND_METADATA_SIZE 10 #define MXS_NAND_BITS_PER_ECC_LEVEL 13 + +#if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32 #define MXS_NAND_COMMAND_BUFFER_SIZE 32 +#else +#define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE +#endif #define MXS_NAND_BCH_TIMEOUT 10000