From: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Tue, 6 Nov 2018 02:04:28 +0000 (+0000)
Subject: Continue work on Risc V port.
X-Git-Tag: V10.2.0~51
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2b9aa53d9d779c695b240b23a47169c3c3467035;p=freertos

Continue work on Risc V port.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2591 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
index 24611a9be..4f09da8ca 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
@@ -50,6 +50,7 @@ static void prvTaskExitError( void );
 
 /* Used to program the machine timer compare register. */
 static uint64_t ullNextTime = 0ULL;
+static const uint64_t ullTimerIncrementsForOneTick = ( uint64_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
 static volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCTRL_BASE + 0x4000 );
 
 /*-----------------------------------------------------------*/
@@ -165,8 +166,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 void vPortSetupTimerInterrupt( void )
 {
 uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
-volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCTRL_BASE + 0xBFF8 );
-volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCTRL_BASE + 0xBFFc );
+volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCTRL_BASE + 0xBFFC );
+volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCTRL_BASE + 0xBFF8 );
 
 	do
 	{
@@ -177,9 +178,12 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCTR
 	ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
 	ullNextTime <<= 32ULL;
 	ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
-	ullNextTime += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+	ullNextTime += ullTimerIncrementsForOneTick;
 	*pullMachineTimerCompareRegister = ullNextTime;
 
+	/* Prepare the time to use after the next tick interrupt. */
+	ullNextTime += ullTimerIncrementsForOneTick;
+
 	/* Enable timer interrupt */
 	__asm volatile( "csrs mie, %0" :: "r"(0x80) );
 }
@@ -192,8 +196,34 @@ volatile uint32_t * const ulSoftInterrupt = ( uint32_t * ) configCTRL_BASE;
 	vTaskSwitchContext();
 
 	/* Clear software interrupt. */
-	*ulSoftInterrupt = 0UL;
+	*( ( uint32_t * ) configCTRL_BASE ) = 0UL;
+}
+/*-----------------------------------------------------------*/
+
+void Timer_IRQHandler( void )
+{
+	/* Reload for the next timer interrupt. */
+	*pullMachineTimerCompareRegister = ullNextTime;
+	ullNextTime += ullTimerIncrementsForOneTick;
+
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		portYIELD();
+	}
 }
 /*-----------------------------------------------------------*/
 
+BaseType_t xPortStartScheduler( void )
+{
+extern void xPortStartFirstTask( void );
+
+	vPortSetupTimerInterrupt();
+	xPortStartFirstTask();
+
+	/* Should not get here as after calling xPortStartFirstTask() only tasks
+	should be executing. */
+	return pdFAIL;
+}
+
+
 
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
index 5efe94f07..d27391d77 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
@@ -38,7 +38,7 @@
 
 #define CONTEXT_SIZE ( 28 * WORD_SIZE )
 
-.global xPortStartScheduler
+.global xPortStartFirstTask
 .global vPortTrapHandler
 .extern pxCurrentTCB
 .extern handle_trap
@@ -46,7 +46,8 @@
 /*-----------------------------------------------------------*/
 
 .align 8
-xPortStartScheduler:
+xPortStartFirstTask:
+
     lw  sp, pxCurrentTCB            /* Load pxCurrentTCB. */
     lw  sp, 0( sp )                 /* Read sp from first TCB member. */
 
@@ -81,7 +82,7 @@ xPortStartScheduler:
     addi    sp, sp, CONTEXT_SIZE
     csrs    mstatus, 8              /* Enable machine interrupts. */
     csrs    mie, 8                  /* Enable soft interrupt. */
-    ret
+     ret
 
 /*-----------------------------------------------------------*/
 
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
index a256d5b0c..828e810bb 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
@@ -70,7 +70,7 @@ not need to be guarded with a critical section. */
 
 
 /* Scheduler utilities. */
-#define portYIELD() {  volatile uint32_t * const ulSoftInterrupt = ( uint32_t * ) configCTRL_BASE;	*ulSoftInterrupt = 1UL; }
+#define portYIELD() *( ( uint32_t * ) configCTRL_BASE ) = 1UL
 #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYield()
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
@@ -80,13 +80,15 @@ not need to be guarded with a critical section. */
 #define portCRITICAL_NESTING_IN_TCB					1
 extern int vPortSetInterruptMask( void );
 extern void vPortClearInterruptMask( int );
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
 
 #define portSET_INTERRUPT_MASK_FROM_ISR() 0
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )
-#define portDISABLE_INTERRUPTS()
-#define portENABLE_INTERRUPTS()
-#define portENTER_CRITICAL()
-#define portEXIT_CRITICAL()
+#define portDISABLE_INTERRUPTS()	__asm volatile( "csrc mstatus, 8" )
+#define portENABLE_INTERRUPTS()		__asm volatile( "csrs mstatus, 8" )
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
 
 /*-----------------------------------------------------------*/