From: York Sun <yorksun@freescale.com>
Date: Wed, 24 Aug 2011 16:40:25 +0000 (-0700)
Subject: powerpc/mpc8xxx: Extend CWL table
X-Git-Tag: v2011.12-rc1~600^2~29
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2bba85f41246d2bc1db00f2b0cce831b5efd4dfe;p=u-boot

powerpc/mpc8xxx: Extend CWL table

Extend CAS write Latency (CWL) table to comply with DDR3 spec

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3824aade89..6aee14a609 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -94,6 +94,10 @@ static inline int fsl_ddr_get_rtt(void)
  *       6 if 2.5ns > tCK >= 1.875ns
  *       7 if 1.875ns > tCK >= 1.5ns
  *       8 if 1.5ns > tCK >= 1.25ns
+ *       9 if 1.25ns > tCK >= 1.07ns
+ *       10 if 1.07ns > tCK >= 0.935ns
+ *       11 if 0.935ns > tCK >= 0.833ns
+ *       12 if 0.833ns > tCK >= 0.75ns
  */
 static inline unsigned int compute_cas_write_latency(void)
 {
@@ -108,8 +112,18 @@ static inline unsigned int compute_cas_write_latency(void)
 		cwl = 7;
 	else if (mclk_ps >= 1250)
 		cwl = 8;
-	else
-		cwl = 8;
+	else if (mclk_ps >= 1070)
+		cwl = 9;
+	else if (mclk_ps >= 935)
+		cwl = 10;
+	else if (mclk_ps >= 833)
+		cwl = 11;
+	else if (mclk_ps >= 750)
+		cwl = 12;
+	else {
+		cwl = 12;
+		printf("Warning: CWL is out of range\n");
+	}
 	return cwl;
 }