From: RichardBarry Date: Sun, 1 Apr 2012 17:54:07 +0000 (+0000) Subject: Update MSP430X IAR port to ensure the power settings are correct for the clock speed. X-Git-Tag: V7.1.1~40 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2bfbd8b34bc1e14830342630555dc52394d7fb1d;p=freertos Update MSP430X IAR port to ensure the power settings are correct for the clock speed. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1706 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/MSP430X_MSP430F5438_IAR/F5XX_6XX_Core_Lib/HAL_PMM.c b/Demo/MSP430X_MSP430F5438_IAR/F5XX_6XX_Core_Lib/HAL_PMM.c new file mode 100644 index 000000000..7e16eae0d --- /dev/null +++ b/Demo/MSP430X_MSP430F5438_IAR/F5XX_6XX_Core_Lib/HAL_PMM.c @@ -0,0 +1,248 @@ +/******************************************************************************* + * + * HAL_PMM.c + * Power Management Module Library for MSP430F5xx/6xx family + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "msp430.h" +#include "HAL_PMM.h" + +/******************************************************************************* + * \brief Increase Vcore by one level + * + * \param level Level to which Vcore needs to be increased + * \return status Success/failure + ******************************************************************************/ + +static uint16_t SetVCoreUp(uint8_t level) +{ + uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; + + // The code flow for increasing the Vcore has been altered to work around + // the erratum FLASH37. + // Please refer to the Errata sheet to know if a specific device is affected + // DO NOT ALTER THIS FUNCTION + + // Open PMM registers for write access + PMMCTL0_H = 0xA5; + + // Disable dedicated Interrupts + // Backup all registers + PMMRIE_backup = PMMRIE; + PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE | + SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE); + SVSMHCTL_backup = SVSMHCTL; + SVSMLCTL_backup = SVSMLCTL; + + // Clear flags + PMMIFG = 0; + + // Set SVM highside to new level and check if a VCore increase is possible + SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level); + + // Wait until SVM highside is settled + while ((PMMIFG & SVSMHDLYIFG) == 0) ; + + // Clear flag + PMMIFG &= ~SVSMHDLYIFG; + + // Check if a VCore increase is possible + if ((PMMIFG & SVMHIFG) == SVMHIFG){ // -> Vcc is too low for a Vcore increase + // recover the previous settings + PMMIFG &= ~SVSMHDLYIFG; + SVSMHCTL = SVSMHCTL_backup; + + // Wait until SVM highside is settled + while ((PMMIFG & SVSMHDLYIFG) == 0) ; + + // Clear all Flags + PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG); + + PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register + PMMCTL0_H = 0x00; // Lock PMM registers for write access + return PMM_STATUS_ERROR; // return: voltage not set + } + + // Set also SVS highside to new level + // Vcc is high enough for a Vcore increase + SVSMHCTL |= (SVSHRVL0 * level); + + // Wait until SVM highside is settled + while ((PMMIFG & SVSMHDLYIFG) == 0) ; + + // Clear flag + PMMIFG &= ~SVSMHDLYIFG; + + // Set VCore to new level + PMMCTL0_L = PMMCOREV0 * level; + + // Set SVM, SVS low side to new level + SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level); + + // Wait until SVM, SVS low side is settled + while ((PMMIFG & SVSMLDLYIFG) == 0) ; + + // Clear flag + PMMIFG &= ~SVSMLDLYIFG; + // SVS, SVM core and high side are now set to protect for the new core level + + // Restore Low side settings + // Clear all other bits _except_ level settings + SVSMLCTL &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + // Clear level settings in the backup register,keep all other bits + SVSMLCTL_backup &= ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + // Restore low-side SVS monitor settings + SVSMLCTL |= SVSMLCTL_backup; + + // Restore High side settings + // Clear all other bits except level settings + SVSMHCTL &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + // Clear level settings in the backup register,keep all other bits + SVSMHCTL_backup &= ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + // Restore backup + SVSMHCTL |= SVSMHCTL_backup; + + // Wait until high side, low side settled + while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)) ; + + // Clear all Flags + PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG); + + PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register + PMMCTL0_H = 0x00; // Lock PMM registers for write access + + return PMM_STATUS_OK; +} + +/******************************************************************************* + * \brief Decrease Vcore by one level + * + * \param level Level to which Vcore needs to be decreased + * \return status Success/failure + ******************************************************************************/ + +static uint16_t SetVCoreDown(uint8_t level) +{ + uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; + + // The code flow for decreasing the Vcore has been altered to work around + // the erratum FLASH37. + // Please refer to the Errata sheet to know if a specific device is affected + // DO NOT ALTER THIS FUNCTION + + // Open PMM registers for write access + PMMCTL0_H = 0xA5; + + // Disable dedicated Interrupts + // Backup all registers + PMMRIE_backup = PMMRIE; + PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE | + SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE); + SVSMHCTL_backup = SVSMHCTL; + SVSMLCTL_backup = SVSMLCTL; + + // Clear flags + PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG); + + // Set SVM, SVS high & low side to new settings in normal mode + SVSMHCTL = SVMHE | (SVSMHRRL0 * level) | SVSHE | (SVSHRVL0 * level); + SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level); + + // Wait until SVM high side and SVM low side is settled + while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0) ; + + // Clear flags + PMMIFG &= ~(SVSMHDLYIFG + SVSMLDLYIFG); + // SVS, SVM core and high side are now set to protect for the new core level + + // Set VCore to new level + PMMCTL0_L = PMMCOREV0 * level; + + // Restore Low side settings + // Clear all other bits _except_ level settings + SVSMLCTL &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + // Clear level settings in the backup register,keep all other bits + SVSMLCTL_backup &= ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + // Restore low-side SVS monitor settings + SVSMLCTL |= SVSMLCTL_backup; + + // Restore High side settings + // Clear all other bits except level settings + SVSMHCTL &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + // Clear level settings in the backup register, keep all other bits + SVSMHCTL_backup &= ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + // Restore backup + SVSMHCTL |= SVSMHCTL_backup; + + // Wait until high side, low side settled + while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)) ; + + // Clear all Flags + PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG); + + PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register + PMMCTL0_H = 0x00; // Lock PMM registers for write access + return PMM_STATUS_OK; // Return: OK +} + +uint16_t SetVCore(uint8_t level) +{ + uint16_t actlevel; + uint16_t status = 0; + + level &= PMMCOREV_3; // Set Mask for Max. level + actlevel = (PMMCTL0 & PMMCOREV_3); // Get actual VCore + // step by step increase or decrease + while ((level != actlevel) && (status == 0)) { + if (level > actlevel){ + status = SetVCoreUp(++actlevel); + } + else { + status = SetVCoreDown(--actlevel); + } + } + + return status; +} + diff --git a/Demo/MSP430X_MSP430F5438_IAR/F5XX_6XX_Core_Lib/HAL_PMM.h b/Demo/MSP430X_MSP430F5438_IAR/F5XX_6XX_Core_Lib/HAL_PMM.h new file mode 100644 index 000000000..ace164149 --- /dev/null +++ b/Demo/MSP430X_MSP430F5438_IAR/F5XX_6XX_Core_Lib/HAL_PMM.h @@ -0,0 +1,113 @@ +/******************************************************************************* + * + * HAL_PMM.h + * Power Management Module Library for MSP430F5xx/6xx family + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef HAL_PMM_H +#define HAL_PMM_H + +#include +#include "HAL_MACROS.h" + +/******************************************************************************* + * Macros + ******************************************************************************/ +#define ENABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVSLE; PMMCTL0_H = 0x00; ) +#define ENABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVMLE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVMLE; PMMCTL0_H = 0x00; ) +#define ENABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVSHE; PMMCTL0_H = 0x00; ) +#define ENABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVMHE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVMHE; PMMCTL0_H = 0x00; ) +#define ENABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLE + SVMLE); PMMCTL0_H = 0x00; ) +#define DISABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLE + SVMLE); PMMCTL0_H = 0x00; ) +#define ENABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHE + SVMHE); PMMCTL0_H = 0x00; ) +#define DISABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSHE + SVMHE); PMMCTL0_H = 0x00; ) + +#define ENABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSLPE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSLPE; PMMCTL0_H = 0x00; ) +#define ENABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMLIE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMLIE; PMMCTL0_H = 0x00; ) +#define ENABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSHPE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSHPE; PMMCTL0_H = 0x00; ) +#define ENABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMHIE; PMMCTL0_H = 0x00; ) +#define DISABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMHIE; PMMCTL0_H = 0x00; ) +#define CLEAR_PMM_IFGS() st(PMMCTL0_H = 0xA5; PMMIFG = 0; PMMCTL0_H = 0x00; ) + +// These settings use SVSH/LACE = 0 +#define SVSL_ENABLED_IN_LPM_FAST_WAKE() st( \ + PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP + SVSLMD); SVSMLCTL &= ~SVSMLACE; PMMCTL0_H = 0x00; ) +#define SVSL_ENABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLMD; SVSMLCTL &= \ + ~(SVSLFP + SVSMLACE); PMMCTL0_H = 0x00; ) + +#define SVSL_DISABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLFP; SVSMLCTL &= \ + ~(SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; ) +#define SVSL_DISABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL &= \ + ~(SVSLFP + SVSMLACE + SVSLMD); PMMCTL0_H = 0x00; ) + +#define SVSH_ENABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHMD; SVSMHCTL &= \ + ~(SVSMHACE + SVSHFP); PMMCTL0_H = 0x00; ) +#define SVSH_ENABLED_IN_LPM_FULL_PERF() st( \ + PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD + SVSHFP); SVSMHCTL &= ~SVSMHACE; PMMCTL0_H = 0x00; ) + +#define SVSH_DISABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL &= \ + ~(SVSMHACE + SVSHFP + SVSHMD); PMMCTL0_H = 0x00; ) +#define SVSH_DISABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHFP; SVSMHCTL &= \ + ~(SVSMHACE + SVSHMD); PMMCTL0_H = 0x00; ) + +// These setting use SVSH/LACE = 1 +#define SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= \ + (SVSLFP + SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; ) +#define SVSH_OPTIMIZED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= \ + (SVSHMD + SVSHFP + SVSMHACE); PMMCTL0_H = 0x00; ) + +/******************************************************************************* + * Defines + ******************************************************************************/ +#define PMM_STATUS_OK 0 +#define PMM_STATUS_ERROR 1 + +/******************************************************************************* + * \brief Set Vcore to expected level + * + * \param level Level to which Vcore needs to be increased/decreased + * \return status Success/failure + ******************************************************************************/ +extern uint16_t SetVCore(uint8_t level); + +#endif /* HAL_PMM_H */ diff --git a/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h b/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h index fd2db001d..704d4fe03 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h +++ b/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd. - + *************************************************************************** * * @@ -69,7 +69,8 @@ #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( 25000000UL ) +#define configCPU_CLOCK_HZ ( 25000000UL ) +#define configLFXT_CLOCK_HZ ( 32768L ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) ) @@ -125,7 +126,7 @@ The timer is configured to interrupt each time it overflows so a count of overflows can be kept - that way a 32 bit time value can be constructed from the timers current count value and the number of overflows. */ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() - + /* Construct a 32 bit time value for use as the run time stats time base. This comes from the current value of a 16 bit timer combined with the number of times the timer has overflowed. */ diff --git a/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_MSP-EXP430F5438.h b/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_MSP-EXP430F5438.h index c1baa94ff..6d97edac0 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_MSP-EXP430F5438.h +++ b/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_MSP-EXP430F5438.h @@ -23,5 +23,6 @@ in order to use MSP-EXP430F5438 HAL. //#include "hal_rf.h" //#include "hal_rtc.h" //#include "hal_tlv.h" +#include "hal_pmm.h" #endif /* HAL_MSP_EXP430F5438_H */ diff --git a/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.c b/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.c index f44d7409a..444741ab7 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.c +++ b/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.c @@ -66,3 +66,43 @@ void halBoardInit(void) PJDIR = 0xFF; P11SEL = 0; } + +/**********************************************************************//** + * @brief Set function for MCLK frequency. + * + * + * @return none + *************************************************************************/ +void hal430SetSystemClock(unsigned long req_clock_rate, unsigned long ref_clock_rate) +{ + /* Convert a Hz value to a KHz value, as required + * by the Init_FLL_Settle() function. */ + unsigned long ulCPU_Clock_KHz = req_clock_rate / 1000UL; + + //Make sure we aren't overclocking + if(ulCPU_Clock_KHz > 25000L) + { + ulCPU_Clock_KHz = 25000L; + } + + //Set VCore to a level sufficient for the requested clock speed. + if(ulCPU_Clock_KHz <= 8000L) + { + SetVCore(PMMCOREV_0); + } + else if(ulCPU_Clock_KHz <= 12000L) + { + SetVCore(PMMCOREV_1); + } + else if(ulCPU_Clock_KHz <= 20000L) + { + SetVCore(PMMCOREV_2); + } + else + { + SetVCore(PMMCOREV_3); + } + + //Set the DCO + Init_FLL_Settle( ( unsigned short )ulCPU_Clock_KHz, req_clock_rate / ref_clock_rate ); +} diff --git a/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.h b/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.h index 603c72836..c4fe6318d 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.h +++ b/Demo/MSP430X_MSP430F5438_IAR/MSP-EXP430F5438_HAL/hal_board.h @@ -27,5 +27,6 @@ static void halBoardGetSystemClockSettings(unsigned char systemClockSpeed, extern void halBoardOutputSystemClock(void); extern void halBoardStopOutputSystemClock(void); extern void halBoardInit(void); +void hal430SetSystemClock(unsigned long req_clock_rate, unsigned long ref_clock_rate); #endif /* HAL_BOARD_H */ diff --git a/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp b/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp index 76af4b41f..8ec55d855 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp +++ b/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp @@ -3796,6 +3796,9 @@ F5XX_6XX_Core_Lib + + $PROJ_DIR$\F5XX_6XX_Core_Lib\HAL_PMM.c + $PROJ_DIR$\F5XX_6XX_Core_Lib\hal_UCS.c diff --git a/Demo/MSP430X_MSP430F5438_IAR/main.c b/Demo/MSP430X_MSP430F5438_IAR/main.c index b7122effa..9577a4395 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/main.c +++ b/Demo/MSP430X_MSP430F5438_IAR/main.c @@ -443,14 +443,10 @@ xQueueMessage xMessage; static void prvSetupHardware( void ) { -/* Convert a Hz value to a KHz value, as required by the Init_FLL_Settle() -function. */ -unsigned long ulCPU_Clock_KHz = ( configCPU_CLOCK_HZ / 1000UL ); - halBoardInit(); LFXT_Start( XT1DRIVE_0 ); - Init_FLL_Settle( ( unsigned short ) ulCPU_Clock_KHz, 488 ); + hal430SetSystemClock( configCPU_CLOCK_HZ, configLFXT_CLOCK_HZ ); halButtonsInit( BUTTON_ALL ); halButtonsInterruptEnable( BUTTON_SELECT ); diff --git a/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dbgdt b/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dbgdt index 46edd8ae7..beeea5c35 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dbgdt +++ b/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dbgdt @@ -31,7 +31,7 @@ - + TabID-11539-27703 @@ -43,20 +43,20 @@ - 0TabID-25774-15685Terminal I/OTerminalIO0TabID-408-3295Debug LogDebug-Log0 + 0TabID-25774-15685Terminal I/OTerminalIO0TabID-408-3295Debug LogDebug-Log0 - TextEditor$WS_DIR$\main.c02301219712197TextEditor$WS_DIR$\..\..\Source\portable\IAR\MSP430X\portext.s4309244024402TextEditor$WS_DIR$\..\..\Source\tasks.c01615513255132520100000010000001 + TextEditor$WS_DIR$\main.c0425199391993900100000010000001 - iaridepm.enu1430fet1debuggergui.enu1-2-2716259-2-212115072024152749155357731161-2-2716514-2-2200200119048203666307143731161-2-21981682-2-216842001002381203666119048203666 + iaridepm.enu1430fet1debuggergui.enu1-2-2716259-2-212115072024152749155357731161-2-2716514-2-2200200119048203666307143731161-2-21981682-2-216842001002381203666119048203666 diff --git a/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dni b/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dni index 3aa7b04f7..f24622ccb 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dni +++ b/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.dni @@ -1,5 +1,5 @@ [DebugChecksum] -Checksum=131837655 +Checksum=1421140093 [DisAssemblyWindow] NumStates=_ 1 State 1=_ 1 @@ -28,6 +28,16 @@ UseTrigger=1 TriggerName=main LimitSize=0 ByteLimit=50 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 [Log file] LoggingEnabled=_ 0 LogFile=_ "" @@ -35,13 +45,16 @@ Category=_ 0 [TermIOLog] LoggingEnabled=_ 0 LogFile=_ "" +[CallStack] +ShowArgs=0 [CallStackLog] Enabled=0 [DriverProfiling] Enabled=0 -Mode=152238872 +Mode=0 Graph=0 Symbiont=0 +Exclusions= [Breakpoints] Count=0 [FET] diff --git a/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt b/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt index 11db5ab79..c5cfe63a4 100644 --- a/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt +++ b/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt @@ -12,7 +12,7 @@ - 235272727 + 335272727 @@ -43,14 +43,14 @@ - TextEditor$WS_DIR$\main.c040121971219700100000010000001 + TextEditor$WS_DIR$\main.c050192361923600100000010000001 - iaridepm.enu1-2-2740309-2-2331267197024271894185119755601-2-21981682-2-216842001002381203666119048203666 + iaridepm.enu1-2-2610409-2-2331267197024271894244643623218-2-23281682-2-216843301002381336049119048203666