From: P.V.Suresh Date: Sat, 4 Dec 2010 05:07:23 +0000 (+0530) Subject: fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controller X-Git-Tag: v2010.12-rc3~9 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2c1764efc2872fc944d0d580e911168c0a231f8c;p=u-boot fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controller eSDHC host controller reset results in clearing of snoop bit also. This patch sets the SNOOP bit after the completion of host controller reset. Without this patch mmc reads are not consistent. Signed-off-by: P.V.Suresh Signed-off-by: Kumar Gala --- diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a368fe60db..57cd4ee1f4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -384,10 +384,6 @@ static int esdhc_init(struct mmc *mmc) int ret = 0; u8 card_absent; - /* Enable cache snooping */ - if (cfg && !cfg->no_snoop) - esdhc_write32(®s->scr, 0x00000040); - /* Reset the entire host controller */ esdhc_write32(®s->sysctl, SYSCTL_RSTA); @@ -395,6 +391,10 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) udelay(1000); + /* Enable cache snooping */ + if (cfg && !cfg->no_snoop) + esdhc_write32(®s->scr, 0x00000040); + esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */