From: Vladimir Barinov Date: Fri, 13 Feb 2015 22:05:18 +0000 (+0300) Subject: serial: sh: fix internal clock source on SCIF X-Git-Tag: v2015.04-rc3~13^2~3 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2cbb17c0e941db629ff2d363c7fef69e47fb7d92;p=u-boot serial: sh: fix internal clock source on SCIF The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows: BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1, the prescaler is 0 due to SCSMR settings, hence n=0 Also SCSCR must be set to use internal or external clock source. Signed-off-by: Vladimir Barinov Signed-off-by: Nobuhiro Iwamatsu --- diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 528aa7351d..941e6eda4c 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -227,7 +227,8 @@ struct uart_port { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) # define SCIF_ORER 0x0001 -# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ +# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) + /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else # error CPU subtype not defined #endif @@ -742,7 +743,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ +#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif