From: Paul Fertser Date: Mon, 22 Oct 2018 20:13:04 +0000 (+0300) Subject: tcl: target: omit apcsw for hla X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2ed21488cd52eb8eac10b7984096bdf0652cbae7;p=openocd tcl: target: omit apcsw for hla When using stlink for CM7 targets we have to rely on its firmware to do the right thing as direct DAP access is not possible. Change-Id: Ieee69f4eeea5c911f89f060f31ce86ed043bdfd0 Signed-off-by: Paul Fertser Reviewed-on: http://openocd.zylin.com/4732 Tested-by: jenkins Reviewed-by: Matthias Welwarsky Reviewed-by: Tomas Vanek --- diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg index 1d026aa9..43962de3 100644 --- a/tcl/target/atsamv.cfg +++ b/tcl/target/atsamv.cfg @@ -45,15 +45,16 @@ if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq + + # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal + # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 + # makes the data access cacheable. This allows reading and writing data in the + # CPU cache from the debugger, which is far more useful than going straight to + # RAM when operating on typical variables, and is generally no worse when + # operating on special memory locations. + $_CHIPNAME.dap apcsw 0x08000000 0x08000000 } set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME -# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal -# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 -# makes the data access cacheable. This allows reading and writing data in the -# CPU cache from the debugger, which is far more useful than going straight to -# RAM when operating on typical variables, and is generally no worse when -# operating on special memory locations. -$_CHIPNAME.dap apcsw 0x08000000 0x08000000 diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg index e06a3459..b0468e21 100755 --- a/tcl/target/stm32f7x.cfg +++ b/tcl/target/stm32f7x.cfg @@ -65,6 +65,14 @@ if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq + + # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal + # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 + # makes the data access cacheable. This allows reading and writing data in the + # CPU cache from the debugger, which is far more useful than going straight to + # RAM when operating on typical variables, and is generally no worse when + # operating on special memory locations. + $_CHIPNAME.dap apcsw 0x08000000 0x08000000 } $_TARGETNAME configure -event examine-end { @@ -146,10 +154,3 @@ $_TARGETNAME configure -event reset-start { adapter_khz 2000 } -# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal -# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 -# makes the data access cacheable. This allows reading and writing data in the -# CPU cache from the debugger, which is far more useful than going straight to -# RAM when operating on typical variables, and is generally no worse when -# operating on special memory locations. -$_CHIPNAME.dap apcsw 0x08000000 0x08000000 diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index e2ea8a84..c9aec761 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -63,6 +63,14 @@ if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq + + # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal + # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 + # makes the data access cacheable. This allows reading and writing data in the + # CPU cache from the debugger, which is far more useful than going straight to + # RAM when operating on typical variables, and is generally no worse when + # operating on special memory locations. + $_CHIPNAME.dap apcsw 0x08000000 0x08000000 } $_TARGETNAME configure -event examine-end { @@ -93,10 +101,3 @@ $_TARGETNAME configure -event reset-init { adapter_khz 4000 } -# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal -# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 -# makes the data access cacheable. This allows reading and writing data in the -# CPU cache from the debugger, which is far more useful than going straight to -# RAM when operating on typical variables, and is generally no worse when -# operating on special memory locations. -$_CHIPNAME.dap apcsw 0x08000000 0x08000000