From: Peter Tyser <ptyser@xes-inc.com>
Date: Thu, 21 May 2009 17:10:00 +0000 (-0500)
Subject: fsl/85xx, 86xx: Sync up DMA code
X-Git-Tag: v2009.08-rc1~153^2~4
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=2f21ce4d546d31289ac49a680f78bcc9a792c6ec;p=u-boot

fsl/85xx, 86xx: Sync up DMA code

The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 331fcc09a4..d88c564620 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -269,9 +269,9 @@ void dma_init(void) {
 	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->satr = 0x02c40000;
-	dma->datr = 0x02c40000;
-	dma->sr = 0xfffffff; /* clear any errors */
+	dma->satr = 0x00040000;
+	dma->datr = 0x00040000;
+	dma->sr = 0xffffffff; /* clear any errors */
 	asm("sync; isync; msync");
 	return;
 }
@@ -286,7 +286,7 @@ uint dma_check(void) {
 		status = dma->sr;
 	}
 
-	/* clear MR0[CS] channel start bit */
+	/* clear MR[CS] channel start bit */
 	dma->mr &= 0x00000001;
 	asm("sync;isync;msync");
 
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f35323ac67..d47cc5ef3a 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -182,20 +182,19 @@ watchdog_reset(void)
 void
 dma_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
 	dma->satr = 0x00040000;
 	dma->datr = 0x00040000;
+	dma->sr = 0xffffffff; /* clear any errors */
 	asm("sync; isync");
 }
 
 uint
 dma_check(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 	volatile uint status = dma->sr;
 
@@ -204,6 +203,10 @@ dma_check(void)
 		status = dma->sr;
 	}
 
+	/* clear MR[CS] channel start bit */
+	dma->mr &= 0x00000001;
+	asm("sync;isync");
+
 	if (status != 0) {
 		printf("DMA Error: status = %x\n", status);
 	}
@@ -213,8 +216,7 @@ dma_check(void)
 int
 dma_xfer(void *dest, uint count, void *src)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
 	dma->dar = (uint) dest;
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 689c720452..a8398348b1 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1295,5 +1295,7 @@ extern immap_t  *immr;
 #define CONFIG_SYS_MPC86xx_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
 #define CONFIG_SYS_MPC86xx_DDR2_OFFSET	(0x6000)
 #define CONFIG_SYS_MPC86xx_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DMA_OFFSET	(0x21000)
+#define CONFIG_SYS_MPC86xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
 
 #endif /*__IMMAP_86xx__*/