From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Fri, 17 Feb 2017 13:49:00 +0000 (+0300)
Subject: x86: Intel MID platforms has no microcode update
X-Git-Tag: v2017.03-rc3~10^2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=308c75e08deac2933fbc63a1e9521343e710279c;p=u-boot

x86: Intel MID platforms has no microcode update

There is no microcode update available for SoCs used on Intel MID
platforms.

Use conditional to bypass it.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 988073cc79..cfd9bb447b 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -248,7 +248,8 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
 	if (!stack)
 		return -ENOMEM;
 	params->stack_top = (u32)(stack + size);
-#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
+	!defined(CONFIG_INTEL_MID)
 	params->microcode_ptr = ucode_base;
 	debug("Microcode at %x\n", params->microcode_ptr);
 #endif