From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Fri, 2 Jun 2017 03:29:04 +0000 (+0800)
Subject: video: atmel_hlcdfb: Fix misaligned cache operation warning
X-Git-Tag: v2017.07-rc2~56^2~2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=31e5c892b35f1ec90c7b90e6faac79d31145d0e9;p=u-boot

video: atmel_hlcdfb: Fix misaligned cache operation warning

Fix the warning,
 ---8<---
CACHE: Misaligned operation at range [3fdffff0, 3fdffffc]
 ---<8---

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 47078fdaae..f77da2ec97 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -426,7 +426,9 @@ static void atmel_hlcdc_init(struct udevice *dev)
 	writel(~0UL, &regs->lcdc_baseidr);
 
 	/* Setup the DMA descriptor, this descriptor will loop to itself */
-	desc = (struct lcd_dma_desc *)(uc_plat->base - 16);
+	desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
+	if (!desc)
+		return;
 
 	desc->address = (u32)uc_plat->base;
 
@@ -436,7 +438,9 @@ static void atmel_hlcdc_init(struct udevice *dev)
 	desc->next = (u32)desc;
 
 	/* Flush the DMA descriptor if we enabled dcache */
-	flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+	flush_dcache_range((u32)desc,
+			   ALIGN(((u32)desc + sizeof(*desc)),
+			   CONFIG_SYS_CACHELINE_SIZE));
 
 	writel(desc->address, &regs->lcdc_baseaddr);
 	writel(desc->control, &regs->lcdc_basectrl);