From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Date: Tue, 16 Jan 2018 17:44:27 +0000 (+0300)
Subject: ARC: HSDK: CGU: Add 'Hz' when printing clock frequency
X-Git-Tag: v2018.03-rc1~119^2~3
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=320c8a1a860e91983955b9d69014324a1c1c0ad8;p=u-boot

ARC: HSDK: CGU: Add 'Hz' when printing clock frequency

Add 'Hz' when printing clock frequency in error messages.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---

diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 64bb1db821..4362d583cb 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -492,7 +492,7 @@ static ulong pll_set(struct clk *sclk, ulong rate)
 		}
 	}
 
-	pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+	pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
 
 	return -EINVAL;
 }
@@ -623,14 +623,14 @@ static ulong idiv_set(struct clk *sclk, ulong rate)
 	}
 
 	if (div_factor & ~CGU_IDIV_MASK) {
-		pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+		pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
 		       rate, parent_rate, div_factor, CGU_IDIV_MASK);
 
 		div_factor = CGU_IDIV_MASK;
 	}
 
 	if (div_factor == 0) {
-		pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+		pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
 		       rate, parent_rate, div_factor);
 
 		div_factor = 1;